Verifying the correctness of the leading zero counter

Abstract

generating a first bit vector based on an input value consisting of multiple digits, each entry of the first bit vector indicating whether a corresponding digit of the input value is equal to zero; calculating a leading zero count of the input value based on the first bit vector; generating a bit mask including a number of leading ones equal to the leading zero count; generating a second bit vector including a one at an index same as a first occurring zero in the bit mask; and verifying the correctness of the leading zero count based on the first bit vector, and one or more of the bit mask and the second bit vector.

Description

[Technical field]

[0001] The field of the invention is data processing, or more specifically, methods, apparatus, and products for verifying the correctness of a leading zero counter. [Background technology]

[0002] The development of the EDVAC computer system in 1948 is often cited as the beginning of the computer age. Since then, computer systems have evolved into extremely complex devices. Today's computers are much more sophisticated than early systems such as the EDVAC. A computer system typically includes a combination of hardware and software components, application programs, operating systems, processors, buses, memory, and input / output devices. As advances in semiconductor processing and computer architectures push computer performance to higher heights, more sophisticated computer software has evolved to take advantage of the higher performance of the hardware, resulting in today's computer systems being much more powerful than they were just a few years ago.

[0003] Leading zero counters are difficult to test using existing test methods. Therefore, if a leading zero counter is defective, the defect may not be detected or may not be detected until after deployment. A defective leading zero counter may overestimate or underestimate the number of leading zeros in a numeric value, causing functional errors.

[0004] The foregoing and other objects, features and advantages of the present invention will become apparent from the following more particular description of exemplary embodiments thereof, as illustrated in the accompanying drawings, in which like reference characters generally represent similar parts of the exemplary embodiments of the present invention. [Brief description of the drawings]

[0005] [Figure 1]FIG. 1 is a block diagram of an example chip for verifying the correctness of a leading zero counter, in accordance with some embodiments of the present disclosure. [Figure 2A] FIG. 11 is a diagram of an example input hexadecimal value for calculating leading zero count, according to some embodiments of the present disclosure. [Figure 2B] FIG. 11 is a diagram of an example bit vector for calculating leading zero count, in accordance with some embodiments of the present disclosure. [Figure 3A] FIG. 11 is a diagram of an example bit mask for verifying the correctness of a leading zero counter, in accordance with some embodiments of the present disclosure. [Figure 3B] FIG. 11 is a diagram of an example bit vector for verifying the correctness of a leading zero counter, in accordance with some embodiments of the present disclosure. [Figure 4] FIG. 1 is a block diagram of an example computer for verifying the correctness of a leading zero counter, in accordance with some embodiments of the present disclosure. [Diagram 5] 1 is a flowchart of an example method for verifying the correctness of a leading zero counter, according to some embodiments of the present disclosure. [Figure 6] 1 is a flowchart of another example method for verifying the correctness of a leading zero counter, according to some embodiments of the present disclosure. [Figure 7] 1 is a flowchart of another example method for verifying the correctness of a leading zero counter, according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] Various computational operations involve counting the number of leading zero digits in a number, such as a hexadecimal number. For example, to output an internally formatted number into a human-readable format that removes the leading zeros, one may count their number so that they can be removed. To do this, a leading zero counter circuit may be employed on a chip or other device.

[0007] Leading zero counters are difficult to test using existing test methods. Therefore, if a leading zero counter is defective, the defect may not be detected or may not be detected until after deployment. A defective leading zero counter may overestimate or underestimate the number of leading zeros in a numeric value, causing functional errors.

[0008] To this end, exemplary methods, apparatus, and products for verifying the correctness of a leading zero counter according to the present invention will be described with reference to the accompanying drawings, beginning with FIG. 1. FIG. 1 illustrates a block diagram of an exemplary system 100 for verifying the correctness of a leading zero counter, according to some embodiments of the present disclosure. The system 100 includes a leading zero counter 102. The leading zero counter 102 accepts an encoded numeric value, such as a hexadecimal number, as an input 104. The leading zero counter 102 outputs a leading zero (LZ) count 106 indicating the number of leading zeros in the input 104 counted by the leading zero counter 102. The number of leading zeros is the number of digits in which each bit of the digit is zero. For example, in the context of a hexadecimal input 104, each digit is 4 bits. Thus, each leading zero includes four zero bits.

[0009] In some embodiments, to calculate the LZ count 106, the leading zero counter 102 applies a bitwise OR to the bits of the digit in the input 104 for each digit in the input 104. Consider the example of a 128-bit hexadecimal input 104 shown in FIG. 2A. The leading zero counter 102 performs 32 4-bit OR operations, one for each of the 32 digits in the input 102. The result is a bit vector 108, where each entry in the bit vector 108 corresponds to the result of the bitwise OR operation on the corresponding digit. Continuing with the above example, as shown in FIG. 2B, the bit vector 108 would contain 32 entries corresponding to the 32 digits in the input 102. Each entry would then contain the result of a 4-bit OR operation on the bits of the corresponding digit. After generating the bit vector 108, the leading zero counter 104 calculates the LZ count 106 by counting the number of leading zeros in the bit vector 108. The LZ count 106 may be encoded, for example, as a binary encoded vector of bits.

[0010] The system 100 also includes a tester 110 that verifies the accuracy of the LZ count 106 produced by the leading zero counter 104. The tester 110 may be implemented, for example, as a device or apparatus coupled to the leading zero counter 102 and configured to receive the LZ count 106 and the bit vector 108 from the leading zero counter 102. As another example, the tester 110 may be implemented as logic or circuitry mounted on the same device, apparatus, board, etc. as the leading zero counter 102. As an example, in some embodiments, the tester 110 is configured to determine whether the LZ count 106 is too large, too small, or neither. The tester 110 accepts as inputs the LZ count 106 from the leading zero counter 102 and the bit vector 108 generated by the leading zero counter 102 that was used to calculate the LZ count 106.

[0011] To that end, the tester 110 generates, from the LZ count 106, a bit mask 112 that includes a number of leading ones equal to the LZ count 106. For example, as shown in FIG. 3A, assuming the LZ count 106 is four, the bit mask 112 includes four leading ones and the remainder are zeros. The size of the bit mask 112 is equal to the number of digits in the input 102. For example, for a 32-digit input 102, the bit mask 112 includes 32 bits. In some embodiments, generating the bit mask 112 includes providing the LZ count 106 to a half decoder 114, which outputs the bit mask 112.

[0012] The tester 110 then generates another bit vector 118 from the bit mask 112. The bit vector 118 is all zeros with a one at an index corresponding to the first zero in the bit mask 112. For example, looking at FIG. 3B, assuming a bit mask 112 with four leading ones, the bit vector 118 would include four leading zeros and a one in the fifth entry. In some embodiments, the tester 110 generates the bit vector 118 by performing a bitwise exclusive-or (XOR) operation on each pair of bits in the bit mask 112. For example, each entry of the bit vector 118 is generated by feeding a corresponding entry of the bit mask 112 and an entry preceding the corresponding entry to a corresponding one of the multiple XOR gates 116. Because the first entry of the bit mask 112 does not have a preceding entry, the first entry of the bit vector 118 may be generated by feeding a one to the first entry of the bit mask 112.

[0013] Tester 110 then verifies LZ count 106 using test logic 120. As an example, in some embodiments, tester 110 determines whether LZ count 106 is too large by performing a bitwise AND of bit vector 108 (e.g., bit vector 108 generated by leading zero counter 102) and bit mask 112. The result of this bitwise AND should be all zeros. If it is not, LZ count 106 is too large.

[0014] As an example, assume a bit vector 108 with four leading zeros, "00001101011...", and a correct LZ count 106, 4. Further assume a bit mask 112 with four leading ones, "11110000...", based on the LZ count 106. The result of the bitwise AND will equal all zeros, indicating that the result is not too large. Instead, assume the same bit vector 108, but with an LZ count 106 of 5, resulting in a bit mask of "11111000...". The result of this bitwise AND operation will be "00001000...". Because the result is not all zeros, this indicates that the LZ count 106 is too large.

[0015] In some embodiments, tester 110 determines whether LZ count 106 is too small by performing a bitwise AND operation on bit vector 108 and bit vector 118 (e.g., bit vector 118 having a 1 corresponding to the first zero in bit mask 112). The result of this bitwise AND operation must not be all zeros. Otherwise, the result is too small. For example, assume that bit vector 108 is "00001101011..." with four leading zeros, and the correct LZ count 106 is 4. Further assume that bit vector 118 is "000010000......". The bitwise AND of bit vector 108 and bit vector 118 is equal to "0000100000". Because the result is not all zeros, LZ count 106 is not too small. Suppose instead that we have the same bit vector 108, but the LZ count 106 is inaccurate at 3, giving us bit vector 118 "0001000...." The result of this bitwise AND operation is all zeros, indicating that the LZ count 106 is too small.

[0016] Those skilled in the art will appreciate that the technique employed by tester 110 is highly efficient, requiring only a half decoder 114 and an XOR gate 116 to generate bit mask 112 and bit vector 118, respectively. Furthermore, those skilled in the art 110 will appreciate that the technique described herein can be used with any type of leading zero counter 102.

[0017] Verification of the correctness of the leading zero counter according to the present application is generally performed on a computer, i.e., an automated calculator. Accordingly, for further explanation, FIG. 4 illustrates a block diagram of a calculator including an exemplary computer 400 configured to verify the correctness of the leading zero counter according to a particular embodiment. The computer 400 of FIG. 4 includes at least one computer processor 402, i.e., "CPU", and random access memory 404 ("RAM") connected to the processor 402 and other components of the computer 400 via a high-speed memory bus 406 and a bus adapter 408.

[0018] Stored in RAM 404 is an operating system 410. Operating systems useful in a computer configured to verify the correctness of a leading zero counter according to certain embodiments include UNIX®, Linux®, Microsoft Windows®, and others that will occur to those skilled in the art. While the example operating system 410 of FIG. 4 is shown in RAM 404, many components of such software are typically also stored in non-volatile memory, such as a data storage device 412, e.g., a disk drive.

[0019] The computer 400 of FIG. 4 includes a disk drive adapter 416 coupled to the processor 402 and other components of the computer 400 via an expansion bus 418 and a bus adapter 408. The disk drive adapter 416 connects non-volatile data storage to the computer 400 in the form of a data storage device 412. Disk drive adapters useful for computers configured to verify the correctness of leading zero counters according to certain embodiments include integrated drive electronics ("IDE") adapters, small computer system interface ("SCSI") adapters, and others as would occur to one of ordinary skill in the art. In some embodiments, the non-volatile computer memory is implemented as an optical disk drive, an electrically erasable programmable read-only memory (so-called "EEPROM" or "flash" memory), a RAM drive, or the like, as would occur to one of ordinary skill in the art.

[0020] The example computer 400 of FIG. 4 includes one or more input / output ("I / O") adapters 420. I / O adapters implement user-oriented input / output, for example through software drivers and computer hardware for controlling output to a display device, such as a computer display screen, and user input from user input devices 422, such as a keyboard and mouse. The example computer 400 of FIG. 4 includes a video adapter 424, which is an example of an I / O adapter specifically designed for graphics output to a display device 426, such as a display screen or computer monitor. The video adapter 424 is connected to the processor 402 via a high-speed video bus 428, the bus adapter 408, and a front side bus 430, which is also a high-speed bus.

[0021] The exemplary computer 400 of FIG. 4 includes a communications adapter 432 for data communications with other computers and with a data communications network. Such data communications may occur sequentially via an RS-232 connection, via an external bus such as a Universal Serial Bus ("USB"), via a data communications network such as an IP data communications network, or in any other manner or combination that would occur to one of ordinary skill in the art. The communications adapter provides a hardware level of data communications for one computer to send data communications directly to another computer or via a data communications network. Examples of communications adapters useful in a computer configured to verify the correctness of a leading zero counter according to certain embodiments include modems for wired dial-up communications, Ethernet (IEEE 802.3) adapters for wired data communications, and 802.11 adapters for wireless data communications.

[0022] For further explanation, FIG. 5 illustrates a flow chart of an example method for verifying the correctness of a leading zero counter according to some embodiments of the present disclosure. The method of FIG. 5 may be performed, for example, by the system 100 as shown in FIG. 1. The method of FIG. 5 includes generating 502 a first bit vector 108 (e.g., by the leading zero counter 102) based on an input value (e.g., the input 104) consisting of multiple digits. The first bit vector 108 includes a number of entries equal to the number of digits of the input 104, and each entry of the first bit vector 108 indicates whether the corresponding digit is all-zero. Thus, if an entry of the first bit vector 108 is equal to zero, the corresponding digit is zero. If an entry of the first bit vector 108 is one, the corresponding digit is not zero.

[0023] In some embodiments, the first bit vector 108 is calculated for each digit of the input 104 by applying a bitwise OR to the bits of that digit. Consider the example of a 128-bit hexadecimal input 104 shown in FIG. 2A. The leading zero counter 102 performs 32 4-bit OR operations, one for each of the 32 digits of the input 102. The result is the bit vector 108, with each entry of the bit vector 108 corresponding to the result of the bitwise OR operation of the corresponding digit. Continuing with the above example, as shown in FIG. 2B, the bit vector 108 now contains 32 entries corresponding to the 32 digits of the input 102. Each entry then contains the result of a 4-bit OR operation on the bits of the corresponding digit.

[0024] 5 also includes calculating 504 (e.g., by the leading zero counter 102) a leading zero count (e.g., LZ count 106) of the input value based on the first bit vector 108. As an example, the LZ count 106 of the input 104 is calculated by calculating the number of leading zeros in the first bit vector 108.

[0025] 5 also includes generating 506 (e.g., by the tester 110) a bit mask 112 that includes a number of 1's equal to the LZ count 106. For example, as shown in FIG. 3A, assuming the LZ count 106 is 4, the bit mask 112 includes four leading 1's and the remainder are 0's. The size of the bit mask 112 is equal to the number of digits in the input 102. For example, for a 32-digit input 102, the bit mask 112 includes 32 bits. In some embodiments, generating the bit mask 112 includes providing 508 the LZ count 106 to the half decoder 114.

[0026] The method of FIG. 5 also includes generating 510 (e.g., by tester 110) a second bit vector 118 that includes a one at the same index as the first occurring zero in bit mask 112. For example, looking at FIG. 3B, assuming a bit mask 112 with four leading ones, bit vector 118 would include four leading zeros and a one in the fifth entry. In some embodiments, tester 110 generates bit vector 118 by performing a bitwise exclusive-or (XOR) operation on each pair of bits in bit mask 112. For example, each entry of bit vector 118 is generated by feeding a corresponding entry of bit mask 112 and an entry that precedes the corresponding entry to a corresponding one of multiple XOR gates 116. Because the first entry of bit mask 112 does not have a preceding entry, the first entry of bit vector 118 may be generated by feeding a one to the first entry of bit mask 112.

[0027] 5 also includes validating 512 the LZ count 106 (e.g., by the tester 110) based on the first bit vector 108 and one or more of the bit mask 112 and the second bit vector 118. As described in more detail below, validating 512 the LZ count 106 may determine whether the LZ count 106 is too large based on the first bit vector 108 and the bit mask 112. As described in more detail below, validating 512 the LZ count 106 may determine whether the LZ count 106 is too small based on the first bit vector 108 and the second bit vector 118.

[0028] For further explanation, Figure 6 illustrates a flow chart of another example method for verifying the correctness of a leading zero counter according to some embodiments of the present disclosure. The method of Figure 6 is similar to Figure 5 in that it includes generating 502 a first bit vector 108 based on an input value (e.g., input 102) consisting of multiple digits, calculating 504 a leading zero count (e.g., LZ count 106) of the input value based on the first bit vector 108, providing 508 the LZ count 106 to a half decoder 114 to generate 506 a bit mask 112 that includes a number of leading ones equal to the LZ count 106, generating 510 a second bit vector 118 that includes a one at the same index as the first occurring zero in the bit mask 112, and verifying 512 the LZ count 106 based on the first bit vector 108 and one or more of the bit mask 112 and the second bit vector 118.

[0029] The method of Figure 6 differs from Figure 5 in that validating 512 the LZ count 106 based on the first bit vector 108 and one or more of the bit mask 112 and the second bit vector 118 includes determining 602 whether the LZ count 106 is too large by determining whether a bitwise AND applied to the first bit vector 108 and the bit mask 112 is all zero. If the result of the bitwise AND is all zero, then the LZ count 106 is not too large. If the result of the bitwise AND is not all zero, then the LZ count 106 is too large.

[0030] As an example, assume a bit vector 108 with four leading zeros, "00001101011...", and a correct LZ count 106, 4. Further assume a bit mask 112 with four leading ones, "11110000...", based on the LZ count 106. The result of the bitwise AND will equal all zeros, indicating that the result is not too large. Instead, assume the same bit vector 108, but with an LZ count 106 of 5, resulting in a bit mask of "11111000...". The result of this bitwise AND operation will be "00001000...". Because the result is not all zeros, this indicates that the LZ count 106 is too large.

[0031] By way of further explanation, Figure 7 illustrates a flowchart of another example method for verifying the correctness of a leading zero counter according to some embodiments of the present disclosure. The method of Figure 7 is similar to Figure 5 in that it includes generating 502 a first bit vector 108 based on an input value (e.g., input 102) consisting of multiple digits, calculating 504 a leading zero count (e.g., LZ count 106) of the input value based on the first bit vector 108, providing 508 the LZ count 106 to a half decoder 114 to generate 506 a bit mask 112 that includes a number of leading ones equal to the LZ count 106, generating 510 a second bit vector 118 that includes a one at the same index as the first occurring zero in the bit mask 112, and verifying 512 the LZ count 106 based on the first bit vector 108 and one or more of the bit mask 112 and the second bit vector 118.

[0032] The method of Figure 7 differs from Figure 5 in that validating 512 the LZ count 106 based on the first bit vector 108 and one or more of the bit mask 112 and the second bit vector 118 includes determining 702 whether the LZ count 106 is too small by determining whether a bitwise AND applied to the first bit vector 108 and the second bit vector 118 is not all zero. If the result of the bitwise AND is not all zero, then the LZ count 106 is not too small. If the result of the bitwise AND is all zero, then the LZ count 106 is too small.

[0033] For example, assume bit vector 108 is "00001101011...", which has four leading zeros, and the correct LZ count 106 is four. Further assume bit vector 114 is "000010000......". The bitwise AND of bit vector 108 and bit vector 114 is equal to "0000100000". Because the result is not all zeros, LZ count 106 is not too small. Instead, assume the same bit vector 108, but with an incorrect LZ count 106 of three, is given bit vector 114 "0001000......". The result of this bitwise AND operation is all zeros, indicating that LZ count 106 is too small.

[0034] In light of the above discussion, the reader will recognize that advantages of verifying the correctness of a leading zero counter in accordance with embodiments of the present invention include improved performance of a computing system by efficiently testing the correctness of a leading zero counter.

[0035] Exemplary embodiments of the present invention are described primarily in the context of a fully functional computer system for verifying the correctness of a leading zero counter. However, those skilled in the art will recognize that the present invention may also be embodied as a computer program product disposed on a computer readable storage medium for use with any suitable data processing system. Such a computer readable storage medium may be any storage medium for machine-readable information, including magnetic, optical, or other suitable media. Examples of such media include magnetic disks in hard drives or diskettes, compact disks for optical drives, magnetic tapes, and others that will occur to those skilled in the art. Those skilled in the art will immediately recognize that a computer system with suitable programming means is capable of executing the steps of the method of the present invention embodied in a computer program product. Those skilled in the art will also recognize that while some of the exemplary embodiments described herein are directed to software installed and executed on computer hardware, alternative embodiments implemented as firmware or as hardware are nevertheless within the scope of the present invention as well.

[0036] The present invention may be a system, method, and / or computer program product, which may include a computer-readable storage medium (or media) having computer-readable program instructions for causing a processor to perform aspects of the present invention.

[0037] A computer readable storage medium may be a tangible device capable of holding and storing instructions for use by an instruction execution device. A computer readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer readable storage media includes: portable computer diskettes, hard disks, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or grooved structures having instructions recorded thereon, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium should not be construed as a transitory signal itself, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable), or electrical signals transmitted over electrical wires.

[0038] The computer readable program instructions described herein may be downloaded from a computer readable storage medium to the respective computing / processing device or to an external computer or storage device via a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network may include copper transmission cables, optical transmission fiber, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface of each computing / processing device receives the computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device.

[0039] The computer readable program instructions for carrying out the operations of the present invention may be assembler instructions, instruction set architecture (ISA) instructions, machine language instructions, machine dependent instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including object oriented programming languages ​​such as Smalltalk®, C++, and traditional procedural programming languages ​​such as the “C” programming language, or similar programming languages. The computer readable program instructions may be executed entirely on the user's computer, partly on the user's computer as a standalone software package, partly on the user's computer and partly on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or wide area network (WAN), or the connection may be made to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) can execute computer readable program instructions to individualize the electronic circuitry by utilizing state information of the computer readable program instructions to perform aspects of the invention.

[0040] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer readable program instructions.

[0041] These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, executed by the processor of the computer or other programmable data processing apparatus, produce means for performing the functions / acts specified in one or more blocks of the flowchart illustrations and / or block diagrams. These computer readable program instructions may also be stored in a computer readable storage medium, such that the computer readable storage medium on which the instructions are stored comprises an article of manufacture including instructions implementing aspects of the functions / acts specified in one or more blocks of the flowchart illustrations and / or block diagrams, and can direct a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner.

[0042] The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause the computer, other programmable apparatus, or other device to perform a series of operable steps to create a computer-implemented process such that the instructions, which execute on the computer, other programmable apparatus, or other device, implement the functions / acts specified in one or more blocks of the flowchart illustrations and / or block diagrams.

[0043] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or part of an instruction, which includes one or more executable instructions for performing the specified logical function(s). In some alternative implementations, the functions described in the blocks may occur out of the order described in the figures. For example, two blocks shown in succession may in fact be executed substantially simultaneously, or the blocks may be executed in the reverse order, depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowchart illustrations, and combinations of blocks in the block diagrams and / or flowchart illustrations, may be implemented by a special-purpose hardware-based system that performs the specified functions or actions or executes a combination of special-purpose hardware and computer instructions.

[0044] From the foregoing description, it will be understood that modifications and changes can be made in various embodiments of the present invention without departing from the true spirit thereof. The description herein is for illustrative purposes only and is not to be construed in a limiting sense. The scope of the present invention is limited only by the language of the following claims.

Claims

1. 1. A method for verifying the correctness of a leading zero counter, the method comprising: generating a first bit vector based on an input value consisting of a plurality of digits, each entry of the first bit vector indicating whether a corresponding digit of the input value is equal to zero; calculating a leading zero count of the input value based on the first bit vector; generating a bit mask containing a number of leading ones equal to said leading zero count; generating a second bit vector that includes a one at an index that is the same as the first occurring zero in the bit mask; validating the leading zero count based on the first bit vector and one or more of the bit mask and the second bit vector; A method comprising:

2. 2. The method of claim 1, wherein each entry of the first bit vector is calculated based on a bitwise OR applied to each bit of the corresponding digit of the input value.

3. 2. The method of claim 1, wherein each digit is encoded using 4 bits.

4. 2. The method of claim 1, wherein generating the bit mask comprises providing the leading zero count to a half decoder.

5. 2. The method of claim 1, wherein generating the second bit vector comprises performing an exclusive-or (XOR) operation on each pair of bits of the bit mask.

6. 2. The method of claim 1, wherein validating the leading zero count comprises determining whether the leading zero count is too large by determining whether a bitwise AND of the first bit vector and the bit mask is all zero.

7. 2. The method of claim 1, wherein validating the leading zero count comprises determining whether the leading zero count is too low by determining whether a bitwise AND of the first bit vector and the second bit vector is not all zero.

8. 1. An apparatus for verifying the correctness of a leading zero counter, the apparatus comprising: receiving a first bit vector of an input value and a leading zero count of the input value based on the first bit vector, each entry of the first bit vector indicating whether a corresponding digit of the input value is equal to zero; generating a bit mask containing a number of leading ones equal to said leading zero count; generating a second bit vector that includes a one at an index that is the same as the first occurring zero in the bit mask; validating the leading zero count based on the first bit vector and one or more of the bit mask and the second bit vector; An apparatus configured to perform the steps including:

9. 9. The apparatus of claim 8, wherein each entry of the first bit vector is calculated based on a bitwise OR applied to each bit of the corresponding digit of the input value.

10. 9. The apparatus of claim 8, wherein each digit is encoded using 4 bits.

11. 9. The apparatus of claim 8, wherein generating the bit mask comprises providing the leading zero count to a half decoder.

12. 9. The apparatus of claim 8, wherein generating the second bit vector comprises performing an exclusive-or (XOR) operation on each pair of bits of the bit mask.

13. 9. The apparatus of claim 8, wherein validating the leading zero count comprises determining whether the leading zero count is too large by determining whether a bitwise AND of the first bit vector and the bit mask is all zeros.

14. 9. The apparatus of claim 8, wherein validating the leading zero count comprises determining whether the leading zero count is too low by determining whether a bitwise AND of the first bit vector and the second bit vector is not all zero.

15. 1. A system for verifying the correctness of a leading zero counter, comprising: generating a first bit vector based on an input value consisting of a plurality of digits, each entry of the first bit vector indicating whether a corresponding digit of the input value is equal to zero; calculating a leading zero count for the first bit vector; a leading zero counter configured to perform steps including: generating a bit mask containing a number of leading ones equal to said leading zero count; generating a second bit vector that includes a one at an index that is the same as the first occurring zero in the bit mask; validating the leading zero count based on the first bit vector and one or more of the bit mask and the second bit vector; a tester for said leading zero counter configured to perform steps including: A system comprising:

16. 16. The system of claim 15, wherein each entry of the first bit vector is calculated based on a bitwise OR applied to each bit of the corresponding digit of the input value.

17. 16. The system of claim 15, wherein generating the bit mask comprises providing the leading zero count to a half decoder.

18. 16. The system of claim 15, wherein generating the second bit vector comprises performing an exclusive-or (XOR) operation on each pair of bits of the bit mask.

19. 16. The system of claim 15, wherein validating the leading zero count comprises determining whether the leading zero count is too large by determining whether a bitwise AND of the first bit vector and the bit mask is all zeros.

20. 16. The system of claim 15, wherein validating the leading zero count comprises determining whether the leading zero count is too low by determining whether a bitwise AND of the first bit vector and the second bit vector is not all zero.

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