Dual Contacts and Power Rails for High Performance Standard Cells

Abstract

Standard cell layouts are disclosed that can be implemented in FinFET or nanosheet FET devices. The standard cell layouts include power connections from both top and bottom metal layers. Devices within the standard cells can be connected to both top and bottom metal layers. Various cell layouts can include control signal paths that go from a first device into the bottom layer and then under a second device. Various implementations of back and top side routing of bit and word lines in a memory array are also disclosed.

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE The embodiments described herein relate to semiconductor devices. More particularly, the embodiments described herein relate to layouts for making connections to transistors on a semiconductor substrate. [Background technology]

[0002] Standard cells are groups of transistors, passive structures, and interconnect structures that can provide logic functions, memory functions, etc. The current trend in standard cell methodology is to reduce the size of the standard cells while increasing the complexity (e.g., circuit density and number of components) within the standard cells. However, as standard cell designs become smaller, it becomes more difficult to provide access (e.g., connections) to the components within the standard cells.

[0003] Furthermore, the performance of a standard cell can become more affected by characteristics within the cell as the size of the standard cell decreases. For example, resistance within a standard cell, such as a metal trace or an interface between a diffusion region and a metal trace within the cell, can reduce the performance of the cell, and as cells become smaller, the impact on performance becomes more of an issue. Therefore, reducing the resistance within a standard cell can improve the performance of the cell. [Brief description of the drawings]

[0004] The features and advantages of the methods and apparatus of the embodiments described in this disclosure will be more fully understood by reference to the following detailed description of presently preferred, but nevertheless exemplary, embodiments in accordance with the embodiments described in this disclosure, taken in conjunction with the accompanying drawings, in which:

[0005] [Figure 1] 1 illustrates a top view of an embodiment of a standard cell having topside connections.

[0006] [Diagram 2] 2 illustrates a cross-sectional view of one embodiment of a standard cell along the cut line shown in FIG. 1.

[0007] [Diagram 3] FIG. 2 illustrates a bottom view of one embodiment of a standard cell with backside power connection.

[0008] [Figure 4] 4 illustrates a cross-sectional view of one embodiment of a standard cell along the cut line shown in FIG. 3.

[0009] [Diagram 5] 1 illustrates a bottom view of one embodiment of a standard cell having both topside and backside connections.

[0010] [Figure 6] 6 illustrates a cross-sectional view of one embodiment of a standard cell taken along section line 6-6 shown in FIG. 5.

[0011] [Figure 7] 7 illustrates a cross-sectional view of one embodiment of a standard cell taken along section line 7-7 shown in FIG. 5.

[0012] [Figure 8] 1 illustrates a cross-sectional view of one embodiment of a system having two standard cells with via programming.

[0013] [Figure 9] 1 illustrates a bottom view of one embodiment of a cell with both topside and backside power connections along with backside signal routing connections.

[0014] [Figure 10] 1 illustrates a bottom view of a layout according to some embodiments.

[0015] [Figure 11] 1 illustrates a top view of a layout according to some embodiments.

[0016] [Figure 11] 1 illustrates a top view of a layout according to some embodiments.

[0017] [Figure 12] 12 illustrates a cross-sectional view of one embodiment of a layout along section line 12-12 of FIGS. 10 and 11, according to some embodiments.

[0018] [Figure 13] 13 illustrates a cross-sectional view of one embodiment of a layout along section line 13-13 of FIGS. 10 and 11, according to some embodiments.

[0019] [Figure 14] 14 illustrates a cross-sectional view of one embodiment of a layout along section line 14-14 of FIGS. 10 and 11, according to some embodiments.

[0020] [Figure 15] 1 illustrates a top view of a memory array showing bit cells and bit lines according to some embodiments.

[0021] [Figure 16] 1 illustrates a top view of a memory array with single-ended bitlines in the bitcells according to some embodiments.

[0022] [Figure 17] 1 illustrates a top view of a memory array showing bit cells and word lines according to some embodiments.

[0023] [Figure 18] 1 illustrates a top view of a memory array having both bit and word lines in top and bottom metal layers according to some embodiments.

[0024] [Figure 19] 1 illustrates a top view of a large memory megacell that replaces two smaller memory megacells according to some embodiments.

[0025] [Figure 20] 1 illustrates a top view of a tall memory megacell that replaces a wide memory megacell according to some embodiments.

[0026] [Figure 21] 1 illustrates a top view of a memory array with hierarchical bitlines according to some embodiments.

[0027] [Figure 22] FIG. 1 is a block diagram of one embodiment of an exemplary system.

[0028] While the embodiments disclosed herein are susceptible to various modifications and alternative forms, specific embodiments have been shown in the drawings and are described in detail herein for purposes of illustration. It should be understood, however, that the drawings and detailed description are not intended to limit the scope of the claims to the particular forms disclosed. On the contrary, the application is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure of the present application, as defined by the appended claims. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] The present disclosure is directed to the use of backside metal layers to provide power and / or control signal connections to transistors in integrated circuit cells (such as standard cells). As used herein, the term "standard cell" refers to a group of transistor, passive, and interconnect structures formed on a substrate to provide logic or memory functions that are standard for various implementations. Integrated circuit cells may also include custom circuit design cells that are individually designed for a particular implementation. Many current designs of cells provide connections and routing for power or signals to transistors (or other structures) on transistors. For example, connections and routing for power or signals may be provided in an upper layer of a device (e.g., a layer above an active layer of a transistor in a device as viewed in a typical cross-sectional view). As used herein, the term "upper side" refers to a region in a device that is vertically above an active layer of a device (e.g., above a transistor region of a device). For example, the upper side may refer to a component such as a contact or layer that is above a transistor region in the vertical dimension as shown in the figures and described herein. In some cases, the term "front side" may be used interchangeably with the term "upper side".

[0030] 1 shows a top view of one embodiment of a standard cell 100 having topside connections. For ease of illustration, the representation of the cell disclosed herein shows only those components relevant to the present disclosure. Those skilled in the art will understand that additional components may be present in any of the cells shown herein.

[0031] In the illustrated embodiment of FIG. 1, standard cell 100 includes gate 102, device 104, source / drain contacts 106, and metal layer 108. Gate 102 (e.g., gates 102A, 102B, 102C) may be polylines (e.g., polysilicon layers or metal layers). In various embodiments, the gate illustrations in this disclosure include gate spacers 103. Device 104 may be a transistor, such as, for example, a FinFET device, a Nanosheet FET (NSH) device, or a GAAFET ("Gate All Around" FET) device. Other embodiments of transistor devices may be contemplated. In various embodiments, contacts 106 or vias 107 provide connections between device 104 and metal layer 108. Metal layer 108 may include one or more metal layers with contacts 106 and vias 107 providing various connections to different metal layers in embodiments having multiple metal layers. For example, contacts 106 can provide a connection between a region within device 104 (e.g., a source / drain region within the device) and a first metal layer (e.g., a ground metal layer), and vias 107 provide a connection between a region within the device and another higher metal layer (e.g., a layer above the first metal layer). In a particular embodiment, metal layer 108 provides routing from device 104 to Vdd (e.g., a supply voltage) and Vss (e.g., ground). Metal layer 108 may also provide routing for connections to control signals to / from device 104, as described herein.

[0032] FIG. 2 illustrates a cross-sectional view of an embodiment of a standard cell 100 along the cut line shown in FIG. 1, according to some embodiments. In the illustrated embodiment, the standard cell 100 includes a substrate 200 having an insulating layer 202 formed on the gate 102. In some embodiments, the gate 102B is an active gate, and the gates 102A and 102C are isolation gates on either side of the active gate, as shown in FIG. 2. In a particular embodiment, the substrate 200 is a silicon substrate, and the insulating layer 202 is an oxide layer. In various embodiments, the substrate 200 may include additional components or features for implementation in the device 104. For example, the substrate 200 may include an insulating layer, a diffusion (e.g., oxide diffusion) region, or a doped region for implementation in the device 104.

[0033] For ease of illustration, the substrate 200 and the insulating layer 202 are shown as a single layer. In some embodiments, the insulating layer 202 includes one or more insulating layers formed on a substrate. For example, the substrate 200 may be a silicon substrate with one or more oxide layers formed on the substrate. The insulating layer 202 may include a single insulating layer or multiple insulating layers. For example, the insulating layer 202 may include multiple oxide layers. In various embodiments, the insulating layer 202 at least partially surrounds or encapsulates regions of the device 104 (e.g., the gate 102, the source / drain regions 204, the contacts 106, etc.).

[0034] 2, the source / drain region 204 of the device 104 is disposed above a substrate 200 in the standard cell 100. The source / drain region 204 may be, for example, a fin or a nanosheet stack in a FinFET or NSH device. Various embodiments may also be contemplated in which the source / drain region 204 is in the substrate 200 or a portion of the source / drain region is in the substrate.

[0035] As shown in FIG. 2, contact 106, via 107, and metal layer 108 are in the upper layer of device 104 above source / drain region 204 and gate 102. In various embodiments, via 107 provides a signal connection to source / drain region 204A, and contact 106 provides a power signal connection to source / drain region 204B. For example, in the embodiment shown in FIGS. 1 and 2, contact 106B connects source / drain region 204B to Vdd via routing in metal layer 108 (note that contact 106B extends horizontally from device 104 to the portion of metal layer 108 that is tied to Vdd, as shown in FIG. 1), and via 107 connects source / drain region 204A to signal routing in metal layer 108 (via contact 106A). Thus, metal layer 108 may include routing for both power and control signal connections. As shown in Figures 1 and 2, providing connections and routing for both power and control signals above the device 104 using contacts 106 and vias 107 may have an area cost above the device within the standard cell 100.

[0036] Some contemplated embodiments for the design of standard cells move connections and routing for power connections to metal layers below the transistors. For example, connections and routing for power may be provided in a backside layer of the device (e.g., a layer below the active layer of the transistors in the device when viewed in a typical cross-sectional view). As used herein, the term "backside" refers to an area in the device that is vertically below the active layer of the device (e.g., below the transistor region of the device). For example, the backside may refer to components such as contacts or layers that are below the transistor region in the vertical dimension as shown in the figures and described herein. It should be noted that as used herein, backside elements disposed below the active layer may be located on, in, or below the silicon substrate on which the active layer is fabricated. That is, as used herein, "backside" is relative to the active layer and not the silicon substrate.

[0037] 3 shows a bottom view of one embodiment of a standard cell 300 with backside layer power connections. In the illustrated embodiment of FIG. 3, the standard cell 300 includes a gate 302, a device 304, a backside via 306, and a backside metal layer 308. The gate 302 and the device 304 may be substantially similar to the gate 102 and the device 104 shown in FIG. 1. The via 306 provides a connection between the device 304 (e.g., a source / drain region in the device) and the backside metal layer 308. The backside metal layer 308 may include one or more metal layers that provide power routing from the device 304 to Vdd (e.g., a supply voltage) and Vss (e.g., ground).

[0038] FIG. 4 illustrates a cross-sectional view of an embodiment of a standard cell 300 along the cut line shown in FIG. 3, according to some embodiments. In the illustrated embodiment, the standard cell 300 includes a substrate 200 having a gate 302, a gate spacer 303, and a source / drain region 404 formed in a device 304. As shown in FIG. 4, the source / drain region 404 of the device 304 is disposed above the substrate 200 and below the insulating layer 202 in the device. The source / drain region 404 may be, for example, a fin or a nanosheet stack in a FinFET, NSH, or GAAFET device. A power connection to the source / drain region 404B is made by a backside via 306 from a backside metal layer 308. Thus, in the illustrated embodiment of FIG. 4, the backside via 306 routes from the source / drain region 404B to the backside metal layer 308, which replaces the power routing in the metal layer 108 to provide a power connection to the device 304.

[0039] As shown in FIG. 4 , the backside via 306 and the backside metal layer 308 are disposed below the device 304 (e.g., in a backside layer of the device below the source / drain region 404). In certain embodiments, the backside via 306 comprises a buried via through the substrate 200 to connect between the source / drain region 404 and the backside metal layer 308. In some embodiments, as shown in the illustrated embodiment, the backside metal layer 308 is formed at or near the bottom surface of the substrate 200. In certain embodiments, the backside metal layer 308 is one or more backside layers of an active layer of the device 304 (e.g., the backside metal layer 308 is vertically below the transistor region of the device 304). In some embodiments, the backside metal layer 308 is one or more buried layers within the substrate 200 (e.g., a metal layer is buried or embedded below the bottom surface of the substrate). In some embodiments, the backside metal layer 308 is buried below a carrier substrate layer (e.g., a silicon carrier substrate). Additional embodiments may be contemplated in which the backside metal layer 308 is not disposed within the substrate 200 .

[0040] As shown in Figures 3 and 4, by moving the power connections to the source / drain regions 404 underneath the device 304, the available area on the device is increased. Note that the contacts 106 and metal layer 108 are shown above the source / drain regions 404 in the device 304 in Figure 4 because the upper metal layer may be utilized for other connections (e.g., control signal connections) within the standard cell 300. For example, in some embodiments, the power connections to the source / drain regions 404B may be made using the backside vias 306 and the backside metal layer 108, while the control signal connections to the source / drain regions 404A are made using the contacts 106A to the metal layer 308. In some embodiments, the space for the contacts 106 above the source / drain regions 404B may be left empty to increase the available area on the source / drain regions and the device 304. This empty area may be left empty or may be used for routing other resources (such as additional contacts for control signals or contacts for other signals).

[0041] 3 and 4 may improve area utilization within a cell layout, as discussed above. However, interface resistance within the cell (e.g., resistance at the interface between source / drain regions 404 and backside vias 306) may present a problem within the cell, especially as the size of the cell decreases. This disclosure recognizes that redundant power connections may be made above and below the device to reduce interface resistance in the standard cell layout.

[0042] Certain embodiments disclosed herein have three broad elements: 1) a transistor having a gate region, a source region, and a drain region, the transistor being disposed above the substrate in a vertical dimension perpendicular to the substrate; 2) a first metal layer disposed above the transistor in the vertical dimension (e.g., above the transistor); and 3) a second metal layer disposed below the transistor in the vertical dimension (e.g., behind the transistor). In some embodiments, one or more rails (such as a power rail) are connected to both the first metal layer and the second metal layer. For example, both a supply voltage rail and a ground rail may be connected to both the first metal layer and the second metal layer (the metal layers have separate routing for supply voltage and ground). In certain embodiments, either the source region or the drain region of the transistor is connected to both the first metal layer and the second metal layer. Connecting the source / drain region to both the first metal layer and the second metal layer provides a redundant connection between the source / drain region and the supply voltage rail, the ground rail, or both rails.

[0043] In a particular embodiment, the source region is connected to a supply voltage rail and the drain region is connected to a ground rail through both the first metal layer and the second metal layer. For example, the source region is connected to a supply voltage routing in both the first metal layer and the second metal layer, the routing in both metal layers connecting to the supply voltage rail. Similarly, the drain region is connected to a ground routing in both the first metal layer and the second metal layer, the routing in both metal layers connecting to the ground rail.

[0044] In various embodiments, the rails connected to the first and second metal layers may be signal rails. For example, embodiments may be contemplated in which the rails provide bitcell signals. Providing redundant signal connections between source / drain regions and signal rails may allow signals to escape the device with less resistance than a single connection. In some embodiments, source or drain regions from adjacent devices (e.g., adjacent transistors) may be selectively connected to the first or second metal layers. For example, via programming may be implemented in a multi-transistor layout to alternate connections from source / drain regions between the first and second metal layers in alternating transistors.

[0045] In short, the inventors have recognized that by providing connections to devices both above and below the device in the cell layout, the performance of the cell is improved. By providing redundant connections above and below the device, the interface resistance within the cell is reduced. For example, the interface resistance between the diffusion region and the metal within the cell is reduced using redundant connections, thereby improving the performance of the cell. The inventors have also recognized that while providing redundant connections above and below the device has an area cost for the connections above the device, the reduction in the interface resistance within the cell still improves the performance of the cell relative to a cell having connections only below the device (as shown in Figures 3 and 4). Furthermore, the redundant connections can reduce the interface resistance within the cell and improve the performance of the cell without having to increase the size of the cell or provide extra power to the cell.

[0046] FIG. 5 illustrates a bottom view of one embodiment of a standard cell 500 having both top and backside power connections. In the illustrated embodiment, the standard cell 500 includes a gate 502 and a device 504. The gate 502 and device 504 may be similar to other embodiments described herein. In a particular embodiment, the gate 502 is a polyline formed from a polysilicon or metal layer, and the device 504 is a transistor (e.g., a FinFET device or a nanosheet FET device). The standard cell 500 includes both a top (source / drain) contact 506 and a top via 507 to a top metal layer 508 and a backside via 510 to a backside metal layer 512. Note that while the top via 507 is shown in FIG. 5, the top via is typically hidden by the top contact 506 in the bottom view. In some embodiments, the top contact 506 provides a control signal connection between the device 504 and the top metal layer 508, and the top via 507 and the backside via 510 provide a power connection from the device to the top metal layer 508 and the backside metal layer 512, respectively.

[0047] In a particular embodiment, the power routing in the top metal layer 508 and the power routing in the back metal layer 512 are coupled to rails 514 and 516. In the illustrated embodiment, rail 514 is a supply voltage rail and rail 516 is a ground rail for the power supply coupled to the rail. Other embodiments in which rail 514 and rail 516 are coupled to different power supplies or carry different potentials may also be contemplated. In various embodiments, top metal layer portion 508A and back metal layer portion 512A provide routing from device 504 to Vdd (e.g., a supply voltage). Similarly, top metal layer portion 508B and back metal layer portion 512B provide routing from device 504 to Vss (e.g., a ground voltage). It should be noted that rails 514 and 516 and the coupling to / from the rails are shown diagrammatically in the illustrated embodiment, and the actual implementation of the rails and the coupling to / from the rails may be done through various designs based on the desired functionality for standard cell 500. Additionally, although top side vias 507 and back side vias 510 are shown in FIG. 5 as not overlapping vertically, various embodiments may be contemplated in which there is partial or complete overlap between the top side vias and back side vias in the vertical direction.

[0048] As shown in FIG. 5, the device 504 is connected to rails 514 and 516 using both the top metal layer 508 and the back metal layer 512. FIG. 6 shows a cross-sectional view of an embodiment of a standard cell 500 along section line 6-6 shown in FIG. 5. In the illustrated embodiment, the standard cell 500 includes a substrate 200 having a gate 502, a gate spacer 503, and a source / drain region 604 formed on the substrate. The source / drain region 604 is a source / drain region of the device 504. The source / drain region 604 may be, for example, a fin or a nanosheet stack in a FinFET or NSH device. In a particular embodiment, the top contact 506A couples to the source / drain region 604A, and the top contact 506B and the top via 507 couple the source / drain region 604B to the top metal layer 508. In some embodiments, as described herein, the upper contact 506B and the upper via 507 connect the source / drain region 604B to power routing in the upper metal layer 508 (e.g., to rail 514 or rail 516), and the upper contact 506A provides signal routing to the source / drain region 604A (e.g., via connected control signal routing in the upper metal layer 508). For example, in the embodiment shown in Figures 5 and 6, the upper contact 506B and the upper via 507 connect the source / drain region 604B to the upper metal layer portion 508A for routing to rail 514 and Vdd. As shown in Figure 6, there is no connection (e.g., via or contact) between the source / drain region 604 and the backside metal layer 512 along the path of cut line 6-6 in Figure 5.

[0049] FIG. 7 illustrates a cross-sectional view of an embodiment of the standard cell 500 along section line 7-7 shown in FIG. 5. In the illustrated embodiment, the backside via 510 and the backside metal layer 512 are disposed below the source / drain region 604 of the device 504 (e.g., within the backside layer of the device). In a particular embodiment, the backside via 510 is a buried via through the substrate 200 to connect the source / drain region 604B to the backside metal layer 512. In various embodiments, the backside metal layer 512 is formed at or near the bottom surface of the substrate 200, as shown in FIG. 7 and described herein. In some embodiments, the backside metal layer 512 is a buried layer within the substrate 200 (e.g., a metal layer is buried or embedded below the bottom surface of the substrate). Additional embodiments may be contemplated in which the backside metal layer 512 is not disposed within the substrate 200.

[0050] In a particular embodiment, the backside via 510 connects the source / drain region 604B to power routing in the backside metal layer 512 (e.g., routing to rail 514 or rail 516). For example, in the embodiment shown in Figures 5 and 7, the backside via 510 connects the source / drain region 604B to the backside metal layer portion 512A for routing to rail 514 and Vdd. As shown in Figure 7, there is no vertical connection (e.g., via) between the source / drain regions 604A, 604B and the top metal layer 508 along the path of cut line 7-7 in Figure 5.

[0051] In various embodiments, as shown in FIGS. 5-7, standard cell 500 includes power connections between device 504 and rails 514 and 516 using connections both above and below the device in the standard cell (e.g., both the top and bottom layers of the device). For example, rail 514 is connected to source / drain region 604B through both top via 507 and top metal layer portion 508A and backside via 510 and backside metal layer portion 512A. Providing power connections both above and below device 504 may reduce interface resistance between diffusion regions (e.g., source / drain region 604B) and metal layers (e.g., top via 507 and backside via 510) in standard cell 500. For example, interface resistance is reduced by using connections to rails 514 and 516 from both above and below device 504 to increase the connection area between the diffusion regions and metal layers, reducing resistance in the path between the rails and the device. In some embodiments, the interface resistance in standard cell 500 is reduced to approximately half of the interface resistance in either standard cell 100 or standard cell 300 because standard cell 500 doubles the number of power connections to rails 514 and 516.

[0052] Providing redundant power connections above and below device 504 in standard cell 300 may have an increased area cost compared to standard cell 500 due to the connections above the device. However, the reduction in interface resistance in standard cell 500 improves the performance of standard cell 500 compared to standard cell 300. For example, standard cell 500 may have about a 5% or greater improvement in performance over standard cell 300. Furthermore, standard cell 500 has better performance over standard cell 100 while having the same area cost. Thus, standard cell 500 can have improved performance without having to increase the size of the cell or provide extra power to the cell.

[0053] In some embodiments, the properties of the metal in the top via 507 and top metal layer 508 versus the metal in the backside via 510 and backside metal layer 512 are used in controlling the properties of the power source supplying power to the device 504. For example, the resistance of the metal in the top via 507 and top metal layer 508 can be characterized relative to the resistance of the metal in the backside via 510 and backside metal layer 512 to determine the relative proportions of power supplied through the top and backside metal layers. The power source supplying power to the standard cell 500 can then be controlled using programming or modeling based on the relative proportions. In some embodiments, one or more tie cells can be coupled to the top and backside metal layers to couple the top and backside metal layers together.

[0054] In some embodiments, a power supply may be connected to the top and bottom metal layers without programming or modeling, such that the power supply distributes power to the top and bottom metal layers based on their relative resistance. In such embodiments, the mismatch between the resistance in the top and bottom metal layers may be small. Small differences may be within acceptable limits such that programming or modeling of the power supply is not required. For example, the difference in voltage on the top and bottom metal layers may be on the order of a few millivolts.

[0055] In some embodiments, the standard cell 500 may be implemented in multiple standard cells with via programming between the cells. Figure 8 illustrates a cross-sectional view of one embodiment of a system having two standard cells 500 with via programming. The system 800 includes a first standard cell 500A and a second standard cell 500B. Although two standard cells are shown, it should be understood that the system 800 may include multiple alternating standard cells similar to the first standard cell 500A and the second standard cell 500B.

[0056] The system 800 can include routing between two voltage sources Vdd1 and Vdd2 to the first and second standard cells 500A and 500B. In the illustrated embodiment, Vdd1 is routed to the back metal layer 512 in the first standard cell 500A, and Vdd2 is routed to the top metal layer 508 in the second standard cell 500B. Via programming is implemented in the system 800 to alternate connections to Vdd1 and Vdd2 in the first and second standard cells 500A and 500B.

[0057] For example, as shown in Fig. 8, in the first standard cell 500A, there is no connection (no contact vias) between the top metal layer 508 (routed to Vdd2) and the source / drain regions 604A, 604B, but there is a connection between the backside metal layer 512 (routed to Vdd1) and the source / drain regions 604B using the backside via 510. Conversely, in the second standard cell 500B, there is a connection by the via 507 between the top metal layer 508 (routed to Vdd2) and the source / drain regions 604B, but there is no connection between the backside metal layer 512 (routed to Vdd1) and the source / drain regions 604A, 604B. Thus, the first standard cell 500A receives Vdd1 and the second standard cell 500B receives Vdd2 based on programming determined by the presence or absence of contact vias in the standard cells.

[0058] 5-8 provide reduced interface resistance for power connections by having connections both above and below device 504. Various embodiments may also be contemplated to provide signal (e.g., control signal) connections for both the top and bottom gates of a transistor device (such as device 504), potentially providing additional benefits for signal transmission within a cell (such as standard cell 500). For example, providing additional signal connections or routing through a cell may reduce RC delays that typically result from resistance in via connections in the upper layers of the cell.

[0059] However, providing a signal connection to the gate in a backside metal layer (e.g., a backside via 510 connection to the backside metal layer 512) can be unreliable and difficult or expensive to implement. For example, placing the signal connection to the gate in a backside layer can place the signal and power connections in close proximity, thereby causing parasitic problems that reduce device reliability. Furthermore, forming the signal connection to the gate in the backside layer can require a highly controlled process to allow for the signal and power connections to be placed in close proximity, thereby increasing costs and reducing device yield. The present disclosure contemplates providing a routing path for the signal connection in the backside layer to reduce resistance in transmitting the signal without requiring a backside layer connection to the gate in close proximity to the power connection. The disclosed techniques can improve the performance of an integrated circuit cell over previous cell layouts such as those shown in FIGS. 1-4 by reducing the RC delay within the cell.

[0060] Certain embodiments disclosed herein have three broad elements: 1) a first transistor and a second transistor disposed in a transistor region of an integrated circuit; 2) a via structure on the side of the first transistor opposite the second transistor; and 3) a control signal routed from the second transistor to the first transistor, from the second transistor into the back metal layer, through the via structure to the top metal layer, through the top metal layer to the gate of the first transistor. In certain embodiments, the control signal path passes under the first transistor in the back metal layer. In some embodiments, the control signal path passes between a signal output of the second transistor and a signal input of the first transistor.

[0061] In various embodiments, the via structures include inactive (e.g., "dummy") source / drain regions and one or more vias that connect the backside metal layer to the top metal layer. In some embodiments, two or more via structures are implemented to transmit control signals between the backside metal layer and the top metal layer. The two or more via structures can transmit control signals in parallel between the backside metal layer and the top metal layer. The via structures can then be connected (e.g., "shorted") to each other within the metal layers to transmit the control signals.

[0062] In essence, the inventors have recognized that by using a via structure on the opposite side of the transistor from the connecting transistor, it is possible to provide a routing connection for a control signal through a back layer without providing an additional gate connection on the back layer. The via structure may be, for example, an inactive (e.g., "dummy") transistor. Providing a routing connection through a via structure, through the back layer, underneath the transistor, provides a control signal path, in addition to other paths, to reduce RC delays in signal transmission. Although the addition of such a via structure may have an area cost, the improvement in performance of the cell with the control signal routed through the via structure may provide a substantial return in signal transmission worth the area cost.

[0063] FIG. 9 shows a bottom view of one embodiment of a cell 900 with both topside and backside power connections along with backside signal routing connections. The cell 900 may be, for example, a standard cell or a custom circuit design cell. In the illustrated embodiment, the cell 900 includes a gate 902 and a device 904. The gate 902 and device 904 may be similar to other embodiments of gates and devices described herein. In a particular embodiment, the gate 902 is a polyline formed from a polysilicon or metal layer, and the device 904 is a transistor (e.g., a FinFET device, a nanosheet FET device, or a GAAFET device). The device 904 also includes both a topside (source / drain) power contact 906, an topside via 907 to a topside metal layer 908, and a backside via 910 to a backside metal layer 912. Topside vias 907 provide power connections (eg, Vdd / Vss connections) between the devices 904 and a topside metal layer 908 , while backside vias 910 provide power connections between the devices and a backside metal layer 912 .

[0064] As described herein, the top metal layer 908 and the back metal layer 912 may be coupled to power rails to provide power connections to the device 904. For example, the top metal layer portion 908A and the back metal layer portion 912A may provide routing from the device 904 to Vdd (e.g., a supply voltage), and the top metal layer portion 908B and the back metal layer portion 912B provide routing from the device 904 to Vss (e.g., a ground voltage). For simplicity of illustration, power rails are not shown in the embodiment of cell 900 of FIG.

[0065] In particular embodiments, the back metal layer 912 includes a back metal layer portion 912C. The back metal layer portion 912C may be implemented to provide a routing connection for control signals through the cell 900 as described herein. The back metal layer portion 912C may be in the same back metal layer as the back metal layer portions 912A and 912B, or may be in a different back metal layer. In various embodiments, the back metal layer portion 912C includes the first back metal layer or the second back metal layer.

[0066] As shown in FIG. 9, the backside via 910 does not contact the backside metal layer portion 912C to avoid shorts between power and signal connections routed through the backside metal layer 912. As discussed above, locating a gate connection in the backside metal layer 912 can be difficult, unreliable, and expensive given the power connections in the backside metal layer (e.g., the backside via 910 and the backside metal layer portions 912A and 912B). Thus, the present disclosure contemplates providing a routing connection through the backside metal layer portion 912C without providing a connection through the backside via 910 under (e.g., in a vertical region of) the device 904. In various embodiments, as shown in FIGS. 10-13, a "dummy" cell can be placed adjacent to the cell 900 to provide routing for control signals.

[0067] FIG. 10 illustrates a bottom view of a layout 1000 according to some embodiments. In the illustrated embodiment, the layout 1000 includes a cell 1001. The cell 1001 includes an inactive ("dummy") gate 1002 with via structures 1010A, 1010B, 1010C disposed between the inactive gates to form an inactive ("dummy") device 1004. In various embodiments, the cell 1001 may be disposed adjacent to an active cell and gate (e.g., cell 900 and gate 902A shown in FIG. 9). In a particular embodiment, the cell 1001 is a unique cell included adjacent to an end of an active cell (e.g., an end of the cell layout) or another signal end point in the cell layout. The cell 1001 includes paths for extensions of three backside metal layer portions 912A, 912B, 912C. In particular embodiments, the extension for backside metal layer portion 912C provides a routing path for control signals associated with an active cell (e.g., device 904). It should be understood that each of metal layer portions 912A, 912B, 912C may be disposed in a single backside metal layer, different backside metal layers, or a combination of backside metal layers.

[0068] In a particular embodiment, the cell 1001 includes one or more via structures 1010. In the illustrated embodiment, the cell 1001 includes three via structures 1010A, 1010B, 1010C, although any number of via structures 1010 may be contemplated. As described herein, the via structures 1010 may include backside vias 910, topside vias 907 (shown in FIG. 11), and inactive (e.g., “dummy”) and source / drain regions 1214 (shown in FIGS. 12 and 13) that connect the backside metal layer portion 912C to the top metal layer 908. The backside vias 910A, 910B, 910C provide connections between the source / drain regions (e.g., source / drain regions 1214 shown in FIGS. 12 and 13) of the device 1004 and the backside metal layer portion 912C.

[0069] FIG. 11 illustrates a top view of a layout 1000, according to some embodiments. In the illustrated embodiment, the via structure 1010 includes upper vias 907A, 907B, 907C that connect source / drain regions of the device 1004 (e.g., source / drain regions 1214 shown in FIGS. 12 and 13) to the upper metal layer portion 908C. In some embodiments, the upper metal layer portion 908C includes multiple portions (e.g., paths). These multiple paths can be connected (e.g., shorted) to each other to provide a connection between the upper via 907 and the active cell, as shown diagrammatically in FIG. 11. For example, a gate via can connect the upper metal layer portion 908C to a gate in the active cell (such as the gate 902 in FIG. 9). In some embodiments, the upper metal layer portion 908C is disposed in a first metal layer in the upper metal layer 908, although other metal layers may be implemented.

[0070] In the embodiment shown in Figures 10 and 11, the top metal layer portions 908A, 908B and the back metal layer portions 912A, 912B are not connected to any portion of the device 1004 in the cell 1001. For example, there are no top vias 907 or back vias 910 connecting source / drain regions in the device 1004 (e.g., source / drain regions 1214 shown in Figures 12 and 13) to the top metal layer portions 908A, 908B or back metal layer portions 912A, 912B. Without these connections, no power connections are provided to the device 1004, and the device 1004 is an inactive (e.g., "dummy") device. When the device 1004 is inactive, the control signal path (e.g., the control signal path 1220 shown in Figures 12 and 13) can pass through the device 1004 without any interference from the power signals.

[0071] FIG. 12 illustrates a cross-sectional view of one embodiment of a layout 1000 along section line 12-12 of FIGS. 10 and 11, according to some embodiments. In the illustrated embodiment, a path (dotted line) of a control signal path 1200 is shown between source / drain regions 1214A, 1214C and an active cell. The control signal path 1200 goes, for example, from source / drain regions 1214A and 1214C through contacts 906 and upper vias 907A and 907C to upper metal layer portion 908C, which then routes to the active cell. In the cross-section of cell 1001 illustrated in FIG. 12, via structures 1010A and 1010C provide a path for the control signal path 1200 to upper metal layer portion 908C above backside metal layer portion 912A (including power routing). Backside vias 910A, 910C are also located along the cross-section illustrated in FIG. 12. However, it should be noted that the backside vias 910A, 910C in the via structures 1010A, 1010C, respectively (as also shown in FIG. 10) provide a connection path to the backside metal layer portion 912C, not the backside metal layer portion 912A. Thus, in the illustrated embodiment of FIG. 12, the control signal path 1200 has a path from the source / drain regions 1214A, 1214C to the backside vias 910A, 910C and then to the backside metal layer portion 912C (which then routes to the active cell), but the backside vias 910A, 910C are not connected to the backside metal layer portion 912A. Thus, as shown in FIG. 12, the control signal path 1200 has a path between the upper layer metal layer portion 908C and the backside metal layer portion 912C through both the source / drain regions 1214A and the source / drain regions 1214C.

[0072] Various embodiments of metal routing between the backside vias 910A, 910C and the backside metal layer portion 912C may be contemplated. The metal routing may include, for example, any combination of metal vias, metal wires, metal traces, etc. that provide a path / route between the two structures. For example, in one embodiment, the backside vias 910A, 910C may extend vertically down into the substrate 200 from the source / drain regions 1214A, 1214C, respectively (as shown in FIG. 12), with additional metal routing connecting the backside vias to the backside metal layer portion 912C.

[0073] FIG. 13 illustrates a cross-sectional view of one embodiment of a layout 1000 along section line 13-13 of FIGS. 10 and 11, according to some embodiments. In the cross-section of cell 1001 illustrated in FIG. 13, via structure 1010B provides a path for control signal path 1200 between source / drain region 912C and backside metal layer portion 1214B. Similar to the cross-section of FIG. 12, in the cross-section of FIG. 13, backside metal layer portion 912B (e.g., power routing) is located under transistor region 1230. However, backside via 910B in via structure 1010B (also illustrated in FIG. 10) provides a connection path for source / drain region 1214B to backside metal layer portion 912C instead of backside metal layer portion 912B. Thus, control signal path 1200 proceeds from source / drain region 1214B through backside via 910B to backside metal layer portion 912C (which then routes to the active cell). As discussed above, various embodiments of metal routing between the bottom of the backside via 910B and the backside metal layer portion 912C may be contemplated. For example, in one embodiment, the backside via 910B extends vertically into the substrate 200, with additional metal routing connecting the backside via to the backside metal layer portion 912C.

[0074] FIG. 14 illustrates a cross-sectional view of one embodiment of a layout 1000 along section line 14-14 of FIGS. 10 and 11, according to some embodiments. In the cross-section of cell 1001 shown in FIG. 14, via structures 1010A, 1010B, and 1010C provide a path for the control signal path 1200 between source / drain regions 1214A, 1214B, 1214C and the active cells through backside metal layer portion 912C. In the illustrated embodiment of the cross-section, backside metal layer portion 912C is disposed below transistor region 1230 in device 1004. Thus, backside vias 910A, 910B, 910C in via structures 1010A, 1010B, 1010C provide direct downward connections into backside metal layer portion 912C for source / drain regions 1214A, 1214B, 1214C, respectively. The control signal path 1200 then runs from the source / drain regions 1214A, 1214B, 1214C to the backside metal layer portion 912C and then to the active cell.

[0075] In the exemplary embodiment of Figures 12-14, the device 1004 is formed in a transistor region 1230 of the cell 1001. The transistor region 1230 includes structures that are typically implemented in the active layer of the device (such as an adjacent active cell). For example, the transistor region 1230 may include the gate 1002, gate spacer 1003, and source / drain regions 1214 found in the active layer of a transistor device. The source / drain regions 1214 may be doped regions of the device 1004 that form, for example, a fin or nanosheet stack in a FinFET or NSH device.

[0076] As discussed above, in cell 1001, gate 1002 and source / drain region 1214 are not connected to any power supplies, and thus transistor region 1230 of device 1004 may be considered an inactive (e.g., "dummy") transistor region. Because transistor region 1230 of device 1004 is inactive, source / drain region 1214 may be implemented within control signal path 1200, as shown in FIGS. 12-14. Thus, as shown in the illustrated embodiment, control signal path 1200 may provide a path between the source / drain region and gate of an active cell, including a path through backside metal layer portion 912C, via structure 1010 (e.g., backside via 910, source / drain region 1214, and via 907), and top metal layer portion 908C.

[0077] In a typical cell layout, routing from the output of an active cell device (e.g., device 904 shown in FIG. 9 has an output at gate 902A) goes from the gate, through top metal layer 908, to the input of a source / drain region in the active cell device. As described herein, such routing may have high resistance that creates RC delays. However, the control signal path 1200 shown in FIGS. 12-14 is a path that includes additional use of the backside metal layer 912 by routing the control signal between top metal layer portion 908C and backside metal layer portion 912C through a structure (e.g., via structure 1010) in cell 1001. Thus, in various embodiments, the via structure 1010 in cell 1001 provides a path for the control signal on the opposite side of an active device (e.g., device 904) from other active devices.

[0078] In a particular embodiment, the cell 1001 includes three via structures 1010A, 1010B, 1010C. As described above, the three via structures 1010A, 1010B, 1010C may be coupled in parallel between the top metal layer portion 908C and the back metal layer portion 912C, with the via structures being connected (e.g., shorted) to each other at the top metal layer portion and the back metal layer portion. Thus, the control signal path 1200 may "split" (e.g., split) going from the back metal layer portion 912C to the via structures 1010A, 1010B, 1010C and run in parallel through the via structures 1010A, 1010B, 1010C. At the top metal layer portion 908C, the control signal may then "recombine" (e.g., couple back together) and connect to a gate in the active cell. 10-14 show three via structures 1010A, 1010B, 1010C, it should be noted that the number of via structures in cell 1001 may be varied. For example, the number of via structures 1010 may be varied to balance area cost (due to the physical presence of the via structures) and performance (more via structures provide higher performance).

[0079] Running the control signals through the backside metal layer 912 provides a low resistance path (e.g., a "highway" path) for the control signals as compared to routing the control signals only through the top metal layer 908, which has relatively small metal structures (traces). Thus, sending the control signals through the backside metal layer 912 and the control signal path 1200 reduces the RC delay in the transmission of the control signals. Note that the control signals may be routed through any backside metal layer that provides a low resistance path under the device 904.

[0080] As shown in Figures 10-14, a control signal may be transmitted to an active device (e.g., device 904) along a control signal path 1200. The control signal path 1200 passes through a backside metal layer having low resistance (e.g., backside metal layer portion 912C) and then passes through multiple via structures 1010 in parallel before reaching a topside metal layer (e.g., topside metal layer portion 908C). The combination of the low resistance paths in the backside metal layer path and the parallel paths through the via structures 1010 can provide a significant reduction in RC delay for transmitting control signals to / from device 904, thereby improving the performance of the devices in cell layout 1000 compared to previous cell layouts.

[0081] An example where providing control signals through both the top and bottom metal layers may be useful is the implementation of layout 1000 in a bitcell erase process. In one such embodiment, the bitcell erase signal may be generated in device 904. Device 904 may be precharged to provide the bitcell erase signal. With lower interface resistance, the same driver power may drive the bitcell erase signal to a larger distance in the layout. For example, device 904 may be capable of sending the bitcell erase signal to a larger group of bitcells (such as 4 bitcells instead of 2 bitcells). As another example, an embodiment may be contemplated in which control signals through both the top and bottom metal layers to / from device 904 may be implemented to provide a differential structure embodiment in layout 1000. In such an embodiment, signals may be routed in parallel to the top and bottom metal layers, with signals escaping from the top on one side of layout 1000 and escaping from the bottom on the other side of the layout. Signals may be routed in parallel such that both the top and bottom metal layers see the same common mode. Additional cell layouts that combine the control signal path 1200 with redundant power connections in the top and back metal layers can be contemplated to provide improved performance in both signal and power transmission over previous cell layouts.

[0082] The above-described embodiments are directed to utilizing a backside metal layer to provide additional connections for power and / or control signals in an integrated circuit cell layout. Various embodiments of implementations of these additional connections are also contemplated in the present disclosure. For example, a standard memory array (e.g., SRAM array) design may be contemplated to utilize additional connections for power and / or control signals in the backside metal layer to improve power, performance, and area (PPA) metrics in the SRAM array. Current designs of SRAM arrays typically provide connections and routing for power or signals to transistors (or other structures) above transistors. As described herein, some embodiments may be contemplated having connections to power in the backside metal layer of the SRAM array (either alone or in combination with upper metal layer power connections).

[0083] Providing power connections in the back metal layer of the SRAM array provides additional benefits for power transmission, but the present disclosure recognizes that additional benefits may be achieved by placing some signal connection paths for the bit lines and / or word lines in the back layer. For example, moving some signal connection paths for the bit lines to the back layer may allow for capacitance (cap) reduction on the bit lines, which improves performance and power utilization in the SRAM array, while moving some signal connection paths for the word lines to the back layer may improve power utilization in the SRAM array. Further improvements in area cost may also be realized by placing the bit lines or word lines in the back layer.

[0084] Certain embodiments disclosed herein have three broad elements: 1) a plurality of bit cells arranged adjacently in an array; 2) a first bit line or a first pair of bit lines spanning alternating bit cells in the array; and 3) a second bit line or a second pair of bit lines spanning every other bit cell from the first bit line or the first pair of bit lines. In various embodiments, the first bit line is a metal wire arranged in a first metal layer on the top side of the device (e.g., the front side or above the bit cells) and the second bit line is a metal wire arranged in a second metal layer on the back side of the device (e.g., below the bit cells). Alternating the first bit line(s) and the second bit line(s) between adjacent bit cells in a memory array can significantly reduce capacitance in the memory array by increasing the separation between different bit lines in the same metal layer. Reducing capacitance in a memory array can provide leverage to improve other parameters in the memory array, such as leakage, as described herein.

[0085] Another embodiment disclosed herein has three broad elements: 1) a number of bit cells arranged adjacently in an array; 2) a first word line spanning the bit cells in the array, the first word line being a first wire in a first metal layer arranged above the bit cells; and 3) a second word line spanning the bit cells in the array, the second word line being a second wire in a second metal layer arranged below the bit cells. In various embodiments, the first word line and the second word line connect to alternating bit cells in the array. For example, a memory array may have four adjacent bit cells, with both word lines spanning the four bit cells. The first word line connects to the first bit cell and the third bit cell, and the second word line connects to the second bit cell and the fourth bit cell in the memory array.

[0086] Alternating the connection between two separate wordlines can provide independent control of the bitcells. For example, a first wordline controls the toggling of the first and third bitcells, and a second wordline controls the toggling of the second and fourth bitcells. Thus, instead of toggling all four bitcells, only half of the bitcells need to be toggled when a single bit is changed, thereby reducing dynamic power consumption in the memory array. Placing the wires for the wordlines in the backside metal layer can also provide an area cost advantage, since the two wordlines can be placed in a similar vertical area (above / below the bitcell) through two separate metal layers (e.g., top and backside metal layers), thereby doubling the wordline capacity without the area cost.

[0087] In summary, the present inventors have recognized that wiring in a backside metal layer can be advantageously implemented in a memory array (e.g., an SRAM array). Utilizing wiring in the backside metal layer for bitline and / or wordline routing can provide various PPA improvements in the memory array. For example, performance and power improvements can be provided by reducing bitline capacitance, which can be further leveraged for other improvements in the memory array, including area reduction opportunities.

[0088] FIG. 15 illustrates a top view of a memory array 1600 showing bit cells and bit lines, according to some embodiments. In the illustrated embodiment, the memory array 1600 includes four bit cells, namely, bit cell 1510A, bit cell 1510B, bit cell 1510C, and bit cell 1510D. Although four bit cells are shown in FIG. 15, it should be understood that the memory array 1500 may include any number of bit cells. In various embodiments, the bit cells 1510A, bit cell 1510B, bit cell 1510C, and bit cell 1510D are adjacently disposed (e.g., adjacent to one another) in the memory array 1500. For example, as shown in FIG. 15, the bit cells 1510A-D are vertically adjacent to one another (e.g., vertically "stacked" on top of one another).

[0089] In a particular embodiment, the memory array 1500 includes a pair of bit lines spanning each bit cell 1510. For example, in the illustrated embodiment, bit line 1520A spans bit cell 1510A, bit line 1520B spans bit cell 1510B, bit line 1520C spans bit cell 1510C, and bit line 1520D spans bit cell 1510D. Each pair of bit lines may be a complementary pair of bit lines (e.g., one bit line is a positive bit line and the other bit line is a negative bit line). In various embodiments, the bit lines 1520 run perpendicular to the direction in which the bit cells 1510 are arranged adjacent to each other (e.g., the direction in which the bit cells 1510A-D are stacked in FIG. 15). In a particular embodiment, the bit lines 1520 are wires (e.g., metal paths, metal traces, metal structures, etc.) formed in a metal layer of the memory device.

[0090] In particular embodiments, bitlines 1520 (e.g., wires within a bitline) are connected to respective bitcells 1510 by via connections 1530. For example, in the illustrated embodiment, bitline 1520A is connected to bitcell 1510A by via connection 1530A, bitline 1520B is connected to bitcell 1510B by via connection 1530B, bitline 1520C is connected to bitcell 1510C by via connection 1530C, and bitline 1520D is connected to bitcell 1510D by via connection 1530D. Note that although via connection 1530 is depicted in FIG. 15 as spanning the bitline pair, each wire within the bitline pair may have its own individual via connection. Thus, each of via connections 1530A-D may include two or more via connections. Additionally, in embodiments having multiple via connections 1530 within a single bitcell, the via connections may be aligned or offset within the bitcell as required by the design rules.

[0091] To improve PPA over a typical SRAM array, the present disclosure contemplates placing pairs of different bitlines 1520 in different metal layers above and below the bitcell 1510, as shown in FIG. 15. In the illustrated embodiment, bitlines 1520A and 1520C are wires in the back metal layer of memory array 1500 (e.g., the metal layer below the transistor regions of bitcells 1510A and 1510C). Conversely, bitlines 1520B and 1520D are wires in the top metal layer of memory array 1500 (e.g., the metal layer above the transistor regions of bitcells 1510B and 1510D). Thus, as shown in FIG. 15, the bitlines alternate between the back metal layer and the top metal layer in adjacent bitcells. For example, bitline 1520A in bitcell 1510A is in the back metal layer, then bitline 1520B in bitcell 1510B switches to the top metal layer, bitline 1520C in bitcell 1510C switches back to the back metal layer, and then bitline 1520D in bitcell 1510D switches back to the top metal layer.

[0092] In various embodiments, the bitlines 1520 may be placed in the top metal layer or the back metal layer using techniques described herein. Note that the bitlines 1520 may be placed in the back metal layer without the need for a gate connection since the bitlines connect to drains in the memory array 1500. Additional embodiments may be contemplated in which each pair of bitlines includes one bitline in the top metal layer and one bitline in the back metal layer. In such embodiments, additional design considerations may be implemented to maintain symmetry between the bitlines in each pair of bitlines.

[0093] In some embodiments of the memory array, single-ended bitlines in the bitcells may be contemplated. FIG. 16 illustrates a top view of a memory array 1600 having single-ended bitlines in the bitcells, according to some embodiments. In the illustrated embodiment, the memory array 1600 includes bitcells 1610A-D with a single bitline 1620A-D spanning the bitcells. As with the embodiment of FIG. 15, the bitlines 1620A-D may be interleaved between the back metal layer and the top metal layer between adjacent bitcells 1610A-D. Although four bitcells are shown in FIG. 16, it should be understood that the memory array 1600 may include any number of bitcells. In various embodiments, via connections 1630A-D provide connections between the bitlines 1620A-D and the respective bitcells 1610A-D.

[0094] In a typical SRAM array, the bitlines are wires in a metal layer on the top (e.g., front) side of the bitcell (e.g., the bitlines are in a metal layer above the transistor regions of the bitcell). However, placing the bitlines in the same metal layer requires high shielding requirements between the bitlines, which can increase the bitline capacitance in the memory array and reduce the performance of the memory array.

[0095] In the present disclosure, bitline capacitance in a memory array is reduced by alternating bitlines between backside and top metal layers in adjacent bitcells, as shown in Figures 15 and 16. For example, alternating bitlines provides a larger separation distance between bitlines (or bitline pairs) in the same metal layer. This increased separation distance reduces shielding requirements for the bitlines, reducing bitline capacitance. Reducing bitline capacitance can be further leveraged in other properties of the memory array. For example, with lower shielding requirements, area utilization by shielding structures can be reduced, thereby increasing area availability in the memory array for other structures. As another example, bitcells in a memory array can be slowed down with reduced bitline capacitance while providing the same performance. Slowing down the bitcells can reduce leakage in the memory array.

[0096] FIG. 17 illustrates a top view of a memory array 1700 showing bit cells and word lines, according to some embodiments. In the illustrated embodiment, the memory array 1700 includes four bit cells, namely, bit cell 1710A, bit cell 1710B, bit cell 1710C, and bit cell 1710D. Although four bit cells are shown in FIG. 17, it should be understood that the memory array 1700 may include any number of bit cells. In various embodiments, the bit cells 1710A, bit cell 1710B, bit cell 1710C, and bit cell 1710D are adjacently disposed (e.g., adjacent to one another) in the memory array 1700. For example, as shown in FIG. 17, the bit cells 1710A-D are vertically adjacent to one another (e.g., vertically "stacked" on top of one another).

[0097] In a particular embodiment, memory array 1700 includes a pair of parallel word lines, word line 1720A and word line 1720B, that span bit cells 1710A-D. Thus, word line 1720A and word line 1720B can be considered to span memory array 1700. In various embodiments, word line 1720A and word line 1720B span bit cells 1710A-D in the same direction that the bit cells are adjacently arranged (e.g., vertically as shown in FIG. 17). Thus, word lines 1720A and 1720B span memory array 1700 along their lengths to provide access to bit cells 1710A-D. In a particular embodiment, word line 1720A is a wire in a back metal layer of memory array 1700, and word line 1720B is a wire in an upper metal layer of the memory array. Placing word line 1720A in the back metal layer and word line 1720B in the top metal layer allows two word lines to be placed over the same group of bit cells (e.g., bit cells 1710A-D) in memory array 1700. Placing two word lines over the same group of bit cells provides area utilization advantages, as described below.

[0098] As shown in FIG. 17, access to (e.g., connection to) bit cells 1710A-D is provided by via connections 1730A-D. Via connections 1730 may be, for example, metal vias that penetrate an insulating layer disposed between the transistor region containing bit cells 1710 and the metal layer containing word lines 1720. In various embodiments, via connections 1730A-D selectively provide connection between bit cells 1710A-D and either word lines 1720A or word lines 1720B as the word lines pass through the bit cells. In particular embodiments, connections to bit cells 1710A-D are alternated between word lines 1720A and 1720B of adjacent bit cells by alternating connections provided by via connections 1730A-D. For example, in the illustrated embodiment, via connection 1730A provides a connection between bit cell 1710A and word line 1720B, which in turn provides a connection between bit cell 1710B and word line 1720A, via connection 1730C in turn provides a connection between bit cell 1710C and word line 1720B, and via connection 1730D provides a connection between bit cell 1710D and word line 1720A. Thus, the connections of bit cells 1710B and 1710D to word line 1720A alternate with the connections of bit cells 1710A and 1710C to word line 1720B.

[0099] In a typical SRAM array, only a single word line in the upper layer is available for an array of adjacent bit cells. For example, only a single word line can be implemented in the upper metal layer because there is insufficient area to place two parallel word lines spanning multiple vertical (as shown) bit cells. With a single word line, when an instruction (e.g., a control signal) is provided to toggle a single bit cell, all bit cells along the word line receive the instruction to toggle. Because all bit cells are toggled, power consumption is unnecessarily increased over toggling only a selected number of bit cells.

[0100] In various embodiments, the wordlines 1720 are disposed in a top or back metal layer using techniques described herein. Note that wordlines 1720 disposed in a back metal layer typically require a gate connection (e.g., to a pass gate). Thus, embodiments may be contemplated in which a connection to a gate through the back layer as described herein is implemented for the wordlines 1720.

[0101] In the present disclosure, the placement of word lines in both the top metal layer and the bottom metal layer may allow connections to bit cells to be alternated between parallel word lines that simultaneously provide access to the same group of bit cells. For example, as shown in FIG. 17, word line 1720A (in the bottom metal layer) and word line 1720B (in the top metal layer) have alternating connections to adjacent bit cells 1710 in memory array 1700. Thus, a single word line (e.g., either word line 1720A or word line 1720B) can provide control signals to a reduced number of bit cells 1710 (e.g., half the bit cells) in memory array 1700. For example, when a control signal to toggle is sent over word line 1720A, only bit cells 1710A and 1710C are toggled, while bit cells 1710B and 1710D remain in their current state. Similarly, when a toggling control signal is sent over word line 1720B, only bit cells 1710B and 1710D are toggled, while bit cells 1710A and 1710C remain in their current state.

[0102] By reducing the number of bit cells toggled by a single control signal, dynamic power consumption in memory array 1700 can be reduced compared to a memory array having a single word line. Providing reduced dynamic power consumption is also achieved at a lower area cost since the word line count is doubled in the vertical region above the bit cells instead of having to increase the area of ​​the bit cells to accommodate multiple word lines. The embodiment of the technique described in FIG. 17 for doubling word lines can also be applied to other control signal lines implemented in an integrated circuit such as a memory array. For example, control signals such as bit line precharge signals, column select signals, column select signals, cross-coupled PMOS structure signals, etc. are control signals that can utilize doubling of lines in the top metal layer and back metal layer. Applying the disclosed technique to these control signals can further reduce power since these signals are full power signals unlike the word line control signals.

[0103] Various embodiments of memory arrays utilizing both bitlines and wordlines disposed in top and bottom metal layers may also be contemplated. FIG. 18 illustrates a top view of a memory array 1800 having both bitlines and wordlines in top and bottom metal layers, according to some embodiments. In the illustrated embodiment, memory array 1800 includes four bit cells, namely, bit cell 1810A, bit cell 1810B, bit cell 1810C, and bit cell 1810D. Although four bit cells are shown in FIG. 18, it should be understood that memory array 1800 may include any number of bit cells. In various embodiments, bit cell 1810A, bit cell 1810B, bit cell 1810C, and bit cell 1810D are adjacently disposed within memory array 1800 (e.g., adjacent to one another). For example, as shown in FIG. 18, bit cells 1810A-D are vertically adjacent to one another (e.g., vertically "stacked" on top of one another).

[0104] The illustrated embodiment of memory array 1800 essentially includes the bit lines of memory array 1500 shown in Figure 15 overlapped with the word lines of memory array 1700 shown in Figure 17. Thus, memory array 1800 includes bit line 1820A spanning bit cell 1810A, bit line 1820B spanning bit cell 1810B, bit line 1820C spanning bit cell 1810C, and bit line 1820D spanning bit cell 1810D. Memory array 1800 further includes word lines 1830A and 1830B spanning bit cells 1810A-D.

[0105] As described in the previous embodiment, the bitlines 1820A-D may comprise bitline pairs in either the top metal layer or the bottom metal layer. For example, in the illustrated embodiment, the bitlines 1820A and 1820C are in the bottom metal layer, and the bitlines 1820B and 1820D are in the top metal layer. Similarly, the wordline 1830A may be in the bottom metal layer, and the wordline 1830B may be in the top metal layer. The via connections 1840A-D then provide alternating connections from the bitcells 1810A-D to the wordlines 1830A and 1830B, and the via connections 1850A-D provide alternating connections between the bitlines 1820A-D and the bitcells 1810A-D, as described herein.

[0106] Although the bit lines 1820 and word lines 1830 are shown crossing each other and are described as both being in a "bottom (or top) metal layer," it should be understood that the bit lines and word lines may be implemented in different metal layers in both the top and bottom layers. For example, the bit lines 1820A may be implemented in a first metal layer in the bottom metal layer, and the word lines 1830A are implemented in a second metal layer in the bottom metal layer. Additional embodiments may be contemplated in which the bit lines and word lines are routed through multiple metal layers to accommodate spacing between the lines. The embodiment of the memory array 1800 shown in FIG. 18 may benefit from various advantages described herein in connection with having both bit lines and word lines in the bottom metal layer and the top metal layer simultaneously.

[0107] In various embodiments, word lines in both the top metal layer and the bottom metal layer may be implemented in large cells (e.g., "megacells") of a memory array to improve area utilization in such cells. FIG. 19 shows a top view of a large memory megacell that replaces two smaller memory megacells, according to some embodiments. In the illustrated embodiment, megacells 1910A and 1910B are combined into a single megacell, megacell 1900. Megacell 1910A includes a memory array bank 1912A and a memory array bank 1912B separated by a bit line logic circuit 1916A, and word line logic circuit 1914A is disposed adjacent to the memory array bank and the bit line logic circuit. Memory array banks 1912A and 1912B may include any of the various memory cells or memory arrays disclosed herein, in addition to other contemplated embodiments of memory cells and memory arrays. Bit line logic circuitry 1914A may include sense amplifiers or other logic for reading data from memory array banks 1912A and 1912B. Word line logic circuitry 1916A may include word line decoder logic, word line selection logic, or multiplexer logic for interacting with the word lines in memory array banks 1912A and 1912B.

[0108] In various embodiments, megacell 1910A also includes global input / output (I / O) circuitry 1918A and global control circuitry 1920A. Global I / O circuitry 1918A may include, for example, write drivers or sense amplifiers. Global control circuitry 1920A may include, for example, clock or decoder logic. Megacell 1910B may be similar to megacell 1910A by including memory array bank 1912C, memory array bank 1912D, bit line logic circuitry 1914B, word line logic circuitry 1916B, global input / output (I / O) circuitry 1918B, and global control circuitry 1920B.

[0109] 19, megacells 1910A and 1910B may be combined to form megacell 1900. Megacell 1900 includes memory array banks 1912A-D having a single instance of bit line logic circuitry 1914, word line logic circuitry 1916, global input / output (I / O) circuitry 1918, and global control circuitry 1920. Thus, megacell 1900 may have a reduced area cost compared to the combination of megacells 1910A and 1910B.

[0110] Megacell 1900 may be formed by implementing wordlines in both the top metal layer and the bottom metal layer. For example, in the illustrated embodiment, megacell 1900 includes wordline 1930A and wordline 1930B for connecting to memory array bank 1912A and memory array bank 1912C, respectively. Similar wordlines may be provided to memory array banks 1912B and 1912D.

[0111] In a particular embodiment, wordline 1930A is disposed in an upper metal layer and wordline 1930B is disposed in a backside metal layer. As shown in FIG. 19, wordline 1930B travels a longer distance to connect to a memory cell in memory array bank 1912C than wordline 1930A must travel to connect to a memory cell in memory array bank 1912A. Because of this longer distance, wordline 1930B may be disposed in a backside metal layer because backside metal layers typically have lower resistance metal wiring than upper metal layers. Using a low resistance backside metal layer for wordline 1930B also eliminates the need for repeaters that may be required for the upper metal layer wordlines that connect to memory array bank 1912C or memory array bank 1912D. Thus, megacell 1900 provides better area utilization, as well as better performance and power metrics, compared to the combination of megacells 1910A and 1910B.

[0112] In various embodiments, wide memory megacells, which may have a large area cost, may be converted to taller, narrower memory megacells to reduce area requirements. FIG. 20 shows a top view of a tall memory megacell replacing a wide memory megacell, according to some embodiments. In the illustrated embodiment, megacell 2000 is a wide memory megacell. Megacell 2000 includes memory array bank 2012A, memory array bank 2012B, memory array bank 2012C, and memory array bank 2012D. Memory array bank 2012A and memory array bank 2012B are separated by and connected to bit line logic circuitry 2014A, and memory array bank 2012C and memory array bank 2012D are separated by and connected to bit line logic circuitry 2014B.

[0113] Megacell 2000 includes a single instance of wordline logic circuitry 2016 (integrated with each of memory array banks 2012A-D), global I / O circuitry 2018, and global control circuitry 2020. As shown in Figure 20, megacell 2000 may be converted into megacell 2050. Megacell 2050 may have a structure similar to memory array 1800 shown in Figure 18, with memory array banks 2012A-D and single instances of bitline logic circuitry 2014, wordline logic circuitry 2016, global I / O circuitry 2018, and global control circuitry 2020.

[0114] The conversion to megacell 2050 may be provided by implementing wordlines in both the top metal layer and the back metal layer, similar to memory array 1800. For example, in the illustrated embodiment, megacell 2050 includes wordline 2030A in the top metal layer to connect to memory array bank 2012A, and wordline 2030B in the back metal layer to connect to memory array bank 2012C. Thus, megacell 2050 provides better area utilization, as well as better performance and power metrics, compared to megacell 2000. Further area savings are also seen in megacell 2050, where the width of wordline logic 2016 is reduced compared to megacell 2000.

[0115] Based on the present disclosure of bitline implementations in both top and bottom metal layers, various embodiments of hierarchical bitline layouts may also be contemplated. Figure 21 shows a top view of a memory array with hierarchical bitlines, according to some embodiments. In the illustrated embodiment, memory array 2100 is a memory array having bitlines spanning bitcells 2110 in two top metal layers. For example, bitline 2120A may be in a first metal layer and bitline 2120B may be in a second metal layer.

[0116] Hierarchical routing of bitlines may be implemented by jumping from bitline 2120A to bitline 2120B at the transition between bitcell bank 2130A and bitcell bank 2130B, as shown in Figure 21. Bitcells 2110 within bitcell bank 2130 may share resources (such as sense amplifiers) to reduce bitline capacitance for large caches of data (e.g., caches with 512 wordlines). Resource sharing may also reduce the number of local I / O connections required within memory array 2100.

[0117] Adding bitline routing to the backside metal layer can further reduce bitline capacitance. For example, memory array 2150 includes three bitlines 2170A, 2170B, 2170C that span bitcells 2160. Bitline 2170A is in a first metal layer in the backside metal layer, bitline 2170B is in a first metal layer, and bitline 2170C is in a second metal layer in the top metal layer. Thus, three bitcell banks 2180A, 2180B, and 2180C can be created by the hierarchy of bitlines 2170A, 2170B, 2170C. Exemplary Computer System

[0118] 22, a block diagram of one embodiment of a system 2200 is shown that may incorporate and / or otherwise utilize the methods and mechanisms described herein. In the illustrated embodiment, the system 2200 includes at least one instance of a system on a chip (SoC) 2206, which may include multiple types of processing units, such as a central processing unit (CPU), a graphics processing unit (GPU), or otherwise, a communications fabric, and interfaces to memory and input / output devices. In some embodiments, one or more processors in the SoC 2206 include multiple execution lanes and similar instruction issue queues. In various embodiments, the SoC 2206 is coupled to an external memory 2202, peripherals 2204, and a power source 2208.

[0119] A power supply 2208 is also provided to provide a supply voltage to the SoC 2206 and to provide one or more supply voltages to the memory 2202 and / or peripherals 2204. In various embodiments, the power supply 2208 represents a battery (e.g., a rechargeable battery in a smartphone, laptop, tablet computer, or other device). In some embodiments, more than one instance of the SoC 2206 is included (and more than one external memory 2202 is also included).

[0120] The memory 2202 may be any type of memory, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM, such as mDDR3, and / or low power versions of SDRAM, such as LPDDR2), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices may be connected to a circuit board to form a memory module, such as a single in-line memory module (SIMM), dual in-line memory module (DIMM), etc. Alternatively, the devices may be mounted on a SoC or integrated circuit in a chip-on-chip, package-on-package, or multi-chip module configuration.

[0121] The peripherals 2204 may include any desired circuitry depending on the type of system 2200. For example, in one embodiment, the peripherals 2204 include devices for various wireless communications, such as Wi-Fi, Bluetooth, cellular, global positioning system, etc. In some embodiments, the peripherals 2204 may also include additional storage, including RAM storage, solid state storage, or disk storage. The peripherals 2204 may also include user interface devices, such as a display screen, including a touch display screen or a multi-touch display screen, a keyboard or other input device, a microphone, a speaker, etc.

[0122] As shown, the system 2200 is shown to have application in a wide range of areas. For example, the system 2200 may be utilized as part of a chip, circuit, component, etc., in a desktop computer 2210, a laptop computer 2220, a tablet computer 2230, a cellular or mobile phone 2240, or a television 2250 (or a set-top box coupled to a television). Also shown is a smart watch and a health monitoring device 2260. In some embodiments, the smart watch may include various general-purpose computing-related functions. For example, the smart watch may provide access to email, mobile phone services, a user calendar, etc. In various embodiments, the health monitoring device may be a dedicated medical device or may otherwise include dedicated health-related functions. For example, the health monitoring device may monitor a user's vital signs, track a user's proximity to other users for epidemiological social distancing, perform contact tracing, and provide communication to emergency services in the event of a health crisis. In various embodiments, the smart watch described above may or may not include some or any health monitoring-related functions. Other wearable devices are contemplated as well, such as devices worn around the neck, devices implantable in the human body, glasses designed to provide an augmented and / or virtual reality experience, etc.

[0123] The system 2200 may further be used as part of a cloud-based service(s) 2270. For example, the devices described above and / or other devices may access computing resources (i.e., remotely located hardware and / or software resources) in the cloud. Additionally, the system 2200 may be utilized in one or more devices in the home 2280 other than those described above. For example, appliances in the home may monitor and detect noteworthy conditions. For example, various devices in the home (e.g., refrigerators, cooling systems, etc.) may monitor the status of the devices and alert the homeowner (or a repair facility) if a particular event is detected. Alternatively, a thermostat may monitor the temperature of the home and automate adjustments to the heating / cooling system based on the homeowner's historical response to various conditions. Also illustrated in FIG. 22 is the application of the system 2200 to various modes of transportation 2290. For example, the system 2200 may be used in control and / or entertainment systems for airplanes, trains, buses, rental vehicles, personal cars, watercraft ranging from private boats to cruise ships, scooters (rented or owned), etc. In various cases, system 2200 can be used to provide automated guidance (e.g., autonomous vehicles), general system control, and other methods. Many other embodiments of any of these are possible and contemplated. Note that the devices and applications illustrated in FIG. 22 are merely illustrative and are not intended to be limiting. Other devices are possible and contemplated. ***

[0124] The present disclosure includes references to "one embodiment" or groupings of "embodiments" (e.g., "some embodiments" or "various embodiments"). Embodiments are different implementations or examples of the disclosed concepts. References to "one embodiment," "one embodiment," "particular embodiment," etc. do not necessarily refer to the same embodiment. Numerous possible embodiments, including those specifically disclosed, are contemplated, as well as modifications or alternatives that are within the spirit or scope of the present disclosure.

[0125] This disclosure may discuss potential advantages that may result from the disclosed embodiments. Not all implementations of these embodiments necessarily exhibit any or all of the potential advantages. Whether advantages are realized for a particular implementation depends on many factors, some of which are outside the scope of this disclosure. Indeed, there are many reasons why an implementation within the scope of the claims may not exhibit some or all of any disclosed advantages. For example, a particular implementation may include other circuitry outside the scope of this disclosure that, in conjunction with one of the disclosed embodiments, negates or reduces one or more of the disclosed advantages. Furthermore, suboptimal design practices of a particular implementation (e.g., implementation techniques or tools) may also negate or reduce the disclosed advantages. Even assuming skilled execution, realization of advantages may still depend on other factors, such as the environmental conditions in which the implementation is deployed. For example, inputs provided to a particular implementation may prevent one or more of the problems addressed in this disclosure from occurring on a particular occasion, such that the benefits of the solution may not be realized. Given the existence of factors external to the present disclosure that may arise, it is expressly intended that any potential advantages described herein should not be construed as claim limitations that must be met in order to demonstrate infringement. Rather, the identification of such potential advantages is intended to illustrate the type or types of improvement available to a designer having the benefit of the present disclosure. The fact that such advantages are permissibly described (e.g., a statement that a particular advantage "may result") is not intended to convey any doubt as to whether such advantage may actually be realized, but rather is intended to recognize the technological reality that realization of such advantages often depends on additional factors.

[0126] Unless otherwise stated, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of the claims made based on this disclosure, even if only a single example is described with respect to a particular feature. The disclosed embodiments are intended to be illustrative, not limiting, unless otherwise stated in the disclosure. The above description is intended to enable claims that cover not only the disclosed embodiments, but also alternatives, modifications, and equivalents that will be apparent to those skilled in the art having the benefit of this disclosure.

[0127] For example, features of the present application may be combined in any suitable manner. Accordingly, new claims may be formulated during prosecution of this application (or an application claiming priority to this application) for any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with features of other dependent claims, including claims that are dependent on other independent claims, as appropriate. Similarly, features from each independent claim may be combined as appropriate.

[0128] Thus, the accompanying dependent claims may each be drafted to be dependent on a single other claim, although additional dependencies are also contemplated. Any combination of features in the dependent claims consistent with this disclosure is contemplated and may be claimed in this or another application. In summary, combinations are not limited to those specifically recited in the accompanying claims.

[0129] Where appropriate, it is contemplated that a claim drafted in one format or statutory type (e.g., apparatus) is also intended to support a corresponding claim in another format or statutory type (e.g., method). ***

[0130] Because this disclosure is a legal document, various terms and phrases may be subject to administrative and judicial interpretation. The definitions provided in the following paragraphs, as well as throughout this disclosure, are hereby publicly advised to be used in interpreting any claims made based on this disclosure.

[0131] Reference to a singular item (i.e., a noun or noun phrase preceded by "a," "an," or "the") is intended to mean "one or more" unless the context clearly indicates otherwise. Thus, a reference to an "item" in a claim does not exclude additional instances of the item without the context requiring otherwise. A "plurality" of an item refers to a set of two or more items.

[0132] The word "may" is used herein in a permissive sense (i.e., having the possibility, being able to) and not in an obligatory sense (i.e., not required).

[0133] The terms "comprising" and "including" and their forms are open ended and mean "including, but not limited to."

[0134] When the term "or" is used in this disclosure in reference to a list of alternatives, it will generally be understood to be used in an inclusive sense unless the context clearly indicates otherwise. Thus, a list of "x or y" is equivalent to "x or y, or both," and thus encompasses 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, the phrase "either x or y, but not both" makes it clear that "or" is used in an exclusive sense.

[0135] The enumeration of "w, x, y, z, or any combination thereof," or "at least one of ... w, x, y, and z" is intended to cover all possibilities including a single element up to the total number of elements in the set. For example, for the set [w, x, y, z], these expressions cover any single element of the set (e.g., w but not x, y, or z), any two elements (e.g., w and x but not y or z), any three elements (e.g., w, x, and y but not z), and all four elements. Thus, the phrase "at least one of ... w, x, y, and z" refers to at least one element of the set [w, x, y, z], thereby covering all possible combinations in this list of elements. This phrase should not be interpreted as requiring that there be at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0136] In this disclosure, various "labels" may precede a noun or noun phrase. Unless the context clearly indicates otherwise, the various labels used for a feature (e.g., "first circuit," "second circuit," "particular circuit," "given circuit," etc.) refer to different instances of the feature. Furthermore, when applied to features, the labels "first," "second," and "third" do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) unless otherwise specified.

[0137] As used herein, the phrase "based on" is used to describe one or more factors that influence the determination. This term does not exclude the possibility that additional factors may influence the decision. That is, the decision may be based only on the specified factors or based on the specified factors as well as other unspecified factors. Consider the phrase "determining A based on B." This phrase specifies that B is a factor that is used to determine A or that influences the determination of A. This phrase does not exclude that the determination of A may also be based on some other factor, such as C. This phrase is intended to cover an embodiment in which A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0138] The phrases "in response to" and "in response to" recite one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may affect or otherwise trigger the effect, either together with the particular factor or independent of the specified factor. That is, the effect may be in response only to these factors or to the specified factors as well as other unspecified factors. Consider the phrase "performing A in response to B." By this phrase, B is a factor that triggers the execution of A or triggers a particular outcome for A. This phrase does not exclude that the execution of A may also be in response to other factors, such as C. This phrase also does not exclude that the execution of A may be in response to both B and C. This phrase is intended to cover an embodiment in which A is performed only in response to B. As used herein, the phrase "in response to" is synonymous with the phrase "at least partially in response to." Similarly, the phrase "in response to" is synonymous with the phrase "at least partially in response to." ***

[0139] Within this disclosure, various entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed as being "configured" to perform one or more tasks or operations. The phrase "entity" configured to perform one or more tasks is used herein to refer to structures (i.e., physical things). More specifically, the phrase is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be said to be "configured to perform" some task even if the structure is not currently operating. Thus, an entity described or explained as being "configured" to perform some task refers to a physical thing, such as a device, a circuit, a system having a processor unit and a memory that stores executable program instructions to perform the task. The phrase is not used herein to refer to intangible things.

[0140] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations, and even if not specifically described, it will be understood that those entities are "configured to" perform those tasks / operations.

[0141] The term "configured to" is not intended to mean "configurable to." For example, an unprogrammed FPGA is not considered to be "configured" to perform a particular function. However, this unprogrammed FPGA may be "configurable" to perform that function. After appropriate programming, the FPGA can then be said to be "configured" to perform a particular function.

[0142] For purposes of filing a U.S. patent application based on this disclosure, reciting a claim as a structure "configured to" perform one or more tasks is not expressly intended to invoke 35 U.S.C. §112(f) for that claim element. If an applicant wishes to invoke 35 U.S.C. §112(f) during prosecution of a U.S. patent application based on this disclosure, it would be to recite a claim element using "means for [performing a function]."

[0143] Various "circuits" may be described in this disclosure. These circuits or "circuitry" constitute hardware including various types of circuit elements such as combinational logic, clocked storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuits may be custom designed or obtained from standard libraries. In various implementations, circuitry may include digital components, analog components, or a combination of both, as appropriate. Certain types of circuits may be generally referred to as "units" (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such units may also be referred to as circuits or circuitry.

[0144] The disclosed circuits / units / components and other elements shown in the drawings and described herein include hardware elements such as those described in the preceding paragraphs. Often, the internal arrangement of hardware elements within a particular circuit may be specified by describing the function of that circuit. For example, a particular "decode unit" may be described as performing the function of "processing the opcode of an instruction and routing the instruction to one or more of a plurality of functional units," meaning that the decode unit is "configured" to perform this function. Description of this function is sufficient to suggest to one skilled in the computer arts a set of possible configurations of the circuit.

[0145] In various embodiments, as described in the previous paragraph, circuits, units, and other elements are defined by the functions or operations they are configured to implement. The arrangement of such circuits / units / components relative to one another and the way they interact form the microarchitectural definition of the hardware that is ultimately fabricated in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitectural definition. Thus, the microarchitectural definition is recognized by those skilled in the art as a structure from which many physical implementations can be derived, all of which belong to the broader structure described by the microarchitectural definition. That is, those skilled in the art presented with the microarchitectural definition provided in accordance with this disclosure may, without undue experimentation, use ordinary skill to implement the structure by coding the description of the circuit / unit / component into a hardware description language (HDL), such as Verilog or VHDL. HDL descriptions are often expressed in a manner that appears to be functional. However, to those skilled in the art, this HDL description is the method used to translate the structure of the circuit, unit, or component into the next level of implementation details. Such HDL descriptions may take the form of behavioral level code (typically not synthesizable), register transfer language (RTL) code (typically synthesizable, as opposed to behavioral level code), or structural code (e.g., a netlist specifying logic gates and their connections). The HDL description may be synthesized against a library of cells designed for a given integrated circuit manufacturing technology, and modified for timing, power, and other reasons, resulting in a final design database that can be sent to a foundry to generate masks and ultimately manufacture the integrated circuit. Some hardware circuits, or portions thereof, may also be custom designed in a schematic editor and incorporated into the integrated circuit design along with the synthesized circuit. The integrated circuit may further include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.), as well as interconnects between the transistors and the circuit elements.Some embodiments may implement multiple integrated circuits connected together to realize the hardware circuit, and / or some embodiments may use discrete elements. Alternatively, the HDL design may be integrated into and implemented in a programmable logic array, such as a field programmable gate array (FPGA). This decoupling between the design of a group of circuits and the subsequent low-level implementation of those circuits typically results in a scenario where the circuit or logic designer does not specify any particular set of structures for the low-level implementation other than describing how the circuit is structured, since this process is performed at a different stage in the circuit implementation process.

[0146] The fact that many different low-level combinations of circuit elements can be used to implement the same specification for a circuit results in numerous equivalent structures for that circuit. As noted above, these low-level circuit implementations may vary depending on changes in manufacturing technology, the foundry selected to manufacture the integrated circuit, the libraries of cells provided for a particular project, etc. In many cases, the choices made by different design tools or methods to generate these different implementations may be arbitrary.

[0147] Furthermore, for a given embodiment, it is common for a single implementation of a particular functional specification of a circuit to include a large number of devices (e.g., millions of transistors). This absolute amount of information therefore makes it impractical to exhaustively enumerate the low-level structures used to implement a single embodiment, let alone the vast amount of equivalent possible implementations. For this reason, this disclosure describes the structure of a circuit using functional abbreviations used in the industry.

Claims

1. 1. An apparatus comprising: A substrate; a transistor having a gate region, a source region, and a drain region disposed above the substrate in a vertical dimension perpendicular to the substrate; a first metal layer disposed above the transistor in the vertical dimension; a second metal layer disposed below the transistor in the vertical dimension; a first rail connected to both the first metal layer and the second metal layer; a second rail connected to both the first metal layer and the second metal layer; A device, wherein at least one of the source region and the drain region is coupled to at least one of the first rail and the second rail via a connection to both the first metal layer and the second metal layer.

2. The device of claim 1 , wherein the first metal layer is disposed above the substrate.

3. The device of claim 1 , wherein the second metal layer is disposed on a backside of the substrate.

4. The apparatus of claim 1 , wherein the first rail and the second rail are power rails connected to one or more power sources.

5. 2. The device of claim 1, wherein the first rail and the second rail are signal rails for the source and drain regions.

6. 2. The device of claim 1, wherein the source region is coupled to the first rail via respective connections to both the first metal layer and the second metal layer, and the drain region is coupled to the second rail via respective connections to both the first metal layer and the second metal layer.

7. 7. The device of claim 6, further comprising: at least one via coupling the source region to the first metal layer; and at least one via coupling the source region to the second metal layer.

8. 7. The device of claim 6, further comprising: at least one via coupling said drain region to said first metal layer; and at least one via coupling said drain region to said second metal layer.

9. 10. The device of claim 1, further comprising at least one via coupling the gate region to at least one of the first metal layer and the second metal layer.

10. A non-transitory computer readable storage medium storing a plurality of instructions that, when executed, produce an integrated circuit device, the integrated circuit device comprising: A substrate; a transistor having a gate region, a source region, and a drain region disposed above the substrate in a vertical dimension perpendicular to the substrate; a first metal layer disposed above the transistor in the vertical dimension; a second metal layer disposed below the transistor in the vertical dimension; a first rail connected to both the first metal layer and the second metal layer; a second rail connected to both the first metal layer and the second metal layer; the source region is coupled to the first rail via respective connections to both the first metal layer and the second metal layer; the drain region is coupled to the second rail via respective connections to both the first metal layer and the second metal layer.

11. 11. The non-transitory computer-readable storage medium of claim 10, wherein the source region receives a first portion of a current from a power source providing a supply voltage through the first metal layer and a second portion of the current from the power source providing the supply voltage through the second metal layer.

12. 12. The non-transitory computer-readable storage medium of claim 11, wherein the first portion of the current and the second portion of the current are controlled based on resistances of the first metal layer and the second metal layer.

13. 11. The non-transitory computer-readable storage medium of claim 10, wherein the first metal layer includes power routing coupled to the first rail and ground routing coupled to the second rail, the source region being coupled to the power routing in the first metal layer and the drain region being coupled to the ground routing in the first metal layer.

14. 11. The non-transitory computer-readable storage medium of claim 10, wherein the second metal layer includes power routing coupled to the first rail and ground routing coupled to the second rail, the source region being coupled to the power routing in the second metal layer and the drain region being coupled to the ground routing in the second metal layer.

15. 1. An integrated circuit device, comprising: A substrate; a transistor having a gate region, a source region, and a drain region; a first metal layer disposed vertically above the transistor toward an upper side of the substrate, the first metal layer having power and ground routing; a second metal layer disposed vertically below the transistor toward a backside of the substrate, the second metal layer having power and ground routing; a first contact between the power routing and the source region in the first metal layer; a second contact in the first metal layer between the ground routing and the drain region; a third contact between the power routing and the source region in the second metal layer; and a fourth contact between the ground routing in the second metal layer and the drain region.

16. 16. The device of claim 15, wherein the power routing and the ground routing in the first metal layer are coupled to a power supply.

17. 17. The device of claim 16, wherein the power routing and the ground routing in the second metal layer are coupled to the power supply.

18. 20. The device of claim 17, wherein the source region is configured to receive a first portion of the current from the power source through the power routing in the first metal layer, and the source region is configured to receive a second portion of the current from the power source through the power routing in the second metal layer.

19. 16. The device of claim 15, wherein the first contact and the second contact are disposed in a first insulating layer vertically above the transistor, and the third contact and the fourth contact are disposed in a second insulating layer vertically below the transistor.

20. 16. The device of claim 15, wherein the gate region is coupled to at least one of the first metal layer and the second metal layer using a via through an insulating layer above the transistor.

21. An apparatus comprising: a first transistor formed within a transistor region of the integrated circuit; a first metal layer disposed above the transistor region in a vertical dimension perpendicular to the transistor region; a second metal layer disposed below the transistor region in the vertical dimension; a first wire disposed in the first metal layer and connected to a signal input of the first transistor; a second wire disposed in the second metal layer, the second wire passing underneath the first transistor in the vertical dimension and from a first side of the first transistor to a second side of the first transistor in a horizontal dimension perpendicular to the vertical dimension; a control signal routed to the signal input of the first transistor, the control signal routed from the second side of the first transistor through the second wire to the first side of the first transistor, then from the second wire to the first wire and routed to the signal input of the first transistor.

22. 22. The apparatus of claim 21, further comprising a power rail connected to a third wire in the first metal layer and a fourth wire in the second metal layer, the first transistor being connected to the power rail via the third wire and the fourth wire.

23. 22. The apparatus of claim 21, further comprising a second transistor formed in the transistor region, the first transistor and the second transistor being separated in the horizontal dimension.

24. 24. The apparatus of claim 23, wherein the control signal is routed between a signal output of the second transistor and the signal input of the first transistor.

25. 22. The apparatus of claim 21, further comprising at least one via structure connecting the first wire to the second wire.

26. 26. The apparatus of claim 25, wherein the at least one via structure includes at least one inactive doped region within the transistor region.

27. 22. The device of claim 21, wherein the first metal layer is disposed above the transistor region and the second metal layer is disposed below the transistor region.

28. 22. The apparatus of claim 21 , wherein the control signal is routed below the first transistor in the vertical dimension.

29. 22. The apparatus of claim 21, further comprising at least one via between the first wire and the first transistor.

30. An apparatus comprising: a first transistor formed within a transistor region of the integrated circuit; a first metal layer disposed above the transistor region in a vertical dimension perpendicular to the transistor region; a second metal layer disposed below the transistor region in the vertical dimension; a first wire disposed in the first metal layer and connected to a signal input of the first transistor; a second wire disposed in the second metal layer, the second wire passing underneath the first transistor in the vertical dimension and from a first side of the first transistor to a second side of the first transistor in a horizontal dimension perpendicular to the vertical dimension; at least one via structure connecting the first wire to the second wire, the at least one via structure being disposed on the first side of the first transistor; a control signal routed to the signal input of the first transistor, the control signal passing through the second wire, through the at least one via structure, and through the first wire to the signal input of the first transistor.

31. 31. The apparatus of claim 30, further comprising a second transistor formed in the transistor region, the control signal being routed between a signal output of the second transistor and the signal input of the first transistor.

32. 31. The apparatus of claim 30, wherein the at least one via structure comprises at least one doped region in the transistor region and one or more via connections between the first wire and the second wire.

33. 31. The apparatus of claim 30, wherein the at least one via structure comprises two or more via structures connected in parallel between the first wire and the second wire.

34. 34. The apparatus of claim 33, wherein the two or more via structures are connected to each other within the first metal layer.

35. The device of claim 30 , wherein the at least one via structure is disposed at an edge of the device.

36. An apparatus comprising: a transistor region of an integrated circuit; a first transistor disposed in the transistor region, the first transistor having a first gate region, a first source region, and a first drain region; a second transistor having a second gate region, a second source region, and a second drain region disposed in the transistor region and disposed on a first side of the first transistor in a horizontal dimension parallel to the transistor region; a first metal layer disposed above the transistor region in a vertical dimension perpendicular to the transistor region; a second metal layer disposed below the transistor region in the vertical dimension; a first connection between the first gate region and a first wire disposed in the first metal layer; a second connection between the second gate region and a second wire disposed in the second metal layer; at least one via structure connecting the first wire to the second wire, the at least one via structure being disposed on a second side of the first transistor in the horizontal dimension; a control signal routed from the second gate region to the first gate region, the control signal traveling from the second gate region through the second connection to the second wire, from the second wire to the at least one via structure, from the at least one via structure to the first wire, and from the first wire through the first connection to the first gate region.

37. 37. The device of claim 36, wherein the first source region and the first drain region are connected to additional wiring in the first metal layer and the second metal layer, and the second source region and the second drain region are connected to additional wiring in the first metal layer and the second metal layer.

38. 37. The apparatus of claim 36, wherein the at least one via structure comprises at least one doped region in the transistor region and one or more via connections between the first wire and the second wire.

39. 37. The apparatus of claim 36, wherein the at least one via structure comprises two or more via structures connected in parallel between the first wire and the second wire.

40. 37. The apparatus of claim 36, wherein the second connection comprises at least one via between the second wire and the second transistor.

41. 1. A memory device, comprising: a plurality of bit cells, the bit cells being adjacently arranged, the plurality of bit cells including a first bit cell adjacent to a second bit cell; a first metal layer disposed above the plurality of bit cells in a vertical dimension perpendicular to the plurality of bit cells; a second metal layer disposed below the plurality of bit cells in the vertical dimension perpendicular to the plurality of bit cells; a first bitline spanning the first bitcell, the first bitline including a wire disposed in the first metal layer, the wire disposed in the first metal layer connecting to the first bitcell; a second bit line spanning the second bit cell, the second bit line including a wire disposed in the second metal layer, the wire disposed in the second metal layer connecting to the second bit cell.

42. 42. The device of claim 41 , wherein the first bit line includes an additional wire disposed in the first metal layer, the wire disposed in the first metal layer and the additional wire disposed in the first metal layer configured as a complementary pair.

43. 42. The device of claim 41 , wherein the second bit line includes an additional wire disposed in the second metal layer, the wire disposed in the second metal layer and the additional wire disposed in the second metal layer configured as a complementary pair.

44. a third bit cell adjacent to the second bit cell in the plurality of bit cells, the third bit cell being on an opposite side of the second bit cell from the first bit cell; a third bitline spanning the third bitcell, the third bitline including an additional wire disposed in the first metal layer, the additional wire disposed in the first metal layer connecting to the third bitcell; 42. The apparatus of claim 41, further comprising:

45. a fourth bit cell adjacent to the third bit cell in the plurality of bit cells, the fourth bit cell being on an opposite side of the third bit cell from the second bit cell; a fourth bitline spanning the fourth bitcell, the fourth bitline including an additional wire disposed in the second metal layer, the additional wire disposed in the second metal layer connecting to the fourth bitcell; 45. The apparatus of claim 44, further comprising:

46. the first bit line and the second bit line span the plurality of bit cells in a first direction, and the device comprises: a first word line spanning the plurality of bit cells in a second direction, the second direction being perpendicular to the first direction, the first word line including an additional wire disposed within the first metal layer; 42. The device of claim 41 , further comprising: a second wordline spanning the plurality of bitcells in the second direction, the second wordline including an additional wire disposed in the second metal layer.

47. 47. The apparatus of claim 46, wherein the first word line connects to the second bit cell and the second word line connects to the first bit cell.

48. 42. The device of claim 41, wherein the first bit lines are parallel to the second bit lines.

49. 42. The device of claim 41 , wherein the bit cells are arranged adjacently in a first direction, and the first bit line and the second bit line span the plurality of bit cells in a second direction perpendicular to the first direction.

50. 1. A memory device, comprising: a plurality of bit cells, the bit cells being adjacently arranged, the plurality of bit cells including a first bit cell adjacent to a second bit cell; a first metal layer disposed above the plurality of bit cells in a vertical dimension perpendicular to the plurality of bit cells; a second metal layer disposed below the plurality of bit cells in the vertical dimension perpendicular to the plurality of bit cells; a first word line spanning the plurality of bit cells, the first word line including a wire disposed in the first metal layer, the wire disposed in the first metal layer connecting to the first bit cell; a second word line spanning the plurality of bit cells, the second word line including a wire disposed in the second metal layer, the wire disposed in the second metal layer connecting to the second bit cell; and a second bit line.

51. 51. The apparatus of claim 50, further comprising a third bit cell adjacent to the second bit cell in the plurality of bit cells, the third bit cell being on an opposite side of the second bit cell from the first bit cell, and the wire disposed in the first metal layer connecting to the third bit cell.

52. 52. The apparatus of claim 51, further comprising a fourth bit cell adjacent to the third bit cell in the plurality of bit cells, the fourth bit cell being on an opposite side of the third bit cell from the second bit cell, and the wire disposed in the second metal layer connecting to the fourth bit cell.

53. 51. The apparatus of claim 50, wherein the bit cells are adjacently arranged in a first direction, and the first word line and the second word line span the plurality of bit cells in the first direction.

54. the first word line and the second word line span the plurality of bit cells in a first direction, and the device comprises: a first bit line spanning the first bit cell in a second direction, the second direction being perpendicular to the first direction, the first bit line including an additional wire disposed within the first metal layer; 51. The apparatus of claim 50, further comprising: a second bitline spanning the second bitcell in the second direction, the second bitline including an additional second wire disposed in the second metal layer.

55. 51. The apparatus of claim 50, further comprising a word line logic cell coupled to the first word line and the second word line, the word line logic cell configured to provide separate control signals to the first word line and the second word line.

56. 1. A system comprising: a transistor region of an integrated circuit; a first metal layer disposed above the transistor region in a vertical dimension perpendicular to the transistor region; a second metal layer disposed below the transistor region in the vertical dimension perpendicular to the transistor region; a word line logic circuit; a first bank of memory cells disposed adjacent to the word line logic circuitry; a second bank of memory cells disposed adjacent to the first bank on an opposite side of the first bank from the word line logic; a first word line extending from the word line logic circuitry into the memory cells in the first bank, the first word line including a wire disposed in the first metal layer, the wire disposed in the first metal layer connecting to the memory cells in the first bank; a second word line extending from the word line logic circuit into the memory cells in the second bank, the second word line passing through the memory cells in the first bank and including a wire disposed in the second metal layer, the wire disposed in the second metal layer connecting to the memory cells in the second bank.

57. 57. The system of claim 56, further comprising a bit line logic circuit adjacent to and spanning the length of the first bank and the second bank.

58. a third bank of memory cells disposed adjacent to the word line logic circuitry; a fourth bank of memory cells disposed adjacent to the third bank on an opposite side of the third bank from the word line logic circuitry; the third bank and the fourth bank are adjacent to the bit line logic circuit on an opposite side of the bit line logic circuit from the first bank and the second bank; 58. The system of claim 57.

59. a third word line extending from the word line logic circuitry into the memory cells in the third bank, the third word line being a third wire disposed in the first metal layer and connecting to the memory cells in the third bank; a fourth word line extending from the word line logic circuitry into the memory cells in the fourth bank, the fourth word line passing through the memory cells in the third bank and being a fourth wire disposed in the second metal layer and connecting to the memory cells in the fourth bank; 60. The system of claim 58, further comprising:

60. 57. The system of claim 56, further comprising: a global control logic circuit coupled to said first bank and said second bank of memory cells, said global control logic circuit comprising one or more clocks and one or more decoders.

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