Tamper-detectable age sensor

Abstract

A sensor (100) and associated tamper detection method for estimating the operational age of an integrated circuit (105) undergoing performance degradation is disclosed. The sensor (100) is operable in a normal use mode or a read mode and includes a performance monitor (101) responsive to temperature and voltage stresses, and an anneal monitor (102) responsive to temperature stress. The performance monitor (101) is configured to receive an operating voltage (V_OP) of the integrated circuit (105) when the sensor is operating in the normal use mode. Each anneal monitor (102) is a pre-stressed monitor, and each performance monitor (101) and each anneal monitor (102) is configured to generate an output signal (S1, S2) indicative of performance degradation of the respective monitor when the sensor is operating in the read mode.

Description

[Technical field]

[0001] The present invention relates to tamper-aware age sensors and their use for in-chip monitoring of performance degradation and detection of tamper attacks that attempt to conceal the true operational age of an integrated circuit that contains the age sensor. [Background technology]

[0002] The present invention also relates to an age sensor for in-chip monitoring of performance degradation that allows for reliable estimation of the true operating age of an integrated circuit by taking into account abnormal or questionable operating conditions of the integrated circuit that includes the age sensor.

[0003] Age sensors, also called age monitoring sensors, silicon age monitors, silicon odometers or performance degradation monitors, are on-chip components widely used for in-situ monitoring of integrated circuits (ICs) or their parts for malfunctions caused by ageing and degradation effects, i.e. aging effects, that adversely affect the performance of the IC or even jeopardize the correct functioning of the IC. In such cases, the output signal of the age sensor can be used to take preventive or protective measures, such as adjusting the operating conditions of the IC. Typically, the clock frequency of the IC is reduced.

[0004] Apart from implementing protective measures for the safe operation of ICs, on-chip age sensors are frequently used as an anti-counterfeiting measure. Indeed, obtaining or deriving an estimate of the IC's working age from the output of an on-chip age sensor allows customers to compare the estimated sensor-based working age of the IC with the declared age of the IC from the distributor. On the one hand, it allows detection of counterfeit or tampered ICs in case of counterfeiting of integrated circuits, where the sensor-based age information differs from the age information declared by the distributor. On the other hand, matching the sensor-based age information with the age information declared by the distributor of the IC gives customers peace of mind that they can trust the distributor.

[0005] Accurately estimating the true working age of semiconductor ICs becomes increasingly important in the context of a circular economy where chips are recycled (e.g., still-functioning chips are removed from damaged or non-functioning circuit boards and refurbished for reuse in new electronic devices). The quality and service life of new electronic devices that contain recycled chips heavily depend on the working age of the recycled chips. Especially when chips are scarce in the global market, customers may be tempted to buy recycled chips from unreliable sellers who may offer them at low prices, but they are not sure whether the working age of the recycled chips declared by the sellers corresponds to their true working age. Also, unscrupulous sellers may try to artificially make recycled chips look like new by annealing them at high temperatures to fix defects.

[0006] Accurate estimation of the true operational life of semiconductor ICs is crucial in military and medical equipment where human lives depend on the reliable functioning of the semiconductor chip for its entire life, which is usually detailed by the vendor. Military and medical equipment are generally expensive and often only pay for themselves once the equipment has been in use for its entire life.

[0007] Publication US 2014 / 0103344 (Tehranipoor [US] et al.) April 17, 2014 discloses an apparatus for distinguishing used integrated circuits, such as recycled or counterfeit ICs, from unused ones. In one embodiment, the apparatus (die recovery sensor) is integrated into an IC and includes a stressed ring oscillator (i.e., a voltage-stressed ring resonator) and a reference ring oscillator. The frequency shift between the stressed ring oscillator and the reference ring oscillator serves as a fingerprint of the IC and is indicative of the age of the IC. Furthermore, statistical data analysis allows separation of process and temperature variations from the effects of aging.

[0008] The disclosed device has the drawback that a reference ring oscillator is always required to estimate the age of the IC, which makes the reliable functioning of the device vulnerable to tampering attacks performed on the reference ring oscillator. Furthermore, the stressed ring oscillator can be manipulated by an anneal attack to at least partially reverse the degradation suffered and hide the true age of the IC containing the stressed ring oscillator. The anneal attack is performed at high temperatures that are much higher than the expected variations in operating temperature that are the basis for the statistical data analysis of the disclosed device.

[0009] Therefore, there is a need for an age sensor that can accurately estimate the operational age of an integrated circuit and whose true operational age cannot be easily concealed by tampering attacks, particularly annealing attacks. Summary of the Invention [Problem to be solved by the invention]

[0010] It is an object of embodiments of the present invention to provide an age sensor for an integrated circuit that accurately estimates the operational age of the integrated circuit and notifies a user of unauthorized annealing attacks aimed at artificially rendering the integrated circuit as good as new. [Means for solving the problem]

[0011] The above objectives are achieved by a method and apparatus according to the present invention.

[0012] In a first aspect, the present invention relates to a sensor for estimating the operational age of an integrated circuit undergoing performance degradation. The sensor is selectively operable in a normal use mode or a read mode and includes at least one performance monitor responsive to temperature stress and voltage stress, the at least one performance monitor configured to receive as an input signal a nominal operating voltage of the integrated circuit when the sensor is operating in the normal use mode and thus undergoes performance degradation. The sensor includes at least one anneal monitor responsive to temperature stress, each anneal monitor being a pre-stressed monitor to allow for accelerated mitigation of performance degradation in the performance monitor and anneal monitor during an incorrect anneal attempt. Each performance monitor and each anneal monitor is configured to generate an output signal indicative of the performance degradation of the respective monitor when the sensor is operating in the read mode.

[0013] The sensor is an age sensor because it can monitor a degradation state that depends on the age of the performance monitor, which in embodiments where the sensor is incorporated into an integrated circuit represents a degradation state of the integrated circuit. The sensor can detect a rogue anneal attack that subjects the sensor to a high temperature annealing treatment with the goal of reversing or nullifying the degradation suffered by the performance monitor. This detection capability is achieved by a second monitor, the anneal monitor, which is a pre-stressed monitor, in which the anneal attack reduces the original high initial degradation present in the pre-stressed monitor.

[0014] In a second aspect, the present invention relates to a sensor for estimating the operational age of an integrated circuit undergoing performance degradation. The sensor is selectively operable in a normal use mode or a read mode and includes at least one performance monitor responsive to temperature and voltage stresses, the at least one performance monitor configured to receive as an input signal a nominal operating voltage of the integrated circuit when the sensor is operating in the normal use mode and thus undergoing performance degradation. The sensor includes at least one anneal monitor responsive to temperature stress. Each anneal monitor includes an electrical isolation structure that permanently disconnects and insulates an input connector of the anneal monitor from the nominal operating voltage. Additionally, each performance monitor and each anneal monitor are configured to generate an output signal indicative of the performance degradation of the respective monitor when the sensor is operating in the read mode.

[0015] The electrical isolation structure may be fusible and provided as part of the input connector of each anneal monitor that has been fused to leave a gap, the electrical isolation structure preventing a user from accessing the input connector of each anneal monitor and applying a voltage stress signal.

[0016] According to an embodiment of the present invention, the sensor may include a readout unit configured to detect output signals generated by the performance monitors and the anneal monitor and to determine a performance variable of each performance monitor and each anneal monitor based on the detected output signals, the performance variable being a digital representation of a performance state of the respective monitor.

[0017] The invention also relates to a sensor system comprising an age sensor of the first aspect and an analysis unit configured to receive the performance variables determined by the readout unit, to detect changes in the performance variables of each performance monitor and to generate an estimate of the operational age of the integrated circuit based thereon.

[0018] It is an advantage of embodiments of the present invention that in ICs that include age sensors, in-situ performance degradation monitoring can be obtained simultaneously with tamper detection, which is a critical source of information that chip manufacturers are often eager to obtain for feedback. This field data allows chip manufacturers to identify reasons for chip failure when the chip is reaching the end of its useful life or in case of premature failure, allowing chip manufacturers to continuously improve their processing processes. The field data also allows comparison of the actual aging degradation incurred by the chip with a chip aging model developed based on accelerated device testing.

[0019] It is an advantage of embodiments of the present invention that they are able to generate a sensor output that can be subject to tamper attacks without the need for a reference signal generator.

[0020] It is an advantage of embodiments of the present invention that the output signal generated by the age sensor can be analyzed in software or hardware, e.g. post-processed and further analyzed. Hardware or software implementations of an analysis unit to this effect can be provided. A software implementation of the analysis unit, or an analysis unit consisting of existing components of an IC that also contains the age sensor, has the advantage that the age sensor itself requires fewer resources, is smaller and is cheaper.

[0021] It is an advantage of embodiments of the present invention that a single age sensor can detect various fraudulent attacks such as annealing attacks, i.e. high temperature annealing attacks, and overvoltage attacks (e.g., when the age sensor is overclocked by applying a high operating voltage (higher than the nominal operating voltage) to an IC to which it is further connected).

[0022] An advantage of embodiments of the present invention is that the tamper-resistant age sensor can be provided in a compact form, for example as an IP block for integrated circuit design, which can be easily integrated and reused in many different IC designs. No additional processing masks or materials are required during IC manufacturing, only the allocation of design space for the IP block. Furthermore, the tamper-resistant age sensor can be easily adapted to function reliably for a variety of manufacturing technologies, including commercial CMOS technology nodes.

[0023] It is an advantage of embodiments of the present invention that different degradation mechanisms, such as bias temperature instability (positive and / or negative), hot carrier degradation, and / or electromigration, can be taken into account in a single age sensor. More specifically, the different relaxation behaviors associated with these different degradation mechanisms can be advantageously taken into account, thereby providing a more accurate estimate of the operational age of an IC that includes the age sensor. A preferred age sensor has a performance and / or anneal monitor that is specifically adapted to enhance one of the degradation mechanisms that contribute to the aging of an IC that includes the age sensor over other degradation mechanisms. Certain embodiments of the present invention can include a performance monitor in the age sensor that is specifically adapted to enhance hot carrier degradation, e.g., a hot carrier injection enhanced performance monitor, the generated output signal of which is more sensitive to the usage time of the IC that includes the age sensor, thereby allowing a more accurate estimation of the operational time / age of the IC.

[0024] In yet another aspect, the present invention relates to a method of detecting fraudulent anneal attempts in an age monitor integrated circuit, the method comprising providing a sensor of the first or second aspect of the present invention, detecting performance degradation of at least one anneal monitor of the sensor, and signaling anneal tampering if the detected performance degradation of the at least one anneal monitor is below a predetermined threshold.

[0025] The method may further include subjecting the at least one performance monitor of the sensor to a constant voltage stress by applying a nominal operating voltage of the integrated circuit to an input of the at least one performance monitor, with no voltage stress being applied to the pre-stressed at least one anneal monitor. Thereafter, performance degradation of the at least one performance monitor is detected, and provided there is no signal indication of anneal tampering, an operational age of the age monitor integrated circuit is estimated. The estimate is based on the detected performance degradation of the at least one performance monitor.

[0026] According to an embodiment of the present invention, providing the sensor of the first aspect may include providing at least one performance monitor and at least one anneal monitor, the at least one performance monitor and the at least one anneal monitor configured to generate output signals indicative of a degradation state of the respective monitor in response to a voltage stress and a temperature stress; subjecting the at least one anneal monitor to a voltage stress signal by applying a voltage stress signal to an input connector of the at least one anneal monitor, thereby achieving pre-stressing of the at least one anneal monitor by accelerated degradation under the applied voltage stress signal; and permanently insulating the input connector of the at least one anneal monitor so that it is inaccessible upon further application of the voltage stress signal. Permanently insulating the input connector of the at least one anneal monitor may include blowing a fuse provided in a fusible portion of the input connector of the at least one anneal sensor, the blowing of the fuse occurring simultaneously with pre-stressing the at least one anneal monitor.

[0027] Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Features from the dependent claims may be combined with features of the independent claims and with features of other dependent claims as appropriate and not merely as explicitly set out in the claims.

[0028] For purposes of summarizing the invention and the advantages achieved over the prior art, certain objects and advantages of the invention have been described herein above. Of course, it should be understood that not necessarily all such objects or advantages can be achieved in accordance with any particular embodiment of the invention. Thus, for example, one skilled in the art will recognize that the invention may be embodied or practiced in a manner that achieves or optimizes one advantage or advantages taught herein, without necessarily achieving other objects or advantages as may be taught or suggested herein.

[0029] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiment(s) described hereinafter. [Brief description of the drawings]

[0030] The invention will now be further described, by way of example only, with reference to the accompanying drawings, in which: [Figure 1] FIG. 1 shows an age sensor according to one embodiment of the present invention. [Diagram 2] FIG. 2 is a diagram illustrating how a fraudulent anneal attempt can differently affect the degradation state of a pre-stressed anneal monitor and an initially unstressed performance monitor that can be used for tamper detection in embodiments of the present invention. [Diagram 3] FIG. 3 illustrates a ring oscillator-based implementation of a performance monitor and an anneal monitor that can be used in embodiments of the present invention. [Figure 4] FIG. 4 shows a different implementation of a performance monitor that uses a reference ring oscillator to achieve a pulsating tone in the output signal generated by the performance monitor and the reference ring oscillator. [Diagram 5]FIG. 5 is a variation of the ring oscillator-based performance and anneal monitor implementation shown in FIG. [Figure 6] FIG. 6 illustrates an age sensor of one embodiment of the present invention that includes a number of specially designed performance monitors and a number of corresponding pre-stressed anneal monitors. [Figure 7] FIG. 7 illustrates a tamper-detecting sensor system of one embodiment of the present invention, including an age sensor and an analysis unit. [Figure 8] FIG. 8 is a graphical representation of a response model for the performance degradation state of a performance monitor or anneal monitor as a function of operating time and operating temperature or operating time and operating voltage table that can be used in embodiments of the present invention. [Figure 9] FIG. 9 is a graphical representation of a response model for the performance degradation state of a performance monitor or anneal monitor as a function of operating time and operating temperature, or operating time and operating voltage, that may be used in embodiments of the present invention. [Figure 10] FIG. 10 illustrates a test IC including an array of age sensors according to an embodiment of the present invention.

[0031] The drawings are only schematic and non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn to scale for illustrative purposes. The dimensions and relative dimensions do not necessarily correspond to actual reduction to practice of the invention.

[0032] Any reference signs in the claims shall not be construed as limiting the scope. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033] The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims.

[0034] The terms first, second, etc. in this specification and claims are used to distinguish between similar elements and are not necessarily used to describe an order in time, space, precedence, or in any other way. The terms so used are interchangeable under appropriate circumstances, and it should be understood that the embodiments of the invention described herein can operate in orders other than those described or illustrated herein.

[0035] It should be noted that the term "comprising" used in the claims should not be interpreted as being limited to the means listed thereafter, nor should it exclude other elements or steps. Thus, the term should be interpreted as specifying the presence of stated features, integers, steps or referenced components, but should not exclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression "a device comprising means A and B" should not be limited to a device consisting of only components A and B.

[0036] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification do not necessarily all refer to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure, in one or more embodiments.

[0037] Similarly, in describing exemplary embodiments of the invention, it should be understood that various features of the invention may be grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in understanding one or more of the various inventive aspects. However, this method of disclosure should not be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of the invention.

[0038] Furthermore, some embodiments described herein include some features and not other features included in other embodiments, but combining features of different embodiments is meant to be within the scope of the present invention and forms different embodiments, as would be understood by one of ordinary skill in the art.

[0039] In the description provided herein, numerous specific details are set forth. However, it will be understood that embodiments of the present invention may be practiced without these specific details. In other instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this specification.

[0040] A sensor for estimating the operational age of an integrated circuit undergoing performance degradation is also referred to herein as an age sensor. Tamper-awareness of an age sensor means that the age sensor is able to detect tamper attacks, in particular unauthorized annealing attacks, collect information and inform or warn the user accordingly. Thus, even if the age sensor is not resistant to tamper attacks per se, i.e. in the sense that it can be physically manipulated with unauthorized intent, a tamper-aware age sensor is tamper-resistant in the sense that it can reliably detect tamper attacks. In the following description, the terms tamper-aware, tamper-resistant and tamper-proof are used synonymously.

[0041] In a first aspect, the present invention relates to an age tamper-recognition sensor for estimating the operational age of an integrated circuit (IC) or integrated circuit die. Age sensors are typically incorporated into ICs whose ages are monitored.

[0042] FIG. 1 shows a tamper-recognizing age sensor 100 according to an embodiment of the present invention. The age sensor 100 includes a performance monitor 101, a pre-stressed anneal monitor 102, an input signal selector 104, and means 103 for permanently isolating the anneal monitor 102 from an input signal connector receiving a nominal operating voltage V_OP of the IC. The operating mode of the age sensor 100 can be switched between a normal use mode and a read mode, which is further described below. Typically, the age sensor 100 forms part of a larger integrated circuit (IC) die 105 and is provided, for example, as an on-chip sensor module for in-situ monitoring of performance degradation. The IC die 105 is powered and operated at a nominal operating voltage V_OP, for example V_OP=0.9V. The output signals S1, S2 of the age sensor 100 are provided to a read unit 106, which is adapted to detect and convert the output signals S1, S2 into digital signals representative of the degradation levels of the performance monitor 101 and the anneal monitor 102, respectively. An input of the analysis unit 107 is connected to the output of the readout unit 106. The analysis unit is configured to determine an estimate of the operational age of the IC 105 including the age sensor 100 and further to detect tampering of the IC 105 including the age sensor 100, in particular unauthorized annealing attacks.

[0043] Although shown as being part of the IC die 105, the readout unit 106 may be an integral part of the age sensor 100 in alternative embodiments of the invention, or may be shared between different age sensors in embodiments of the invention including multiple age sensors. In certain embodiments of the invention, the readout unit 106 may be provided off-chip, such as when the output signals S1, S2 are provided to a pair of readout electrodes (e.g., pads) from which they can be read out by a needle probe. Similarly, in alternative embodiments, the analysis unit 107 may be provided as part of the age sensor 100, or may even be external to the IC die 105. The analysis unit may be implemented in hardware, for example as a dedicated or general-purpose processing unit, or in software.

[0044] The performance monitor 101 is a measurement circuit suitable for monitoring the performance degradation of its underlying circuit components (e.g., transistors), which is assumed to be representative of the performance degradation experienced by the IC die 105 on which the age sensor 100 is mounted. The performance monitor 101 is thus configured to receive as an input signal the nominal operating voltage V_OP of the IC 105 when the age sensor 100 is operating in a normal use mode. This input signal exerts a voltage stress on the components of the performance monitor 101, which causes the components to degrade (e.g., by the generation of defects) depending on the magnitude, duration and frequency (if applicable) of the input signal. The degradation mechanisms include bias temperature stress, which is a static stress component exerted on the transistor gate subjected to a bias voltage, and hot carrier degradation, electromigration, or a combination of both, which are dynamic stress components caused by high energy carrier generation in the conductive channel. These degradation mechanisms are well known in the field of reliability testing of semiconductor devices and are described in more detail in state-of-the-art publications. Performance monitor 101 is further configured to generate an output signal S1 indicative of a performance degradation state of age sensor 100 when age sensor 100 is operating in read mode.

[0045] In order to make age sensor 100 tamper-recognition enabled, an anneal monitor 102 is provided in addition to performance monitor 101. Similar to performance monitor 101, anneal monitor 102 is a measurement circuit suitable for monitoring the performance degradation of its underlying circuit components (e.g., transistors). Anneal monitor 102 is configured to receive a measurement voltage V_MS and generate an output signal S2 indicative of its performance degradation state when age sensor 100 is operated in a read mode. However, anneal monitor 102 is inactive, e.g., unpowered, when age sensor 100 is operated in a normal use mode. In contrast to performance monitor 101, anneal monitor 102 is disconnected from the nominal operating voltage V_OP of IC 105 when age sensor 100 is operated in a normal use mode. Furthermore, anneal monitor 102 is a pre-stressed monitor, i.e., a monitor characterized by a significant amount of initial performance degradation. In other words, the pre-stressed components of anneal monitor 102 contain a large amount of defects, e.g., more defects than are present in the components of performance monitor 101 that are intentionally introduced during manufacture. Pre-stressing anneal monitor 102 is described in more detail below.

[0046] Preferably, embodiments of the present invention use performance monitors that are unstressed, i.e., have substantially no initial pre-stress and contain only a limited number of defects in the component parts. Thus, the performance monitors are generally not subject to accelerated aging caused by high voltage stress signals during manufacture. However, alternative embodiments of the present invention may tolerate some degree of pre-stressing of the performance monitor, provided that the amount of pre-stress of the anneal monitor significantly exceeds the amount of pre-stress of the performance monitor, e.g., greater than 10%, more preferably greater than 20%, e.g., 30% or more, e.g., 50%-80%. Those skilled in the art will appreciate that the amount of pre-stress can be quantified in a variety of terms, such as the average defect density present in the performance monitor or anneal monitor components (e.g., gate oxide defects in FETs), a frequency shift in a frequency-based performance monitor or anneal monitor (e.g., operates at a particular frequency that is degrading and generates an output signal related to this frequency), a current shift in a current-based performance monitor or anneal monitor (e.g., operates or switches at a particular current that is degrading and generates an output signal related to this current), a threshold voltage shift in a performance monitor or anneal monitor that uses FETs, etc.

[0047] Performance monitor 101 and anneal monitor 102 may be implemented as identical structures (different only in the number of defects) or different structures. Implementations of performance monitor 101 and anneal monitor 102 may include, but are not limited to, the following electronic structures or devices: current mirrors, ring oscillators, and single transistor devices (e.g., FETs). Even when implemented as similar structures, e.g., ring oscillators, performance monitor 101 and anneal monitor 102 may differ in certain design parameters, such as a different number of oscillator stages (e.g., inverter stages) in the ring oscillator structure.

[0048] The readout unit 106 is adapted to detect the output signals S1, S2 generated by the monitors 101, 102. By way of example, the readout unit 106 may include or consist of a current sensor if the performance monitors and the anneal monitor are implemented as current mirrors, or may include or consist of a frequency counter if the performance monitors and the anneal monitor are implemented as ring oscillators.

[0049] In another example, a single device FET can be used as a performance monitor and / or an anneal monitor. In this case, a FET-based monitor can be used as a power switch for a ring oscillator, with the ring oscillator acting as a load. One or more pFETs in the inverter stage of the ring oscillator can be connected to one FET-based monitor that is degrading. The current in the power switch can be read by a readout unit, which may include circuits such as current mirrors, sense amplifiers, and current-to-voltage converters.

[0050] The input isolation means 103 is preferably a permanent tamper-proof disconnection means or access blocking means, such as an intentional gap in a current conductor or an intentionally broken input pin. In a preferred embodiment, the input isolation means 103 is provided as a fusible connection, e.g., a fuse, that is blown such that an open circuit connection is established between the anneal monitor 102 and an input connector receiving the nominal operating voltage V_OP of the IC. This ensures that once the anneal monitor 102 has been successfully manufactured, packaged, and pre-stressed, a user cannot tamper with the anneal monitor 102 with unauthorized intent. The fusible connection of the input isolation means 103 has the advantage that it can be specifically designed to blow after forcing a predetermined current through it. This allows the amount of pre-stress applied to the anneal monitor 102 to be precisely controlled, and is automatically terminated when the fusible connection blows. Here, the amount of pre-stress can be defined by the constant or time-dependent voltage or current stress signal used to achieve the accelerated performance degradation of the anneal monitor, and the duration for which the voltage or current stress signal is applied to the anneal monitor. Typically, the accelerated degradation voltage stress signal is greater in magnitude than the nominal operating voltage V_OP applied during normal use mode. Typically, the nominal operating voltage to which the age sensor is subjected is equal to or close to the positive supply voltage (e.g., VDD) of the IC containing the age sensor, e.g., 0.7V to 1.3V, whereas the accelerated degradation voltage stress signal may be 1.5 to 3 times greater than the nominal operating voltage (e.g., if the nominal operating voltage of interest is 0.9V, an accelerated voltage stress signal of 2.4V may be applied).

[0051] The input signal selector 104 is preferably implemented as a selection circuit, such as a set of multiplexing structures or a set of transmission gates, and is controllable via a selection signal SEL that allows the age sensor 100 to be switched between a normal use mode and a read mode.

[0052] In this embodiment, input signal selector 104 is configured to operably connect performance monitor 101 to a nominal operating voltage V_OP when age sensor 100 is operating in a normal use mode, thereby subjecting the performance monitor to the (normal) voltage stress experienced by an IC in which the age sensor is integrated. In contrast, input signal selector 104 is configured to operably connect performance monitor 101 to a measurement voltage V_MS when age sensor 100 is operating in a read mode. As a result, input signal selector 104 selectively connects performance monitor 101 to either the operating voltage V_OP or the measurement voltage V_MS depending on the currently selected operating mode for age sensor 100. With respect to anneal monitor 102, input signal selector 104 allows anneal monitor 102 to be selectively connected to and disconnected from measurement voltage V_MS. The anneal monitor 102 is preferably operably connected to the measurement voltage V_MS when the age sensor 100 is operating in a read mode, but is preferably disconnected from the measurement voltage V_MS when the age sensor 100 is operating in a normal use mode. This ensures that the anneal monitor 102 is not subjected to unnecessary voltage stress and also reduces energy consumption. During the manufacturing and pre-stressing steps of the age sensor, for example while manufacturing the age sensor of the present invention, the input isolation means 103 may not yet be present or may not yet be functional. For example, the fuse portion of the fusible connection as the input isolation means has not yet been blown. Thus, the input signal selector 104 may be used to operably connect the accelerated performance degradation high voltage stress signal to the input connector receiving the nominal operating voltage during the pre-stressing steps performed on the anneal monitor.

[0053] In some embodiments of the present invention, the measured voltage may be smaller than the nominal operating voltage, i.e., V_MS < V_OP, and the measured voltage is applied at a time interval shorter than the nominal operating voltage. This has the advantage that, in contrast to the constant voltage stress applied by the nominal operating voltage during normal use mode, each performance degradation measurement cycle (in the read mode) contributes only very little, for example negligible, to the overall performance degradation state of the performance monitor 101. In a particular embodiment of the present invention, the age sensor is configured to generate a measured voltage based on the nominal operating voltage, for example via an internal voltage division circuit. In other embodiments of the present invention, the measured voltage may be equal to or even greater than the nominal operating voltage. This can be the case, for example, when the operating voltage (such as that of a CPU) can change dynamically, for example when it drops from a high voltage (e.g., the CPU operates in burst mode) to a low voltage (e.g., the CPU operates in low energy mode).

[0054] The output signals S1, S2 can be continuously generated by the monitors 101, 102 so as to be available during normal use mode and read mode. Optionally, an output enabling structure (not shown in FIG. 1) can be provided to selectively supply the output signals S1, S2 only when the age sensor is operating in the read mode. In that case, a selection signal SEL, or another control signal, can be supplied as a control signal to the output enabling structure.

[0055] During operation, age sensor 100 is repeatedly switched between normal use mode and read mode such that performance degradation measurements are made, and output signals S1, S2 of monitors 101, 102 are generated and sampled at predetermined time intervals. More precisely, these performance degradation measurements are made when age sensor 100 is operating in read mode. Both performance monitor 101 and anneal monitor 102 are operatively coupled to a measurement voltage V_MS, which serves as a power supply for monitors 101, 102 during read mode. This coupling may occur via input signal selector 104 and preferably lasts for a short period of time, e.g., the time required for accurate reading of the output signals, e.g., tens to hundreds of microseconds. Performance monitor 101 and anneal monitor 102 then actively generate their respective output signals S1 and S2.

[0056] Between the two subsequent performance degradation measurements, i.e., when the sensors are operating in normal use mode, performance monitor 101 is subjected to a constant voltage stress by being connected to the nominal operating voltage V_OP of IC 105, e.g., by being connected to a power rail of IC 105 to supply the nominal operating voltage, while the anneal monitor remains disconnected from the operating voltage V_OP of IC 105 and is not subjected to voltage stress. As a result, performance monitor 101 is subjected to performance degradation when age sensor 100 is operating in normal use mode, while anneal monitor 102 is not subjected to performance degradation but rather is relaxed while age sensor 100 is operating in normal use mode.

[0057] The switching of the age sensor 100 between the normal use mode and the read mode may occur periodically at fixed time intervals, for example, without user intervention. Alternatively, the age sensor 100 may be configured to switch to the read mode upon receiving a control signal, perform a performance degradation measurement, and then switch to the normal use mode. The control signal may be issued via control software, e.g., a user requesting an output signal of the age sensor that requires a performance degradation measurement in the read mode, or via a hardware implemented controller. For example, the hardware or software implemented controller may be programmed according to a measurement schedule (e.g., daily, weekly, etc.), rule based (e.g., after each power on cycle), and / or event based (e.g., after detection of a performance peak (e.g., CPU load), supply voltage peak, etc.). In the read mode, it is not necessary to sample all output signals of the anneal monitor 102. The control bits of the control signal are set by the controller only when flagging an anneal, verifying the output signal from the performance monitor 101, or cross-referencing the output signals from both the performance monitor and the anneal monitor are requested.

[0058] The above-described method of operation of the age sensor is exemplary and can be modified in various ways: for example, the normal use mode and the read mode may be one and the same sensing mode of the age sensor, if the bias voltage for measuring the performance degradation corresponds to the nominal operating voltage of the IC and the output signal is continuously generated, e.g. continuously available at the output signal connector of a ring oscillator.

[0059] The tamper-recognition of age sensor 100, ie, the ability of age sensor 100 to detect tampering, particularly unauthorized annealing, will now be described.

[0060] The performance monitor 101 not only responds to a form of performance degradation induced by a constant voltage stress, i.e., the nominal operating voltage, but also to temperature changes. In other words, the performance degradation state of the performance monitor 101 evolves as a function of the applied voltage, the duration of the voltage stress, the relaxation time, and the temperature. This evolution of the performance degradation state is reflected by the output signal S1. As a further complication, the performance degradation state partially relaxes as soon as the performance monitor is no longer subjected to the voltage stress signal, e.g., when the voltage stress is removed. This is because some of the defects created in the components of the performance monitor (e.g., transistors, e.g., FETs) during the voltage stress condition are reversible and repair over time. Temperature in particular has a large effect on the relaxation and defect repair behavior of the performance monitor and age sensor in general. A strong anneal, e.g., above 200°C, e.g., between 200°C and 300°C, or even above 300°C, to make the age sensor look like new can be an efficient tamper attack, since it can artificially reduce the amount of performance degradation induced by the nominal operating voltage of the performance monitor. In fact, if the performance monitor of the age sensor is annealed such that only negligible performance degradation remains as indicated by the output signal S1, the age sensor, and thus any IC containing the age sensor, will appear to be new, allowing an unauthorized anneal attack to conceal the true operational age of the age sensor, and thus the true operational age of any IC containing the age sensor. Here, "negligible performance degradation remains" means that only performance degradation remains that can be expected from die-to-die variations in initial performance characteristics derived from the output signal of the performance monitor.

[0061] To avoid that the estimate of the operational age of an IC including an age sensor can be easily tampered with, for example, by placing the IC including the age sensor in an oven to perform an anneal of the IC, the age sensor 100 of the present invention also includes an anneal monitor 102. Like the performance monitor 101, the anneal monitor 102 responds to temperature changes, with the associated performance degradation level varying with relaxation time and temperature. However, unlike the performance monitor, the evolution of the performance degradation level of the anneal monitor 102 does not depend on the applied voltage stress and the duration of application of the voltage stress, since the anneal monitor 102 is disconnected from the nominal operating voltage V_OP of the IC 105 during the normal use mode of the age sensor 100, thereby ensuring that the anneal monitor is not subjected to a constant voltage stress during the normal use mode. As with the performance monitor 101, the evolution of the performance degradation state of the anneal monitor 102 is reflected by a corresponding output signal during the read mode of the age sensor, namely the output signal S2.

[0062] Anneal monitor 102 is a pre-stressed monitor, meaning that significant performance degradation is intentionally introduced into anneal monitor 102 during manufacturing. This can be accomplished by applying a high voltage stress signal to the anneal monitor for a predetermined period of time, which is higher than the nominal operating voltage, resulting in accelerated aging of the components in the anneal monitor or the IC containing the age sensor, either before or immediately after packaging of the age sensor or the IC containing the age sensor. Thereafter, once manufacturing of the age sensor is complete and before a user has purchased the age sensor, the corresponding input connector is isolated from the anneal monitor, for example, by intentionally breaking the electrical connection path between the input connector and the anneal monitor, by breaking or securely sealing the input connector, or by other suitable isolation means that cannot be easily tampered with.

[0063] Here, a significant amount of initial pre-stress on the anneal monitor refers to a performance degradation level, i.e., a level indicated by output signal S2, that is equal to or greater than the sum of the statistically expected performance variation of the anneal monitor before pre-stressing (i.e., in an unstressed state) and the expected mitigation of performance degradation over the rated or guaranteed life of the age sensor or IC containing it (e.g., 2-20 years, 2-10 years, or 2-5 years). The minimum amount of initial pre-stress on the anneal monitor 102 corresponds to the minimum amount of performance degradation induced during pre-stressing of the anneal monitor and observable through the output signal S2 generated by the anneal monitor. The amount of performance degradation induced during pre-stressing of the anneal monitor 102 can be defined relative to a baseline, e.g., a statistically expected average performance of an unstressed anneal monitor that is a predetermined value for a given semiconductor technology and layout of the age sensor. This baseline value is typically provided to the customer as part of a specification or manual for the age sensor or IC containing the age sensor.

[0064] The statistically expected performance variation of an anneal monitor relates to the statistical uncertainty of the performance of a given anneal monitor before pre-stressing, which is due to processing variations. A population of age sensors will have die-to-die variation with respect to the performance variable based on the output signal S2 of the anneal monitor 102 before pre-stressing. This variation remains in the population of age sensors even after the anneal monitor is pre-stressed and must be considered when determining the amount of pre-stressing. The statistically expected performance variation of an anneal monitor 102 before pre-stressing may be expressed as the standard deviation or a multiple of the performance variable when measured across the population of age sensors on different dies. Other measures of the statistical deviation of the performance variable may be used instead. Similarly, the statistically expected average performance of an unstressed anneal monitor corresponds to the average value of the performance variable based on the output signal S2 of the anneal monitor 102 before pre-stressing, e.g., measured for the population of age sensors on different dies. Depending on the particular implementation of anneal monitor 102, the performance variable may correspond to or be derived from the magnitude of output signal S2 itself, e.g., the leakage current of a FET, the current of a current mirror, etc. Thus, the statistically expected performance variation and the statistically expected average performance of anneal monitor 102 before pre-stressing correspond to a predetermined value that can be reproduced by statistical measurements of multiple aged sensors with unstressed anneal monitors.

[0065] In an exemplary embodiment, the performance variable based on the output signal S2 generated by the anneal monitor 102 may deviate from a predetermined reference value by 10% or more for the anneal sensor 120 to be considered pre-stressed. For example, the initial deviation of the performance variable (e.g., the current of a current mirror or the frequency of a ring oscillator) from a reference value may be greater than 20%, e.g., 20%-80%, e.g., 30%-70%, e.g., 50%-60%, in a new age sensor immediately after pre-stressing the anneal monitor. This deviation may decrease over time as a result of non-malicious degradation mitigation, e.g., reaching 10%-30%, e.g., 10%-20%, at the end of the useful life of the age sensor or IC including the age sensor. The decrease in deviation at the end of the useful life of the age sensor or IC including the age sensor corresponds to the above-mentioned expected mitigation of performance degradation of the anneal monitor over its rated or recommended life. Depending on the application and conditions of use, the service life of an age sensor or an IC containing an age sensor can range from 5 to 20 years.

[0066] FIG. 2 illustrates how the pre-stressed anneal monitor enables the detection of unauthorized annealing aimed at artificially making the age sensor or an IC containing the age sensor 100 like new. The original state of the performance monitor 21 and the anneal monitor 22, e.g., immediately after manufacture and pre-stressed, is shown diagrammatically on the left side of FIG. 2 (solid circle and square markers). The pre-stressed anneal monitor 22 is originally degraded as a result of the pre-stressing to a level d+r, where r is the tamper detection threshold and d is the gap between the threshold r and the intrinsic degradation of the pre-stressed anneal monitor 22. During normal use of the age sensor, the performance monitor 21 is subjected to voltage stress and degrades over time (stress time axis), while the anneal monitor 22 relaxes over time (relaxation time axis). As a result, the performance monitor 21 moves upwards along the diagonal and the anneal monitor moves downwards along the same line. Under normal use conditions, after a given operating time of the age sensor, the anneal monitor approaches threshold r (dashed square marker) without exceeding threshold r. At the same time, performance monitor 21 also accumulates damage and degrades (dashed circle marker). If the degradation of the anneal monitor does not fall below threshold r, the fraudulent anneal attempt will not be detected, resulting in a valid combination of degradation states measured for the performance and anneal monitors. In contrast, a fraudulent anneal attempt will reverse or even nullify the performance degradation of performance monitor 21, just like the original performance degradation of pre-stressed monitor 22. This situation is depicted on the right side of FIG. 2, where the solid markers show the results of a weak anneal attack and the dashed markers show the results of a strong anneal attack. The fraudulent attack causes a significant and abrupt shift or deviation in the output signal S2 generated by the anneal monitor, which is not expected under normal, i.e., non-fraudulent, use conditions of the age sensor or an IC equipped with the age sensor. At the end of the fraudulent anneal attack, the degradation state of the anneal monitor 22 falls below the threshold r, signaling the tampering.

[0067] Thus, tampering with the age sensor or the IC including the age sensor can be detected and flagged during read mode by determining a performance variable (indicative of a state of degradation) based on output signal S2 of anneal monitor 102, comparing the so determined performance variable with a predefined threshold and determining whether the threshold has been exceeded (above). These steps can be performed in software or hardware, e.g., in a software-implemented or hardware-implemented analysis unit. The analysis unit can be provided on-chip, e.g., as analysis unit 107 forming part of age sensor 100 or IC die 105 including age sensor 100, or can be provided external to age sensor 100 or IC die 105 including age sensor 100.

[0068] Additionally or alternatively, the software-implemented or hardware-implemented analysis unit may be programmed to determine an estimate of the operational age of the IC die 105 including the age sensor 100 based at least on the output signal S1 of the performance monitor 101, and to refute or verify the age estimate based on a determination of whether the determined performance variable of the anneal monitor exceeds a threshold value.

[0069] In an embodiment of the present invention, the analysis unit may additionally or alternatively be programmed to determine an estimate of the physical age of the age sensor or IC including the age sensor based on at least the performance variables determined for the anneal monitor 102, and to determine whether a combination of the physical age estimate and the operational age estimate is feasible / acceptable in the context of normal use conditions. If the combination is feasible, the age information obtained for the anneal monitor 102 may be used to refine the operational age estimate obtained for the performance monitor 101. If the combination is not feasible, an out-of-standard use of the age sensor or IC including the age sensor may be detected and the user may be notified accordingly. The exemplary analysis unit may be configured to receive or store a relaxation model of the performance variables obtained from the anneal monitor 102, which describes the performance of the anneal monitor as a function of relaxation time and temperature, and to calculate the relaxation time using the relaxation model of the anneal monitor and the measured performance variables as model inputs. A further model input, temperature, may be set to the nominal operating temperature of the age sensor or IC including the age sensor.

[0070] The analysis unit may be configured to combine information from multiple performance monitors and / or multiple anneal monitors in embodiments where the age sensor includes multiple performance monitors and / or multiple anneal monitors. Such embodiments are described below with reference to Figures 6 and 7. Combining information from multiple performance monitors and / or multiple anneal monitors has the advantage that different degradation mechanisms can be represented and modeled by the analysis unit, thereby allowing a more accurate estimation of the operating age. Similarly, combining information from multiple performance monitors and / or multiple anneal monitors has the advantage that the analysis unit can estimate the operating age differently on different time scales, for example using part of the information to estimate the operating age for the first hours or months and then using another part of the information to estimate the operating age for the remaining time of the useful life.

[0071] In an embodiment of the present invention, the analysis unit may also be programmed to estimate the remaining life of the age sensor or an IC including the age sensor, during which the age sensor or an IC including the age sensor can still operate reliably and safely in the event of failure.

[0072] FIG. 3 shows an example of a hardware implementation of a performance monitor 310 and an anneal monitor 320 that can be used in embodiments of the present invention. The performance monitor 310 and the anneal monitor 320 are measurement circuits that generate respective output signals S1, S2 when the age sensor is operating in a read mode. In this particular embodiment, the performance monitor 310 and the anneal monitor 320 are implemented as electronic ring oscillators, each consisting of a chain of inverter stages 311 (an odd number of them) and a feedback signal connection 312 that connects the output of the last inverter stage of the chain back to the input of the first inverter stage of the chain. The oscillation frequency of the ring oscillator is determined by the design of the individual inverter stages and is inversely proportional to the number of inverter stages in the respective chain. The number of inverter stages can vary depending on the technology and output signal detection technique used. The ring oscillators 310, 320 used in embodiments of the present invention can include 3 to 31 inverter stages and a typical fundamental oscillation frequency can be on the order of GHz, for example 1 to 2 GHz. These figures are given for reference only and embodiments of the present invention are not limited thereto. The output signals S1, S2 correspond to a portion of the free oscillation signal in the ring oscillators 310, 320 when biased by the measurement voltage V_MS during the read mode of the age sensor. This portion of the free oscillation signal in the ring oscillators may correspond to a portion of the feedback signal taken towards the output connectors of the performance monitor and the anneal monitor, respectively. The output signals S1 and S2 indicate the performance degradation state (i.e., the degradation level) of the respective ring oscillators and thus the performance degradation state of the integrated circuit or integrated circuit die containing the age sensor. In particular, the oscillation frequency of the output signals S1 and S2 allows a reliable and accurate characterization of the performance degradation suffered by the respective ring oscillators 310 and 320. During the normal use mode, the ring oscillator 310 corresponding to the performance monitor is biased by the nominal operating voltage V_OP, and therefore continues to oscillate and is subject to dynamic voltage stresses (e.g., induced by the load currents of the switching inverters of the inverter chain) and static voltage stresses (e.g., induced by the bias voltage V_OP applied to the inverters of the chain).In contrast, the ring oscillator 320 corresponding to the anneal monitor does not receive a bias voltage during normal use mode, so when the age sensor is switched to normal use mode, the ring oscillator 320 will stop oscillating and will degrade. In alternative embodiments of the present invention, the inverter stages of the ring oscillator may be replaced with other suitable electronic stages, such as NAND gates or NOR gates.

[0073] Referring now to FIG. 4, an alternative performance monitor 410 that can be used in the age sensor of the present invention is shown. This performance monitor is frequency-based, meaning that its generated output signal "OUT" conveys information about the performance degradation state of the performance monitor 410 as a detectable change in the output frequency. The performance monitor 410 includes two independent ring oscillators 411, 412. The first ring oscillator 411 is a functional part of the readout unit, generates an intermediate output signal having a first frequency f1, and preferably operates (i.e. oscillates) only during the readout mode. The second ring oscillator 412 generates an intermediate output signal having a second frequency f2, and operates (i.e. oscillates) during both normal use mode and readout mode. In this embodiment, the output signal of the first ring oscillator 411 serves as a reference for the output signal of the second ring oscillator 412.

[0074] The ring oscillator 412 is configured to receive a nominal operating voltage V_OP as an input signal for biasing the ring oscillator during normal use mode (bias connections for the read mode are not shown in FIG. 4) and therefore degrades under constant voltage stress. Temperature changes affect both ring oscillators 411, 412 independently of the voltage stress, and affect the performance degradation level of both ring oscillators, particularly through defect mitigation mechanisms. When the age sensor is switched to the read mode, an output signal having a first frequency f1 and an output signal having a second frequency f2 are superimposed, whereby the superposition of both output signals is the beating frequency. Here, the superposition of the output signals is understood to include the case where the two output signals are simultaneously applied to the input of the detection unit. The performance monitor 410 further includes a beating frequency detection unit 413 as a functional part of the readout unit of the age sensor including the performance monitor 410. The beat frequency detection unit 413 is configured to receive the output signals from the two ring oscillators 411 and 412, superimpose them if not done before receiving them, detect the beat frequency, and generate an output signal indicative of a frequency shift Δf between the first frequency f1 and the second frequency f2 based on the detected beat frequency. Exemplary beat frequency detection units include a flip-flop and a pulse counter. The flip-flop receives the output signal of the first ring oscillator 411 as a clock signal and the output signal of the second ring oscillator 412 as an input signal, and generates a pulse train at its output. The pulse train depends on the difference in frequencies Δf. The pulse counter is used to determine the frequency shift of this pulse train.

[0075] An alternative anneal monitor may include something similar to the performance monitor of Figure 4, i.e., a first ring oscillator as a reference and a second ring oscillator for degradation measurement, except that the second ring oscillator is pre-stressed and the input connector "IN" is made inaccessible to the nominal operating voltage V_OP, for example, by blowing a fusible pin immediately after fabrication and packaging.

[0076] Referring now to FIG. 5, a variation of the performance monitor and anneal monitor of FIG. 3 is shown with a readout unit 506. The ring oscillator 510 (i.e., corresponding to the performance monitor) and the anneal monitor 520 (i.e., corresponding to the anneal monitor) differ from the ring oscillator of FIG. 3 in that they include a NAND gate in the feedback signal connection as an electronic switch 511 for selectively opening and closing the feedback loop of the respective ring oscillator. The ring oscillator 510 with an open feedback line experiences only a static or DC voltage stress component since oscillation is prevented when biased by the nominal operating voltage V_OP such that the inverter stage of the ring oscillator 510 is still subjected to a constant voltage stress. This static voltage stress component causes degradation of the performance state of the ring oscillator 510 governed by the bias temperature instability (BTI) aging mechanism. Thus, the advantage of providing an electronic switch in the feedback line of the ring oscillator is that the effect of BTI aging and its mitigation over time can be detected separately from other aging mechanisms in a performance degradation monitor using this ring oscillator. On the other hand, when the electronic switch 511 is closed, it closes the feedback line of the ring oscillator 510, the ring oscillator biased at the nominal operating voltage V_OP is no longer prevented from oscillating, and the inverter stage of the ring oscillator starts to switch dynamically. As a result, the ring oscillator 510 with the closed feedback connection is simultaneously subjected to both static (i.e. DC) and dynamic (i.e. AC) voltage stress components. As mentioned above, the static voltage stress component causes the degradation of the performance state of the ring oscillator 510 dominated by the bias temperature instability (BTI) aging mechanism. This is joined by the dynamic stress component, which causes the degradation of the performance state of the ring oscillator 510 dominated by a hot carrier degradation (HCD) mechanism, e.g. hot carrier injection.A performance monitor using a closed feedback connected ring oscillator 510 cannot measure the static and dynamic voltage stress components independently of each other and cannot separate the BTI aging mechanism from the HCD aging mechanism. However, a possibility exists to enhance the HCD aging mechanism in the ring oscillator of the performance monitor, resulting in an HCD enhanced performance monitor where the effects of HCD dominate more strongly than those of BTI. This possibility is described below with reference to FIG. 6. An electronic switch 511 in the ring oscillator 520 corresponding to the anneal monitor is used to pre-stress the anneal monitor with different voltage stress scenarios, e.g., different combinations of the aging mechanisms described with reference to the ring oscillator 510.

[0077] In Fig. 5, transmission gates are used to relay bias voltages to the ring oscillators 510, 520 in a controlled manner. Different control signals are used for the ring oscillators 510 corresponding to the performance monitors to selectively bias the inverter stages of the ring oscillators at a nominal operating voltage V_OP when the age sensor is operating in normal use mode and at a measurement voltage V_MS when the age sensor is operating in read mode. One or more divider stages 512 are connected between a frequency counter 513 and the output of each of the ring oscillators 510, 520. The frequency counter 513 preferably includes a digital interface, which provides a digital output of the determined frequency count for the two ring oscillators 510, 520 in read mode. The divider stages 512 and the frequency counter 513 form part of the read module 506 of the age sensor. The divider stages 512 are optional and are only provided if the output signals of the ring oscillators 510, 520 are also accessible to an external measurement device, such as a needle probe. In such a case, output pads 514 are provided for inserting needle probes into the divider output signals S1, S2 of the ring oscillators 510, 520.

[0078] An input side transmission gate, or more generally electronic switching means, is advantageous in embodiments where a time dependent control of the voltage stress time, i.e. the time during which the nominal operating voltage, which is a constant voltage stress signal, is applied to the performance monitor, is required. In such an embodiment, a modulated version of the nominal operating voltage can be applied as an input signal subjecting the performance monitor to a constant voltage stress. Modulating the nominal operating voltage at the input of the performance monitor can be achieved by repeatedly enabling and disabling the input connection of the performance monitor via the input side switching means (e.g. an electronic switch). The modulation frequency of the applied nominal operating voltage can be set to be representative (e.g. proportional) of the operating load of the IC, including the age sensor, or other suitable activity indicator of the IC.

[0079] In some embodiments of the present invention, it may be advantageous to provide multiple performance monitors and / or multiple anneal monitors subjected to different stress conditions, allowing for more flexible or complete sensing of the stress parameters affecting the IC, including the age sensor.

[0080] For example, an age sensor including multiple performance monitors can be configured to operably connect each performance sensor to a different voltage stress signal when the age sensor is operating in a normal use mode. This is useful in applications where different portions of an IC are designed to operate at different voltages, e.g., a core voltage (i.e., a nominal operating voltage) and an I / O voltage, where the I / O voltage is greater than the core voltage, e.g., two times or more. Output from each performance monitor can be used to estimate the operational lifetime of different portions of the IC, and the outputs of the different performance monitors can be combined to obtain an estimate regarding the remaining lifetime of the IC as a whole.

[0081] Another example is to operably connect each performance sensor to a different voltage stress signal when the age sensor operates in a normal use mode, even when the IC uses a nominal operating voltage as the only power supply voltage, or when the nominal operating voltage of the IC is the only power supply voltage of interest for age sensing. The age sensor of an embodiment of the present invention can include a voltage divider structure and / or a voltage level shift structure to generate different voltage stress signals from the nominal operating voltage and provide the different voltage stress signals to the respective performance monitors. A performance monitor that receives a voltage stress signal that is 1.1 or 1.2 times higher than the nominal operating voltage during the normal use mode will age faster than a performance monitor that receives a lower voltage stress signal during the normal use mode. As a result, the degradation level of a performance monitor that receives a higher voltage stress signal during the normal use mode is more easily and reliably detected during the initial use period of the IC including the age sensor, e.g., the first few hours, weeks, or months (depending on the application), and the operational age of the IC during this initial period is more accurately estimated. After the initial period, a performance monitor that receives a higher voltage stress signal during the normal use mode may be too degraded to provide a more reliable estimate of the operational age. Thus, from this point on, estimates of the operational age of the IC may be obtained only for those performance monitors that experience lower voltage stress signals during normal use modes and are likely to experience less performance degradation. A less coarse division of monitoring time for individual performance monitors may be employed. The operational age estimates of the different performance monitors may be checked against a physical age estimate obtained from at least one anneal monitor. Similarly, one or more anneal monitors may be used to detect anneal tampering of the age sensor or the IC die that contains the age sensor.

[0082] Referring to FIG. 6, age sensor 600 is depicted that includes a set of performance monitors 610 and a corresponding set of pre-stressed anneal monitors 620. Although performance monitors 610 are shown as having the same number as anneal monitors, different combinations of the number of performance monitors and the number of anneal monitors are feasible. Each performance monitor 610-1-610-3 in the set of performance monitors 610 is configured to receive as an input signal the nominal operating voltage V_OP of the IC during normal use mode, while anneal monitors 620-1-620-3 are permanently disconnected from the nominal operating voltage V_OP, e.g., via fused input pin 603 that is fused immediately following manufacture of the age sensor. Although not shown in FIG. 6, performance monitors 610-1-610-3 and anneal monitors 620-1-620-3 can be operatively connected to a measurement voltage V_MS during a read mode. Output selectors 601 and 602, e.g., pass gates, multiplexing structures, etc., are provided to select output signals S1 and S2 from the set of performance monitors 610 and the set of anneal monitors 620, respectively. The output signals S1 and S2 are sent to a readout unit and an analysis unit, both of which can be provided either on-chip or off-chip. The age sensor, readout unit and analysis unit are elements of a tamper-recognizing age sensor system. In an alternative embodiment, the readout unit and analysis unit may be incorporated into the age sensor.

[0083] The performance monitors 610-1 to 610-3 are designed to respond differently to the nominal operating voltage of the IC when applied to each performance monitor in the normal use mode of the age sensor 600. Different responses mean different changes or shifts in the output signal of each performance monitor under the same stress conditions, i.e., the same voltage stress signal, voltage stress time, and operating temperature. Furthermore, the response of each performance monitor can be specifically designed to modify the contribution of a particular aging mechanism to the overall performance degradation of that performance monitor. For example, the first performance monitor 610-1 can be designed to degrade under the combined effects of BTI and HCD, and the evolution of its output signal, or the performance variable detected with respect to the output signal, is modified by a first response function r1(V stress , t stress , T), where T is the operating temperature of the performance monitor and the IC die, and t stress and V stress are the stress time and stress voltage, respectively. Here, the stress time refers to the operating time of the performance monitor, i.e., the time when the performance monitor is degraded under voltage stress. Note that from the perspective of the anneal monitor, the stress time is included in the relaxation time because the anneal monitor is not voltage stressed during normal use mode. The detected performance variables can be frequency or frequency shift (e.g., if the performance monitor is a ring oscillator), current or current shift (e.g., if the performance monitor is a current mirror or ring oscillator), threshold voltage shift (e.g., if the performance monitor is a FET), etc. Continuing with this example, a second performance monitor 610-2 can be designed to degrade primarily under the influence of HCD (i.e., an HCD-enhanced performance monitor), and the evolution of its output signal, or the performance variable detected with respect to the output signal, can be determined by a second response function r2(V stress , t stress Finally, a third performance monitor 610-3 may be designed to degrade exclusively under the influence of BTI (i.e., a BTI-only performance monitor), and the evolution of its output signal, or a performance variable detected with respect to the output signal, may be modeled according to a third response function r3(V stress, t stress , T). For each measurement cycle performed during the readout mode of the age sensor, the output signal measured for the performance monitor corresponds to a particular result R1, R2, and R3 of the respective response functions r1, r2, and r3. In other words, the tuple (V (i) stress , t (i) stress , T (i) ), the following correspondence holds: R1 = r1(V (i) stress、 t (i) stress , T (i) ), R2 = r2 (V (i) stress , t (i) stress , T (i) ), and R3=r3(V (i) stress , t (i) stress , T (i) ).

[0084] There are various ways to obtain different weightings of the effects of HCD and BTI with respect to the ageing process experienced in each performance monitor. A BTI-only performance monitor, in which the feedback loop of the ring oscillator-based performance monitor is interrupted by switching means and only static voltage stresses can be caused on the ring oscillator components, has already been described with reference to FIG. 5. A combination of the effects of BTI and HCD can be achieved by providing a ring oscillator-based performance monitor with a closed feedback loop, thus causing static and dynamic voltage stresses on the ring oscillator components. By reducing the number of stages in the ring oscillator, the effects of HCD can be strengthened over those of BTI. Reducing the number of stages results in faster switching of the ring oscillator and a higher oscillation frequency, making the effects of HCD more prominent. Alternatively, the capacitance value of each stage of the ring oscillator can be increased to produce a larger drive current and therefore a stronger effect of HCD.

[0085] Since BTI and HCD are characterized by different relaxation behaviors, providing different performance monitors specifically adapted to specific ageing mechanisms would also have the advantage of allowing more accurate measurement of relaxation times in age sensors.

[0086] The pre-stressed anneal monitors 620-1-620-3 can be designed to have a similar structure to the corresponding performance monitors 610-1-610-3, except that they are not subjected to constant voltage stress during normal use mode. This has the advantage that stress relaxation (i.e., defect relaxation for reversible defects) and temperature stress affect the performance monitors and the corresponding anneal monitors in the same way, which simplifies comparison and cross-referencing of their output signals, e.g., less signal post-processing steps are required to make the output signals of the performance monitors and the corresponding anneal monitors comparable. More specifically, the first anneal monitor 620-1 can have a BTI-only monitor design, the second anneal monitor 620-2 can have a combined BTI and HCD monitor design, and the third anneal monitor 620-3 can have a HCD-included monitor design. The evolution of the output signals generated by anneal monitors 620-1 through 620-3, or performance variables derived from these generated output signals, can be modeled according to response functions q1(T,t), q2(T,t), and q3(T,t), respectively, where variables T and t represent actuation temperature and relaxation time (e.g., time since fabrication), respectively. For each measurement performed during the read mode, the measured output signal of the anneal monitor is specified by the set of measured (i.e., detected) performance variables Q1, Q2, and Q3.

[0087] The analytical unit receives three independent measurements of the performance variables R1-R3 and, based on the model description of the three response functions r1-r3, calculates the three unknown parameters V stress , t stress, and T. Further, the analysis unit is configured to detect the presence of unauthorized annealing by comparing at least one of the measured performance variables Q1, Q2, Q3 with expected results of the corresponding response functions q1, q2, and q3 evaluated under normal use conditions for the operating temperature. This situation is depicted in FIG. 7 for a tamper-aware age sensor system 700 including a tamper-aware age sensor 701 including multiple performance monitors and multiple anneal sensors, and an analysis unit 702.

[0088] The analysis unit 702 is configured to receive and store in a model storage module 703 a model description (i.e., model) of the responses r1-r3 and q1-q3. The description relates the modeled sensor responses r1-r3 and q1-q3 to the measured performance variables R1-R3 and Q1-Q3, respectively. Figure 8 graphically illustrates a model using composite performance degradation measurements (e.g., in terms of output signal shift, e.g., frequency shift) of the performance monitors 610-1 and 610-3, i.e., the BTI-only and HCD-enhanced performance monitors, to interpolate pairs of operating temperatures T and operating times t (T, t) corresponding to the intersections of the performance degradation contour lines of the BTI-only and HCD-enhanced performance monitors, respectively. 9 illustrates a model using the composite performance degradation measurements (e.g., in terms of output signal shift, e.g., frequency shift) of performance monitors 610-1 and 610-2, i.e., the BTI-only and composite BTI+HCD performance monitors, to interpolate the applied voltage stress signal (i.e., the value of the IC's actuation voltage) and actuation time t pairs (V, t) corresponding to the intersections of the performance degradation contour lines for the BTI-only and composite BTI+HCD performance monitors, respectively. The two models illustrated in FIG. 8 and FIG. 9 can be combined and integrated into a single three-dimensional model that uses readouts from all three performance sensors 610-1, 610-2, 610-3 to determine the triples (V, T, t) of applied voltage stress signal / actuation voltage, temperature T, and actuation time t corresponding to the intersections of the performance degradation contour lines for the three performance monitors.

[0089] The response function can be modeled using an empirical model whose fitting parameters are pre-determined by statistical measurements of the performance monitor output signals for different die populations under various stress conditions, for example as graphically represented in Figures 8 and 9. For example, a power law dependency can be used to describe the frequency or current shift ΔS in the output signal of a ring oscillator based performance monitor, e.g. [Formula 1] TIFF2025510153000002.tif727 (where the constant A and exponents n1 and n2 are fitting parameters obtained from statistical performance degradation measurements for both static and dynamic voltage stress components). Furthermore, the relaxation behavior due to BTI effects and HCD effects can be considered by incorporating the universal recovery model and Stessmans passivation model, respectively.

[0090] The analysis unit 702 in FIG. 7 may be a post-processing unit implemented in hardware or software that is external to the age sensor 701, e.g. an off-chip post-processing unit implemented in hardware or software, which receives the output signal from the on-chip age sensor 701 via a readout unit and data transmission means, e.g. via an on-chip I / O circuit. In other embodiments of the invention, the age sensor system may be provided as an integrated system, i.e. an IC die including the age sensor and the analysis unit (including in the case of an age sensor including an analysis unit). Various signals or warnings O1, O2, O3 may be output by the analysis unit for each measurement in the readout mode of the age sensor and / or for a series of such measurements over time. The output signals or warnings O1-O3 generated by the analysis unit may include a state of health, an overvoltage flag, an operating age estimate, a tamper detection / flag, remaining life of the IC, etc. A series of measurements has the advantage that the analysis unit can reconstruct a usage trajectory of the IC including the age sensor. The usage trajectory may include the estimated stress conditions extracted for each measurement "i". <V (i)stress >, <t (i) stress >, <T (i) This allows users of recycled ICs to accurately see the IC's previous usage history and identify possible risks associated with overheating, annealing attacks, overvoltage conditions, overclocking, or run times of the IC that seem abnormal given its intended use.

[0091] According to an embodiment of the invention, an IC or IC die includes at least one tamper-recognizing age sensor. Typically, one or more free spaces in the design layout of the IC are allocated to a layout block for the age sensor. Often, one age sensor is sufficient to obtain the required age estimate for the IC. However, embodiments using several on-chip age sensors, e.g., an array or irregular structure of age sensors located adjacent to each other or distributed over the IC, may be useful if different parts of the IC are subject to different aging mechanisms. For example, if the IC is adapted to provide different operating voltages to different circuits or components that are part of the IC, or if different parts of the IC are subject to different cooling / thermal conduction, or are capable of operating with digital or analog signals, different clock speeds, etc. Instead of providing many different age sensors, one larger age sensor can be provided that includes multiple performance monitors and / or multiple anneal sensors. Different performance sensors can then be provided and configured to receive different operating voltages, to be switched on and off (during normal use mode) at different frequencies, etc.

[0092] An example of an IC 1000 including an array of age sensors 1001-1 through 1001-9 is shown in FIG. 10. Although only nine age sensors are shown for clarity, the IC 1000 can include a larger array of age sensors, e.g., hundreds of age sensors. The age sensors 1001-1 through 1001-9 may correspond to replicated unit cells of a single layout design of the age sensor. The IC 1000 may be a test IC of a test wafer that can be used to obtain ensemble statistics such as wafer statistics, die-to-die manufacturing variations, and intra-die manufacturing variations. For example, ensemble statistics regarding die-to-die manufacturing variations of oscillation frequencies of ring oscillator-based performance monitors and anneal monitors in the age sensor (e.g., but not limited to, respective mean values ​​and standard deviations) can be more easily collected using specially designed test ICs. Age sensors 1001-1 through 1001-9, IC 1000 further includes an on-chip readout unit 1006 (e.g., corresponding to a readout unit described herein above), and I / O circuitry 1002 configured to transmit performance degradation measurements off-chip, such as to an off-chip analysis unit 1007. Various additional components may be provided on IC 1000, such as, for example, layered shift registers for individually addressing multiple age sensors on a die, output pads for inserting needle probes into individual age sensors on the chip, voltage supply lines and voltage sources for providing nominal operating and measurement voltages to the age sensors of the array (e.g., a force sense arrangement for biasing the age sensors and simultaneously reading out the output signals).

[0093] The present invention also relates to a method for manufacturing the age sensor of the present invention, the method comprising the steps of: - providing at least one performance monitor and at least one anneal monitor, the at least one performance monitor and the at least one anneal monitor configured to respond to voltage and temperature stresses and to generate output signals indicative of a state of degradation of the respective monitor; - subjecting said at least one anneal monitor to a voltage stress signal by applying said voltage stress signal to an input connector of said at least one anneal monitor, thereby achieving pre-stressing of said at least one anneal monitor by accelerated aging / degradation under said applied voltage stress signal; and The method may include permanently disconnecting or isolating the input connector of the at least one anneal monitor so that it is inaccessible during application of further voltage stress signals.

[0094] In a preferred embodiment of the present invention, the age sensor is fabricated on a semiconductor die or chip, for example a packaged semiconductor chip or die that includes an IC that monitors aging.

[0095] In a preferred embodiment of the present invention, the at least one performance monitor is not pre-stressed during manufacture, e.g., when a purchaser begins using the IC with the age sensor, there is substantially no initial stress applied to the at least one performance monitor.

[0096] The disconnecting or isolating step can include blowing a fuse on a fusible portion of an input connector of the at least one anneal sensor, which may occur simultaneously with the pre-stressing step of the at least one anneal monitor, for example, if the pre-stressing step is terminated by blowing the fusible portion of the input connector as a result of an open circuit or non-conductive gap being formed in the input connector.

[0097] Pre-stressing the at least one anneal monitor may include pre-stressing the at least one anneal monitor for a time sufficient to accumulate a predetermined amount of performance degradation, e.g., a time sufficient to observe a measurable shift in an output signal generated by the at least one anneal monitor relative to a baseline value of the generated output signal. The baseline value may correspond to an average performance state of the at least one anneal monitor prior to pre-stressing, the average being a statistical average calculated across a collection of anneal monitors located at different locations on the same die and / or located on different dies.

[0098] Pre-stressing the at least one anneal monitor may include applying a constant voltage signal for a predetermined period of time, e.g., greater than a nominal operating voltage of the IC to be monitored, e.g., at least twice the nominal operating voltage, forcing a constant current for a predetermined period of time, or a combination of both. More generally, the applied voltage stress signal, or the forced current that induces the voltage stress signal, may be varied over time according to a stress protocol.

[0099] In embodiments of the invention, multiple performance monitors and / or multiple anneal monitors may be provided, with pre-stressing performed on each anneal monitor. Different performance monitors may be specifically adapted to enhance a particular aging mechanism compared to other aging mechanisms, e.g., to enhance a BTI aging mechanism or an HCD aging mechanism. Different performance monitors may be specifically adapted to obtain a predefined weighting for the contribution of each aging mechanism in affecting the performance state of the performance monitor.

[0100] The performance monitor and / or the anneal monitor may be provided as a ring oscillator.

[0101] In a further aspect, the present invention relates to a method for detecting unauthorized anneal attempts in an age monitor integrated circuit, the method comprising: - providing an age sensor of the first aspect of the invention, preferably by carrying out the steps of the manufacturing method of the second aspect of the invention; - detecting performance degradation of the at least one anneal monitor; and - signaling anneal tampering if the detected performance degradation of the at least one anneal monitor is below a predetermined threshold. Includes.

[0102] In an embodiment of the invention, the method also comprises: - subjecting the at least one performance monitor of the age sensor to a constant voltage stress by applying a nominal operating voltage of the integrated circuit to an input of the at least one performance monitor, where no voltage stress is applied to the at least one pre-stressed anneal monitor; - detecting performance degradation of the at least one performance monitor; and - estimating an operational age of the age monitor integrated circuit based on the detected performance degradation of the at least one performance monitor, provided that there is no indication of anneal tampering by a signal. It may also include.

[0103] Detecting the performance degradation of at least one performance monitor, e.g., each performance monitor, may include detecting a shift in an output signal generated by the at least one performance monitor and / or detecting a shift in a performance variable derived from the output signal generated by the at least one performance monitor. The shift in the output signal generated by the at least one performance monitor and / or the shift in the performance variable derived from the output signal generated by the at least one performance monitor may be detected relative to a reference value of the output signal and / or the performance variable derived from the output signal. The reference value may correspond to an average value of the performance state of the at least one performance monitor at or immediately after manufacture, i.e., before the step of subjecting the at least one performance monitor to a constant voltage stress, the average value being a statistical average value calculated over a collection of anneal monitors located at different positions on the same die and / or located on different dies. Alternatively, the shift in the output signal generated by the at least one performance monitor or the shift in the performance variable derived from the output signal generated by the at least one performance monitor may be detected relative to an output signal of a reference device or relative to a performance variable derived from the output signal of a reference device. This includes superimposing the output signals generated by at least one performance monitor and the reference device, e.g., pulsating the two output signals. The reference device is not voltage stressed when the at least one performance monitor is voltage stressed. All of the above steps can also be applied to at least one anneal monitor, e.g., each anneal monitor.

[0104] In a preferred embodiment of the present invention, the shift in the output signal generated by the at least one performance monitor corresponds to a frequency shift of a ring oscillator. In alternative embodiments, the shift in the output signal generated by the at least one performance monitor may correspond to a current shift of a current monitor, a load or leakage current shift of a transistor device (e.g., a FET), a threshold voltage shift of a transistor device (e.g., a FET), etc.

[0105] The step of subjecting the at least one performance monitor to a constant voltage stress may include repeatedly connecting and disconnecting the at least one performance monitor to a voltage stress signal line, the connection and disconnection preferably occurring at regular time intervals proportional to a workload or activity measurement of the IC monitored by the age sensor.

[0106] In an embodiment of the invention, the operational age of a monitor integrated circuit can be estimated by providing a response model for each performance monitor in the age sensor and determining the operational time using the response model and the detected performance degradation of each performance monitor as input to the response model. The response model describes the functional relationship between the detected performance degradation on the one hand and the operational time, voltage stress and operating temperature on the other hand.

[0107] In addition to operating time (i.e., years), other operating conditions of the performance monitor and the integrated circuit containing it can be determined from the response model, such as, for example, applied voltage stress signals and operating temperature, etc. Thus, over-voltage and / or over-temperature conditions can also be signaled.

[0108] The process of estimating the operational age may be repeated for multiple time instants. A usage trajectory of the age monitor integrated circuit may be obtained from the determined values ​​of the operational age, stress voltage and temperature at the multiple time instants. A true physical age of the monitor integrated circuit may be derived from the usage trajectory.

[0109] In an embodiment of the present invention, the response model preferably takes into account the relaxation behavior of different ageing mechanisms.

[0110] Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite articles "a" or "an" do not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be interpreted as limiting the scope.

Claims

1. A sensor (100) for estimating an operational age of an integrated circuit (105) undergoing performance degradation, said sensor (100) being selectively operable in a normal use mode or a read mode and including at least one performance monitor (101) responsive to temperature and voltage stresses, said at least one performance monitor (101) configured to receive as an input signal a nominal operating voltage (V_OP) of said integrated circuit (105) when said sensor is operating in said normal use mode and thus undergoing performance degradation; the sensor (100) includes at least one anneal monitor (102) responsive to a temperature stress; each anneal monitor (102) being a pre-stressed monitor taking into account said performance monitor during an incorrect anneal attempt and accelerated mitigation of said performance degradation in the anneal monitor; A sensor, wherein each performance monitor (101) and each anneal monitor (102) is configured to generate an output signal (S1, S2) indicative of performance degradation of the respective monitor when said sensor is operating in a read mode.

2. Each performance monitor (101) is substantially free of initial stress to account for performance degradation of said integrated circuit (105) during normal use; The sensor (100) of claim 1.

3. the amount of pre-stress applied to each anneal monitor (102) corresponds to a difference in the performance degradation indicated by the output signal generated by the pre-stressed anneal monitor relative to a predetermined reference value, the difference being at least 20% of the reference value, preferably at least 50% of the reference value; The sensor (100) of claim 1.

4. the predetermined reference value corresponds to a statistical average of a performance condition indicated by the output signal generated by an unstressed replica of the anneal monitor, the statistical average being formed for a collection of age sensors distributed on one or more integrated circuit dies; The sensor of claim 3.

5. an amount of pre-stress applied to each anneal monitor (102) corresponds to a difference in the performance degradation indicated by the output signal generated by the anneal monitor relative to a predetermined reference value, the difference being equal to or greater than a predetermined amount of performance degradation mitigation in the pre-stressed anneal monitor plus a predetermined amount of die-to-die and / or intra-die variation in the performance degradation of an unstressed replica of the anneal monitor, where the predetermined amount of performance degradation mitigation corresponds to an extrapolated amount of performance degradation mitigation of the pre-stressed anneal monitor at the end of the life of the age sensor, provided the age sensor is not subjected to a fraudulent anneal attempt; The sensor (100) of claim 1.

6. The performance monitor (310) and the anneal monitor (320) are provided as a multi-stage ring oscillator. The sensor according to any one of claims 1 to 5.

7. the multi-stage ring oscillator of at least one performance monitor (510) includes a controllable switch (511) in a feedback connection of the multi-stage ring oscillator for selectively enabling and disabling feedback of the multi-stage ring oscillator; The sensor of claim 6.

8. a readout unit (106) configured to detect the output signals (S1, S2) generated by the performance monitors (101) and the anneal monitors (102) and to determine a performance variable of each performance monitor (101) and each anneal monitor (102) based on the detected output signals, said performance variables being digital representations of a performance state of the respective monitor. The sensor according to any one of claims 1 to 7.

9. said read unit (506) comprising a frequency counter (513) and optionally a frequency divider stage (512); The sensor of claim 8.

10. said read-out unit being partially implemented in said at least one performance monitor (410), said read-out unit comprising a reference ring oscillator (411) and a beat frequency detection unit (413) configured to detect a beat frequency in a superposition of output signals generated by said reference ring oscillator and a further ring oscillator (412) of said performance monitor, The sensor of claim 8.

11. A sensor system (700) comprising a sensor (701) according to any one of claims 8 to 10 and an analysis unit (702) configured to receive the performance variables determined by the readout unit (106), to detect changes in the performance variables for each performance monitor and to generate an estimate of the operational age of the integrated circuit based thereon.

12. the analysis unit (701) is further configured to detect a change in the performance variable of the at least one anneal monitor and to signal an incorrect anneal attempt if the change in the performance variable of the at least one anneal monitor exceeds a predefined threshold. The sensor system of claim 11.

13. the analysis unit (702) includes a model storage module (703) that stores a response model for each performance monitor and each anneal monitor, each response model associating a set of operating conditions of the integrated circuit with the performance variables of the respective monitor, the set of operating conditions including at least the predicted operating time and the predicted operating temperature of the integrated circuit, and the analysis unit is configured to determine the set of operating conditions from the performance variables received for the performance monitors based on the stored response models. The sensor system of claim 12.

14. the set of operating conditions further comprising the nominal operating voltage of the integrated circuit. The sensor system of claim 13.

15. the age sensor and the analysis unit are provided on the same integrated circuit die and / or the analysis unit forms part of the age sensor; The sensor system according to any one of claims 11 to 14.

16. a plurality of performance monitors (610), each performance monitor being specifically adapted to respond to voltage stresses through a preselected combination of aging mechanisms that degrades the performance of the performance monitor; A sensor (600) or a sensor system according to any one of the preceding claims.

17. a first performance monitor of the plurality of performance monitors is specifically adapted to respond to voltage stress by a bias temperature instability aging mechanism, and a second performance monitor of the plurality of performance monitors is specifically adapted to respond to voltage stress by a combination of the bias temperature instability aging mechanism and a hot carrier injection aging mechanism; A sensor (600) or a sensor system according to claim 16.

18. the second performance monitor of the plurality of performance monitors is specifically adapted to enhance the hot carrier injection aging mechanism relative to the bias temperature instability aging mechanism.

20. A sensor (600) or a sensor system according to claim 17.

19. the input connector of the at least one anneal monitor (102) is fusible; A sensor or sensor system according to any one of the preceding claims.

20. Providing a sensor according to claim 1; detecting a degradation in performance of the at least one anneal monitor of the sensor; and signaling anneal tampering if the detected performance degradation of the at least one anneal monitor falls below a predetermined threshold.

23. A method for detecting unauthorized anneal attempts in an age-monitored integrated circuit, comprising:

21. applying a nominal operating voltage of the integrated circuit to an input of the at least one performance monitor to subject the at least one performance monitor of the sensor to a constant voltage stress while subjecting the at least one pre-stressed anneal monitor to no voltage stress; detecting performance degradation of the at least one performance monitor; and and estimating an operational age of the age-monitored integrated circuit based on the detected performance degradation of the at least one performance monitor, provided there is no indication of anneal tampering by the signal. Further comprising:

21. The method of claim 20.

22. providing the sensor; providing at least one performance monitor and at least one anneal monitor, the at least one performance monitor and the at least one anneal monitor configured to generate output signals indicative of a state of degradation of the respective monitor in response to voltage and temperature stresses; subjecting the at least one anneal monitor to a voltage stress signal by applying the voltage stress signal to an input connector of the at least one anneal monitor, thereby accomplishing pre-stressing the at least one anneal monitor by accelerated degradation under the applied voltage stress signal; and permanently isolating the input connector of the at least one anneal monitor so that it is inaccessible during further application of the voltage stress signal. Including, 22. The method of claim 20 or 21.

23. the step of permanently insulating the input connector of the at least one anneal monitor includes blowing a fuse disposed in a fusible portion of the input connector of the at least one anneal monitor, the blowing of the fuse occurring simultaneously with pre-stressing the at least one anneal monitor.

23. The method of claim 22.

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