Solid-state imaging device including a difference circuit for frame difference

Abstract

The present invention provides an improved problem of noise that deteriorates image quality, particularly under low illumination conditions, in a solid-state imaging device that uses frame differences based on analog pixel signals. [Solution] The solid-state imaging device includes a plurality of pixel circuits and a differential circuit, each of the pixel circuits being configured to output a pixel signal onto a data signal line in response to an active row selection signal during a row selection period, each of the pixel circuits including a floating diffusion, a voltage level of the pixel signal being determined by a floating diffusion potential of the floating diffusion, the differential circuit being configured to receive, for each of the pixel circuits, two pixel signals transmitted consecutively from the pixel circuit on the data signal line during the same row selection period and to obtain a differential signal from the two pixel signals, and the solid-state imaging device is configured to control each of the pixel circuits to output a previous pixel signal and a new pixel signal during the same row selection period, the previous pixel signal and the new pixel signal including image information relating to scenes captured at different points in time.

Description

[Technical field]

[0001] The present disclosure relates to a solid-state imaging device including a difference circuit for frame difference, and more particularly, to a solid-state imaging device including a difference circuit for frame difference based on analog pixel signals. [Background technology]

[0002] The image sensor in the solid-state imaging device includes a photoelectric conversion element that generates a photocurrent proportional to the intensity of the irradiated radiation. The pixel circuit converts the small photocurrent generated by the photoelectric conversion element into a voltage signal. The source follower circuit outputs a corresponding pixel signal on the data line during the row selection period. For intensity readout, a downstream analog-to-digital converter (ADC) converts the pixel signal into a digital pixel value.

[0003] Various frame differencing techniques compare successive pixel signals acquired from the same pixel circuit to generate information indicative of changes in the captured scene. Frame differencing facilitates a fast method for detecting motion in a captured scene and estimating motion vectors representing the speed and direction of moving objects in the captured scene. Frame differencing may use digital pixel values, which may be acquired by a double sampling technique to reduce noise. Summary of the Invention [Problem to be solved by the invention]

[0004] Solid-state imaging devices using frame differencing with analog pixel signals suffer from noise that degrades image quality, especially in low light conditions. The present disclosure improves upon such shortcomings of the prior art described for frame differencing. In particular, the impact of noise on image quality can be reduced by providing a differencing circuit configuration that allows the implementation of various noise reduction techniques with little additional effort. [Means for solving the problem]

[0005] For such purpose, the solid-state imaging device according to the present disclosure includes a plurality of pixel circuits, each of which outputs a pixel signal onto a data signal line in response to an active row selection signal during a row selection period. Each of the pixel circuits includes a floating diffusion, and a voltage level of the pixel signal is determined by a floating diffusion potential of the floating diffusion. A differential circuit receives, for each of the pixel circuits, two pixel signals transmitted consecutively from the pixel circuit on the data signal line during the same row selection period. The differential circuit obtains a differential signal from the two pixel signals. The solid-state imaging device controls each of the pixel circuits to output a previous pixel signal and a new pixel signal during the same row selection period, the previous pixel signal and the new pixel signal including image information related to scenes captured at different times.

[0006] In particular, the components of the difference circuit can also be used in the noise reduced double sampling circuit and / or can be combined with the kTC noise reduction circuit.

[0007] A more complete understanding of the present disclosure and many of the attendant advantages thereof will be readily obtained as the same become better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, in which: [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a simplified block diagram showing a solid-state imaging device including a differential circuit and a noise reduction double sampling circuit according to an embodiment of the present technology. [Diagram 2] FIG. 2 is a simplified block diagram showing a solid-state imaging device including a difference circuit and a kTC noise reduction circuit according to an embodiment of the present technology. [Diagram 3] FIG. 3 is a simplified block diagram of a portion of an image sensor assembly including a difference circuit and a threshold drift compensation circuit in accordance with another embodiment of the present technology. [Figure 4]FIG. 4 is a simplified block diagram of a portion of an image sensor assembly including a differencing circuit and a double sampling circuit in accordance with another embodiment of the present technology. [Diagram 5] FIG. 5 is a simplified block diagram of a portion of an image sensor assembly including a difference circuit including a sample capacitor, a gain capacitor, and an amplifier circuit, in accordance with another embodiment of the present technology. [Figure 6A] FIG. 6A is a simplified block diagram illustrating a portion of an image sensor assembly including a difference circuit including a sample capacitor, a gain capacitor, and an amplifier circuit, a kTC noise reduction circuit, and a 5T pixel circuit in accordance with another embodiment of the present technology. [Figure 6B] FIG. 6B is a simplified timing diagram illustrating various internal and output signals of the image sensor assembly shown in FIG. 6A. [Figure 7A] FIG. 7A is a simplified block diagram of a portion of an image sensor assembly including a difference circuit including a sample capacitor, a gain capacitor, and an amplifier circuit, and a 4T pixel circuit, in accordance with another embodiment of the present technology. [Figure 7B] FIG. 7B is a simplified timing diagram illustrating various internal and output signals of the image sensor assembly shown in FIG. 7A. [Figure 8A] FIG. 8A is a simplified block diagram illustrating a portion of an image sensor assembly including a difference circuit including a fully differential amplifier in accordance with another embodiment of the present technology. [Figure 8B] FIG. 8B is a simplified timing diagram illustrating various internal and output signals of the image sensor assembly shown in FIG. 8A. [Figure 9A] FIG. 9A is a simplified block diagram of a portion of an image sensor assembly including a difference circuit for noise reduction by CDS on new pixel signals in accordance with another embodiment of the present technology. [Figure 9B] FIG. 9B is a simplified timing diagram illustrating various internal and output signals of the image sensor assembly shown in FIG. 9A. [Figure 10]FIG. 10 is a simplified block diagram of a portion of an image sensor assembly combining a difference circuit for CDS noise reduction and kTC noise reduction on new pixel signals in accordance with another embodiment of the present technology. [Figure 11] FIG. 11 is a simplified timing diagram illustrating various internal and output signals of the image sensor assembly shown in FIG. [Figure 12] FIG. 12 is a simplified block diagram showing a converter circuit including a comparator section according to an embodiment of the present technology. [Figure 13] FIG. 13 is a simplified block diagram illustrating a converter circuit including an AD converter with adjustable threshold levels in accordance with one embodiment of the present technology. [Figure 14] FIG. 14 is a simplified flow chart illustrating a method of operating the converter circuit according to FIG. [Figure 15A] FIG. 15A is a simplified block diagram illustrating a portion of an image sensor assembly including a difference circuit that outputs a binary difference signal in accordance with one embodiment of the present technology. [Figure 15B] FIG. 15B is a simplified timing diagram illustrating various internal and output signals of the image sensor assembly shown in FIG. 15A. [Figure 16A] FIG. 16A is a simplified block diagram illustrating a portion of an image sensor assembly with a difference circuit integrated with an AD converter in accordance with one embodiment of the present technology. [Figure 16B] FIG. 16B is a simplified timing diagram illustrating various internal and output signals of the image sensor assembly shown in FIG. 16A. [Figure 17] FIG. 17 is a diagram illustrating an example of a layered structure of a solid-state imaging device according to an embodiment of the present disclosure. [Figure 18] FIG. 18 is a block diagram showing an example of a schematic configuration of a vehicle control system. [Figure 19] FIG. 19 is an explanatory diagram showing an example of the installation positions of the vehicle outside information detection unit and the imaging unit in the vehicle control system shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment for implementing the technology of the present disclosure (hereinafter also referred to as "embodiment") will be described in detail with reference to the drawings. The technology of the present disclosure is not limited to the described embodiment, and various numerical values ​​in the embodiment are merely examples. The same components or components having the same functions are indicated by the same reference numerals. Duplicate explanations will be omitted.

[0010] The connected electronic elements may be electrically connected via a direct, permanent, low resistance connection, e.g., a conductive line. The terms "electrically connected" and "signal connection" may include connections via other electronic elements that provide and are suitable for permanent and / or temporary signal transmission and / or energy transmission. For example, electronic elements may be electrically or signal connected via resistors, capacitors, and electronic switches, such as transistors or transistor circuits, e.g., field effect transistors (FETs) and transmission gates. The load path of a transistor is the control path of the transistor. For example, a voltage applied to the gate of a FET controls the flow of current in the load path between the source and drain by the field effect.

[0011] In the following, techniques for reducing temporal noise are described in the context of a particular type of image sensor for intensity readout, but the techniques can also be used for other types of image sensors.

[0012] 1 and 2 show a configuration example of a solid-state imaging device 90 including an image sensor assembly 10 and a signal processing unit 80 according to an embodiment of the present technology. The image sensor assembly 10 may include a pixel array unit 11, a row decoder 12, a pixel driver unit 13, a column signal processing unit 14, and a sensor controller 15.

[0013] The pixel array portion 11 includes a plurality of identical pixel circuits 100. The pixel circuits 100 may be any active pixel sensor for intensity readout having at least four field effect transistors (FETs). In the illustrated embodiment, each pixel circuit 100 includes one photoelectric conversion element PD and five FETs for controlling the output signal of the pixel circuit 100. Other embodiments may refer to pixel circuits 100 having more than four FETs or four FETs or pixel circuits 100 having two or more photoelectric conversion elements PD.

[0014] The photoelectric conversion elements PD of the pixel array unit 11 may be arranged in a matrix of rows and columns. A subset of pixel circuits 100 assigned to photoelectric conversion elements PD in the same column may form pixel columns 31-1, ..., 31-N. A subset of pixel circuits 100 assigned to photoelectric conversion elements PD in the same row may form pixel rows 32-1, ..., 32-M.

[0015] The row decoder 12 and the pixel driver unit 13 control the driving of each pixel circuit 100 or each pixel row 32-1, ..., 32-M arranged in the pixel array unit 11. In particular, the row decoder 12 may supply a control signal to the pixel driver unit 13 for selecting the pixel circuit 100 of the selected pixel row 32-1, ..., 32-M in response to an address latch signal from the sensor controller 15. The pixel driver unit 13 may control the FET of the selected pixel row 32-1, ..., 32-M in response to a driver timing signal supplied from the sensor controller 15 and a control signal supplied from the row decoder 12. The output signals (pixel signals) of the pixel circuits 100 of the same pixel column 31-1, ..., 31-N are continuously supplied to at least one data signal line (vertical line) VSL. Each data signal line VSL passes the output signal (pixel signal) of the pixel circuit 100 of one pixel column of the pixel columns 31-1, ..., 31-N to the column signal processing unit 14.

[0016] In particular, the solid-state imaging device 90 includes a plurality of pixel circuits 100 arranged in pixel columns 31-1, ..., 31-N, each of which is assigned to one data signal line VSL, and the signal outputs of the pixel circuits 100 in the same pixel column 31-1, ..., 31-N are connected to the same common data signal line VSL.

[0017] In each pixel circuit 100, the photoelectric conversion element PD photoelectrically converts the incident electromagnetic radiation into an electric charge. The amount of electric charge generated in the photoelectric conversion element PD corresponds to the intensity of the incident electromagnetic radiation. For example, the photoelectric conversion element PD may include or be composed of a photodiode that converts the electromagnetic radiation incident on its detection surface into a detector current by photoelectric effect. The electromagnetic radiation may include visible light, infrared light, and / or ultraviolet light. The amplitude of the detector current corresponds to the intensity of the incident electromagnetic radiation, and in the intensity range of interest, the detector current increases approximately linearly with increasing intensity of the detected electromagnetic radiation.

[0018] The configuration example of the pixel circuit 100 shown in the figure includes, in addition to the photoelectric conversion element PD, a floating diffusion region FD that accumulates the charge supplied from the photoelectric conversion element PD, a PD reset transistor 104, a transfer transistor 101, an FD reset transistor 102, an amplification transistor 103, and a selection transistor 108. Each transistor is a FET or includes a FET.

[0019] The load path of the PD reset transistor (photodetector reset transistor) 104 is connected between a positive pixel supply potential VDDP and the cathode of the photoelectric conversion element PD. The PD reset transistor 104 functions as a reset element that precharges the cathode of the photoelectric conversion element PD. A PD reset signal PDR is supplied to the gate of the PD reset transistor 104 via a PD reset signal line. The PD reset signal PDR has an active signal level and an inactive signal level. In particular, an active PD reset signal PDR sets the potential at the cathode of the photoelectric conversion element PD to be equal or nearly equal to the positive pixel supply potential VDDP.

[0020] The load path of the transfer transistor 101 is electrically connected between the cathode of the photoelectric conversion element PD and the floating diffusion region FD. The transfer transistor 101 functions as a transfer element for transferring charges from the photoelectric conversion element PD to the floating diffusion region FD. The floating diffusion region FD functions as a temporary local charge storage unit. A transfer signal TG is supplied to a gate (transfer gate) of the transfer transistor 101 via a transfer control line. The transfer signal TG has an active signal level and an inactive signal level. In response to an active transfer signal TG, the transfer transistor 101 may transfer electrons photoelectrically converted by the photoelectric conversion element PD to the floating diffusion region FD. The load path of the FD reset transistor (floating diffusion reset transistor) 102 is electrically connected between a positive pixel reset voltage Vres and the floating diffusion region FD. The FD reset transistor 102 functions as a reset element for resetting the floating diffusion potential Vfd of the floating diffusion region FD. The FD reset signal RFD is provided to the gate of the FD reset transistor 102 via a reset control line. The FD reset signal RFD has an active signal level and an inactive signal level. In particular, an active FD reset signal RFD sets the floating diffusion potential Vfd to be equal to or approximately equal to the pixel reset voltage Vres. The pixel reset voltage Vres may be a fixed voltage, such as a positive pixel supply voltage VDDP, or may be adaptively controlled by a threshold drift compensation circuit.

[0021] The floating diffusion region FD is connected to the gate of the amplification transistor 103 that functions as an amplification element. The floating diffusion region FD functions as an input node of the amplification transistor 103.

[0022] The amplification transistor 103 and the selection transistor 108 are connected in series between a positive pixel supply voltage VDDP and a data signal line VSL. Thus, the amplification transistor 103 is connected to the data signal line VSL via the selection transistor 108. A row selection signal SEL is provided to the gate of the selection transistor 108 via a selection control line. The row selection signal SEL has an active signal level and an inactive signal level.

[0023] An active row selection signal SEL turns on the selection transistor 108 during the row selection period. When the selection transistor 108 is turned on, the amplification transistor 103 operates in a source follower configuration and outputs a pixel signal to the data signal line VSL at a voltage level that depends on the current floating diffusion potential Vfd. The data signal line VSL passes the pixel signal Vout from the pixel circuit 100 to the column signal processor 14.

[0024] In the same row selection period, the pixel circuit 100 outputs at least two different pixel signals having different image contents recorded at different times, and in the case of the earlier pixel signal (previous pixel signal), the photoelectric conversion element PD of the pixel circuit 100 is exposed to light at an earlier time, for example, in the previous row selection period, than in the case of the later pixel signal (new pixel signal).

[0025] Since the gates of the transfer transistor 101, the PD reset transistor 104, the FD reset transistor 102, and the selection transistor 108 are connected in units of pixel rows 32-1, ..., 32-M, these operations can be performed simultaneously for each pixel circuit 100 in one pixel row 32-1, ..., 32-M.

[0026] Each data signal line VSL is further connected to at least one of the signal conversion units 20. Each signal conversion unit 20 includes a constant current circuit 250, and each constant current circuit 250 is electrically connected between the data signal line VSL and a negative pixel supply potential VSSP. Each constant current circuit 250 may include a constant current source or a switched capacitor current source that at least temporarily supplies a constant current to the data signal line VSL.

[0027] The amplifying transistor 103 of the pixel circuit 100 connected to the data signal line VSL and the constant current circuit 250 connected to the data signal line VSL complement a source follower circuit that passes the pixel signal Vout controlled by the floating diffusion potential Vfd to the column signal processing unit 14. The column signal processing unit 14 may include one or more signal conversion units 20. Each signal conversion unit 20 converts a signal obtained from the analog pixel signal Vout into digital data. The column signal processing unit 14 may include the same number of signal conversion units 20 as the number of data signal lines VSL included in the pixel array unit 11. Alternatively, the number of signal conversion units 20 may be less than the number of data signal lines VSL, and each signal conversion unit 20 may be multiplexed between two or more data signal lines VSL. In particular, one data signal line VSL may connect the signal conversion units 20 to all pixel circuits 100 in the same pixel column 31-1, ..., 31-N.

[0028] Each signal conversion unit 20 includes a differential circuit 200. The differential circuit 200 continuously receives a previous pixel signal and a new pixel signal during the same row selection period from each pixel circuit 100 connected to the same data signal line VSL. The differential circuit 200 generates a differential signal Vrd from the two consecutively received pixel signals. The differential signal Vrd may be an analog differential signal, and the voltage level of the analog differential signal Vrd is a function of the voltage difference between the previous pixel signal and the new pixel signal, or may be a binary differential signal indicating whether the voltage difference meets a predetermined requirement.

[0029] The converter circuit 400 derives digital pixel difference data PDD from the difference signal Vrd. The pixel difference data PDD may include, for example, difference data and / or event information obtained by AD conversion of the analog difference signal Vrd. The difference circuit 200 and / or the converter circuit 400 may be activated in response to an active control signal and may be deactivated in response to an inactive difference control signal.

[0030] Additionally, each signal conversion section 20 may include an ADC section 500 that performs analog-to-digital conversion of a single pixel signal (Vout) and outputs digital pixel intensity data PID. The ADC section 500 may be activated in response to an active ADC control signal, and may be deactivated in response to an inactive ADC control signal.

[0031] The read buffer circuit 25 receives the pixel difference data PDD and / or the pixel intensity data PID.

[0032] The sensor controller 15 controls the column signal processing unit 14. In particular, the sensor controller 15 may synchronize the AD conversion in the ADC unit 500 and the difference calculation in the difference circuit 200 with a control signal of the pixel circuit 100. Furthermore, the sensor controller 15 may generate a read control signal that controls reading of the pixel difference data PDD and / or the pixel intensity data PID from the read buffer circuit 25 to, for example, the signal processing unit 80.

[0033] The image sensor assembly 10 may further include noise reduction circuitry. The noise reduction circuitry may include a dual sample circuit 310, a kTC noise reduction circuit 320, and a threshold drift compensation circuit 330.

[0034] 1 shows one dual sample circuit 310 for each pixel column. The dual sample circuit 310 is fully integrated into the signal conversion unit 20 of the pixel columns 31-1, ..., 31-N. For at least one or both of the previous pixel signal and the new pixel signal, a noise signal and a data signal are successively sampled and subtracted from each other, and then a difference operation between the previous pixel signal and the new pixel signal is performed. The dual sample circuit may reduce noise by correlated double sampling (CDS) and / or differential double sampling (DDS).

[0035] 2 shows one kTC noise reduction circuit 320 per pixel circuit 100 and one threshold drift compensation circuit 330 per pixel column. The threshold drift compensation circuits 330 are integrated in the signal conversion units 20 of the pixel columns 31-1, ..., 31-N. Each kTC noise reduction circuit 320 is integrated in one of the pixel circuits 100. The threshold drift compensation circuit 330 generates a feedback signal FB on a feedback signal line FSL. The feedback signal line FSL may connect the output of the threshold drift compensation circuit 330 to the input of the kTC noise reduction circuit 320.

[0036] 3 and 4 show a part of an image sensor assembly 10 including a pixel circuit 100 and a difference circuit 200. Each pixel circuit 100 outputs a pixel signal Vout on a data signal line VSL in response to an active row selection signal SEL during a row selection period. Each pixel circuit 100 includes a floating diffusion FD, and a floating diffusion potential Vfd of the floating diffusion FD determines the voltage level of the pixel signal Vout. For each pixel circuit 100, the difference circuit 200 receives two pixel signals Vout successively transmitted from the pixel circuit 100 on the data signal line VSL during the same row selection period, and obtains a difference signal Vrd from the two pixel signals. The solid-state imaging device 90 controls each pixel circuit 100 to output a previous pixel signal and a new pixel signal during the same row selection period, and the previous pixel signal and the new pixel signal may include image information related to scenes captured at different times.

[0037] The differential circuit 200 is a part of the pixel array section 11, and the input of the differential circuit 200 is directly connected to the data signal line VSL that is connected to the pixel output of the pixel circuit 100 in the same pixel column.

[0038] In the same row selection period, the difference circuit 200 receives the previous pixel signal and the new pixel signal, and derives a difference signal Vrd from the two pixel signals. The difference signal Vrd contains information about the voltage difference between the previous pixel signal and the new pixel signal.

[0039] Considering the information obtained from all pixel circuits 100 of the image sensor assembly 10, the image sensor assembly 10 can output a frame difference image without complex digital processing in a downstream processor.

[0040] The difference signal Vrd may be an analog difference signal, the voltage level of which is a function of the voltage difference between the two pixel signals Vout, or may be a binary signal indicating whether the difference between the pixel signals exceeds a predetermined threshold.

[0041] The pixel circuit 100 may be any pixel circuit suitable for intensity readout, provided that it includes an output section with an amplifying transistor 103 controlled by a floating diffusion potential Vfd of the floating diffusion FD and a selection transistor 108 for selectively connecting one selected pixel circuit 100 to a data signal line VSL. The charge sampled by the photocurrent during the exposure time is transferred to the floating diffusion FD some time after the exposure time has elapsed. The floating diffusion potential Vfd is applied to the gate of the amplifying transistor 103. A row selection signal SEL is applied to the gate of the selection transistor 108. The load paths of the amplifying transistor 103 and the selection transistor 108 are electrically connected in series between a positive pixel supply potential VDDP and a pixel output 109. The data signal line VSL electrically connects the pixel outputs 109 of a plurality of identical pixel circuits 100 in the same pixel column. The constant current circuit 250 is connected between the data signal line VSL and a negative pixel supply potential VDDP. When the selection transistor 108 is turned on during a row selection period, the amplification transistor 103 and the constant current circuit 250 complement each other to form a source follower circuit.

[0042] In particular, the solid-state imaging device controls the floating diffusion FD to maintain the floating diffusion potential Vfd from the readout of a new pixel signal in the first row selection period of the pixel circuit 100 to the readout of the previous pixel signal in the second row selection period of the pixel circuit 100.

[0043] The first and second row select periods are successive row select periods for the same pixel row, and the time interval between the first row select period and the second row select period is approximately equal to the reciprocal of the frame rate.

[0044] The floating diffusion FD is designed so that the current leaking from the floating diffusion in the period between two readouts of the same pixel row is negligible.

[0045] The differential circuit 200 may include an amplifier circuit 205, a sample capacitor 201 in a first input leg between a data signal line VSL and an inverting input of the amplifier circuit 205, and a switchable feedback path 202 between the output of the amplifier circuit 205 and the inverting input of the amplifier circuit 205.

[0046] A solid-state imaging device 90, for example, the sensor controller 15 shown in FIG. 2, may control a differential circuit 200 to sample a voltage corresponding to the signal level of a first pixel signal across a sample capacitor 201 in a first phase, and obtain an analog differential signal Vrd from the difference between the voltage sampled by the sample capacitor 201 and the voltage level of a second pixel signal applied to the input electrode of the sample capacitor 201 in a second phase.

[0047] In particular, the amplifier circuit 205, sample capacitor 201 and switchable feedback path 202 may be used to directly compare the previous and new pixel signals, or double sampling, e.g., subtracting a pixel noise signal from the pixel data signal for the previous and / or new pixel signals.

[0048] The difference circuit 200 and the constant current circuit 250 may be part of a signal conversion unit 20 connected to a data signal line VSL. The signal conversion unit 20 further includes an ADC unit 500 that performs analog-to-digital conversion of a single pixel signal Vout and outputs digital pixel intensity data PID. The ADC unit 500 may be activated in response to an active ADC control signal AEN, and may be deactivated in response to an inactive ADC control signal AEN. When deactivated, the ADC unit 500 typically consumes only a negligible amount of electrical energy. The signal conversion unit 20 may further include a converter circuit 400 that obtains digital pixel difference data PDD from the difference signal Vrd. The pixel difference data PDD may include, for example, difference data and / or event information obtained by AD conversion of an analog difference signal.

[0049] 3, the pixel circuit 100 includes an FD reset transistor 102 for resetting the potential of the floating diffusion FD in response to an active FD reset signal. The image sensor assembly 10 further includes a kTC noise reduction circuit 320 and a threshold drift compensation circuit 330. The kTC noise reduction circuit 320 reduces the kTC noise generated at the floating diffusion FD by turning off the FD reset transistor 102. To this end, the kTC noise reduction circuit 320 provides a parallel capacitive path for charge carriers when the FD reset transistor 102 is turned off, and then turns off the parallel capacitive path such that the kTC noise is partially generated at a node that has less impact on the pixel signal and only a portion of the kTC noise is generated at and / or transferred to the floating diffusion FD.

[0050] When the floating diffusion FD is reset, the threshold drift compensation circuit 330 compensates for fluctuations in the threshold voltage of the amplification transistor 103 by individually adjusting the reset voltage of the floating diffusion FD for each pixel circuit 100 in accordance with the voltage level on the data signal line VSL.

[0051] 4, the image sensor assembly 10 includes a double sampling circuit 310 that reduces noise by applying a double sampling method such as CDS (Correlated Double Sampling) and / or DDS (Differential Double Sampling). The double sampling method relies on double readout of the same pixel circuit 100 after the floating diffusion FD receives the charge generated during exposure and before the FD is reset, and after the FD is reset, or vice versa, i.e., before the floating diffusion FD receives the charge generated during exposure.

[0052] In particular, each readout of the pixel circuit 100 includes two intervals. In a first period (data phase, D phase), a first pixel signal (data signal) is read out after the floating diffusion FD receives the charge generated and sampled during the exposure time. In a second period (preset phase, P phase), a second pixel signal (noise signal) of a non-illuminated pixel is read out, for example, after the FD is reset and before the floating diffusion FD receives the charge generated during the exposure time. The second period may be immediately before or after the first period. The final pixel output value is obtained by subtracting the second pixel signal (noise signal) from the sampled first pixel signal (data signal), which can reduce the effect of noise on the final pixel output value. According to the CDS readout method, the P phase precedes the D phase. According to the DDS readout method, the D phase precedes the P phase.

[0053] The operations of the dual sample circuit 310 and the difference circuit 200 may be related, and the dual sample circuit 310, the difference circuit 200, and / or the pixel circuit 100 may share some resources, such as one or more circuit elements, that perform different tasks in different circuits.

[0054] The dual sample circuit 310 may be formed entirely as part of the signal conversion section 20. Reducing noise without feedback to the pixel circuit 100 allows for faster operation, for example faster frame readout.

[0055] 5 and further embodiments, the pixel circuit 100 is based on a floating diffusion FD, whose floating diffusion potential Vfd determines the voltage level of the pixel signal Vout. The pixel circuit 100 may further include a photoelectric conversion element PD that determines the floating diffusion potential Vfd by a photocurrent, and a transfer transistor 101 that connects the cathode of the photoelectric conversion element PD and the floating diffusion FD in response to an active transfer signal TG during a row selection period. The transfer transistor 101 may be capable of outputting two pixel signals resulting from two successive exposures if the leakage current from the floating diffusion is sufficiently small.

[0056] The pixel circuit 100 may further include a photodetector reset transistor 104 that resets the potential at the cathode of the photoelectric conversion element PD to a fixed potential in response to an active photodetector reset signal PDR. The photodetector reset transistor 104 provides a margin for determining the length of the exposure time.

[0057] Furthermore, the pixel circuit 100 may include a floating diffusion reset transistor 102 that connects the floating diffusion FD to a pixel reset voltage Vres in response to at least an active floating diffusion reset signal FDR. The reset of the floating diffusion FD may be controlled by the floating diffusion reset signal FDR alone or in combination with one or more other control signals. The pixel reset voltage Vres may be a fixed voltage, such as, for example, the positive pixel supply potential VDDP, or an adaptive voltage.

[0058] In FIG. 5 , the differential circuit 200 includes an amplifier circuit 205, a sample capacitor 201 electrically connected between a data signal line VSL and the inverting input of the amplifier circuit 205, and a switchable feedback circuit 202 between the output of the amplifier circuit 205 and the inverting input of the amplifier circuit 205.

[0059] The feedback circuit 202 includes a gain capacitor 203 electrically connected between an output (amplifier output) of the amplifier circuit 205 and an inverting input (inverting amplifier input) of the amplifier circuit 205. An auto-zero switch element 204 is electrically connected between the amplifier output and the inverting amplifier input. An active auto-zero signal AZ turns on the auto-zero switch element 204 and sets the potential at the inverting amplifier input to the potential applied to the non-inverting amplifier input. The potential applied to the non-inverting amplifier input may be fixed or variable.

[0060] 2 controls a difference circuit 200 to sample a voltage corresponding to the signal level of a previous pixel signal across a sample capacitor 201 in a first phase, and to derive an analog difference signal Vrd in a second phase from the difference between the voltage sampled on the sample capacitor 201 and the voltage level of a next pixel signal applied to the input electrode of the sample capacitor 201. The previous pixel signal and the new pixel signal contain image information about scenes captured at different times.

[0061] The difference circuit 200 uses a sample capacitor 201 , an amplifier circuit 205 , a gain capacitor 203 , and an auto-zero switch element 204 to compare the new pixel signal with the previous pixel signal.

[0062] The amplifier circuit 205 receives a constant reference voltage Vref at its non-inverting input.

[0063] The difference circuit 200 successively receives a previous pixel signal and a new pixel signal from the same pixel circuit 100 during the same row selection period, stores a voltage corresponding to the voltage level of the previous pixel signal across the sample capacitor 201 by setting the potential at the inverting amplifier input equal to the potential at the non-inverting amplifier input during a first phase, and subtracts the voltage across the sample capacitor 201 from the voltage level of the new pixel signal by floating the inverting amplifier input during a second phase. As a result, the amplifier circuit 205 outputs an analog difference signal Vrd, whose voltage level is a function, in particular an approximately linear function, of the difference between the signal levels of the previous pixel signal and the new pixel signal.

[0064] Essentially, the difference circuit 200 uses the floating diffusion FD in each pixel circuit 100 as a storage element that stores a new floating diffusion potential corresponding to a new pixel signal, for each pixel circuit 100, until the pixel circuit 100 is addressed in the next frame. In the next frame, the previous "new" floating diffusion potential Vfd becomes the next "previous" floating diffusion potential Vfd and determines the next previous pixel output signal.

[0065] The difference circuit 200 shown in FIG. 5 may be combined with various noise reduction circuits.

[0066] The solid-state imaging device may include a kTC noise reduction circuit configured to reduce kTC noise in the pixel signals before obtaining the differential signal Vrd.

[0067] In particular, each pixel circuit 100 may include a kTC noise reduction circuit 320 that can reduce reset noise generated by charge accumulated in the floating diffusion FD each time the floating diffusion FD is isolated from the positive pixel supply potential VDDP.

[0068] Figure 6A combines the difference circuit 200 shown in Figure 5 with a kTC noise reduction circuit 320 and a threshold drift compensation circuit 330. The pixel circuit 100 is a 5T pixel that includes a PD reset transistor 104 controlled by a PD reset signal PDR.

[0069] The solid-state imaging device includes a threshold drift compensation circuit 330 that controls the pixel reset voltage Vres as a function of the current voltage of the pixel signal Vout on the data signal line VSL.

[0070] In particular, the threshold drift compensation circuit 330 may include a column feedback amplifier 305. A pixel signal Vout on a data signal line VSL is applied to an inverting input of the column feedback amplifier 305. A standard voltage Vst is applied to a non-inverting input of the column feedback amplifier 305. The standard voltage Vst serves as a reference for the pixel signal generated by the pixel circuit 100. For example, the standard voltage Vst may correspond to an expected signal level of the pixel signal of a non-illuminated pixel.

[0071] The column feedback amplifier 305 generates a feedback signal FB on a feedback signal line FSL. The voltage level of the feedback signal FB is a function of the difference between the pixel signal Vout and a standard voltage Vst. The feedback signal line FSL connects the output of the column feedback amplifier 305 to a kTC noise reduction circuit 320. The solid-state imaging device further includes a kTC noise reduction circuit 320 integrated in the pixel circuit 100. To this end, the pixel circuit 100 further includes an auxiliary transistor 321 and a pixel coupling capacitor 323. The auxiliary transistor 321 is electrically connected in series between the FD reset transistor 102 and a node that supplies a pixel reset voltage Vres. The auxiliary transistor 321 connects the FD reset transistor 102 to the node that supplies the pixel reset voltage Vres in response to an active auxiliary signal AXR. The pixel coupling capacitor 323 is electrically connected in parallel to the FD reset transistor 102.

[0072] In the illustrated embodiment, the auxiliary transistor 321 is electrically connected between the feedback signal line FSL and the side of the FD reset transistor 102 away from the floating diffusion FD. An active auxiliary signal AXR turns the auxiliary transistor 321 on.

[0073] Each kTC noise reduction circuit 320 may further include a pixel storage capacitor 322 electrically connected between a constant voltage, e.g., a positive pixel supply potential VDDP, and a node between the FD reset transistor 102 and the auxiliary transistor switch 321, and a pixel coupling capacitor 323 electrically connected between the floating diffusion FD and the node between the FD reset transistor 102 and the auxiliary transistor 321. The capacitance of the pixel storage capacitor 322 may be of the same order, e.g., approximately the same, as the capacitance of the floating diffusion FD. The capacitance of the pixel coupling capacitor 323 may be smaller than the capacitance of the floating diffusion FD.

[0074] When the reset transistor 102 is turned off in a pixel circuit 100 without a pixel coupling capacitor 323, a reset kTC noise is generated in the floating diffusion FD. The noise charge is a function of kTC, where k is the Boltzmann constant, T is the temperature, and C is the capacitance of the floating diffusion FD. Reducing the C of the floating diffusion FD reduces the dynamic range of the pixel circuit 100. On the other hand, when the FD reset transistor 102 is turned off in the pixel circuit 100 shown in FIG. 6A, if the auxiliary transistor 321 is still on, the pixel coupling capacitor 323 and the auxiliary transistor 321 form an alternative path for the charge carriers. When the auxiliary transistor 321 is then turned off, less reset noise is generated in the floating diffusion FD.

[0075] The sensor controller 15 shown in FIG. 2 may control the selection signal SEL, the PD reset signal PDR, the FD reset signal FDR, the transmission signal TG, and the auxiliary signal AXR in accordance with the timing diagram shown in FIG. 6B.

[0076] Between t=t1 and t=t2, a reset pulse in the PD reset signal PDR resets the potential at the cathode of the photoelectric conversion element PD to the positive pixel supply potential VDDP. The end of the reset pulse at t=t2 marks the start of the exposure time.

[0077] At t=t3, an active row select signal SEL turns on select transistor 108 and applies the previous pixel signal to data line VSL according to the previous floating diffusion potential Vfd. At the end of a short pulse of the autozero signal between t=t4 and t=t5, the voltage level of the previous pixel signal is sampled across sample capacitor 201. From t=t5, the non-inverting input of amplifier circuit 205 is floated and the difference signal Vrd at the output of amplifier circuit 205 is a function of the voltage difference between the current signal on data line VSL and the previous pixel signal.

[0078] At t=t6, both the FD reset signal FDR and the auxiliary signal AXR become active. The FD reset transistor 102 and the auxiliary transistor 321 turn on, connecting the floating diffusion FD to the feedback signal line FSL. The floating diffusion FD is set to a reset potential that compensates to some extent for temperature drift and / or pixel-to-pixel variation of the threshold voltage of the amplifier transistor 103.

[0079] At t=t7, first, the FD reset signal FDR becomes inactive, turning off the FD reset transistor 102. Because of the parallel path via the coupling capacitor 323, no reset noise or only a small reset noise occurs in the floating diffusion FD. Then, at t=t8, the auxiliary signal AXR becomes inactive, turning off the auxiliary transistor 321. The floating diffusion finally switches to free without generating a large reset noise in the floating diffusion FD.

[0080] Between t=t8 and t=t9, the transfer transistor 101 is turned on, connecting the floating diffusion FD to the cathode of the photoelectric conversion element PD. The exposure time of the new pixel signal ends at t=t8. After t=t9, the pixel circuit 100 outputs a new pixel signal that exhibits only slight kTC noise.

[0081] The new pixel signal is available on the data signal line VSL until t=t10, when the pixel circuit 100 is deselected. Between t=t9 and t=t10, the voltage level of the analog difference signal Vrd is a function, in particular a substantially linear function, of the difference between the signal levels of the previous pixel signal and the new pixel signal. The converter circuit 400 may latch the difference signal Vrd between t=t9 and t=t10, as shown in FIG.

[0082] The floating diffusion FD stores the floating diffusion potential Vfd of the new pixel signal until the next pixel circuit readout, when the previous new pixel signal becomes the new previous pixel signal.

[0083] The pixel circuit 100 shown in Fig. 7A differs from the pixel circuit shown in Fig. 5 in that there is no PD reset transistor 104. Therefore, the exposure time is determined by the time distance between two consecutive pulses in the transfer signal TG, as shown in Fig. 7B. The pixel circuit 100 can be used in combination with any of the difference circuits 200 of the present disclosure, as long as the exposure time can be made constant and equal to the inverse of the frame rate.

[0084] As described above, the solid-state imaging device 90, for example, the sensor controller 15 shown in FIG. 2, may control the differential circuit 200 to sample a voltage corresponding to the signal level of a first pixel signal across the sample capacitor 201 in a first phase, and obtain an analog differential signal Vrd from the difference between the voltage sampled by the sample capacitor 201 and the voltage level of a second pixel signal applied to the input electrode of the sample capacitor 201 in a second phase.

[0085] In the above-described embodiment, the difference circuit 200 compared the new pixel signal as the second pixel signal with the previous pixel signal as the first pixel signal, but in the following embodiment, the same components are used to perform double sampling to obtain a noise-reduced previous pixel signal and / or new pixel signal.

[0086] In particular, the first pixel signal is a pixel noise signal for the pixel signal and the second pixel signal is a pixel data signal for the pixel signal. Alternatively, the first pixel signal is a pixel data signal for the pixel signal and the second pixel signal is a pixel noise signal for the pixel signal. The pixel noise signal originates from an unexposed pixel and the pixel data signal originates from an exposed pixel. In other words, the pixel noise signal corresponds to a pixel output signal of an unexposed (dark) pixel and the pixel data signal corresponds to a pixel output signal of any exposed (light) pixel. The pixel data signal includes noise.

[0087] The pixel signal may be the new pixel signal or the previous signal, or the approach is used separately for both the new pixel signal and the previous signal, as in the next embodiment.

[0088] 8A shows an embodiment of a difference circuit 200 including a fully differential amplifier 217 and a sample / hold circuit 218 electrically connected at a first input leg between the data signal line VSL and a first input of the fully differential amplifier 217. A second input leg couples the data signal line VSL to a second input of the fully differential amplifier 217.

[0089] The fully differential amplifier 217 is a high-gain electronic voltage amplifier having a differential input and a differential output. The first input (first amplifier input) of the fully differential amplifier 217 may be an inverting input of the differential input. The second input (second amplifier input) of the fully differential amplifier 217 may be a non-inverting input of the differential input. The first output (first amplifier output) of the fully differential amplifier 217 may be an inverting output of the differential output. The second output (second amplifier output) of the fully differential amplifier 217 may be a non-inverting output of the differential output. The differential output signal directly provides the analog difference signal Vrd.

[0090] The sample / hold signal S / H controls the sample / hold circuit 218. An active sample / hold signal S / H controls the sample / hold circuit to pass the signal present on the data signal line VSL to the output of the sample / hold circuit 218. When the sample / hold signal goes inactive, the output of the sample / hold circuit 218 is isolated from the input and from the data signal line VSL.

[0091] In a first pixel signal phase, the data signal line VSL passes the previous pixel signal to the sample / hold circuit 218, which passes the previous pixel signal to the first amplifier input. In a second pixel signal phase, the sample / hold circuit 218 blocks the path between the data signal line VSL and the first amplifier input, such that the new pixel signal is passed only to the second amplifier input in the second pixel signal phase.

[0092] The fully differential amplifier 217 is embedded in a local feedback circuit such that the fully differential amplifier 217 outputs an analog difference signal Vrd whose voltage level is a function of the difference between the signal levels of the first amplifier input and the second amplifier input.

[0093] The dual sample circuit 310 modifies the previous pixel signal and the new pixel signal before the analog difference signal Vrd is processed.

[0094] For this reason, the solid-state imaging device includes a first sample capacitor 211 in a portion of the first input leg between the sample / hold circuit 218 and the first input of the differential amplifier circuit 217, a second sample capacitor 311 in a second input leg between the data signal line VSL and the second input of the differential amplifier circuit 217, a first gain capacitor 213 in a first feedback path between the second amplifier output and the first amplifier input, and a second gain capacitor 313 in a second feedback path between the first amplifier output and the second amplifier input.

[0095] The first and second gain capacitors 213 and 313 may be resettable, with the electrodes of the first gain capacitor 213 being temporarily shorted and the electrodes of the second gain capacitor 313 being temporarily shorted.

[0096] The first sample capacitor 211 and the first gain capacitor 213 facilitate double sampling of the previous pixel signal by successively applying a pixel data signal for the previous pixel signal and a pixel noise signal for the new pixel signal to the input electrodes of the first sample capacitor 211 with an intermediate reset of the potential at the first amplifier input to subtract the pixel noise signal from the pixel data signal.

[0097] The second sample capacitor 311 and the second gain capacitor 313 facilitate double sampling of the new pixel signal by continuously applying the pixel noise signal and the pixel data signal for the new pixel signal to the input electrode of the second sample capacitor 311 with an intermediate reset of the potential at the second amplifier input to subtract the pixel noise signal from the pixel data signal. The pixel noise signal for the new pixel signal is used for both DDS with the pixel data signal for the previous pixel signal and CDS with the pixel data signal for the new pixel signal.

[0098] The fully differential amplifier 217 is part of both the differencing circuit 200 and the double sampling circuit 310 .

[0099] To reset the first and second gain capacitors 213 and 313 and initialize the difference circuit 200, the double sampling circuit 310 includes a first auto-zero switch 212 between the second amplifier output and the first amplifier input, and a second auto-zero switch 312 between the first amplifier output and the second amplifier input. An active first auto-zero signal AZ1 turns on the first auto-zero switch 212 and resets the potential at the first amplifier input with the potential at the second amplifier output. An active second auto-zero signal AZ2 turns on the second auto-zero switch 312 and resets the potential at the second amplifier input with the reference potential Vref.

[0100] The first initialization switch 315 is connected between the second amplifier output and a reference potential Vref, and the second initialization switch 316 is connected between the first amplifier output and a reference potential Vref. A first side of the third initialization switch 317 is connected to the second auto-zero switch 312 and the second initialization switch 316. A second side of the third initialization switch 317 is connected to the second gain capacitor 313 and the first amplifier output. An active initialization signal INIT turns on the first initialization switch 315 and turns off the third initialization switch 317. The potential at the first amplifier input is reset to the reference potential Vref if the first auto-zero switch 212 is on. Furthermore, an active initialization signal INIT turns on the second initialization switch 316 and resets the potential at the second amplifier input to the reference potential Vref if the second auto-zero switch 312 is on.

[0101] The sensor controller 15 shown in Figure 1 may control the select signal SEL, the FD reset signal, the transmit signal TG, the initialization signal INIT, the first auto-zero signal AZ1, the second auto-zero signal AZ2, and the sample / hold signal S / H according to the timing diagram shown in Figure 8B. At t=t1, an active row select signal SEL turns on the select transistor 108, and the pixel data signal for the previous pixel signal is applied to the data signal line VSL.

[0102] At t=t2, the initialization signal INIT, the first autozero signal AZ1, the second autozero signal AZ2, and the sample / hold signal S / H become active. The potentials at the first amplifier input and the second amplifier input are reset to a reference potential Vref. The sample / hold circuit 215 becomes transparent and the pixel data signal for the previous pixel signal is applied to the first sample capacitor 211. A voltage corresponding to the difference between the voltage level of the pixel data signal of the previous pixel signal and the reference voltage drops across the first sample capacitor 211.

[0103] At t=t3, the initialization signal INIT becomes inactive, turning off the first and second initialization switches 315 and 316. At t=t4, the first auto-zero signal AZ1 becomes inactive, turning off the first auto-zero switch 212, and the potential at the first amplifier input begins to float.

[0104] In pixel circuit 100, an FD reset pulse active between t=t5 and t=t6 sets the floating diffusion potential Vfd to a reset voltage. Pixel circuit 100 outputs a pixel noise signal for the new pixel signal. The resulting potential at the floating first amplifier input is a function of the difference between the signal level of the pixel data signal and the pixel noise signal for the previous pixel signal. In this way, the portion of the double sampling circuit connected to the first amplifier input performs differential double sampling for the previous pixel signal using the pixel data signal for the previous pixel signal and the pixel noise signal for the new pixel signal.

[0105] The falling edge of the sample / hold signal S / H at t=t7 causes the sample / hold circuit 215 to disconnect the first amplifier input from the data signal line VSL. The potential resulting from the DDS of the previous pixel signal is maintained at the first amplifier input.

[0106] Meanwhile, the same pixel noise signal is applied to the second sample capacitor 311. At t=t8, when the second autozero signal AZ2 becomes inactive, the second autozero switch 312 turns off, the potential at the second amplifier input starts to float, and a voltage drop corresponding to the voltage level of the pixel noise signal is sampled across the second sample capacitor 311. This pixel noise signal is considered to be the noise component of the new pixel.

[0107] An active transfer signal TG between t=t9 and t=10 connects the cathode of the photoelectric conversion element PD to the floating diffusion FD. The pixel circuit 100 outputs a pixel data signal for the new pixel signal. The resulting potential at the floating second amplifier input of the difference circuit 200 is a function of the difference between the signal level of the pixel data signal and the pixel noise signal for the new pixel signal. In this way, the portion of the noise reduction circuit connected to the second amplifier input performs correlated double sampling on the new pixel signal using the pixel data signal for the new pixel signal and the pixel noise signal for the new pixel signal.

[0108] At t=t11, the select signal becomes inactive. Between t=t10 and t=t11, the fully differential amplifier outputs an analog difference signal whose voltage level is a function, e.g., an approximately linear function, of the difference between the voltage levels of the previous DDS corrected pixel signal and the new CDS corrected pixel signal. In Fig. 9A, the signal conversion unit 20 performs noise reduction by double sampling using a difference circuit 200 having a sample capacitor 201, an amplifier circuit 205, a gain capacitor 203, and an auto-zero switch element 204, as described with reference to Fig. 5.

[0109] The sample capacitor 201 receives the pixel signal at a first capacitor electrode (capacitor input electrode). The second capacitor electrode of the sample capacitor 201 is electrically connected to an inverting input of an amplifier circuit 205. The gain capacitor 203 is electrically connected between an output (amplifier output) of the amplifier circuit 205 and an inverting input (inverting amplifier input) of the amplifier circuit 205. The auto-zero switch element 204 is electrically connected between the amplifier output and the inverting amplifier input. An active auto-zero signal AZ turns on the auto-zero switch element 204 and sets the potential at the inverting amplifier input to the potential applied to the non-inverting amplifier input. The potential applied to the non-inverting amplifier input is switchable.

[0110] Auxiliary sample capacitor 221 is in a path connecting data signal line VSL and a non-inverting input (non-inverting amplifier input) of amplifier circuit 205. A first sample switch element 222 is electrically connected between the data signal line VSL and a first electrode of auxiliary sample capacitor 221. An active first auto-zero signal AZ1 turns on first sample switch element 222 and connects auxiliary sample capacitor 221 to the data signal line VSL.

[0111] A constant reference voltage Vref is applied to the non-inverting amplifier input. A second sample switch element 223 is electrically connected between a second electrode of the auxiliary sample capacitor 221 and the non-inverting amplifier input. An active first auto-zero signal AZ1 turns on the second sample switch element 223, connecting the auxiliary sample capacitor element 221 to the non-inverting amplifier input and the reference voltage Vref.

[0112] The second autozero switch element 224 is electrically connected between the amplifier output and the second electrode of the auxiliary sample capacitor 221. An active second autozero signal AZ2 turns on the second autozero switch element 224 and sets the potential at the second electrode of the auxiliary sample capacitor 221 to the potential at the amplifier output.

[0113] An input of an output buffer 225 is electrically connected to the first electrode of the auxiliary sample capacitor 221 and outputs an analog difference signal Vrd that is a function, in particular an approximately linear function, of the voltage difference between the previous pixel signal and the new pixel signal.

[0114] The sensor controller 15 shown in FIG. 1 may control the selection signal SEL, the FD reset signal FDR, the transmit signal TG, the auto-zero signal AZ, the first auto-zero signal AZ1, and the second auto-zero signal AZ2 according to the timing diagram shown in FIG. 9B.

[0115] At t=t1, an active row select signal SEL turns on the select transistor 108 and a pixel data signal for the previous pixel signal is applied to the data signal line VSL. At t=t2, the autozero signal AZ and the first autozero signal AZ1 become active. The potential at the inverting amplifier input is reset to the reference potential Vref. The first sample switch element 222 and the second sample switch element 223 connect the auxiliary sample capacitor 221 to the data signal line VSL and the non-inverting amplifier input.

[0116] At t=t3, the first sample switch element 222 and the second sample switch element 223 disconnect the auxiliary sample capacitor 221 from the data signal line VSL and the non-inverting amplifier input, and the previous pixel signal is sampled to the voltage across the auxiliary sample capacitor 221.

[0117] An FD reset pulse active between t=t4 and t=t5 sets the floating diffusion potential Vfd to a reset voltage derived from the output of the column feedback amplifier 305, compensating for temperature related variations in the threshold voltage of the amplifying transistor 103. At t=t5, the pixel circuit 100 outputs a pixel noise signal for the new pixel signal.

[0118] When the autozero signal AZ becomes inactive at t=t6 and the autozero switch element 204 opens, the potential at the second amplifier input begins to float and a voltage drop corresponding to the voltage level of the pixel noise signal is sampled across the sample capacitor 201.

[0119] Between t=t7 and t=t8, an active transfer signal TG connects the cathode of the photoelectric conversion element PD to the floating diffusion FD. The pixel circuit 100 outputs a pixel data signal for the new pixel signal. The resulting potential at the floating second amplifier input is a function of the difference between the signal level of the pixel data signal and the pixel noise signal for the new pixel signal. In this way, the combination of the amplifier circuit 205, the sample capacitor 201, the gain capacitor 203, and the auto-zero switch element 204 performs correlated double sampling for the new pixel signal, and the amplifier circuit 205 outputs a CDS corrected new pixel signal.

[0120] Between t=t9 and t=t10, the amplifier output is connected to a second electrode of auxiliary sample capacitor 221. The voltage at the first electrode of sample capacitor 211 corresponds to the difference between the amplifier output signal and the voltage sampled across sample capacitor element 211 at t=t3. Buffer circuit 215 outputs a buffered output signal whose voltage level is a function, e.g., an approximately linear function, of the difference in voltage levels between the previous pixel signal and the CDS corrected new pixel signal.

[0121] FIG. 10 shows a combination of a difference circuit 200 that performs integrated CDS correction on new pixel signals as shown in FIG. 9A, and the kTC noise reduction circuit 320 described with reference to FIG. 6A.

[0122] The sensor controller 15 shown in FIG. 1 may control the selection signal SEL, the FD reset signal FDR, the auxiliary signal AXR, the transmit signal TG, the auto-zero signal AZ, the first auto-zero signal AZ1, and the second auto-zero signal AZ2 according to the timing diagram shown in FIG.

[0123] The timing diagram shown in Figure 11 differs from that shown in Figure 9B in that at t = t4, auxiliary transistor 321 is turned on simultaneously with FD reset transistor 102 so that the floating diffusion potential Vfd is set to a reset voltage derived from feedback signal FB to compensate for pixel-to-pixel and / or temperature related variations in the threshold voltage of amplifier transistor 103. When the FD reset transistor is turned off at t = t5, no or only little reset noise is generated in the floating diffusion FD due to the parallel path through auxiliary transistor 321 and pixel coupling capacitor 323. When auxiliary transistor 321 is turned off at t = t51, only little reset noise is generated in the floating diffusion FD.

[0124] The analog difference signal Vrd may be A / D converted by a common ADC used for intensity readout, for example the same ADC may be switchable to A / D convert a single pixel signal Vout in intensity readout mode and to A / D convert the analog difference signal Vrd in frame difference mode.

[0125] According to the following embodiment, the solid-state imaging device includes a converter circuit 400 that gates the difference signal Vrd with at least one threshold signal.

[0126] Each threshold signal may be a constant voltage, which may be fixed, configurable, or adaptive. Alternatively, the threshold signals may vary over time. Converter circuit 400 allows pre-processing of the analog difference signal Vrd output from difference circuit 200 to reduce the computational burden of the downstream image processor.

[0127] According to one embodiment, the converter circuit 400 may derive the event information signal EV from the difference signal Vrd. To this end, the converter circuit 400 may gate the analog difference signal Vrd by two constant threshold voltages to derive a digital event information signal. The two constant threshold voltages may be fixed voltage levels or may be adjusted during operation.

[0128] 12 shows a converter circuit 400 including a sample / hold section 410 for latching an analog differential signal Vrd. A first comparator section 421 compares the latched analog differential signal Vrd with a first threshold voltage. A binary output signal of the first comparator section 421 has an active voltage level ("1") only if the latched analog differential signal Vrd is higher than the first threshold voltage. A second comparator section 422 compares the latched analog differential signal Vrd with a second threshold voltage. A binary output signal of the second comparator section 422 has an active voltage level ("1") only if the latched analog differential signal Vrd is lower than the second threshold voltage.

[0129] 13, the converter circuit 400 includes a sample / hold unit 410, a low resolution analog to digital converter 430 that converts the analog difference signal Vrd to a digital difference signal, and an event encoder 440. The analog to digital converter 430 may include a 2-bit quantizer circuit with an adjustable threshold level to detect frame differences for addressed pixel circuits 100 in the positive or negative direction that exceed the adjustable threshold.

[0130] The event encoder 440 maps the result of the AD conversion to a digital event code. For example, a negative event may be encoded as "00", a positive event as "11", and no event as "01" and / or "10". The event encoder 440 may output the encoded event in a data stream, or may append the pixel address of the pixel circuit where the event was detected, so that the event encoder 440 outputs only the pixel address and, for each pixel address, a data bit indicating the type of event. FIG. 14 shows another embodiment of the converter circuit 400 including an analog-to-digital converter 430. The solid-state imaging device 90 is configured to control the analog-to-digital converter 430 such that the difference signal Vrd is quantized with high precision only if the difference signal Vrd exceeds a predetermined frame difference threshold after k out of N possible quantization steps.

[0131] Otherwise, quantization is stopped. In this way, irrelevant or less relevant quantization can be omitted, reducing the power consumption of the converter circuit. The N possible quantization steps are determined by the resolution of the analog-to-digital converter.

[0132] The output data may include a pixel address combined with the quantized frame difference, or a pixel address combined with binary information ("0" or "1") indicating whether the quantized frame difference exceeds a frame difference threshold.

[0133] FIG. 15A shows an embodiment in which the amplifier circuit 205 outputs a binary difference signal Vrd.

[0134] The difference circuit 200 includes an amplifier circuit 205, a sample capacitor 201 in a first input leg between a data signal line VSL and an inverting input of the amplifier circuit 205, and an auto-zero switch element 204 between an output of the amplifier circuit 205 and an inverting input of the amplifier circuit 205. Furthermore, the difference circuit 200 receives a variable threshold signal Vthr at a non-inverting input of the amplifier circuit 205. The gain capacitor 203 described with reference to FIG. 5 may be omitted.

[0135] The variable threshold signal Vthr may be a digital signal whose voltage level changes between at least two different voltage levels, for example a ternary signal whose voltage level changes between three different voltage levels. When the auto-zero switch element 204 in the switchable feedback path 202 between the amplifier output and the inverting amplifier input is turned off, the amplifier output and the inverting amplifier input are completely isolated and the feedback loop is opened. The amplifier circuit 205 outputs a binary difference signal Vrd indicating whether the voltage difference between the previous pixel signal and the new pixel signal has exceeded or fallen below a predetermined threshold value that depends on the current voltage level of the variable threshold signal Vthr.

[0136] The converter circuit 400 includes a first 1-bit memory 451 and a second 1-bit memory 452 that successively latch the result of a comparison of the voltage difference between a previous pixel signal and a new pixel signal.

[0137] 15B, the first 1-bit memory 451 latches the result of the comparison with the positive or higher threshold voltage Vthr_Off applied to the non-inverting input of the amplifier circuit 205 at the rising edge of the LAT_OFF signal at t=t12 or the falling edge of the LAT_OFF signal at t=t13. The second 1-bit memory 452 latches the result of the comparison with the negative or lower threshold voltage Vthr_On applied to the non-inverting input of the amplifier circuit 205 at the rising edge of the LAT_ON signal at t=t14 or the falling edge of the LAT_ON signal at t=t15.

[0138] 16A, the components of converter circuit 400 and amplifier circuit 205 complement each other to form an analog-to-digital converter that directly converts the voltage difference between the previous pixel signal and the next pixel signal into a multi-bit digital value. In particular, the solid-state imaging device may include a ramp generator 461 that applies a voltage ramp to the non-inverting input of amplifier circuit 205.

[0139] The amplifier circuit 205, the sample capacitor 201, and the auto-zero switch element 204 are controlled to subtract the new pixel signal from the previous pixel signal using the voltage sampled across the sample capacitor 201. The ramp generator 461 generates a voltage ramp and applies the generated voltage ramp to the non-inverting input of the amplifier circuit 205. The amplifier circuit 205 operates as a comparator and changes the voltage level of the binary difference signal Vrd when the sign of the voltage difference between the voltage difference between the previous pixel signal and the next pixel signal and the voltage ramp changes. The pulse generator 462 generates regular clock pulses and passes the generated clock pulses to the counter circuit 465. The counter circuit 465 starts counting in synchronization with the start of the voltage ramp and stops counting when the voltage level of the binary difference signal Vrd switches.

[0140] 16B shows the synchronous start of the count and voltage ramp at t=t21 and the end of the voltage ramp at t29. The turning points of the binary difference signal Vrd are between t=t21 and t=t29 and depend on the voltage difference between the previous and new pixel signals.

[0141] 17 is a perspective view showing an example of a layered structure of a solid-state imaging device 23020 in which a plurality of pixel circuits are arranged in a matrix array. Each pixel circuit includes at least one photoelectric conversion element.

[0142] The solid-state imaging device 23020 has a stacked structure of a first chip (upper chip) 910 and a second chip (lower chip) 920. The stacked first and second chips 910 and 920 may be electrically connected to each other via a TC(S)V (through contact (silicon) via) formed in the first chip 910. The solid-state imaging device 23020 may be formed to have a stacked structure in which the first and second chips 910 and 920 are bonded together at the wafer level and cut out by dicing.

[0143] In the stacked structure of two chips, upper and lower, the first chip 910 may be an analog chip (sensor chip) that includes at least one analog component of each pixel circuit, for example, photoelectric conversion elements arranged in an array.

[0144] For example, the first chip 10 may include only the photoelectric conversion element of the pixel circuit as described with reference to the above figures. Alternatively, the first chip 910 may include other components of each pixel circuit. For example, the first chip 910 may include at least the transfer transistor, reset transistor, amplification transistor, and / or selection transistor of the pixel circuit in addition to the photoelectric conversion element. Alternatively, the first chip 910 may include each component of the pixel circuit. In addition to the components of the pixel circuit, the first chip 910 may include one, some, or all components of the signal conversion unit, for example, some or all components of the difference circuit, constant current circuit, and / or converter circuit as described above. The second chip 920 may be a logic chip (digital chip) mainly including components that complement the components on the first chip 910 to configure the pixel circuit and / or the signal conversion unit. The second chip 920 may include an analog circuit, for example, a circuit that quantizes an analog signal transferred from the first chip 910 via a TCV. For example, the second chip 920 may include all or at least some of the components of the ADC section as described with reference to the previous figures.

[0145] The second chip 920 may have one or more bonding pads BPD, and the first chip 910 may have an opening OPN used for wire bonding to the second chip 920. A solid-state imaging device 23020 having a stacked structure of the two chips 910 and 920 may have the following characteristic configuration.

[0146] The electrical connection between the first chip 910 and the second chip 920 is made, for example, via a TCV. The TCV may be disposed at the end of the chip, or may be disposed between the pad section and the circuit region. The TCVs that transmit the control signals and supply power may be disposed mainly, for example, concentrated in the four corners of the solid-state imaging device 23020. This allows the signal wiring area of ​​the first chip 910 to be reduced.

[0147] The technology of the present disclosure may be implemented in a light receiving device mounted on any type of moving object, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0148] FIG. 18 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a moving object control system to which the technology according to the present disclosure can be applied.

[0149] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 18, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also, as functional configurations of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053 are illustrated.

[0150] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0151] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as head lamps, back lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves or signals of various switches transmitted from a portable device that replaces a key may be input to the body system control unit 12020. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, and the like of the vehicle.

[0152] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for a person, a car, an obstacle, a sign, or characters on a road surface, based on the received image.

[0153] The imaging unit 12031 may be a solid-state imaging device equipped with a signal conversion unit having a differential circuit according to an embodiment of the present disclosure, or may include the solid-state imaging device. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0154] The in-vehicle information detection unit 12040 may be an individual imaging device that detects information inside the vehicle and has a live driver assembly according to an embodiment of the present disclosure, or may include the individual imaging device. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera equipped with an individual imaging device and focused on the driver. The in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing.

[0155] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the outside-of-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0156] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0157] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12030 based on the information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0158] The audio / image output unit 12052 transmits at least one output signal of audio and image to an output device capable of visually or audibly notifying information to the passengers of the vehicle or the outside of the vehicle. In the example of Fig. 18, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as the output devices. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display, each of which may include a solid-state imaging device including a comparison circuit described with reference to the above figures.

[0159] FIG. 19 is a diagram showing an example of the installation position of the imaging unit 12031, and the imaging unit 12031 may have imaging units 12101, 12102, 12103, 12104, and 12105.

[0160] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield in the vehicle interior of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield in the vehicle interior mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided at the upper part of the windshield in the vehicle interior is mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

[0161] 19 shows an example of the imaging ranges of the imaging units 12101 to 12104. An imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and an imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.

[0162] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of a plurality of imaging elements, an imaging element having pixels for detecting a phase difference, or a ToF module including a dynamic range image sensor including a signal conversion unit having a differential circuit according to an embodiment of the present disclosure.

[0163] For example, the microcomputer 12051 can extract, as a preceding vehicle, a three-dimensional object that is the closest three-dimensional object on the travel path of the vehicle 12100 and travels at a predetermined speed (for example, 0 km / h or more) in approximately the same direction as the vehicle 12100, by calculating the distance to each three-dimensional object in the imaging ranges 12111 to 12114 and the change over time of this distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. Furthermore, the microcomputer 12051 can set a vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving that travels autonomously without relying on the driver's operation.

[0164] For example, the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0165] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured images of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

[0166] An example of a vehicle control system to which the technology disclosed herein can be applied has been described above. By applying an image sensor including a signal conversion unit having a differential circuit according to the present disclosure, power consumption can be further improved and the response time of the sensor can be improved.

[0167] Furthermore, the embodiments of the present technology are not limited to the above-described embodiments, and various modifications are possible within the scope of the present technology without departing from the gist of the present technology.

[0168] A solid-state imaging device including an image sensor assembly including a signal conversion unit having a differential circuit according to the present disclosure may be any device used to analyze and / or process radiation such as visible light, infrared light, ultraviolet light, and X-rays, etc. For example, the solid-state imaging device may be any electronic device in the fields of transportation, home appliances, medicine and healthcare, security, beauty, sports, agriculture, image reproduction, eye tracking, structured light devices, etc.

[0169] Specifically, in the field of eye tracking, due to the fast eye movement and the required optical flow accuracy, image sensors usually operate at high frame rates of 200 Hz or more. Image sensors having conversion circuits based on the difference circuits described in this disclosure can reduce the number and range of AD conversions and generate less useful information, thereby reducing sensing and processing power. Frame differencing in the digital domain may be reduced or even omitted completely.

[0170] In a structured light system, a laser pulse scans the scene at high speed. The image sensor observing the scanned scene must be fast enough to reliably detect the reflected laser light. This embodiment, and in particular the embodiment described with reference to Figures 9A to 16B, allows for a significant speed increase compared to other CIS sensors. The pixel circuit is made up of only four to five transistors and is small in size, allowing a high resolution to be obtained.

[0171] In the field of image reproduction, the solid-state imaging device may be a device for capturing images to be provided for viewing, such as a digital camera, a smartphone, a mobile phone with a camera, etc. In the field of transportation, for example, the solid-state imaging device may be integrated into an on-board sensor for capturing images of the front, rear, surroundings, interior, etc. of a vehicle for safe driving such as automatic stopping and driver status recognition, a surveillance camera for monitoring vehicles and roads while traveling, or a distance measurement sensor for measuring the distance between vehicles.

[0172] In the field of home appliances, the solid-state imaging device may be integrated into any kind of sensor that is provided in home appliances such as television sets, refrigerators, and air conditioners, and can be used in devices that capture user gestures and perform device operations according to the gestures. Thus, the solid-state imaging device may be integrated into home appliances such as television sets, refrigerators, and air conditioners and / or devices that control home appliances. Furthermore, in the field of medicine and health care, the solid-state imaging device may be integrated into any kind of sensor, such as a solid-state imaging device used for medical and health care applications, such as an endoscope or a device that receives infrared light and performs angiography.

[0173] In the security field, the solid-state imaging device can be integrated into devices used for security purposes, such as security cameras for crime prevention and cameras for person authentication. Furthermore, in the beauty field, the solid-state imaging device can be used in devices used for beauty purposes, such as skin measuring devices that photograph skin and microscopes that photograph probes. In the sports field, the solid-state imaging device can be integrated into devices used for sports purposes, such as action cameras and wearable cameras for sports. Furthermore, in the agriculture field, the solid-state imaging device can be used in devices used for agricultural purposes, such as cameras that monitor the condition of fields and crops.

[0174] The present technology may be configured as follows. (1) A plurality of pixel circuits; Differential circuit and A solid-state imaging device comprising: Each of the pixel circuits is configured to output a pixel signal onto a data signal line in response to an active row selection signal during a row selection period, each of the pixel circuits includes a floating diffusion, and a voltage level of the pixel signal is determined by a floating diffusion potential of the floating diffusion; The differential circuit is configured to receive, for each of the pixel circuits, two pixel signals successively transmitted on the data signal line from the pixel circuit in the same row selection period and obtain a differential signal from the two pixel signals, and the solid-state imaging device is configured to control each of the pixel circuits to output, in the same row selection period, a previous pixel signal and a new pixel signal, the previous pixel signal and the new pixel signal including image information relating to a scene captured at different times. Individual imaging device. (2) The solid-state imaging device according to (1), The solid-state imaging device is configured to control the floating diffusion to maintain a floating diffusion potential from a readout of a new pixel signal in a first row selection period of the pixel circuit to a readout of a previous pixel signal in a second row selection period of the pixel circuit. Individual imaging device. (3) The solid-state imaging device according to (1) or (2), The difference circuit includes an amplifier circuit, a sample capacitor in a first input leg between the data signal line and an inverting input of the amplifier circuit, and a switchable feedback path between an output of the amplifier circuit and the inverting input of the amplifier circuit. Individual imaging device. (4) The solid-state imaging device according to (3), The solid-state imaging device is configured to control the differential circuit to sample a voltage corresponding to a signal level of a first pixel signal across the sample capacitor in a first phase, and to obtain the differential signal from a difference between the voltage sampled by the sample capacitor and a voltage level of a second pixel signal applied to an input electrode of the sample capacitor in a second phase. Individual imaging device. (5) The solid-state imaging device according to (3), the solid-state imaging device is configured to control the differential circuit to sample a voltage corresponding to a signal level of a previous pixel signal across the sample capacitor in a first phase, and to obtain the differential signal from a difference between the voltage sampled by the sample capacitor and a voltage level of a next pixel signal applied to an input electrode of the sample capacitor in a second phase; The previous pixel signal and the new pixel signal contain image information about a scene captured at different times. Individual imaging device. (6) The solid-state imaging device according to any one of (1) to (5), further comprising: a noise reduction circuit configured to reduce kTC noise in the pixel signals before obtaining the difference signal. Equipped with Individual imaging device. (7) A solid-state imaging device according to any one of (1) to (6), the differential circuit includes a fully differential amplifier and a sample / hold circuit electrically connected at a first input leg between the data signal line and a first input of the fully differential amplifier; A second input leg couples the data signal line to a second input of the fully differential amplifier. Individual imaging device. (8) The solid-state imaging device according to (1), further comprising: a first sample capacitor in a portion of the first input leg between the sample / hold circuit and the first input of the differential amplifier circuit; a second sample capacitor in the second input leg between the data signal line and the second input of the differential amplifier circuit; a first gain capacitor in a first feedback path between the second amplifier output and the first amplifier input; a second gain capacitor in a second feedback path between the first amplifier output and the second amplifier input; Equipped Individual imaging device. (9) A solid-state imaging device according to any one of (1) to (8), The pixel circuit further comprises: a photoelectric conversion element configured to determine the floating diffusion potential by a photocurrent; a transfer transistor configured to connect the cathode of the photoelectric conversion element and the floating diffusion in response to a transfer signal that is active during the row selection period; Includes Individual imaging device. (10) The solid-state imaging device according to (9), The pixel circuit further includes a photodetector reset transistor configured to reset the potential at the cathode of the photoelectric conversion element to a fixed potential in response to an active photodetector reset signal. Individual imaging device. (11) A solid-state imaging device according to any one of (1) to (10), The pixel circuit further comprises: a floating diffusion reset transistor configured to connect the floating diffusion to a pixel reset voltage in response to at least an active floating diffusion reset signal; an auxiliary transistor electrically connected in series between the floating diffusion reset transistor and a node supplying the pixel reset voltage, the auxiliary transistor being configured to connect the floating diffusion reset transistor to the node supplying the pixel reset voltage in response to an active auxiliary signal; a pixel coupling capacitor electrically connected in parallel to the floating diffusion reset transistor; Includes Individual imaging device. (12) A solid-state imaging device according to any one of (1) to (11), The pixel circuit further comprises: a floating diffusion reset transistor configured to connect the floating diffusion to a pixel reset voltage in response to at least an active floating diffusion reset signal; a threshold drift compensation circuit configured to control the pixel reset voltage as a function of a current voltage of the pixel signal on the data signal line; Includes Individual imaging device. (13) The solid-state imaging device according to any one of (1) to (12), further comprising: a converter circuit configured to gate said differential signal with at least one threshold signal; Equipped with Individual imaging device. (14) The solid-state imaging device according to (13), The converter circuit is configured to obtain digital event information from the differential signal. Individual imaging device. (15) The solid-state imaging device according to (13) or (14), The converter circuit includes an analog-to-digital converter; The solid-state imaging device is configured to control the analog-to-digital converter such that the difference signal is quantized with high precision only if the difference signal exceeds a predetermined frame difference threshold after k out of N possible quantization steps. Individual imaging device. (16) A solid-state imaging device according to any one of (1), (2), and (6) to (12), the difference circuit includes an amplifier circuit, a sample capacitor in a first input leg between the data signal line and an inverting input of the amplifier circuit, and an auto-zero switch element between an output of the amplifier circuit and the inverting input of the amplifier circuit; The difference circuit is configured to receive a variable threshold signal at the non-inverting input of the amplifier circuit. Individual imaging device. (17) The solid-state imaging device according to (16), further comprising: a ramp generator configured to apply a voltage ramp to the non-inverting input of the amplifier circuit; Equipped with Individual imaging device.

Claims

1. A plurality of pixel circuits (100); A differential circuit (200) and A solid-state imaging device comprising: Each of the pixel circuits (100) is configured to output a pixel signal (Vout) onto a data signal line (VSL) in response to an active row selection signal (SEE) during a row selection period, each of the pixel circuits (100) includes a floating diffusion (FD), and a voltage level of the pixel signal (Vout) is determined by a floating diffusion potential (Vfd) of the floating diffusion (FD), The difference circuit (200) is configured to receive, for each of the pixel circuits (100), two pixel signals (Vout) successively transmitted on the data signal line (VSL) from the pixel circuit (100) during the same row selection period, and to obtain a difference signal (Vrd) from the two pixel signals (Vout). The solid-state imaging device (90) is configured to control each of the pixel circuits (100) to output a previous pixel signal and a new pixel signal during the same row selection period, the previous pixel signal and the new pixel signal including image information relating to a scene captured at different times. Individual imaging device.

2. 2. The solid-state imaging device according to claim 1, The solid-state imaging device (90) is configured to control the floating diffusion (FD) to maintain a floating diffusion potential (Vfd) from readout of a new pixel signal in a first row selection period of the pixel circuit (100) to readout of a previous pixel signal in a second row selection period of the pixel circuit (100). Individual imaging device.

3. 2. The solid-state imaging device according to claim 1, The differential circuit (200) includes an amplifier circuit (205, 247), a sample capacitor (201, 211) in a first input leg between the data signal line (VSL) and an inverting input of the amplifier circuit (205, 217), and a switchable feedback path (202) between an output of the amplifier circuit (205, 217) and the inverting input of the amplifier circuit (205, 217). Individual imaging device.

4. 4. The solid-state imaging device according to claim 3, The solid-state imaging device (90) is configured to control the differential circuit (200) to sample a voltage corresponding to a signal level of a first pixel signal across the sample capacitor (201) in a first phase, and to obtain the differential signal (Vrd) from a difference between the voltage sampled by the sample capacitor (201) and a voltage level of a second pixel signal applied to an input electrode of the sample capacitor (201) in a second phase. Individual imaging device.

5. 4. The solid-state imaging device according to claim 3, The solid-state imaging device (90) is configured to control the differential circuit (200) to sample a voltage corresponding to a signal level of a previous pixel signal across the sample capacitor (201) in a first phase, and to obtain the differential signal (Vrd) from a difference between the voltage sampled on the sample capacitor (201) and a voltage level of a next pixel signal applied to an input electrode of the sample capacitor (201) in a second phase; The previous pixel signal and the new pixel signal contain image information about a scene captured at different times. Individual imaging device.

6. 2. The solid-state imaging device according to claim 1, further comprising: a noise reduction circuit configured to reduce kTC noise in the pixel signal before obtaining the difference signal (Vrd); Equipped with Individual imaging device.

7. 2. The solid-state imaging device according to claim 1, The differential circuit (200) includes a fully differential amplifier (217) and a sample / hold circuit (218) electrically connected at a first input leg between the data signal line (VSL) and a first input of the fully differential amplifier (217); A second input leg couples the data signal line (VSL) to a second input of the fully differential amplifier (217). Individual imaging device.

8. The solid-state imaging device according to claim 7, further comprising: a first sample capacitor (211) in a portion of the first input leg between the sample / hold circuit (218) and the first input of the differential amplifier circuit (217); a second sample capacitor (311) in the second input leg between the data signal line (VSL) and the second input of the differential amplifier circuit (217); a first gain capacitor (213) in a first feedback path between a second amplifier output and the first amplifier input; a second gain capacitor (313) in a second feedback path between the first amplifier output and the second amplifier input; Equipped Individual imaging device.

9. 2. The solid-state imaging device according to claim 1, The pixel circuit (100) further comprises: A photoelectric conversion element (PD) configured to determine the floating diffusion potential (Vfd) based on a photocurrent; a transfer transistor (101) configured to connect the cathode of the photoelectric conversion element (PD) and the floating diffusion (FD) in response to an active transfer signal (TG) during the row selection period; Includes Individual imaging device.

10. 10. The solid-state imaging device according to claim 9, The pixel circuit (100) further includes a photodetector reset transistor (104) configured to reset the potential at the cathode of the photoelectric conversion element (PD) to a fixed potential in response to an active photodetector reset signal (PDR). Individual imaging device.

11. 2. The solid-state imaging device according to claim 1, The pixel circuit (100) further comprises: a floating diffusion reset transistor (102) configured to connect the floating diffusion (FD) to a pixel reset voltage (Vres) in response to at least an active floating diffusion reset signal (FDR); an auxiliary transistor (321) electrically connected in series between the floating diffusion reset transistor (102) and a node supplying the pixel reset voltage (Vres), and configured to connect the floating diffusion reset transistor (102) to the node supplying the pixel reset voltage (Vres) in response to an active auxiliary signal (AXR); a pixel coupling capacitor (323) electrically connected in parallel to the floating diffusion reset transistor (102); Includes Individual imaging device.

12. 2. The solid-state imaging device according to claim 1, The pixel circuit (100) further comprises: a floating diffusion reset transistor (102) configured to connect the floating diffusion (FD) to a pixel reset voltage (Vres) in response to at least an active floating diffusion reset signal (FDR); a threshold drift compensation circuit (330) configured to control the pixel reset voltage (Vres) as a function of the current voltage of the pixel signal (Vout) on the data signal line (VSL); Includes Individual imaging device.

13. 2. The solid-state imaging device according to claim 1, further comprising: A converter circuit (400) configured to gate said differential signal (Vrd) with at least one threshold signal. Equipped with Individual imaging device.

14. The solid-state imaging device according to claim 13, The converter circuit (400) is configured to derive digital event information (EV) from the differential signal (Vrd). Individual imaging device.

15. The solid-state imaging device according to claim 13, The converter circuit (400) includes an analog-to-digital converter (430); The solid-state imaging device (90) is configured to control the analog-to-digital converter (430) such that the difference signal (Vrd) is quantized with high precision only if the difference signal (Vrd) exceeds a predetermined frame difference threshold after k out of N possible quantization steps. Individual imaging device.

16. 2. The solid-state imaging device according to claim 1, The differential circuit (200) includes an amplifier circuit (205), a sample capacitor (201) in a first input leg between the data signal line (VSL) and an inverting input of the amplifier circuit (205), and an auto-zero switch element (204) between the output of the amplifier circuit (205) and the inverting input of the amplifier circuit (205); The difference circuit (200) is configured to receive a variable threshold signal (Vthr) at the non-inverting input of the amplifier circuit (205). Individual imaging device.

17. The solid-state imaging device according to claim 16, further comprising: a ramp generator (461) configured to apply a voltage ramp to the non-inverting input of the amplifier circuit (205); Equipped with Individual imaging device.

Images