MEMORY HAVING BIT CELL POWER BOOST - Patent application

Abstract

A memory is provided that includes a bitcell VDD boost to increase read margin. In some implementations, the positive boost for the bitcell VDD can be provided by a capacitor that is also used for the negative boost of the write driver.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims priority to and the benefit of U.S. Patent Application No. 17 / 657,231, filed March 30, 2022, the disclosure of which is incorporated herein by reference in its entirety as if fully set forth below and for all applicable purposes.

[0002] This application relates to memories, and more particularly to memories with positively boosted power in bitcells. [Background technology]

[0003] In conventional static random-access memory (SRAM), bit cells connect to pairs of bit lines. Prior to a write operation, the bit lines are precharged to the power supply voltage used for the bit cells. Depending on the data to be written to the bit cells, a write multiplexer may discharge either the true or the complementary bit line in the bit line pair from its precharged state.

[0004] Some conventional SRAM devices may further employ word line underdrive (WLUD) to mitigate the loss of read static noise margin from lower power supply levels. However, word line underdrive may result in lower read current in memory cells, which may itself degrade read performance.

[0005] There is a need in the art for memories with improved read performance. Summary of the Invention

[0006] In one implementation, a circuit includes a random-access memory (RAM) cell coupled to a first power rail; and a boost circuit coupled to the first power rail, the boost circuit including a capacitor having a first terminal and a second terminal, the first terminal of the capacitor coupled to a first power supply through a first transistor and to ground through a second transistor, the second terminal of the capacitor coupled to a first plurality of parallel transistors, the first plurality of parallel transistors coupled to a plurality of power rails including the first power rail, and a second plurality of parallel transistors coupled to the plurality of power rails and to a second power supply.

[0007] In another implementation, a method includes coupling a first terminal of a capacitor, the second terminal of which is floating and coupled to a node charged to a power supply voltage, to ground through a first transistor, decoupling the first terminal from ground, coupling the first terminal to a power supply through a second transistor, and coupling the second terminal to a power rail through a third transistor, the power rail serving the memory bank, and boosting the power supply voltage for memory cells of the memory bank, the boosting including discharging the capacitor onto the power rail.

[0008] In another implementation, a random access memory (RAM) includes a first memory bank having a plurality of bit cells arranged in columns and rows, means for matching a voltage level of input data to a level suitable for writing to the first memory bank, means for detecting output data read from the first memory bank, means for providing a negative boost to the means for matching the voltage levels, and means for providing a positive boost to a power rail coupled to memory cells in the first memory bank.

[0009] In yet another implementation, a system on chip (SOC) includes a random access memory having a write driver and a memory bank, a plurality of power rails, each of the power rails corresponding to a respective core in the memory bank, each of the power rails being coupled to a power input of a memory cell in the respective core, and a boost circuit coupled to the write driver and to the memory bank, the boost circuit including a capacitor having a first terminal and a second terminal, the capacitor coupled between a power supply and a first node, the first node coupled to the second terminal and to the plurality of power rails.

[0010] These and additional advantages may be more fully understood through the following detailed description of the invention. [Brief description of the drawings]

[0011] [Figure 1] 1 illustrates a multi-bank memory with boosting according to one implementation. [Diagram 2] 2 illustrates an exemplary boost circuit in the memory of FIG. 1; [Diagram 3] 2 illustrates an exemplary write driver circuit for the memory of FIG. 1. [Figure 4] 2 illustrates an exemplary memory cell in the implementation of FIG. 1. [Diagram 5] 5 shows an example timing diagram of signals in the boost circuits and memory cells of FIGS. 2-4. [Figure 6] 2 shows a flowchart of an example method that may be performed by the memory of FIG. 1. [Figure 7] 1 illustrates an exemplary system-on-chip (SOC) that may incorporate memory, according to one aspect of the present disclosure.

[0012] Implementations of the present disclosure and their advantages are best understood by referring to the following detailed description, it being understood that like reference numerals are used to identify like elements shown in one or more of the figures. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] An exemplary write operation includes a negative boost in the write driver such that the binary data includes a binary 0 that is pulled down by the negative boost. The purpose is to increase the write margin by pulling either the bit line or the complementary bit line lower than otherwise. In other words, the negative boost makes the difference between the bit line and the complementary bit line larger than it would be without the negative boost, thereby reducing the chance of a failed write operation.

[0014] Also, as mentioned above, word line underdrive (WLUD) may be used in combination with lowering the power supply (VDD) to mitigate the loss of read static noise margin from lower VDD, but WLUD may still leave the read static noise margin lower than may be desired for some implementations.

[0015] Therefore, various implementations boost the VDD at the memory bitcells of a memory bank during a read operation to increase the amount of read current, thereby increasing the read static noise margin.

[0016] An exemplary circuit may include boost circuitry coupled to memory cells (e.g., static random access memory bitcells) and configured to boost the VDD of those memory cells. Continuing with the example, the boost circuitry may include a capacitor having a first terminal and a second terminal, the first terminal coupled to a first power supply through a first transistor and to ground through a second transistor. The second terminal of the capacitor is coupled to a first plurality of parallel transistors, the first plurality of transistors coupled to a plurality of power rails. The plurality of power rails are coupled to a string of bitcells and configured to provide power to the string of bitcells. The boost circuit may also include a second plurality of parallel transistors between the plurality of power rails and an external power supply.

[0017] Thus, the capacitor may be used to boost voltages on multiple power rails by charging and discharging the capacitor in parallel with turning on or off the first and second multiple transistors, in other words, the capacitor may be used to boost VDD on multiple power rails, which power the memory cells.

[0018] An advantage of some implementations is that the positive boost VDD can increase the amount of read current in a selected memory cell. The increased read current can correspond to an increased read static noise margin. Increasing the read static noise margin can further increase device performance by enabling reliable read operations at faster speeds even when VDD can be lowered when not actively reading. Furthermore, lowering VDD can result in increased power efficiency, which when combined with VDD boosting for read operations can result in increased power efficiency without adversely affecting reliability and speed.

[0019] In some implementations, the capacitor may be shared with the negative boost circuitry that provides a negative boost to the write driver. Thus, the memory device may include both a positive boost for VDD and a negative boost for the write driver. An advantage of some implementations is that the dual use for the capacitor may be realized at negligible cost in terms of semiconductor area. Thus, some implementations may enjoy the benefits of both a positive boost and a negative boost with little or negligible impact on device size.

[0020] 1 is a diagram of a memory system 100 according to one implementation. The memory system 100 is a multi-bank memory system, in this case using two memory banks, bank b0 195 and bank b1 196. As one skilled in the art would appreciate, the boosting techniques disclosed herein can be applied to a multi-bank memory system having any number of memory banks. Each of the memory banks 195, 196 includes multiple columns of bit cells, each column having a bit line and a complementary bit line, and each of the memory banks is traversed by multiple word lines. The bit lines and complementary bit lines 190, 191 are shown as having four pairs each, it being understood that a given memory bank may include any suitable number of bit line pairs corresponding to any suitable number of columns.

[0021] Looking at multiplexer 110, it corresponds to bank b0 195, which multiplexes bit line pair 190 to data inputs wdin, wdin_n and sense nodes q and qb. Similarly, multiplexer 120 corresponds to bank b1 196, which multiplexes bit line pair 191 to data inputs wdin, wdin_n and sense nodes q, qb. In this example, each of multiplexers 110, 120 receives three signals including pre_n (bit line precharge), rm[0:3] (read multiplexing signal), and wm[0:3] (write multiplexing signal). Note that here signals rm and wm are shown as selecting among four columns, and as mentioned above, a range of implementations support any number of columns that may be multiplexed.

[0022] Sense node q and complementary sense node qb are inputs to sense amplifier 113. Furthermore, in this example, memory system 100 performs either a read or a write operation on one of memory banks 195, 196 at a given time, but not on both memory banks 195, 196 simultaneously. In response to a read operation on one of memory banks 195, 196, sense amplifier 113 bases a bit decision on the difference in voltage between a given sense node pair corresponding to that respective bank. The output of sense amplifier 113 is sa_out, which indicates the value read from the bit cell.

[0023] A write operation may include receiving differential data for gdin, gdin_n from a data source (not shown). The write driver 130 matches the voltage levels of the differential data to levels suitable for writing to the memory banks 195, 196. The voltage level shifted data wdin, wdin_n is sent to the multiplexers 110, 120. One of the multiplexers 110, 120 has a column selected by the signal wm to write data to its respective memory bank 195, 196. For example, for the multiplexer 110, there are four wm signals [0:3], with three unselected columns corresponding to a digital value of 0 and one selected column corresponding to a digital value of 1. Similarly for the multiplexer 120.

[0024] The boost circuit 150 provides a negative boost to one of the differential data portions that is a digital zero through the write driver 130. The negative boost is indicated by vss_boost, which will be described in more detail with respect to FIG. 3. The negative boost of the data can increase the write margin experienced by the memory banks 195, 196. The boost circuit 150 can also provide a positive boost to the VDD at the memory cells using the power rails vddhx_core<0-3>. The positive boost to the VDD at the memory cells can increase the read static noise margin.

[0025] 2 illustrates an example boost circuit 150, according to one implementation. Capacitor C0 provides both a negative boost to vss_boost and a positive boost to the vddhx_core power rail.

[0026] This description first looks at an example of a write operation with negative boost. Consider an example where the input data gdin_n is 1 and gdin is 0. The boost circuit 150 reduces vss_boost to 0-Δv1 by using capacitor C0. Applying a 1 to the gates of transistors N4, N5 reduces the voltage at vss_boost to ground. Applying a 1 to the gates of transistors N4, N5 uses a 0 in signals nbl_control and a 1 in bst_cntrlb. The 0 value of nbl_control is applied to series inverter 251, which also makes node 201 1. Next, transistor N4 is turned off by applying a digital 0 at its gate (i.e., nbl_control changes to 1), which floats vss_boost and node 201 transitions from 1 to 0 by series inverter 251. This action applies a more negative voltage at node vss_boost by using capacitive coupling, which causes node vss_boost to drop to 0-Δv1.

[0027] The operation of the boost circuit 150 is further described with respect to FIG. 3. As mentioned above, in this example, gdin_n is 1 and gdin is 0. Transistor M5 is on, as is transistor M2, and transistors M3 and M4 are both off. Thus, wdin_n goes to vss_boost and wdin goes to VDD. Now, if vss_boost is actually lower than Vss (e.g., ground level), the voltage level difference between the two data lines wdin, wdin_n is larger than VDD, which can be expected to lead to a higher write margin.

[0028] However, applying a negative boost may reduce the source voltage of transistor M4, which may cause M4 to leak. Because of this leakage, it may be undesirable to lower vss_boost below some negative voltage level. In fact, increased leakage may not only cause undesirable power usage, but may also degrade write margins in some cases. Thus, various implementations herein may use a capacitor C0 sized for a negative voltage boost that is not expected to result in undesirable levels of leakage.

[0029] 1, during a read operation, boost circuit 150 applies a positive boost to the power supplies at both memory banks 195, 196. The positive boost increases the voltage at VDD to vddhx plus Δv2 through capacitor C0.

[0030] Looking at a read operation, nbl_control starts out as 0 and remains at 0 for the duration of the read operation. As a result, N4 remains on, N6 remains off, and node 201 is precharged to VDD. Signal bst_cntrl starts out as 0, which turns on transistor P9 and transistor P8 is off. Transistor N5 is on, which pulls vss_boost down to 0. At this point, node 201 corresponds to one terminal of capacitor C0, which is at VDD, and the other terminal of capacitor C0 at node vss_boost is at 0.

[0031] Continuing with our example, transistors P<0-3> have a 1 applied to their gates, so they are off. Transistors P<4-7> have a 0 applied to their gates, so they are on, thereby charging the power rail vddhx_core<0-3> to VDD by the external chip-level power supply vddehx.

[0032] When it is time to perform a read operation and discharge capacitor C0 for a positive boost, signal bst_cntrl transitions from 0 to 1. When bst_cntrl changes from 0 to 1, its complement (bst_cntrlb) changes from 1 to 0, which turns off N5. Transistor P9 is turned off, and by default, nbl_control is low, which also turns off transistor N6.

[0033] When signal bst_cntrl transitions from 0 to 1 (and bst_cntrlb transitions from 1 to 0), transistors P<0-3> and P8 turn on and transistors P<4-7> turn off, causing capacitor C0 to transfer its charge to power rail vddhx_core<0-3>, thereby raising the voltage on power rail vddhx_core<0-3> to vddhx plus Δv2.

[0034] The positive boost (Δv2) may be any suitable value, possibly between 50 and 100 mV. The magnitude of the positive boost may be influenced by selecting the capacitance of capacitor C0 commensurate with the desired Δv2. For example, in one exemplary implementation, the effective total boost capacitance value is 10 fF and the effective total vddhx_core capacitance value is 320 fF (80 fF per bitcell column). Therefore, in this example, Δv2=10 / (320+10)=3% boost, although the range of implementations is not limited to any particular values ​​for capacitance or voltage.

[0035] The read operation of the memory circuit, and more specifically, the positive boost operation of boost circuit 150, is further illustrated by Figures 4-5. Figure 4 illustrates an exemplary memory cell according to one implementation.

[0036] In the example of Figure 4, memory cell 400 is a static random access memory (SRAM) bit cell. In the architecture of Figure 1, memory cells such as bit cell 400 would be arranged in columns in memory banks 195, 196. A particular memory bit cell can be selected by a given multiplexer 110, 120 using multiplexing signals rm and wm.

[0037] Prior to a read operation, bitlines BL and BLB are precharged to VDD but are floating. A given memory cell in a column can be selected according to its wordline WL. Data is stored in memory cell 400 using cross-coupled transistors M10-M13. The cross-coupled transistors are coupled between VSS (ground) and a power rail vddhx_core, which couples memory cell 400 to the power supply.

[0038] Continuing with the example, transistor M10 receives a 1 at its gate, transistor M11 receives a 0 at its gate, transistor M12 receives a 1 at its gate, and transistor M13 receives a 0 at its gate.

[0039] As part of a read operation, word line transistors M14, M15 receive a digital 1 at their gates and are turned on. Transistor M13 is off because its gate receives a 0. The boosted VDD is applied to the gate of M12, thereby turning M12 on, and the increased gate-source voltage at M12 results in an incrementally higher value for the read current Iread. Therefore, the voltage at BL changes from VDD to VSS incrementally faster, and that faster response results in a differential voltage between BL and BLB such that the digital value stored in memory cell 400 is more easily detected by sense amplifier 113 (FIG. 1).

[0040] Of course, the scenario illustrated in Figure 4 is for one particular value stored in memory cell 400. If memory cell 400 stores the complementary value, a similar read operation will discharge the BLB.

[0041] 5 is a diagram of example signal timelines during a read operation and according to one implementation, with reference to signals shown in FIGS.

[0042] Prior to time T1, bst_cntrl and WL are both digital 0. Similarly, the voltage on the power rail vddhx_core is at ground. During a read operation, bst_cntrl changes from 0 to 1 (and, correspondingly, bst_cntrlb changes from 1 to 0). As explained above, this turns on transistors P<0-3> and P8. At time T2, the voltage on the power rail vddhx_core begins to rise, eventually reaching VDD+Δv2 around time T3. The extra voltage boost (Δv2) is due to capacitor C0 discharging onto the voltage rail vddhx_core.

[0043] In one example, the level of VDD may be approximately 645mV, and the boosted voltage level at the power rail vddhx_core may be approximately 665mV for a boost of approximately 3%. Of course, in various implementations, any suitable boost level may be used, and the size of the capacitor C0 may be selected to correspond to the desired boost level. For example, in other examples, a larger capacitor size may result in a larger boost of 5% or 10%. Similarly, a smaller boost of 2% or 1% may also be used, if desired.

[0044] Additionally, various control signals (e.g., nbl_control, bst_cntrl, and their complements) may be provided by a memory controller or other control circuitry (not shown), which may include, for example, the memory itself or digital logic implemented within a processor, such as a central processing unit (CPU), a graphics processing unit (GPU), or the like.

[0045] At time T3, the word line WL signal also goes high, which turns on transistors M14, M15 (FIG. 4) and allows either BL or BLB to discharge. The discharge of one of the bit lines produces a read current Iread, which affects the voltage sensed by the sense amplifier 113 (FIG. 1).

[0046] At time T4, WL is deasserted, and at time T5, the bst_contrl signal is also deasserted. Deasserting bst_cntrl changes bst_cntrlb to a digital 1, which turns off transistors P<0-3> and P8. At time T6, the voltage at the power rail vddhx_core drops to ground.

[0047] Some implementations may include one or more advantages. For example, simulations show that using a nominal VDD with a 5% VDD read boost during a read operation (as described above) can result in an 8% increase in read current Iread, a 6% improvement in access time, almost no extra semiconductor area usage, and only a 5% power penalty. Similarly, simulations show that using a slightly reduced VDD with a 5% VDD read boost and WLUD can result in a 10% increase in read current Iread, a 5% improvement in access time, almost no extra semiconductor area usage, and the same 5% power penalty. In other words, the boost circuit and method described herein can be used to improve the noise margin and access time of the read signal with only a small power penalty and almost no area penalty. The no area penalty can be achieved through reusing existing capacitors in the design for positive VDD boost in the memory cell.

[0048] An exemplary method for operating a memory device will now be discussed with reference to the flow chart shown in Figure 6. Method 600 may be performed by a memory device such as that shown in Figure 1 as it operates under the control of control circuitry that provides the various control signals of Figures 1-4. In other words, method 600 may be performed by a single or multi-bank memory system having at least one boost capacitor.

[0049] In action 610, the method includes coupling a first terminal of a capacitor to ground through a first transistor. One example may include coupling capacitor C0 to ground through transistor N4. A second terminal of the capacitor is coupled to a node that is floating and charged to a power supply voltage, such as that shown in FIG. 2, where node 201 is charged through the action of series inverter 251.

[0050] At action 620, the method includes disconnecting the first terminal from ground. For example, transistor N4 can be turned off by changing the polarity of signal nbl_control.

[0051] In action 630, the method includes coupling the first terminal to a power supply through a second transistor. For example, the first terminal of capacitor C0 may be coupled to vddhx through transistor P8.

[0052] In action 640, the method includes coupling the second terminal of the capacitor C0 to the power rail through a third transistor. Up until this point, node 201 may be floating, and then transistor P<0-3> is turned on by the same signal that turned on transistor P8. Transistor P<0-3> is coupled to node 201, and the second terminal of capacitor C0 is coupled to the power rail vddhx_core.

[0053] At action 650, the method includes boosting a power supply voltage of memory cells of the memory bank. In the example of Figure 2, various power rails vddhx_core are coupled to and through the memory bank to columns of memory cells.

[0054] The power rails in this example are coupled to a set of cross-coupled transistors, such as those shown in Figure 4. Specifically, the power rails are coupled to the cross-coupled transistors at one end of the memory cell, and the other end of the memory cell is coupled to ground (e.g., VSS). The power rails provide voltage to the gates of two of the transistors in the memory cell at a time. The power rails are physically separate from the bitlines BL, BLB, and wordlines.

[0055] As a result of the boosted power supply, the transistor of the memory cell is turned on and passes a read current (e.g., Iread) from one of the bit lines through the source and drain of the transistor to ground. The difference in voltage on the bit lines BL, BLB may allow the memory cell to be read by a sense amplifier.

[0056] In action 660, the method includes applying a negative boost to the write driver, including discharging the capacitor during a write operation. Specifically, in some implementations, the same capacitor may be used for both a positive boost during a read operation and a negative boost during a write operation. For example, the capacitor C0 may be charged by being coupled to ground at its first terminal through a first transistor (e.g., N4 in FIG. 2) and to a power supply at its second terminal through, for example, a series inverter 251. The first terminal may then be disconnected from ground while applying a ground voltage to the second terminal, for example, by changing the polarity of a control signal at the series inverter 251. As a result, a negative boost is applied to VSS at the write driver.

[0057] 2, it is noted that a capacitor C0 is coupled at its first terminal to a node vss_boost that is used to provide a negative boost to the write driver. The same capacitor C0 is coupled by its second terminal to the power rail vddhx_core. In other words, the same capacitor C0 can be charged and discharged during both read and write operations to provide the desired boost to either the write circuit or the memory cell.

[0058] The scope of implementations is not limited to the sequence of actions described with respect to FIG. 8. Rather, other implementations may add, omit, rearrange, or modify one or more actions. For example, during operation of the memory system, a read operation may be performed on a first memory bank or on a second memory bank, and then a subsequent read operation may be performed on either the first memory bank or the second memory bank, and so on and so forth. The read operations may or may not be interspersed with write operations, and the operations may be repeated as necessary. Also, some implementations may omit the negative boost during write operations.

[0059] 7 is a diagram of an exemplary SOC 700 according to one implementation. In this example, the SOC 700 is implemented on a semiconductor die and includes multiple system components 710-770. Specifically, in this example, the SOC 700 includes a CPU 710, which is a multi-core general-purpose processor having four processor cores, core 0-core 3. Of course, the scope of implementations is not limited to any particular number of cores, as other implementations may include two cores, eight cores, or any other suitable number of cores in the CPU 710. The SOC 700 further includes other system components, such as a first digital signal processor (DSP) 740, a second DSP 750, a modem 730, a GPU 720, a video subsystem 760, a wireless local area network (WLAN) transceiver 770, and a video-front-end (VFE) subsystem 780. The SOC 700 also includes a RAM memory unit 790 that may operate as a system RAM for any of the components 710-780. For example, the RAM memory unit 790 may receive data and instructions from any of the components 710-780.

[0060] The RAM memory unit 790 may include boost circuitry, such as that described above with respect to Figures 1-5. Additionally, the RAM memory unit 790 may perform the operations of Figure 6 to perform read and write operations.

[0061] As will be appreciated by those skilled in the art at present, and depending on the specific application at hand, numerous modifications, substitutions, and variations can be made in and to the materials, arrangements, configurations, and methods of use of the devices of the present disclosure without departing from the scope thereof. In light of this, and as the specific embodiments illustrated and described herein are merely by way of example of some of the same, the scope of the present disclosure should not be limited to the scope of such specific implementations, but rather should be fully equivalent to the scope of the following appended claims and their functional equivalents.

[0062] The following numbered clauses describe example implementations. 1. A circuit comprising: a random access memory (RAM) cell coupled to the first power rail; a boost circuit coupled to a first power rail, the boost circuit including a capacitor having a first terminal and a second terminal, the first terminal of the capacitor coupled to a first power supply through a first transistor and to ground through a second transistor, the second terminal of the capacitor coupled to a first plurality of parallel transistors, the first plurality of parallel transistors coupled to a plurality of power rails including the first power rail, and a second plurality of parallel transistors coupled to the plurality of power rails and to the second power supply. 2. 13. The circuit of claim 1, further comprising a write driver coupled between the first power supply and the first terminal of the capacitor. 3. The circuit of clause 2, wherein a first terminal of the first transistor and the capacitor are coupled to ground through a second transistor and a third transistor, the first transistor and the third transistor are gate-coupled to a first signal, and the second transistor is gate-coupled to a second signal. 4. The circuit of claim 3, wherein a first plurality of parallel transistors are gate-coupled to a first signal and a second plurality of parallel transistors are gate-coupled to a complement of the first signal. 5. The circuit of claim 4, wherein the first transistor comprises a p-type metal oxide semiconductor (PMOS) device and the second transistor comprises an n-type metal oxide semiconductor (NMOS) device. 6. The circuit of clause 4, wherein the first plurality of parallel transistors comprises p-type metal-oxide semiconductor (PMOS) devices and the second plurality of parallel transistors comprises PMOS devices. 7. The circuit of claim 4, wherein the capacitor includes a p-type metal oxide semiconductor (PMOS) transistor gate-coupled to the first transistor, the second transistor, and the write driver. 8. The circuit of clause 7, wherein the source of the PMOS transistor and the drain of the PMOS transistor are coupled to either the source or the drain of the first plurality of parallel transistors, and the second terminal of the capacitor is coupled to a second signal through a plurality of inverters. 9. The circuit of any one of clauses 1 to 8, wherein each power rail of the plurality of power rails corresponds to a respective memory core of the plurality of memory cores, and the RAM cell corresponds to a first memory core of the plurality of memory cores and corresponds to a first column of the first memory core. 10. A method of operating a memory system, the method comprising: coupling a first terminal of a capacitor to ground through a first transistor, the first terminal of the capacitor being floating and coupled to a node charged to a power supply voltage; disconnecting the first terminal from ground; coupling the first terminal to a power supply through a second transistor; coupling the second terminal through a third transistor to a power rail, the power rail serving the memory bank; boosting a power supply voltage for memory cells of the memory bank, the boosting including discharging a capacitor onto a power rail; A method comprising: 11. The method of claim 10, wherein coupling the first terminal to ground through the first transistor includes charging a capacitor according to a first polarity. 12. 12. The method of claim 10 or 11, further comprising reading a bit stored in the memory cell, the reading comprising discharging the bit line through a fourth transistor, the fourth transistor being gate-coupled to a power supply voltage of the memory cell. 13. The method of any one of clauses 10 to 12, wherein boosting the power supply voltage of the memory cells is performed during a read operation of the memory bank. 14. coupling the first terminal to ground through a first transistor while coupling the second terminal to a power source through a series of inverters; disconnecting the first terminal from ground while coupling the second terminal to ground; applying a negative boost to a write driver, the negative boost including discharging a capacitor during a write operation of the memory system; 14. The method of any one of clauses 10 to 13, further comprising: 15. Applying a negative boost to the write driver 15. The method of claim 14, comprising lowering a source voltage of a fourth transistor in the write driver to a value below ground. 16. The method of any one of clauses 10 to 15, wherein the first transistor comprises an n-type metal oxide semiconductor (NMOS) device, the second transistor comprises a p-type metal oxide semiconductor (PMOS) device, and the third transistor comprises a PMOS device. 17. A random access memory (RAM), comprising: a first memory bank having a plurality of bit cells arranged in columns and rows; means for matching a voltage level of the input data to a level suitable for writing to the first memory bank; means for detecting output data read from the first memory bank; means for providing a negative boost to the means for matching voltage levels; means for providing a positive boost to a power rail coupled to memory cells in the first memory bank; Equipped with RAM. 18. The RAM of clause 17, wherein the means for providing a negative boost and the means for providing a positive boost share a capacitor. 19. The means for providing a negative boost includes: 19. The RAM of clause 17 or 18, comprising a capacitor having a first terminal and a second terminal, the first terminal of the capacitor being coupled to a first power supply through a first transistor and coupled to ground through a second transistor. 20. The means for providing a positive boost includes: a first plurality of parallel transistors coupled to the second terminal of the capacitor, the first plurality of parallel transistors being coupled to the power rail; and a second plurality of parallel transistors coupled to the power rail and to a second power supply; RAM as described in clause 19, including 21. A RAM as described in clause 20, wherein the first terminal of the first transistor and the capacitor are coupled to ground through a second transistor and a third transistor, the first transistor and the third transistor are gate-coupled to a first signal, and the second transistor is gate-coupled to a second signal. 22. The RAM of clause 21, wherein a first plurality of parallel transistors are gate-coupled to a first signal and a second plurality of parallel transistors are gate-coupled to a complement of the first signal. 23. The RAM of clause 22, wherein the first transistor comprises a p-type metal oxide semiconductor (PMOS) device and the second transistor comprises an n-type metal oxide semiconductor (NMOS) device. 24. The RAM of clause 22, wherein the first plurality of parallel transistors comprises p-type metal oxide semiconductor (PMOS) devices and the second plurality of parallel transistors comprises PMOS devices. 25. The RAM of clause 22, wherein the capacitor includes a p-type metal oxide semiconductor (PMOS) transistor gate-coupled to the first transistor, the second transistor, and the means for matching voltage levels. 26. The RAM of clause 25, wherein the source of the PMOS transistor and the drain of the PMOS transistor are coupled to either the source or the drain of the first plurality of parallel transistors, and the second terminal of the capacitor is coupled to a second signal through a plurality of inverters. 27. A system on chip (SOC), comprising: a random access memory having a write driver and a memory bank; a plurality of power rails, each of the power rails corresponding to a respective core in the memory bank, each of the power rails being coupled to a power input of a memory cell in the respective core; a boost circuit coupled to the write driver and to the memory bank, the boost circuit including a capacitor having a first terminal and a second terminal, the capacitor coupled between a power supply and a first node, the first node coupled to the second terminal and to a plurality of power rails. 28. The boost circuit is a first transistor coupling the first terminal of the capacitor to ground; and a plurality of series inverters coupling the second terminals of the capacitors to a power source; The SOC as set forth in Clause 27 further includes: 29. The SOC of clause 28, wherein the first terminal of the capacitor is coupled to either the source or the drain of the write driver transistor. 30. The SOC of clause 27, wherein a plurality of power rails are coupled to a non-shipping voltage source through a first plurality of transistors, the first plurality of transistors being gate-coupled to a signal that is also gate-coupled to a transistor coupling the first terminal of the capacitor to the power supply.

Claims

1. A random access memory (RAM), comprising: First power rail (vddhx_core <0> ) and multiple power rails (vddhx_core<0-3>) a first memory bank having a plurality of bit cells arranged in columns and rows; means for matching the voltage level of input data to a level suitable for writing to said first memory bank; means for detecting output data read from the first memory bank; means for providing a negative boost to said means for matching said voltage levels; means for providing a positive boost to the plurality of power rails (vddhx_core<0-3>) coupled to memory cells in the first memory bank; Equipped with said means for providing said negative boost comprising: a capacitor (C0) having a first terminal and a second terminal, the first terminal of the capacitor being coupled to a first power supply (vddhx) through a first transistor (P8) and to ground through a second transistor (N4); said means for providing said positive boost comprising: a first plurality of parallel transistors (P<0-3>) coupled to the second terminal of the capacitor, the first plurality of parallel transistors coupled to the plurality of power rails; and a second plurality of parallel transistors (P<4-7>) coupled to the plurality of power rails and to a second power supply (vddehx); Contains RAM.

2. The first terminal of the first transistor and the capacitor are coupled to the ground through the second transistor and the third transistor, the first transistor and the third transistor are gate-coupled to a first signal, and the second transistor is gate-coupled to a second signal. The RAM of claim 1.

3. The first plurality of parallel transistors are gate coupled to the first signal, and the second plurality of parallel transistors are gate coupled to the complement of the first signal. The RAM of claim 2.

4. The first transistor comprises a p-type metal oxide semiconductor (PMOS) device and the second transistor comprises an n-type metal oxide semiconductor (NMOS) device. The RAM of claim 3.

5. The first plurality of parallel transistors includes p-type metal oxide semiconductor (PMOS) devices, and the second plurality of parallel transistors includes PMOS devices. The RAM of claim 3.

6. The capacitor includes a p-type metal oxide semiconductor (PMOS) transistor gate-coupled to the first transistor, the second transistor, and the means for matching voltage levels. The RAM of claim 3.

7. The source of the PMOS transistor and the drain of the PMOS transistor are coupled to either the sources or drains of the first plurality of parallel transistors, and the second terminal of the capacitor is coupled to the second signal through a plurality of inverters. The RAM of claim 6.

8. 1. A method of operating a memory system, said method comprising: a capacitor (C0), the second terminal of which is floating and coupled to a node (201) charged to a power supply voltage, the first terminal of which is coupled to ground via a first transistor (N4); disconnecting the first terminal from ground; coupling the first terminal to a power supply (vddhx) through a second transistor (P8); coupling the second terminal to a power rail (vddhx_core) through a third transistor, the power rail serving a memory bank; boosting the power supply voltage for memory cells of the memory bank, the boosting including discharging the capacitor onto the power rail; Including, Boosting the power supply voltage comprises: coupling a first plurality of parallel transistors (P<0-3>) to the second terminal of the capacitor, the first plurality of parallel transistors being coupled to the power rail; and coupling a second plurality of parallel transistors (P<4-7>) to the power rail and a second power supply (vddehx); method.

9. Coupling the first terminal to ground through the first transistor includes charging the capacitor according to a first polarity. The method of claim 8.

10. and reading a bit stored in the memory cell, the reading including discharging a bit line through a fourth transistor, the fourth transistor having a gate coupled to the power supply voltage of the memory cell. The method of claim 8.

11. Boosting the power supply voltage of the memory cells is performed during a read operation of the memory bank. The method of claim 8.

12. coupling the first terminal to ground through the first transistor while coupling the second terminal to the power supply through a series of inverters; decoupling the first terminal from ground while coupling the second terminal to ground; applying a negative boost to a write driver, the negative boost including discharging the capacitor during a write operation of the memory system; Further includes The method of claim 8.

13. applying the negative boost to the write driver; reducing the source voltage of a fourth transistor in the write driver to a value below ground. The method of claim 12.

14. The first transistor comprises an n-type metal oxide semiconductor (NMOS) device, the second transistor comprises a p-type metal oxide semiconductor (PMOS) device, and the third transistor comprises a PMOS device. The method of claim 8.

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