Test system for high voltage and high current testing of multiple power semiconductor devices contained in a wafer, and contact system - Patents.com

Abstract

A test system (100) for high voltage and high current testing, particularly dynamic high voltage and dynamic high current testing, of power semiconductor devices contained in a wafer (W) is described. The test system (100) comprises a tester, a needle probe card (500) and a contact system (200). The contact system (200) comprises a wafer receiving conductive portion (202) and a test electrical circuit closure contact conductive portion (204). The test electrical circuit closure contact conductive portion (204) of the contact system is shaped and extends to determine respective linear and continuous current conduction paths (A) from each power semiconductor device to at least one test electrical circuit closure terminal (T) disposed in a predetermined non-variable direction (504). Each current conduction path (A) extends along a direction parallel to or coincident with the predetermined non-variable direction (504). The contact system (200) is also described.

Description

[Technical field]

[0001] The present invention relates generally to the field of high voltage and high current testing of multiple power semiconductor devices contained in a wafer, and in particular to a test system for high voltage and high current testing of multiple power semiconductor devices contained in a wafer, and in particular to a test system for testing dynamic parameters of such semiconductor devices. The present invention also relates to a contact system for use in such a test system. [Background technology]

[0002] In the field of semiconductor devices, it is common practice to perform testing on electronic devices before they are properly packaged into substrates or chips and sold for electrical / electronic applications.

[0003] Currently, it is known to perform tests on semiconductor devices for static parameters and dynamic parameters of the same device.

[0004] The two tests are typically performed at different points in the manufacturing process of a semiconductor device.

[0005] In particular, tests of static parameters are carried out under direct current.

[0006] In contrast, in dynamic parametric testing, alternating electronic signals are applied to the semiconductor device, for example involving state switching or polarity reversals.

[0007] Tests for characterization and validation of dynamic parameters in the presence of switching can pose problems with parasitic inductance. Indeed, parasitic inductance during signal switching can cause overvoltages that can damage both the tester and the semiconductor device under test.

[0008] As a result, it is very difficult to perform tests to evaluate dynamic parameters, especially early in the manufacturing / production process, and especially tests to verify and / or evaluate the actual operation of the device under test.

[0009] Furthermore, tests for the evaluation and / or verification of dynamic parameters become even more complicated when performed on power semiconductor devices, where the tests are performed at high voltages and currents and the powers involved are therefore very large.

[0010] Even if the parasitic inductance is very small, during high voltage and high current testing, the parasitic inductance may cause overvoltages that can cause irreparable damage to the power semiconductor device under test.

[0011] There are several known functional tests for semiconductor electronic devices, especially power devices, known in the industry by the abbreviations RBSOA, FBSOA, and SCSOA. To perform such functional tests, voltages on the order of kilovolts (kVolts) and currents of hundreds and up to thousands of amperes (kA) are expected to be used.

[0012] There is an increasing demand from manufacturers of power semiconductor devices to be able to detect possible defects in power semiconductor devices as early as possible in the manufacturing process of the power semiconductor devices. In particular, there is an increasing demand to test such power semiconductor devices while they are still in the early stages of the manufacturing process. As known to those skilled in the art, it is desirable to perform testing directly on a semiconductor wafer in which a plurality of devices are fabricated.

[0013] In the prior art, no test machine / test system is known that is capable of performing high voltage and high current tests on power electronic devices while the power electronic devices are still assembled on a wafer with other electronic devices, in particular to perform tests to evaluate and / or verify dynamic parameters of the power electronic devices before the power electronic devices are individually separated.

[0014] Contact systems for testing machines comprising a contact disk and a test circuit closing conductive plate are known in the art, in particular for static testing, in which the contact disk is only electrically connected to the test circuit closing conductive plate by means of flexible electrical wiring extending freely between the contact disk and the test circuit closing conductive plate.

[0015] However, the use of such electrical wiring for connecting the contact disks to the test electrical circuit closure conductors makes the contact system unsuitable for use in high voltage and high current testing of multiple power semiconductor devices, especially for testing dynamic parameters.

[0016] The use of such electrical wiring results in high parasitic inductance during dynamic parametric testing.

[0017] Modern power semiconductor devices are now designed with faster switching times, which advantageously reduces energy dissipation, and therefore these semiconductor devices should be tested at faster switching times, taking into account their fast switching times.

[0018] Unfortunately, the known contact systems mentioned above generate high parasitic inductances during dynamic parametric testing and may therefore be unusable for this type of testing.

[0019] In fact, if the parasitic inductance is large, it is not possible to supply power to the power semiconductor device and therefore to test the power semiconductor device at the desired switching speed. Summary of the Invention

[0020] One object of the present invention is to provide a test system capable of performing high voltage and high current testing, in particular dynamic high voltage and high current testing, on a plurality of power semiconductor devices comprised in a wafer, and a contact system for use in such a test system.

[0021] It is a further object of the present invention to provide a test system, and a contact system for use in such a test system, that is capable of performing dynamic high voltage and high current testing even when desired switching speeds are high.

[0022] The above mentioned and other objects and advantages are achieved according to a first aspect of the invention by a test system for high voltage and high current testing on a plurality of power semiconductor devices contained in a wafer having the features defined in claim 1 and according to a further aspect of the invention by a contact system having the features defined in claim 15. Preferred embodiments of the invention are defined in the dependent claims, the content of which is to be understood as an integral part of this specification.

[0023] In the following, functional and structural features of some preferred embodiments of a system for high voltage and high current testing of a plurality of power semiconductor devices contained in a wafer and a contact system according to the present invention will be described, with reference to the accompanying drawings. [Brief description of the drawings]

[0024] [Figure 1] FIG. 1 illustrates an example external structure of a test system for high voltage and high current testing of multiple power semiconductor devices contained in a wafer. [Diagram 2]FIG. 1 illustrates an exemplary embodiment of a contact system for a test system according to the present invention. [Diagram 3] FIG. 1 is an exploded perspective view of a contact system in which the test electrical circuit closure contact conductive portion and the wafer receiving conductive portion are two distinct elements. [Figure 4] FIG. 1 shows an exemplary embodiment of a handling system according to the invention; [Figure 5a] FIG. 1 illustrates an exemplary needle probe card. [Figure 5b] FIG. 1 illustrates an exemplary needle probe card when connected to a test electrical circuit closure terminal. [Figure 5c] 5b when the contact system is brought into contact with a test electrical circuit closure terminal. FIG. [Figure 6] 4 is an example of a possible movement of the contact system performed by a handling system according to the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] Before describing several embodiments of the present invention in detail, it is to be made clear that the application of the present invention is not limited to the design details and configuration of components set forth in the following description or illustrated in the drawings. The present invention may contemplate other embodiments and may actually be implemented or constructed in different ways. It is also to be understood that the phraseology and terminology are for descriptive purposes and should not be construed as limiting. The use of "include" and "comprise" and variations thereof are intended to include (cover) additional elements and their equivalents in addition to the elements listed thereafter and their equivalents.

[0026] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following, an embodiment of a test system for high voltage, high current testing, particularly high voltage, high current dynamic testing, on a plurality of power semiconductor devices included in a wafer will be described.

[0027] In one embodiment, the test system 100 comprises a tester configured to perform predetermined high voltage and high current test functions on a plurality of power semiconductor devices.

[0028] For example, a given test function may perform tests known by abbreviations such as RBSOA, FBSOA, and SCSOA, among others.

[0029] The current supplied to the power semiconductor device under test may be determined, for example, by a predetermined high voltage, high current test function performed by a tester.

[0030] The test system 100 further comprises a needle probe card 500 configured to be connected to a tester as described above. The needle probe card 500 comprises a plurality of needles 502 adapted to contact at least one power semiconductor device under test at a time among a plurality of power semiconductor devices included in a wafer W. Each needle is adapted to pass a current through at least one power semiconductor device under test. An exemplary needle probe card 500 is shown in FIG. 5a.

[0031] For example, all of the power semiconductor devices of a wafer W disposed on the wafer receiving conductive portion 202 may be brought into contact with the multiple needles 502 and subjected to testing, at least one at a time.

[0032] For example, during testing, the needles 502 (or at least a portion of the needles) may contact only one power semiconductor device at a time, or the needles 502 (or at least a portion of the needles) may simultaneously contact one subset of the power semiconductor devices of all of the power semiconductor devices at a time.

[0033] For example, in the field of testing of power semiconductor devices, the needle probe card 500 may contact multiple needles 502 to pass a current through the emitter or anode of at least one power semiconductor device under test. The needle probe card 500 comprises a large number of needles 502. This allows a very large current to be applied to the power semiconductor device while maximizing the use of the area of ​​the semiconductor device to reduce the current density per unit area of ​​the device and split the current among multiple needles. The needle probe card 500 may comprise an intrinsic safety system that monitors the current input to the probe card. This safety system may be capable of cutting off the input current to the needle probe card 500 if the total input current to the needle probe card 500 exceeds a predetermined DC current value. The needle probe card 500 may be coupled / associated with a suitable safety system such as that described in WO 2021 / 240431 (the applicant is the same as the applicant of the present patent application).

[0034] The test system further comprises a contact system 200. The contact system 200 is illustrated in Figure 2. The left side of Figure 2 shows a perspective view of the contact system 200, and the right side shows a top view of the same contact system 200.

[0035] The contact system 200 includes a wafer housing conductive portion 202 and a test electrical circuit closing contact conductive portion 204 .

[0036] The wafer receiving conductive portion 202 is provided to receive a wafer W that is contacted by the plurality of needles 502 of the needle probe card 500 during testing.

[0037] For example, the wafer receiving conductive portion 202 may extend along a given support surface.

[0038] The test electrical circuit closure contact conductive portion 204 is electrically connected to the wafer receiving conductive portion 202 .

[0039] The test system 100 further comprises at least one test electrical circuit closing terminal T.

[0040] As seen, for example, in FIG. 5 a , the at least one test electrical circuit closure terminal T is disposed at a predetermined, non-variable distance d 1 in a predetermined, non-variable direction 504 from a plurality of needles 502 of a needle probe card 500 .

[0041] Preferably, there may be a plurality of test electrical circuit closure terminals T, T', T'' arranged in respective predetermined directions 504, 504', 504'', as seen in FIG. 5a.

[0042] For example, at least one test electrical circuit closure terminal T may comprise one or more pogo pins.

[0043] At least one test electrical circuit closure terminal T is configured to be brought into contact with the test electrical circuit closure contact conductive portion 204 of the contact system 200 in use.

[0044] At least one test electrical circuit closure terminal T is coupled to the tester by a conductive path 506 disposed along a predetermined non-variable direction 504 .

[0045] For example, as described in more detail below, the at least one test electrical circuit closure terminal T may be directly coupled to the tester by the conductive path 506, or may be indirectly coupled to the tester by a needle probe card. In the latter case, the at least one test electrical circuit closure terminal T is connected to the needle probe card by the conductive path 506, and the needle probe card is connected to the tester.

[0046] At least a portion of the conductive path 506 facing the test electrical circuit closure contact conductive portion 204 is straight and parallel to the test electrical circuit closure contact conductive portion 204 of the contact system 200 .

[0047] For example, preferably, the portion of conductive path 506 facing test electrical circuit closure contact conductive portion 204 may be located between a fraction of a millimeter and several millimeters away from the conductive portion.

[0048] The test electrical circuit closure contact conductive portions 204 of the contact system 200 are shaped and extend to define respective linear and continuous current conduction paths A from each power semiconductor device to at least one test electrical circuit closure terminal T.

[0049] Each current conduction path A extends along a direction parallel to or coincident with the predetermined non-variable direction 504 described above.

[0050] In other words, each linear current conduction path A may extend along a direction parallel to or coincident with a predetermined non-variable direction 504 in which a test electrical circuit closing terminal T coupled to the tester via a conductive path 506 is located.

[0051] Advantageously, since 1) the part of the conductive path 506 facing the test electrical circuit closure contact conductive portion 204 is linear and parallel to the test electrical circuit closure contact conductive portion 204 of the contact system, and 2) the current conduction path A is linear and extends along a direction parallel to or coincident with the predetermined non-variable direction 506 along which the current-flowing conductive path 506 is disposed, the parasitic inductance is compensated and kept at a low level, thereby allowing dynamic testing to be performed even on power semiconductor devices.

[0052] As is well known in the art, inductance increases as the area between conductors increases. Because current conduction path A and conductive path 506 are parallel to one another, the area between the conductors is reduced, which reduces the parasitic inductance.

[0053] FIG. 1 illustrates a possible external structure of the aforementioned test system 100. This structure may include an external housing. The external housing may contain elements of the test system. For example, block 101 ("test machine") may contain a test machine. Block 103 ("chuck handler") may include a contact system, a test electrical circuit closure terminal, and a needle probe card. Between blocks 101 and 103, block 102 ("probe card interface") may be provided. Block 102 may include a needle probe card interface module. For example, block 102 may be associated with or included in block 101.

[0054] Preferably, the contact system 200 comprises: a) configured to receive a current output from at least one power semiconductor device under test; or b) may be configured to deliver a current provided as an input to the at least one power semiconductor device under test.

[0055] In case a), the test electrical circuit closure terminal T may be configured to receive a current flowing into the contact system.

[0056] In case b), the test electrical circuit closure terminal T may be configured to supply an electric current to the contact system 200 .

[0057] In other words, when the power semiconductor device is tested (the power semiconductor device is subjected to test), current entering or exiting the power semiconductor device can be caused to flow in the test electrical circuit closure contact conductive portion 204 of the contact system 200 along an associated linear and continuous current conduction path A toward the test electrical circuit closure terminal T.

[0058] It may occur for each power semiconductor device that current entering or leaving the power semiconductor device under test may flow along an associated linear and continuous current conduction path A towards the test electrical circuit closure terminal T in the test electrical circuit closure contact conductive portion 204 of the contact system 200.

[0059] Preferably, as seen in FIG. 5b, a first end 506′ of the conductive path 506 may be configured to be connected to at least one test electrical circuit closure terminal T. A second end 506″ opposite to the first end of the conductive path 506 may be configured to be connected to a needle probe card 500 that is connected to a tester. FIG. 5c shows the needle probe card 500 illustrated in FIG. 5b when the contact system 200 is brought into contact with the test electrical circuit closure terminal T. The left side of FIG. 5c shows a perspective view of the contact system and the needle probe card, and the right side of FIG. 5c shows a side view of the contact system and the needle probe card.

[0060] In an alternative example, not shown, a first end of the conductive path may be configured to be connected to at least one test electrical circuit closure terminal, and a second end of the conductive path opposite the first end may be configured to be directly connected to a test machine.

[0061] In any example, the conductive path 506 may include one or more electrical cables. For example, all electrical cables may be encapsulated and embedded in an insulating sheath. The insulating sheath may be made of a non-deforming material because the position of the test electrical circuit closure terminal T relative to the multiple needles 502 of the needle probe card 500 is not variable.

[0062] Preferably, the test circuit closing contact conductive portion 204 and the wafer receiving conductive portion 202 may be made integrally.

[0063] 3, the test electrical circuit closure contact conductive portion 204 and the wafer receiving conductive portion 202 of the contact system 200 may be at least two different elements. In such a case, the test electrical circuit closure contact conductive portion 204 may be stably fixed in contact with the wafer receiving conductive portion 202.

[0064] For example, to achieve stable fixation (coupling), the test electrical circuit closing contact conductive portion 204 may be stably fixed to the wafer receiving conductive portion 202 via a suitable coupling or fastening means 206 (e.g., via an interlocking means or screws).

[0065] Preferably, the test electrical circuit closure contact conductive portion 204 may include a through hole 208 or housing configured to receive (accommodate) the wafer-receiving conductive portion 202 .

[0066] Preferably, the wafer receiving conductive portion 202 may be included in a contact disk 300 .

[0067] For example, the contact disk may be of any type already known in the art. In general, the contact disk is typically provided to accommodate the wafer under test.

[0068] For example, although not required, the wafer receiving conductive portion 202 (e.g., a contact disk) may include suction holes, e.g., connected to a pump. Air drawn by the pump through the suction holes may be used to hold the wafer in place during testing. Indeed, any shifting of the wafer W during testing may cause damage to the wafer and / or the testing machine performing the test. For example, the suction holes may be formed in a support surface of the wafer receiving conductive portion 202. Also, by drawing the wafer W into the wafer receiving conductive portion 202, contact resistance may be reduced.

[0069] For example, a heating system may be associated with the wafer receiving conductive portion 202. Such a heating system may be configured to heat the wafer receiving conductive portion 202. For example, because dynamic testing is typically performed at a temperature of 175° C. (i.e., the junction temperature indicated by the data sheet of the power semiconductor device), the heating system may bring the wafer to a temperature of substantially 175° C.

[0070] Preferably, the test electrical circuit closing contact conductive portion 204 and the wafer receiving conductive portion 202 may be arranged on separate planes parallel to each other, or both may be arranged on a single plane (e.g., the single plane coincides with the wafer receiving plane 202).

[0071] Preferably, the contact system 200 may have a generally triangular shape, as can be seen, for example, in Figures 2 and 3. One or more apexes of the triangle may be rounded. The wafer-receiving conductive portion 202 of the contact system 200 may be located at one of the apexes of the triangle.

[0072] In an exemplary embodiment, the contact system 200 may have the shape of an isosceles triangle with rounded apexes, where the wafer-receiving conductive portion 202 may be located at the apex of the triangle opposite the base of the triangle.

[0073] It will be apparent that in different embodiments, the shape of the contact system 200 may also be different (eg, rectangular, square, etc.).

[0074] Preferably, the test electrical circuit closure contact conductive portion 204 may be made of the same conductive material as the wafer receiving conductive portion 202. The test electrical circuit closure contact conductive portion 204 may have a thickness in the range of several millimeters.

[0075] Preferably, the test system 100 may include a handling system 400. The handling system 400 is configured to move the contact system such that all of the power semiconductor devices of the wafer W arranged on the wafer receiving conductive portion 202, at least one at a time, come into contact with the multiple needles 502 and can be tested.

[0076] An exemplary embodiment of the handling system is shown in FIG.

[0077] Handling is performed such that at any position to which the contact system 200 is moved by the handling system 400, at least one test electrical circuit closure terminal T is configured to contact the test electrical circuit closure contact conductive portion 204 of the contact system 200.

[0078] For example, suitable guides 402 may be provided for moving the contact system 200, and the movement may be caused by one or more electric motors M1, M2.

[0079] Preferably, as can be seen in figures 5c and 6, the handling system may be configured to move the contact system according to three mutually orthogonal movement directions x, y, z.

[0080] In particular, figure 5c shows the direction z in which the contact system may move, and figure 6 shows the directions of movement x, y in which the contact system may move.

[0081] For example, the center of FIG. 6 shows a case where the center O of the wafer-receiving conductive part 202 of the contact system is aligned with the intersection of the x and y directions of movement. The right side of FIG. 6 shows a case where the contact system is shifted in the positive direction of the x direction of movement with respect to the intersection of the x and y directions of movement. The left side of FIG. 6 shows a case where the contact system is shifted in the negative direction of the x direction of movement with respect to the intersection of the x and y directions of movement. The top side of FIG. 6 shows a case where the contact system is shifted in the negative direction of the y direction with respect to the intersection of the x and y directions of movement. The bottom side of FIG. 6 shows a case where the contact system is shifted in the positive direction of the y direction with respect to the intersection of the x and y directions of movement. It is clear that the positions of the needle probe card 500, the test electrical circuit closure terminal T and the conductive path 506 do not change in any of the four movement examples shown in FIG. 6.

[0082] Preferably, the handling system 400 may be configured to move the contact system 200 according to a pre-defined path.

[0083] Preferably, the pre-defined paths may be stored in a suitable storage medium associated with or included in the test system 100 .

[0084] For example, the storage medium may be a memory, such as the following memory: -Non-volatile memory, i.e. memory that can retain information even in the absence of power (examples of non-volatile memory include ROM, flash memory, and most magnetic memories). -Volatile memory (temporary memory), which, unlike non-volatile memory, requires a continuous supply of power to continue to store data (examples of non-volatile memory include RAM [DRAM or SRAM], T-RAM, Z-RAM, TT-RAM, etc.).

[0085] For example, the above-mentioned path may be appropriately determined by a user depending on the type of test to be performed and the shape of the wafer W.

[0086] Alternatively, the pre-defined path may be determined by a pre-defined high voltage, high current test function performed by the tester, or in other words, the path may be automatically determined by a pre-defined wafer map function performed by the tester.

[0087] In a further aspect, the present invention relates to a contact system 200 for use in a test system 100 according to any of the above-described embodiments.

[0088] The contact system is - a wafer receiving conductive portion 202, and a test electrical circuit closing contact conductive portion 204;

[0089] The wafer receiving conductive portion 202 is provided to receive a wafer W that is contacted by the plurality of needles 502 of the needle probe card 500 during testing.

[0090] The test electrical circuit closure contact conductive portion 204 is electrically connected to the wafer receiving conductive portion 202 .

[0091] In use, the test electrical circuit closure contact conductive portion 204 is configured to contact at least one test electrical circuit closure terminal T of the test system 100 such that the test electrical circuit closure contact conductive portion 204 of the contact system 200 is parallel to a test system conductive path 506 that couples the at least one test electrical circuit closure terminal T of the test system 100 to a tester of the test system 100.

[0092] As a result, the following advantages are achieved: A test system is provided that can reduce parasitic inductance that may occur when performing high voltage tests and high current tests, particularly dynamic high voltage tests and dynamic high current tests, on a plurality of semiconductor devices included in a wafer, and that can perform these tests on power semiconductor devices that remain embedded in the wafer along with other electronic devices, and a contact system for use in such a test system is provided.

[0093] A further advantage is that it provides a solution for testing power semiconductor devices at desired switching speeds.

[0094] Various aspects and embodiments of a test system and contact system for high voltage and high current testing of a plurality of power semiconductor devices contained in a wafer according to the present invention have been described. It should be understood that each embodiment can be combined with any other embodiment. Furthermore, the present invention is not limited to the above-described embodiments, and various modifications are possible within the scope defined by the appended claims.

Claims

1. A test system (100) for high-voltage, high-current testing, particularly dynamic high-voltage, dynamic high-current testing, of multiple power semiconductor devices contained in a wafer (W), A test machine configured to perform predetermined high-voltage and high-current test functions on the aforementioned plurality of power semiconductor devices, The system includes a needle probe card (500) configured to be connected to the aforementioned testing machine, The needle probe card (500) is The wafer (W) comprises a plurality of needles (502) adapted to contact at least one power semiconductor device under test at a time, and each needle is adapted to conduct current through the at least one power semiconductor device under test. The aforementioned test system further, The contact system (200) comprises a wafer housing conductive portion (202) and a test electrical circuit closed contact conductive portion (204), The wafer housing conductive portion (202) is provided for housing the wafer (W) which will be in contact with the plurality of needles (502) of the needle probe card (500) during testing. The test electrical circuit closed contact conductive portion (204) is electrically connected to the wafer housing conductive portion (202), The test system (100) further comprises at least one test electrical circuit closed terminal (T) positioned at a predetermined non-variable distance (d1) from the plurality of needles (502) of the needle probe card (500) in a predetermined non-variable direction (504), The at least one test electrical circuit closed terminal (T) is configured to be able to contact the test electrical circuit closed contact conductive portion (204) of the contact system (200), The at least one test electrical circuit closed terminal (T) is connected to the test machine by a conductive path (506) arranged along the predetermined non-variable direction (504). A portion of the conductive path (506) facing the test electrical circuit closed contact conductive portion (204) is linear and parallel to the test electrical circuit closed contact conductive portion (204) of the contact system (200). The test electrical circuit closed contact conductive portion (204) of the contact system has a shape that defines a linear and continuous current conduction path (A) from each power semiconductor device to the at least one test electrical circuit closed terminal (T), and extends in such a manner. A test system in which each current conduction path (A) extends along a direction parallel to the predetermined non-variable direction (504) or a direction coinciding with the predetermined non-variable direction (504).

2. The aforementioned contact system (200) is It is configured to receive the current from at least one of the power semiconductor devices under test, or It is configured to transmit the current supplied as input to the at least one power semiconductor device under test, If the contact system (200) is configured to receive the current from the at least one power semiconductor device under test, the at least one closed test electrical circuit terminal (T) is configured to receive the current flowing into the contact system (200). The test system according to claim 1, wherein if the contact system (200) is configured to transmit a current supplied as input to the at least one power semiconductor device under test, the at least one closed test electrical circuit terminal (T) is configured to supply the current to the contact system (200).

3. The first end (506') of the conductive path (506) is configured to be connected to the at least one test electrical circuit closed terminal (T), The test system according to claim 1 or 2, wherein the second end (506'') of the conductive path (506) opposite to the first end is configured to be connected to the needle probe card (500).

4. The test system according to claim 1 or 2, wherein the test electrical circuit closed contact conductive portion (204) and the wafer housing conductive portion (202) are integrally manufactured.

5. The test electrical circuit closed contact conductive portion (204) and the wafer housing conductive portion (202) are made of at least two separate elements. The test system according to claim 1 or 2, wherein the test electrical circuit closed contact conductive portion (204) is in contact with and stably fixed to the wafer housing conductive portion (202).

6. The test system according to claim 5, wherein the test electrical circuit closed contact conductive portion (204) comprises a through hole (208) or housing configured to receive the wafer housing conductive portion (202).

7. The test system according to claim 1 or 2, wherein the test electrical circuit closed contact conductive portion (204) and the wafer housing conductive portion (202) are arranged on separate planes parallel to each other, or both are arranged on a single plane.

8. The contact system (200) has a substantially triangular shape, One or more vertices of the aforementioned triangle are rounded, The test system according to claim 1 or 2, wherein the wafer housing conductive portion (202) of the contact system is located at one of the vertices of the triangle.

9. The test system according to claim 1 or 2, wherein the test electrical circuit closed contact conductive portion (204) is made of the same conductive material as the wafer housing conductive portion (202).

10. The test system according to claim 1 or 2, wherein the wafer housing conductive portion (202) is included in the contact disk (300).

11. A handling system (400) is provided, and the handling system (400) is configured to move the contact system (200) so that at least one at a time all of the power semiconductor devices of the wafer arranged on the wafer housing conductive portion come into contact with the plurality of needles (502) and are subject to testing. The test system according to claim 1 or 2, wherein at any position where the contact system (200) is moved by the handling system, the at least one test electrical circuit closed terminal (T) is configured to contact the test electrical circuit closed contact conductive portion (204) of the contact system (200).

12. The test system according to claim 11, wherein the handling system (400) is configured to move the contact system according to three mutually orthogonal directions of movement (x, y, z).

13. The test system according to claim 11, wherein the handling system (400) is configured to move the contact system (200) according to a predetermined path.

14. The aforementioned pre-configured route is stored in an appropriate storage means associated with or included in the test system, or The test system according to claim 13, wherein the pre-set path is determined by a predetermined wafer mapping function performed by the test machine.

15. A contact system (200) for use in the test system (100) according to claim 1 or 2, wafer housing conductive section (202), The test electrical circuit includes a closed contact conductive part (204), The wafer housing conductive portion (202) is provided for housing a wafer (W) that will be in contact with a plurality of needles (502) of a needle probe card (500) during testing. The test electrical circuit closed contact conductive portion (204) is electrically connected to the wafer housing conductive portion (202), A contact system in which, when in use, the test electrical circuit closed contact conductive portion (204) is brought into contact with at least one test electrical circuit closed terminal (T) of the test system (100), and the test electrical circuit closed contact conductive portion (204) of the contact system is made parallel to the conductive path (506) of the test system that connects at least one test electrical circuit closed terminal (T) of the test system to the test machine of the test system.

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