Memory and memory access methods

Abstract

The memory includes an array of memory cells, memory access logic programmable to generate write assignments that map an input including a first sequence of data elements to a plurality of memory cells of the array and read assignments that map the plurality of memory cells of the array to an output including a second sequence of data elements, and a memory controller configured to write the plurality of data elements at the input to the array based on the write assignments and to read the plurality of data elements stored in the array to the output based on the read assignments.

Description

[Technical field]

[0001] The present invention relates to memory. The present invention is particularly, but not exclusively, applicable to methods and apparatus for programmable non-random access memory arrays, which may provide cell-based memory reading and writing. [Background technology]

[0002] The memory architecture is essential for reducing latency in intensive computing applications such as fully homomorphic encryption, Fourier transforms, and artificial intelligence.

[0003] Data stored in random access memory (RAM) typically consists of multiple rows, and read / write operations are typically performed across rows of data (consisting of multiple columns). Data throughput from RAM can be affected by read / write conflicts (also known as non-repeatable reads or reading uncommitted data). Uncommitted data is data that is being updated but not yet durably committed to the database. In other words, data that has been updated but the updates have not yet been persisted. In memory architectures, when both a read and a write operation attempt to access the same location in memory, a read / write conflict occurs, resulting in the write operation writing a value that is inconsistent with the database compared to the value read by the read operation. This slows down intensive computing tasks. Many traditional computer architectures suffer from a limitation known as the von Neumann bottleneck, which provides high processing power but slow memory access.

[0004] Register memory is a fast memory that is typically used for buffering data. However, register memory has a limited capacity. Therefore, register memory is generally only used to hold frequently used data, instructions, and memory addresses for easy access. Summary of the Invention [Problem to be solved by the invention]

[0005] The invention is defined in the accompanying independent claims.

[0006] This Summary is intended to introduce concepts that are more fully described in the Detailed Description. This Summary is not intended to identify essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0007] This disclosure describes a hybrid memory architecture that allows data to be stored discontinuously in any memory cell location that is programmed and synchronized using a state machine controller and a write state counter. Similarly, data is read from any memory cell location that is determined using a similar program and synchronized by another state machine controller and a read state counter. The state machine controller is a controller that can respond to a finite number of different conditions, and the state machine is a behavioral model called a finite state machine (FSM). The memory architecture includes in-memory arithmetic logic that can perform simple arithmetic operations (addition, two's complement conversion, increment, decrement, bit shift, etc.) and logical operations (AND, OR, XOR, NOR, NAND, etc.) on the data. The in-memory arithmetic logic allows arithmetic and logical operations to be performed on the data stored in the memory cells, reducing latency. [Means for solving the problem]

[0008] The present disclosure provides a memory including an array of memory cells, memory access logic programmable to generate write assignments that map an input including a data element to a plurality of memory cells of the array and read assignments that map the plurality of memory cells of the array to an output including a plurality of data elements, and a memory controller configured to write the plurality of data elements of the input to the array based on the write assignments and to read the plurality of data elements stored in the array to the output based on the read assignments.

[0009] Thus, there is provided a memory including an array of a plurality of memory cells, memory access logic programmable to generate a write assignment that maps an input including a plurality of data elements in a first sequence to a plurality of memory cells of the array and a read assignment that maps the plurality of memory cells of the array to an output including a plurality of data elements of a second sequence, and a memory controller configured to write the plurality of data elements at the input to the array based on the write assignment and to read the plurality of data elements stored in the array to the output based on the read assignment.

[0010] Optionally, the first sequence is different from the second sequence, and a first sequence order of the plurality of data elements at the input is different from a second sequence order of the plurality of data elements at the output.

[0011] Optionally, the inputs are parallel inputs of a first width and the outputs are parallel outputs of a second width, preferably the first width and the second width being the same.

[0012] Optionally, the memory access logic is configured to be reprogrammed to generate different write and read allocations.

[0013] Optionally, the data elements at the input and output are either single bits of a data word or multi-bit words of a data string.

[0014] Optionally, the most significant bit to the least significant bit of each single bit or the most significant word to the least significant word of each multi-bit word is mapped to the input or read to the output in parallel.

[0015] Optionally, the write assignment maps the input to a first subset of each of the plurality of memory cells of the array in a first subset order, and the read assignment reads a second subset of each of the plurality of memory cells to the output in a second subset order.

[0016] Optionally, each of the first subsets includes a first arrangement of the plurality of memory cells of the array, and each of the second subsets includes a second arrangement of the plurality of memory cells of the array.

[0017] Optionally, each first arrangement is different from each second arrangement.

[0018] Optionally, each of the first arrangements has a width equal to the first width of the input and the second width of the output.

[0019] Optionally, the first arrangement and the second arrangement each have a width equal to a first width of the input and a second width of the output.

[0020] Optionally, the first subset order is different from the second subset order.

[0021] Optionally, each of the first subsets constitutes a row or column of multiple memory cells of the array.

[0022] Optionally, each of the first subsets constitutes a row of a plurality of memory cells of the array.

[0023] Optionally, each of the first subsets constitutes a column of a plurality of memory cells of the array.

[0024] Optionally, each of the second subsets constitutes a row or column of multiple memory cells of the array.

[0025] Optionally, each of the second subsets constitutes a row of multiple memory cells of the array.

[0026] Optionally, each of the second subsets constitutes a column of a plurality of memory cells of the array.

[0027] Optionally, each of a first subset of the plurality of memory cells of the array are adjacent, and the input is mapped to each of the first subset of the plurality of adjacent memory cells of the array, and each of a second subset of the plurality of memory cells of the array are adjacent, and the output is read from each of the second subset of the plurality of adjacent memory cells of the array.

[0028] Optionally, each single bit or each multi-bit word is mapped to a respective first subset of adjacent memory cells of the array, and each single bit or each multi-bit word is read to the output from a respective second subset of adjacent memory cells of the array.

[0029] Optionally, the second subset order of the plurality of memory cells of the array that is read to the output is a predetermined shift of the first subset order of the plurality of memory cells of the array.

[0030] Optionally, the second subset order of the plurality of memory cells of the array that is read to the output is a rotation of the first subset order of the plurality of memory cells of the array.

[0031] Optionally, the first subset order is a butterfly transpose of the multiple data elements in the input.

[0032] Optionally, each of the first subset of the plurality of memory cells of the array and each of the second subset of the plurality of memory cells of the array both include at least one single bit from a respective data word or at least one multi-bit word from a respective data string at the input.

[0033] Optionally, each row or column of memory cells of the first subset of the array includes a plurality of multi-bit words of one data string of the plurality of data strings at the input, and each second subset of the plurality of memory cells of the array includes at least one multi-bit word from a respective data string of the plurality of data strings at the input.

[0034] Optionally, the memory access logic includes read logic and write logic, the read logic generating the read allocations and the write logic generating the write allocations.

[0035] Optionally, the memory access logic includes a read state controller and a write state controller.

[0036] Optionally, the memory further comprises a memory interface configured to transfer a plurality of data elements at an input to a plurality of memory cells of the array, and to transfer a plurality of data elements stored in the plurality of memory cells of the array to an output.

[0037] Optionally, the memory interface includes a read data bus and a write data bus, the read data bus and the write data bus configured to transfer instructions to the memory access logic for programming the memory access logic.

[0038] Optionally, the read data bus and the write data bus are configured to provide a read counter, a write counter and status control to the memory access logic.

[0039] Optionally, the read state controller and the write state controller are configured to use the read and write counters and status controls to set, reset, read or write both data and sequence counters in the memory access logic.

[0040] Optionally, the memory further includes a data allocator switch fabric configured to connect the memory cells to the memory access logic and the memory controller.

[0041] Optionally, the data allocator switch fabric includes a switch fabric, a read data allocator, and a write data allocator, the read data allocator and the write data allocator configured to decode an address of the array corresponding to a read allocation or a write allocation.

[0042] Optionally, the switch fabric is mapped to the size of the bus according to the bit number of each piece of data.

[0043] Optionally, the plurality of memory cells of the array are divided into a first memory cell sub-group and a second memory cell sub-group, and the input includes a first input frame and a second input frame, the first input frame including a first data element and a second data element, and the second input frame including a third data element and a fourth data element.

[0044] Optionally, the write allocation maps a first data element to a first memory cell in the first memory cell subgroup, a second data element to a first memory cell in the second memory cell subgroup, a third data element to a second memory cell in the first memory cell subgroup, and a fourth data element to a second memory cell of the second memory cell subgroup.

[0045] Optionally, a translation relationship between the positions of the first memory cells and the positions of the second memory cells in the first memory cell subgroup corresponds to or is the same as a translation relationship between the positions of the first memory cells and the positions of the second memory cells in the second memory cell subgroup.

[0046] Optionally, the transformation relationship is a translation relationship or a rotation relationship, and optionally the transformation relationship is a rotation or translation by a single memory cell from one memory cell to an adjacent memory cell.

[0047] Optionally, an order of the first data elements in the first input frame corresponds to an order of the third data elements in the second input frame, and an order of the second data elements in the first input frame corresponds to an order of the fourth data elements in the second input frame.

[0048] Optionally, the read assignment maps a plurality of memory cells of the array to an output including a first output frame including the first data element and the third data element, and a second output frame including the second data element and the fourth data element.

[0049] Optionally, an order of the first data elements in the first output frame matches an order of the second data elements in the second output frame.

[0050] Optionally, an order of the third data elements in the first output frame matches an order of the fourth data elements in the second output frame.

[0051] Optionally, the first input frame and the second input frame each include data corresponding to light intensity values ​​detected at an output plane of the optical Fourier transform stage.

[0052] Optionally, each of the first data element and the second data element corresponds to a light intensity value detected at one of a plurality of ports in an array at an output face of an optical Fourier transform stage, and each of the third data element and the fourth data element corresponds to a light intensity value detected at one of a plurality of ports in an array at an output face of the same or another optical Fourier transform stage.

[0053] Optionally, the relative order of the first and second data elements in the first input frame and the relative order of the third and fourth data elements in the second input frame each correspond to a relative position of one of the multiple ports in the array at the output face of the respective optical Fourier transform stage, optionally the relative order being adjacent or subsequent positions in the order and the relative positions being adjacent positions of the multiple ports in the array.

[0054] Optionally, the first data element corresponds to a first detected intensity at a first port of a plurality of ports in an array at an output face of the optical Fourier transform stage, and the third data element corresponds to a second detected intensity at the first port.

[0055] Optionally, the second data element corresponds to a third detection strength at a second port of the plurality of ports in the array, and the fourth data element corresponds to a fourth detection strength at the second port.

[0056] Also provided is a method that includes generating, in memory access logic, write assignments that map an input to a plurality of memory cells of a memory cell array and read assignments that map memory cells of the array to outputs in a second sequence, writing a plurality of data elements at the input to the array based on the write assignments, and reading a plurality of data elements stored in the array to the output based on the read assignments. [Brief description of the drawings]

[0057] Specific embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0058] [Figure 1A] Here is an example of rearranging data using a butterfly transpose. [Figure 1B] Here is an example of rearranging data using a butterfly transpose. [Diagram 2] Here is an example of using rotation to rearrange data. [Diagram 3] Here is an example of using shifts to rearrange data. [Figure 4] 1 shows a memory with its main functions. [Figure 5A] 1 is an example of an embodiment of a memory architecture and memory access logic. [Figure 5B] 1 is an example of an embodiment of a memory architecture and memory access logic. [Figure 6] 1 is an example of an embodiment of a memory architecture and memory access logic. [Figure 7] 1 is an example of a state diagram of a memory architecture. [Figure 8A] 1 is an example of reading and writing data to a memory. [Figure 8B] 1 is an example of reading and writing data to a memory. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0059] In the drawings, like reference numbers indicate like parts.

[0060] Data reordering and data transposition are useful for intensive computations such as Fully Homomorphic Encryption (FHE), Fourier Transform (FT), and Convolutional Neural Network (CNN) based Artificial Intelligence (AI) operations. To serve the demands of data reordering and transposition, data must be moved multiple times and kept in expensive register memories when using existing memory architectures. Furthermore, with the advent of optical and photonic computing, which uses photons to perform mathematical operations, memory access and latency become even more critical due to the high speed operations inherent in optical and photonic computing.

[0061] The Optical Fourier Transform (OFT) can compute the FT in one clock cycle. To compute large FTs of any dimension and precision, the native OFT data must be rearranged or transposed in memory. Performing such operations in traditional (SRAM / DRAM / cache or register) memory requires numerous data shifts and multiple passes of reading and writing data. For high-performance computing applications and workflows, this creates a significant bottleneck and introduces latency, which reduces the overall performance of the computation. Transposing data with data shifts is especially common in systems where processing occurs much faster than memory access speeds, such as optical computing. In such systems, the processing speed is limited by the memory access speed.

[0062] In each of Figures 1A-3, the inputs of the example memory architecture are parallel inputs of a first width and the outputs are parallel outputs of a second width. The width of the input or output indicates the amount of bits or words. The write allocation maps the inputs to a first subset of each of the plurality of memory cells of the array in the order of the first subset, and the read allocation reads a second subset of each of the plurality of memory cells to the output in the order of the second subset. In each of Figures 1A-3, the order of the first subset is different from the order of the second subset.

[0063] OFT requires native FT data to be fragmented, reordered, or transposed before being written to memory. Native FT data may be referred to as an input, a number of data elements, a number of data elements in a first sequence, a frame, or a native FT frame. It consists of a FT of a specified size in one dimension (1D) or two dimensions (2D), determined by the native resolution of the photonic core of the photonic device in use. An example of data reordering is shown in FIG. 1A, where an input 110, 111 includes a number of data elements of a first sequence. In other words, a native FT frame 110, 111 includes a number of data points. A number of native FT frames 100, 101 (write frame 1, ..., write frame N) are sequentially reordered or transposed according to a predefined mapping. The predefined mapping is programmed by memory access logic, which generates write allocations and read allocations. The write allocation maps an input 110, 111 containing a plurality of data elements of a first sequence (or a native FT frame 110, 111 containing a plurality of data points) to a plurality of memory cells of the array 120, and the read allocation maps a plurality of memory cells of the array 120 to an output 110, 111 containing a plurality of data elements of a second sequence (or a permuted or transposed native FT frame 110, 111). In this embodiment, the first sequence is different from the second sequence, and the first sequence order of the plurality of data elements of the input is different from the second sequence order of the plurality of data elements of the output, although the first sequence and the second sequence may be the same. This mapping may be a butterfly permutation used in fast FT (FFT) computation. The memory controller writes the plurality of data elements at the input to the array 120 based on the write allocation, and reads the plurality of data elements stored in the array 120 to the output based on the read allocation.The write assignments map the inputs 100, 101 to a first subset of each of the plurality of memory cells of the array 120 in the order of the first subset, and the read assignments can read a second subset of each of the plurality of memory cells of the array 120 to the outputs 110, 111 in the order of the second subset. The order of the first subsets is different from the order of the second subsets. Each of the first subsets constitutes a first arrangement of the plurality of memory cells of the array 120, and each of the second subsets includes a second arrangement of the plurality of memory cells of the array 120. Each of the first arrangements is different from each of the second arrangements. The first width of the inputs 100, 101 and the second width of the outputs 110, 111 are the same. The first arrangements and the second arrangements have widths equal to the first width of the inputs 100, 101 and the second width of the outputs 110, 111, respectively.

[0064] The butterfly sorting logic may be programmed using a dedicated instruction set architecture (ISA) via a processor, microcontroller, coprocessor, secondary host, or other similar logic circuit. In the illustrated embodiment, each native FT frame 100, 101 is composed of nine data points representing an array, more specifically, a 2D array, and even more specifically, a 2D mathematical array. A total data set is processed that includes 9x9 data points in each frame, where the total array includes a 3x3 subset. Furthermore, each of the nine native FT frames forms a logical constellation of 3x3 frames or 3x3 subsets. That is, a total data set of 9x9 data points is processed, where each frame includes a 3x3 subset of the total array. Each data point is displayed in a different color for differentiation purposes only. According to a predefined logic, an incoming frame containing native FT data 100, 101 is fragmented or reordered such that each data point in the array 120 is offset by two positions (one horizontally and one vertically) relative to its original position in the array and frame number. This is repeated for N=9 frames, transposing the data for all 9 frames to form a 9x9 array of data points.

[0065] 1A and described above, the 9x9 array of data points, i.e., total data set 120, can be viewed as a logical arrangement of nine 3x3 memory cell subgroups, where the first, second, and third memory cell subgroups form a first row of the total data set, the fourth, fifth, and sixth memory cell subgroups form a second row of the total data set, and the seventh, eighth, and ninth memory cell subgroups form a third row of the total data set. Thus, the first, fourth, and seventh memory cell subgroups form a first column of the total data set, the second, fifth, and eighth memory cell subgroups form a second column of the total data set, and the third, sixth, and ninth memory cell subgroups form a third column of the total data set. The write allocation maps each input frame to a respective first subset (the first through ninth memory cell subgroups) of the plurality of memory cells of the array in a first subset order. Each data point in the first frame 100 (Write Frame 1) is reordered or transposed to be in the first row, first column position within each memory cell subgroup. Data is written to each position simultaneously from left to right, writing to the first row of the Total Data Set, the second row of the Total Data Set, and the third row of the Total Data Set.For example, the data point in row 1, column 1 of the first frame is transposed to row 1, column 1 of the first memory cell subgroup, the data point in row 1, column 2 of the first frame is transposed to row 1, column 1 of the second memory cell subgroup, the data point in row 1, column 3 of the first frame is transposed to row 1, column 1 of the third memory cell subgroup, the data point in row 2, column 1 of the first frame is transposed to row 1, column 1 of the fourth memory cell subgroup, and the data point in row 2, column 2 of the first frame is transposed to row 1, column 1 of the fourth memory cell subgroup. The data point in the first frame is transposed to the first row, first column of the fifth memory cell subgroup, the data point in the second row, third column of the first frame is transposed to the first row, first column of the sixth memory cell subgroup, the data point in the third row, first column of the first frame is transposed to the first row, first column of the seventh memory cell subgroup, the data point in the third row, second column of the first frame is transposed to the first row, first column of the eighth memory cell subgroup, and the data point in the third row, third column of the first frame is transposed to the first row, first column of the ninth memory cell subgroup. The first row, first column may be referred to as the first position, the first row, second column may be referred to as the second position, the first row, third column may be referred to as the third position, the second row, first column may be referred to as the fourth position, the second row, second column may be referred to as the fifth position, the second row, third column may be referred to as the sixth position, the third row, first column may be referred to as the seventh position, the third row, second column may be referred to as the eighth position, and the third row, third column may be referred to as the ninth position. Each data point in the second frame is transposed in the same manner, but to a second position in each memory cell subgroup. Each data point in the first through Nth frames is said to be transposed, in the first subset order, to the first through Nth positions in each memory cell subgroup of the total data set.

[0066] Once all data points from the native FT frames 100, 101 (Write Frame 1,..., Write Frame N) have been transposed and the total data set 120 is ready for processing, the total data set 120 is logically divided into a number of individual frames 110, 111 (Read Frame 1,..., Read Frame N), shown in FIG. 1A as alternating grey and white boxes, and are read from memory and further processed by read assignments that read a second subset of each of the plurality of memory cells 110, 111 in a second subset order to an output. As previously mentioned, in this embodiment, the total data set 120 can be viewed as nine 3x3 memory cell subgroups, such that each of the individual read frames are a first through ninth memory cell subgroup. In this case, the first through ninth memory cell subgroups correspond to the first through nth read frames, defined herein as the second subset (Read Frame 1,..., Read Frame N). If the data elements of the input 110, 101 and output 110, 111 are either single bits of a data word or multi-bit words of a data string, then both the first subset of each of the memory cells of the array 120 and the second subset of each of the memory cells of the array 120 are comprised of at least one single bit from each data word of the input or at least one multi-bit word from each data string. In this manner, the first subset order is a butterfly transpose of the data elements of the input.

[0067] The embodiment described in connection with Figure 1A may be more generally described as follows: a plurality of memory cells of an array are divided into a first memory cell subgroup and a second memory cell subgroup, and an input includes a first input frame (or write frame) and a second input frame (or write frame), the first input frame includes a first data element and a second data element, and the second input frame includes a third data element and a fourth data element, where a write assignment maps the first data element to a first memory cell in the first memory cell subgroup, maps the second data element to a first memory cell in the second memory cell subgroup, maps the third data element to a second memory cell of the first memory cell subgroup, and maps the fourth data element to a second memory cell of the second memory cell subgroup.

[0068] A conversion relationship between the positions of the first memory cells and the positions of the second memory cells in the first memory cell subgroup corresponds to or is the same as a conversion relationship between the positions of the first memory cells and the positions of the second memory cells in the second memory cell subgroup.

[0069] The transformation relationship can be a translation relationship or a rotation relationship. Optionally, the transformation relationship is a rotation or translation by a single memory cell from one memory cell to an adjacent memory cell, although the disclosure is not limited thereto and other transformations are contemplated.

[0070] The first data element order of the first input frame corresponds to the third data element order of the second input frame, and the second data element order of the first input frame corresponds to the fourth data element order of the second input frame.

[0071] The read assignment maps a number of memory cells of the array to an output that includes a first output frame (or read frame) that includes a first data element and a third data element, and a second output frame (or read frame) that includes a second data element and a fourth data element.

[0072] The order of the first data elements in the first output frame may correspond to the order of the second data elements in the second output frame, and the order of the third data elements in the first output frame may correspond to the order of the fourth data elements in the second output frame.

[0073] The first input frame and the second input frame each include data corresponding to light intensity values ​​detected at an output plane of the optical Fourier transform stage.

[0074] In some implementations, the memory is read by reading data in multiple memory cell subgroups, one subgroup at a time (optionally, but not necessarily, in the order in which the data appears in the multiple memory cell subgroups), in which case one read frame corresponds to one memory cell subgroup, while in other implementations the read frames may each sample data from a different memory cell subgroup, or may sample a subset of data from one memory cell subgroup.

[0075] It will be appreciated that these general principles (and by analogy, the embodiments described herein, including those described with reference to Figures 1A and 1B) can be applied to commit (write) a memory output frame of an OFT stage or OFT device. The type of OFT device in question is one that performs an optical Fourier transform of an optical input function. The optical output (Fourier transform) function is derived by sampling an interference pattern at the Fourier plane of the OFT stage or device. The sampling can be performed using detectors distributed in an array. The detectors can detect light collected at an array of multiple output ports arranged at the Fourier plane. A frame can be thought of as a snapshot of the complete OFT or a sample thereof. A frame of output of an OFT device corresponds to one of the input frames (e.g., the first and second mentioned above) to multiple memory cells (i.e., one of the write frames). Alternatively, multiple write frames may correspond to a single optical Fourier transform output frame (or sample different regions or areas of a single optical Fourier transform output frame).

[0076] In particular, following a more general description of the principles illustrated in FIG. 1A, the first and second input frames may be optical intensity values ​​detected at one of a plurality of ports in an array at an output face of an optical Fourier transform stage, and each of the third and fourth data elements corresponds to an optical intensity value detected at one of a plurality of ports in an array at an output face of the same or another optical Fourier transform stage.

[0077] The relative order of the first and second data elements in the first input frame and the relative order of the third and fourth data elements in the second input frame each correspond to a relative position of one of the multiple ports in the array at the output face of the respective optical Fourier transform stage, optionally where the relative order is adjacent or subsequent positions in the order and the relative positions are adjacent positions of the multiple ports in the array.

[0078] In this case, the first data element may be said to correspond to a first detected intensity at a first one of the multiple ports in the array at the output face of the optical Fourier transform stage, the third data element may correspond to a second detected intensity detected at the first port, the second data element may correspond to a third detected intensity at a second one of the multiple ports in the array, and the fourth data element may correspond to a fourth detected intensity at the second port. In other words, the first and second input frames sample different frames of the optical Fourier transform, and two different optical Fourier transform functions (or samples thereof) may be written to memory.

[0079] FIG. 1B shows an embodiment similar to FIG. 1A, and is a further example of how the generalized principle above may be implemented. In FIG. 1B, the plurality of memory cell subgroups are not defined by a 9x9 array as in FIG. 1A, but by diagonal rows of memory cells, indicated by the numbers 1-9 and arrows in FIG. 1B. Applying the above generalized description to FIG. 1B, the first memory cell subgroup is the group of memory cells indicated by the diagonal arrow labeled with the number 1. The second memory cell subgroup is the group of memory cells indicated by the diagonal arrow labeled with the number 2 (including the cell in the 9th row, 1st column), etc. Then, the first memory cell of the first memory cell subgroup is the cell in the first row, 1st column, the first memory cell of the second memory cell subgroup is the cell in the first row, 2nd column, the second memory cell of the first memory cell subgroup is the cell in the second row, 2nd column, and the second memory cell of the second memory cell subgroup is the cell in the second row, 3rd column.

[0080] In another embodiment of Figure 1B, rather than each first subset of the plurality of memory cells of array 120 and each second subset of the plurality of memory cells of array 120 both including at least one single bit from a respective data word or at least one multi-bit word from a respective data string at the input, each first subset includes a row of the plurality of memory cells of the array, and the first subset includes a multi-bit word of one of the plurality of data strings. Thus, each row of the plurality of memory cells of the array of the first subset of Figure 1B includes a plurality of multi-bit words of one of the plurality of data strings at the input, and each second subset of the plurality of memory cells of the array includes at least one multi-bit word from a respective data string of the plurality of data strings at the input.

[0081] Referring to FIG. 2, another transposition of data useful for OFT processing is shown. In this embodiment, data is rotated, more specifically, data points are shuffled similar to left / right rotation. Each of the first and second subsets includes a row or column of memory cells of the array. In this embodiment, each of the first and second subsets includes a row of memory cells of the array. As described above, the write assignment maps the input to a first subset of each of the memory cells of the array in a first subset order 200, and the read assignment reads a second subset of each of the memory cells of the array to the output in a second subset order 210. The second subset order of the memory cells of the array read to the output in FIG. 2 is a rotation of the first subset order of the memory cells of the array. In this embodiment, the array 200 is rearranged or transposed such that the data points are rotated, in this example, 180 degrees around the central data point (number 41). Thus, a first row 201 of the array or received frame 200 includes data points 1-9 from the first column through the ninth column. In the transposed array or frame 210, data points 1-9 are in a ninth row 211 (in reverse order) when looking from the ninth column through the first column. Each of the first subsets includes a first arrangement of a plurality of memory cells of the array, and each of the second subsets includes a second arrangement of a plurality of memory cells of the array. Each of the first arrangements is different from each of the second arrangements.

[0082] FIG. 3 illustrates another transposition of data ordered by a memory architecture and memory access logic. This can be programmed using dedicated read / write access logic built into the memory driver circuit. An arithmetic logic unit (ALU) may be built into the memory driver to perform computations and logical operations on the data in the memory. The computations in the memory are performed on the transposed data during read / write operations in the memory. In this embodiment, the first and second subsets each include a row or column of a plurality of memory cells of the array. The second subset order of the plurality of memory cells of the array read to the output is a predetermined or arbitrary shift of the first subset order of the plurality of memory cells of the array. Each of the plurality of first subsets includes a first arrangement of the plurality of memory cells of the array, and each of the plurality of second subsets includes a second arrangement of the plurality of memory cells of the array. Each of the first arrangements is different from each of the second arrangements. The plurality of data points of the 9×9 array 300 shown in FIG. 3 are shifted down one row and right one column to output a transposed array 310.

[0083] The memory 40 helps in the transposition of ordered data and can be considered to have five main elements as shown in FIG. 4. The memory cell 400 includes a plurality of memory cells in an array. The memory cell 400 stores data. The data allocator switch (or switching) fabric 410 allows parallel read / write data transfer between the memory cell 400 and the memory controller and driver 420. In general, the data allocator switch fabric 410 controls the traffic between two nodes / ports and is a combination of hardware and software. The data allocator switch fabric 410 includes read and write data allocators and a fabric that acts as a switch, more specifically, a switch and a multiplexing / demultiplexing network. The data allocator switch fabric 410 allows for faster read and write data transfers than other memory architectures. It allows for dynamic allocation, thus providing more flexibility in determining the network throughput. The memory controller and driver 420 (or memory controller and driver circuitry) writes data to the memory cell 400 and reads data from the memory cell 400. Memory access logic 430 processes access control instructions to regulate access to memory and controls the order in which memory requests (from memory interface 440) are processed by memory controller and driver 420. Memory interface 440 interfaces memory 40 with a read bus and a write bus, which carry instructions to program, control, and access memory 40, respectively. The write bus carries data to memory 40, and the read bus carries data from memory 40.

[0084] The details of some aspects of memory 40, such as the architecture of memory access logic 430 and memory cells 400, vary depending on the size of the data requiring transposition, i.e., whether the data is one or multiple bits. If the data being transposed and processed is single-bit data, where a single bit of multiple data words or a bit of a multi-bit word from a data string is transposed, as shown in FIG. 5A, the data transposition is performed at the bit level, so that each bit is transposed individually. If the data being transposed and processed is multi-bit data that forms a multi-bit word as part of a data string, as shown in FIG. 5B and FIG. 6, the data transposition is performed on the multi-bit word, so that each word is transposed individually, ensuring that each word is not altered. In the embodiment of FIG. 5B, the single-bit unit cells of FIG. 5A are replaced with multi-bit cells, and data allocator switch fabric 410 is a multi-dimensional switch network that allows parallel data transfer of multiple bits between each multi-bit cell and the controller circuit. In the embodiment of FIG. 6, multiple memory blocks are provided with a width equal to the width of the multi-bit word. Because multiple memory blocks are required, the data allocator switch fabric may be a wide bus that allows parallel data transfer between the memory access logic and the multiple memory blocks.

[0085] Figures 5A, 5B and 6 all show exemplary embodiments of memory architecture and memory access logic. Figure 5A shows an embodiment for storing and reading / writing a single bit, and Figures 5B and 6 show an embodiment for storing and reading / writing a multi-bit word. Figures 5A, 5B and 6 each include elements described with reference to Figure 4 and will be described in general terms covering both embodiments.

[0086] [Memory cell] Memory cell 400 includes any conventional memory cell.

[0087] [Data Allocator Switch Fabric] The data allocator switch fabric 410 acts as a bridge between the memory cells 400, the memory controller and drivers 420, and the memory access logic 430. The data allocator switch fabric 410 decodes the address (or location) of the memory cells 400 and opens channels in the data allocator switch fabric 410 to connect the memory cells 400 to the memory controller and drivers 420 through which data is transferred to and from the memory cells 400. The data allocator switch fabric 410 facilitates the movement of data transferred to and from the memory cells 400. The data allocator switch fabric 410 is an interconnect architecture between connection points or nodes. In this embodiment, the connection points are the memory cells 400, the memory controller and drivers 420, and the memory access logic 430. The channels in the data allocator switch fabric 410 ensure that the data is transferred to and from the appropriate location (such as the memory cells 400, the memory controller and drivers 420, or the memory access logic 430). The use of the data allocator switch fabric 410 and the memory access logic 430 avoids read / write collisions. The data allocator switch fabric 410 of this embodiment includes a read data allocator and a write data allocator. This is because the data allocator switch fabric 410 decodes the addresses of the cells of the memory cells 400 required for transferring data, and the memory access logic 430 controls the read / write access to the memory cells 400. The decoding scheme of the data allocator switch fabric 410 depends on the size of the data that needs to be rearranged or transposed. The decoding scheme can be described with reference to any of FIG. 5A, FIG. 5B, and FIG. 6.

[0088] [Transposing and processing single-bit data] If the data requiring rearrangement or transposition are one-bit data words, the memory cells 400 are designed such that each cell in the memory has a unique address. Each memory cell is connected to a read / write data allocator through an M-dimensional fabric, where M is the width of the data bus. The width of the data bus indicates the maximum amount of data that can be transferred on the bus, or the number of bits that make up the bus. Thus, the size of the fabric depends on the number of bits of the data bus. The fabric is mapped to the bus size according to the bit number of the individual data bits. The bit number identifies the bit position in a binary number from the most significant bit (MSB) to the least significant bit (LSB).

[0089] The memory access logic 430 includes a read / write address FIFO (ADDR FIFO) that stores a sequence of memory addresses (or multiple memory addresses) generated by the read / write address logic (ADDR logic). As described above, the data allocator switch fabric 410 and the memory access logic 430 interact when data is transferred to or from the memory cells 400, where access to the memory cells 400 is granted or data is transferred to or from the memory cells 400 if the address of the cell is present in the address sequence fetched from the FIFO.

[0090] All M bits of the word transferred to memory cell 400 are read and written in parallel. Addresses from the read / write FIFO are fetched for all M bits. The address of each bit in the M-bit word is sent to the corresponding layer in the fabric according to the bit number of the individual data bit. The fabric opens a link between the memory cell and the memory controller, enabling the data transfer.

[0091] [Rearrangement or transposition, processing of multi-bit data] In an embodiment where data transposition occurs on words of multi-bit data (i.e., the bits forming the word are not changed), the multi-bit data forms words of width W bits, and a memory block of width W can be used for multiple words forming a data string of K words. Each memory block is connected to a read data allocator and a write data allocator (or data allocator switch) via a K×A address fabric (A is the address of row X in the memory block that stores one word in the string) and a K×W data fabric. The address and data fabric is high bandwidth. The fabric is mapped according to the bit number of individual words. The bit number identifies the position of the word in the binary string of multi-words from the most significant word (MSW) to the least significant word (LSW). The memory access logic 430 includes a read / write address FIFO (ADDR FIFO) that stores the sequence of memory addresses (or addresses) generated by the read / write address logic (ADDR LOGIC). As described above, the data allocator switch fabric 410 and the memory access logic 430 interact when data is transferred to or from memory cells. Now, if the row or block address is present in the address FIFO, access is granted to the memory cells 400 storing the word, or data is transferred to or from the memory cells.

[0092] All K×W bits transferred to or from memory cells 400 are read and written in parallel. Addresses from the read / write FIFO are fetched for all K words. The address of each word is sent to the corresponding layer in the address fabric according to the bit number of the individual data word. The fabric opens a link between the selected row of memory blocks and the memory controller, enabling the data transfer.

[0093] [Memory controllers and drivers] The memory controller and driver 420 includes a controller and input / output (IO) buffer, a read and write address decoder, a sense amplifier, and a write driver. The address decoder is a binary decoder with two or more inputs for address bits and one or more outputs for a select signal. The inputs of the read and write address decoder are the controller and IO buffer containing the address bits, and the output of the read and write address decoder is a memory cell select signal sent to the data allocator switch fabric 410 for selection of the memory cell 410. The sense amplifier inputs data to the controller and IO buffer. Typically, the sense amplifier receives the stored data signal from the memory cell and appropriately amplifies it so that the amplified value conforms to recognizable logic levels and the read data is correctly interpreted by the rest of the digital circuitry external to the memory. The write driver sends data to the memory cell through the write allocator switch fabric if single-bit data reordering or transposition is required, or directly to the row-selected memory cell if multi-bit data reordering or transposition is required. If single-bit data transposition is required, an in-memory ALU is incorporated into the memory controller and driver circuit. When multi-bit data transposition is required, an ALU is incorporated into the memory access logic to allow arithmetic and logic operations on multi-bit words fetched from one or more memory blocks.

[0094] [Memory access logic] As previously described, read and write accesses to memory cells 400 are controlled by memory access logic 430. The memory access logic is configured to be reprogrammed to generate different write and read assignments to eliminate conflicts and improve latency. The read and write access logic eliminates conflicts and improves latency. Both the read and write logic are comprised of similar logic and circuitry consisting of read / write logic and a read / write state machine controller, read / write address logic, read / write address FIFO, read / write counters, and in-memory ALUs.

[0095] The read / write logic is used to program and control the sequence and order in which the memory cells are accessed for reading / writing data. During programming, the read / write logic may read the memory cell's initialization address (INIT ADDR) or start address (START ADDR) to calculate the requested cell's address and instruct the read / write address logic to generate the address sequence in which the memory cell access occurs. The read / write state machine controller in the read / write logic is used to set / reset / read / write both the data counter and sequence counter in the memory access logic according to the read / write counter and status provided by the read / write data bus. A state machine is a behavioral model that configures the states that a system can take to model the behavior of the system. The various states of the system can be represented using a state machine. The sequence counter exists because the memory architecture relies on both the current input and the history of inputs to generate the address sequence. The state machine sends a read signal to the read / write FIFO and sends the memory cell's read / write address to the memory controller and driver.

[0096] The read / write address logic generates a sequence of addresses to which the memory is read / written.

[0097] When multiple single bits of a data word are permuted and transposed, each address sequence consists of memory addresses of multiple memory cells, each memory cell corresponding to a bit of the data word. The addresses can be arranged according to the bit number of the individual data bits. When multi-bit words are permuted and transposed, each address sequence consists of memory addresses of multiple memory cells (Figure 5B) or an identifier of a memory block and a row address where the data is stored within the memory block (Figure 6). The addresses are arranged according to the word number of the individual data words.

[0098] The read / write address FIFO stores memory addresses (READ ADDR, WRITE ADDR) generated by the read / write address logic. The memory addresses are read when triggered by the read / write logic and sent to the memory controller driver by the read / write state machine controller. Only the read / write address logic can write to the FIFO. If the state machine is programmed to repeat the same transposition for multiple batches of data, the FIFO read values ​​are written back to the FIFO. That is, the read values ​​are pushed to the back of the FIFO queue. In this way, the memory access logic does not need to generate the same address for every data set. By reusing the addresses in the FIFO, the access logic is faster.

[0099] The read / write counters are used to synchronize the read / write address FIFO read values ​​with requests made via the read / write bus. The data / values ​​in the counters are set / reset depending on the access workflow programmed into the read / write logic and the read / write state machine controller.

[0100] In cases where multi-bit data transposition is required, an in-memory ALU is incorporated into memory controller and driver 420.

[0101] [Memory interface] The memory interface 440 to the memory 40 is a write data bus, a read data bus, a write control bus, and a read control bus. The write data bus and the read data bus carry information to and from the memory 40. The write control bus and the read control bus carry additional information such as instructions for the in-memory computation ALU logic, instructions for programming the access control logic (or read / write logic) and state machines in the read / write state machine controller, status controls (such as handshake signals and access modes such as page and burst) for configuring the memory access logic, and read / write counters for synchronizing with the read / write state machine. Status controls include, but are not limited to, handshake signals and access modes such as page and burst. Page and burst modes improve performance by supporting high speed data transfers.

[0102] [Specific embodiment] In each of the embodiments shown in Figures 5A, 5B, and 6, black arrows indicate data flow, grey arrows indicate address flow, and dashed arrows indicate instruction flow.

[0103] Figures 5A and 5B are similar in configuration, but memory cell 501 in Figure 5A is configured to store one bit of data, and memory cell 502 in Figure 5B is configured to store multiple bits of data. In other words, Figure 5A shows an embodiment where the data is a one-bit word, and Figure 5B shows an embodiment where the data is a multi-bit word that may be part of a string.

[0104] In the embodiment of Figures 5A and 5B, data to and from memory cells 501, 502 is configured to flow through data allocator switch fabric 410, specifically, data is configured to flow from memory cells 501, 502 to read data allocator 511 and from write data allocator 512 to memory cells 501, 502. This is to connect memory cells 501, 502 to memory controller and driver circuitry. Memory controller and driver 420 may include at least one of controller and IO buffer 525, read address decoder 521, write address decoder 522, sense amplifier 523, and write driver 524. Data is configured to flow from read data allocator 511 to controller and IO buffer 525 and to in-memory ALU 539 of memory access logic 430, preferably via sense amplifier 523. Data is then configured to flow from the controller and IO buffer 525 and in-memory ALU 539, preferably via write driver 524, to the write data allocator 512. As described above, data is configured to flow back from the write data allocator 512 to the memory cells 501, 502. Within that data flow, addresses are configured to flow from the controller and IO buffer 525 to the read and write address decoders 521, 522 and to the read and write data allocators 511, 512. Addresses are also configured to flow between the memory cells 501, 502 and the read and write address decoders 521, 522. The read and write data allocators 511, 512 may include row and column decoders. The read and write address decoders 521, 522 may include row and column decoders.

[0105] In this data flow, data is configured to flow into and out of the memory circuit interface via a read data bus 541 and a write data bus 542. The data buses allow for bit-wise data flow. The interface may also include a read controller 543 and a write controller 544 that transmit at least one of instructions for the in-memory ALU 539, instructions for programming the read address logic 531, the write address logic 532, the read logic state machine controller 533, and the write logic state machine controller 534 via the data flow. The read and write address logic 531, 532 are configured to send read and write addresses to the controller and IO buffer 525 via the read and write address FIFOs 535, 536. The controller IO buffer 525 may be configured to send address information back to the memory access logic, more specifically, the read and write logic state machine controllers 533, 534. The interface, and more specifically the read and write control buses 553, 554, may carry status control information to the read and write logic state machine controllers 533, 534. Read and write counters in the read and write control buses 553, 554 and read and write counters 537, 538 in the memory access logic aid in synchronization.

[0106] In the embodiment shown in Figure 6, instead of memory cells 501, 502 described with reference to Figures 5A and 5B, the memory comprises memory cells 602 in memory block 654, which are arranged to store multi-bit data in a slightly different manner than memory cells 502 of Figure 5B. Like the data in the embodiment shown in Figure 5B, the data in Figure 6 may be a multi-bit word which may be part of a string.

[0107] In FIG. 6, data to and from each memory cell 602 is configured to flow to a column decoder in a read decoder 621. Each memory cell 602 is connected to a memory controller and driver 420. Each memory controller and driver 420 may include at least one of a controller and IO buffer 625, a read decoder 621, a write decoder 622, a sense amplifier 623, and a write driver 624. Data is configured to flow from each controller and IO buffer 625 through fabric 613 to a read data allocator 611, and from a write data allocator 612 through fabric 613 to each controller and IO buffer 625. This connects each memory cell 602 to the read and write data allocators 611, 612, memory access logic 430, and memory interface 440. Fabric 613 is an address and data fabric and may transfer both addresses and data to and from each memory cell 602. Fabric 613 is preferably configured to have a high bandwidth. Data flows from the controller and IO buffer 625 through the column decoder in the write driver 624 and write decoder 622 to the memory cells 602. Data flows from the memory cells 602 through the column decoder and sense amplifier 623 in the read decoder 621 to the controller and IO buffer 625. Data is then configured to flow from each controller and IO buffer 625 to the ALU 639 and write data allocator 612. Within that data flow, addresses are configured to flow from the read and write data allocators 611, 612 through the fabric 613 to the controller and IO buffer 625 and from the controller and IO buffer 625 through the fabric 613 to the read and write decoders 621, 622.Addresses may flow from the read and write data allocators 611, 612 through the fabric 613 to row decoders of the read and write decoders 621, 622, thereby bypassing the flow between the read and write data allocators 611, 612 and the controller and IO buffer 625 through the fabric 613. Addresses are configured to flow between each memory cell 602 in the respective block and the respective read and write address decoders 621, 622, respectively. The read and write data allocators 611, 612 may include decoders, more specifically, block decoders and address decoders. The read decoder 621 and the write decoder 622 may include row decoders and column decoders.

[0108] In this data flow, data is configured to flow into and out of the memory interface 440 of the memory via a read data bus 641 and a write data bus 642. The data buses allow for bit-wise data flow. The memory interface 440 includes a read control bus 643 and a write control bus 644 that carry at least one of the instructions of the ALU 639, the read address logic 631, the write address logic 632, the read logic 633, the write address logic 634, the write address logic 635, the write address logic 636, the write address logic 637, the write address logic 638, and the write address logic 639. The state machine controller 633 and the write logic state machine controller 634 communicate via the data flow. The read and write address logic 631, 632 are configured to send read and write addresses to the controller and IO buffer 621 via the read and write address FIFOs 635, 636. The read and write address logic 631, 632 may send read and write addresses directly to row decoders in the read and write decoders 621, 622 via read and write address FIFOs 635, 636. The controller IO buffer 625 may be configured to send address information from the fabric 613 back to the memory access logic 430, more specifically, the read and write logic state machine controllers 633, 634. The memory interface 440, more specifically, the read and write control buses 643, 644 may carry status control information to the read and write logic state machine controllers 633, 634. The read and write counters of the read and write control buses 643, 644 and the read and write counters 637, 638 of the memory access logic aid in synchronization.

[0109] A method of any embodiment of the application, including the memory architectures of Figures 5A, 5B, and 6, can be described using the state diagram of Figure 7. Specifically, Figure 7 describes a method that includes generating, in memory access logic, write assignments that map inputs to a plurality of memory cells of a memory cell array in a first sequence, and read assignments that map a plurality of memory cells of the array to outputs in a second sequence, writing a plurality of data elements at the input to the array based on the write assignments, and reading a plurality of data elements stored in the array to the output based on the read assignments. The state diagram illustrates the various states of a system through transitions in the diagram and is used to illustrate the functionality of a status machine.

[0110] The first step of the method is to initialize the system. Initializing the system (701) involves resetting the system's counters (702). The memory interface 440, and more specifically the read and write control buses, includes instructing the read and write logic (703). The read and write logic is programmed to generate read and write addresses (704) and stores the read and write addresses in the read and write FIFOs (705), so that data is stored and retrieved, preferably in parallel. The status of the system changes to ready (706). Each time data is input or output to a memory cell, an address is written and read according to the read address FIFO or write address FIFO. The address is written back to the read address FIFO and write address FIFO for use the next time data is input or output to the memory cell. This allows for "recycling" of addresses. For example, an address may be used to write data to multiple memory cells of the array during one clock cycle, and the same address may be used to write data to multiple memory cells of the array during another clock cycle, until the read and write address FIFOs are instructed not to write data back to the read and write address FIFOs. Once the system status is ready, the read and write logic state machine controllers can respond to requests and instructions from the read and write control buses.

[0111] When a write command is transmitted over the write control bus, data is read from the write data bus (707) and flows to the ALU. If directed by a write command from the write control bus, the ALU processes the data (712) and sends the data to the write data allocator via the write driver (713). The location of the write address is provided by the write address FIFO (714) and the write counter is updated by the write logic state machine controller (715). The write address location is sent to the controller via the write address decoder (709) and then to the write data allocator (710). Once both the data and address from the ALU are sent to the write data allocator, the data is written to multiple memory cells by the write data allocator (711). The write logic state machine controller sends an acknowledgement, more specifically, a write success status, to the write control bus (716).

[0112] When a read command is transmitted over the read control bus (717), a read address location is provided by the read address FIFO (718) and a read counter is updated by the read logic state machine controller (719). The read address location is sent to the controller via the read address decoder (720) and then to the read data allocator switch (721). Data is read from the plurality of memory cells by the read data allocator (722) and sent to the ALU. The ALU processes the data if instructed (712) and either sends the processed data to the read data bus to be written to the read data bus (723) or sends the data via the write logic state machine controller to the write data allocator to be written back to the plurality of memory cells. The read logic state machine controller then sends an acknowledgement, more specifically, a read success status, to the read control bus (724).

[0113] The embodiments of Figures 8A and 8B illustrate the use of an allocator switch fabric, or allocator switch, or switch fabric, or fabric. Allocator switch fabric 800 of Figure 8A is configured for single-bit operations, and allocator switch fabric 810 of Figure 8B is configured for multi-bit operations. In other words, allocator switch fabric 800 of Figure 8A allows for the transmission of single-bit data, and allocator switch fabric 810 of Figure 8B allows for the transmission of multi-bit data.

[0114] In each embodiment, the read and write data allocators read or write data according to the location of the data's bits in the row and column addresses from the read and write address FIFOs. In Figures 8A and 8B, each bit or multi-bit word is colored according to the importance of the bit. For example, blue is the most significant bit (MSB) or word (MSW) and red is the least significant bit (LSB) or word (LSW).

[0115] In FIG. 8A, the allocator switch fabric 800 has a width of M×B, where M is the number of bits in a single data set and B is the bit length. Since FIG. 8A deals with a single bit, B=1 and the bit length is always 1. In this example, the number of bits is 3, i.e., M=3. The allocator switch fabric reads or writes data to the multiple memory cells 801 of the array according to the position of the bit in the data set. This causes the most significant bit (MSB), the least significant bit (LSB), and all other bits in the data set to be read from or written to different memory cells. Since the multiple memory cells 801 of the array are provided in units of the bit size, each bit is written to or read from a different memory cell. The write allocations generated by the memory access logic 430 map the input to a first subset of each of the multiple memory cells 801 of the array in a first subset order, and the read allocations read a second subset of the multiple memory cells to the output in a second subset order. The inputs and outputs in this embodiment are single-bit data, or single-bit words. The read allocator includes a row address (ROW ADDR), a column address (COL ADDR), and data (READ DATA, DATA). The MSB is read from the coordinate (7,0) of the first memory cell 804 in the plurality of memory cells 801 of the array, the adjacent bit is read from the coordinate (0,0) of the second memory cell 803 in the plurality of memory cells 801 of the array, and the LSB is read from the coordinate (7,7) of the third memory cell 802 in the plurality of memory cells 801 of the array. The write allocator includes a row address (ROW ADDR), a column address (COL ADDR), and data (WRITE DATA, DATA). The MSB is written to coordinate (3,3) of the fourth memory cell 807 in the plurality of memory cells 801 of the array, the adjacent bit is read from coordinate (0,6) of the fifth memory cell 806 in the plurality of memory cells 801 of the array, and the LSB is read from coordinate (6,6) of the sixth memory cell 805 in the plurality of memory cells 801 of the array.

[0116] Referring to FIG. 8B, the width of the allocator switch fabric 810 is M×B, where M is the number of words in a single data set and B is the bit length of each word. In this example, the number of words is 3, i.e., M=3. The bit length of each word is 3, i.e., B=3. The allocator switch fabric reads or writes data to multiple memory cells 811 of the array depending on the position of the word in the string, so that the most significant word (MSW), least significant word (LSW), and all other words in the string are read from or written to different memory cells. The multiple memory cells 811 are provided in units of the word size, so that each word can be written to or read from different memory cells (or different subsets of memory cells) without transposition. As described above, the write allocations generated by the memory access logic 430 map inputs to a first subset of each of the plurality of memory cells 811 of the array in a first subset order, and the read allocations read a second subset of each of the plurality of memory cells to outputs in a second subset order. Each memory cell in each first subset is adjacent, and the inputs are mapped to each adjacent memory cell in each first subset, and each memory cell in each second subset is adjacent, and the outputs are read from adjacent memory cells in the second subset of the array. The read allocator includes a row address (ROW ADDR), a column address (COL ADDR), and data (READ DATA, DATA). The MSW is read from a first memory cell 814 of a first subset of the plurality of second subsets 821, an adjacent word (e.g., adjacent words in a data stream) is read from a second memory cell 813 of a second subset of the plurality of second subsets 822, and the LSW is read from a third memory cell 812 of a third subset of the plurality of second subsets 823. The write allocator includes a row address (ROW ADDR), a column address (COL ADDR), and data (WRITE DATA, DATA).The MSW is written to a fourth memory cell 817 of a first subset of the plurality of first subsets, the adjacent word is read from a fifth memory cell 816 of a second subset of the plurality of first subsets, and the LSW is read from a sixth memory cell 815 of a third subset of the plurality of first subsets. The address of the column decoder of the read allocator may include an address of the MSB or LSB and a width of the multi-bit data, which allows relative addressing so that adjacent memory cells storing word data can be accessed from a single address.

[0117] The first, second and third subsets of the plurality of first subsets of the plurality of memory cells 811 of the array are in a first subset order, with the first subset order having coordinates (7,0), (0,0), and (7,7). The first, second and third subsets of the plurality of first subsets include a first arrangement of the plurality of memory cells 811 of the array having coordinates (7,0), (0,0), and (7,7), respectively. The first, second and third subsets of the plurality of second subsets of the plurality of memory cells 811 of the array are in a second subset order, with the second subset order having coordinates (3,3), (0,6), and (6,6). The first, second and third subsets of the plurality of second subsets include second arrangements of the plurality of memory cells 811 of the array having coordinates (3,3), (0,6) and (6,6), respectively. Each of the first arrangements is different from each of the second arrangements.

[0118] Each embodiment described herein is provided by way of illustration and is not intended to limit the present disclosure. As will be appreciated by those skilled in the art, various modifications may be made to the embodiments. The present disclosure is defined by the appended claims.

[0119] The following numbered embodiments are also described herein: EMBODIMENT 1 an array of memory cells; memory access logic programmable to generate write assignments that map an input comprising a first sequence of data elements to a plurality of memory cells of the array, and read assignments that map a plurality of memory cells of the array to an output comprising a second sequence of data elements; a memory controller configured to write a plurality of data elements at the input to the array based on the write assignment and to read a plurality of data elements stored in the array to the output based on the read assignment. Memory. EMBODIMENT 2 the first sequence is different from the second sequence, and a first sequence order of the plurality of data elements at the input is different from a second sequence order of the plurality of data elements at the output; 2. A memory as described in embodiment 1. EMBODIMENT 3 the input is a parallel input of a first width and the output is a parallel output of a second width; Preferably, the first width and the second width are the same. A memory according to embodiment 1 or embodiment 2. EMBODIMENT 4 the memory access logic is configured to be reprogrammed to generate different write and read allocations. A memory according to any one of the first to third embodiments. EMBODIMENT 5 The data elements at the input and output are either single bits of a data word or multi-bit words of a data string. A memory according to any one of embodiments 1 and 4. EMBODIMENT 6 the most significant bit to the least significant bit of each single bit, or the most significant word to the least significant word of each multi-bit word, are mapped to the input or read to the output in parallel; A memory as described in embodiment 5. EMBODIMENT 7 the write assignment maps the inputs to a first subset of each of the plurality of memory cells of the array in a first subset order, and the read assignment reads a second subset of each of the plurality of memory cells to the outputs in a second subset order. A memory according to any one of the first to sixth embodiments. EMBODIMENT 8 the respective first subsets including respective first arrangements of the plurality of memory cells of the array, and the respective second subsets including respective second arrangements of the plurality of memory cells of the array. A memory as described in embodiment 7. EMBODIMENT 9 each said first configuration is different from each said second configuration; A memory as described in embodiment 8. EMBODIMENT 10 each said first arrangement having a width equal to a first width of said input and a second width of said output; A memory according to embodiment 8 or embodiment 9. EMBODIMENT 11 said respective first arrangements and said respective second arrangements having a width equal to said input first width and said output second width; A memory according to embodiment 8 or embodiment 9. EMBODIMENT 12 the first subset order is different from the second subset order; A memory according to any one of embodiments 7 to 11. EMBODIMENT 13 each said first subset constituting a row or column of a plurality of memory cells of said array; A memory according to any one of embodiments 7 to 12. EMBODIMENT 14 each said second subset constituting a row or column of memory cells of said array; A memory according to any one of embodiments 7 to 13. EMBODIMENT 15 a first subset of each of the plurality of memory cells of the array are contiguous, the input is mapped to the first subset of each of the adjacent plurality of memory cells of the array, a second subset of each of the plurality of memory cells of the array are contiguous, and the output is read from the second subset of each of the adjacent plurality of memory cells of the array; A memory according to any one of embodiments 7 to 14. EMBODIMENT 16 16. A memory as claimed in any one of claims 7 to 15, wherein each single bit or each multi-bit word is mapped to a respective first subset of adjacent memory cells of the array, and each single bit or each multi-bit word is read to the output from a respective second subset of adjacent memory cells of the array, A memory as described in embodiment 5. EMBODIMENT 17 the second subset order of the plurality of memory cells of the array read at the output is a predetermined shift of the first subset order of the plurality of memory cells of the array. A memory according to any one of embodiments 7 to 14. EMBODIMENT 18 the second subset order of the plurality of memory cells of the array read at the output is a rotation of the first subset order of the plurality of memory cells of the array. A memory according to any one of embodiments 7 to 14. EMBODIMENT 19 the first subset order being a butterfly transpose of the data elements in the input; A memory according to any one of embodiments 7 to 12. EMBODIMENT 20 a first subset of each of the plurality of memory cells of the array and a second subset of each of the plurality of memory cells of the array both including at least one single bit from a respective data word or at least one multi-bit word from a respective data string at the input; A memory according to any one of embodiments 7 to 19. EMBODIMENT 21 20. The memory of claim 15 or 19, wherein each row or column of the plurality of memory cells of the array of the first subset includes a plurality of multi-bit words of one data string of the plurality of data strings at the input, and each second subset of the plurality of memory cells of the array includes at least one multi-bit word from each data string of the plurality of data strings at the input, A memory as described in embodiment 13. EMBODIMENT 22 the memory access logic includes read logic and write logic, the read logic generating the read allocation and the write logic generating the write allocation; A memory according to any one of embodiments 1 to 21. EMBODIMENT 23 the memory access logic includes a read state controller and a write state controller; A memory according to any one of embodiments 1 to 22. EMBODIMENT 24 a memory interface configured to transfer a plurality of data elements of the input to a plurality of memory cells of the array and to transfer a plurality of data elements stored in the plurality of memory cells of the array to the output. A memory according to any one of embodiments 1 to 23. EMBODIMENT 25 the memory interface includes a read data bus and a write data bus, the read data bus and the write data bus configured to transfer instructions to the memory access logic for programming the memory access logic; 25. A memory as described in embodiment 24. EMBODIMENT 26 the read data bus and the write data bus are configured to provide read counters, write counters and status control to the memory access logic; A memory according to embodiment 24 or embodiment 25. EMBODIMENT 27 27. The memory of embodiment 26, wherein the read state controller and the write state controller are configured to use the read counter, the write counter, and the status control to set, reset, read, or write both a data counter and a sequence counter in the memory access logic; A memory as described in embodiment 23. EMBODIMENT 28 a data allocator switch fabric configured to connect the plurality of memory cells to the memory access logic and to the memory controller. A memory according to any one of embodiments 1 to 27. EMBODIMENT 29 the data allocator switch fabric includes a switch fabric, a read data allocator, and a write data allocator, the read data allocator and the write data allocator configured to decode an address of the array corresponding to the read allocation or the write allocation; A memory as described in embodiment 28. EMBODIMENT 30 The switch fabric is mapped to the size of the bus according to the bit number of each data. A memory according to embodiment 28 or embodiment 29. EMBODIMENT 31 The plurality of memory cells of the array are divided into a first memory cell subgroup and a second memory cell subgroup; the input includes a first input frame and a second input frame; the first input frame includes a first data element and a second data element; the second input frame includes a third data element and a fourth data element; the write allocation maps the first data element to a first memory cell in the first memory cell subgroup, maps the second data element to a first memory cell in the second memory cell subgroup, maps the third data element to a second memory cell in the first memory cell subgroup, and maps the fourth data element to a second memory cell in the second memory cell subgroup. A memory according to any one of embodiments 1 to 31. EMBODIMENT 32 a conversion relationship between the locations of the first and second memory cells in the first memory cell subgroup corresponds to or is the same as a conversion relationship between the locations of the first and second memory cells in the second memory cell subgroup; A memory as described in embodiment 31. EMBODIMENT 33 the transformation relationship is a translation relationship or a rotation relationship, and optionally, the transformation relationship is a rotation or a translation by a single memory cell from one memory cell to an adjacent memory cell; A memory as described in embodiment 32. EMBODIMENT 34 an order of first data elements in the first input frame corresponds to an order of third data elements in the second input frame, and an order of second data elements in the first input frame corresponds to an order of fourth data elements in the second input frame. A memory according to any one of embodiments 31 to 33. EMBODIMENT 35 the read allocation includes mapping a plurality of memory cells of the array to an output including a first output frame including the first data element and the third data element, and a second output frame including the second data element and the fourth data element. A memory according to any one of embodiments 31 to 34. EMBODIMENT 36 an order of first data elements in the first output frame matches an order of second data elements in the second output frame; A memory as described in embodiment 35. EMBODIMENT 37 an order of third data elements in the first output frame matches an order of fourth data elements in the second output frame; A memory according to embodiment 35 or embodiment 36. EMBODIMENT 38 each of the first input frame and the second input frame includes data corresponding to light intensity values ​​detected at an output plane of an optical Fourier transform stage; A memory according to any one of embodiments 31 to 37. EMBODIMENT 39 each of the first data element and the second data element corresponds to a light intensity value detected at one of a plurality of ports in an array at an output face of an optical Fourier transform stage, and each of the third data element and the fourth data element corresponds to a light intensity value detected at one of a plurality of ports in an array at an output face of the same or another optical Fourier transform stage; A memory according to any one of embodiments 31 to 38. EMBODIMENT 40 a relative order of the first and second data elements in the first input frame and a relative order of the third and fourth data elements in the second input frame correspond to a relative position of a port of a plurality of ports in an array at an output face of a respective optical Fourier transform stage, optionally the relative order being adjacent or successive positions in order, the relative positions being adjacent positions of a plurality of ports in the array; A memory as described in embodiment 39. EMBODIMENT 41 the first data element corresponds to a first detected intensity at a first one of a plurality of ports in an array at an output face of an optical Fourier transform stage, the third data element corresponds to a second detected intensity at the first port, and optionally the second data element corresponds to a third detected intensity at a second one of a plurality of ports in the array, and the fourth data element corresponds to a fourth detected intensity at the second port. A memory according to any one of embodiments 31 to 40. EMBODIMENT 42 generating, in the memory access logic, write assignments that map inputs to a plurality of memory cells of a memory cell array in a first sequence and read assignments that map memory cells of the array to outputs in a second sequence; writing a plurality of data elements at the input to the array based on the write assignments; reading a plurality of data elements stored in the array to the output based on the read assignments; method.

Claims

1. An array of multiple memory cells, A memory access logic programmable to generate write assignments that map inputs containing multiple data elements of a first sequence to multiple memory cells of the array, and read assignments that map multiple memory cells of the array to outputs containing multiple data elements of a second sequence. A memory controller configured to write a plurality of data elements in the input to the array based on the write assignment and to read a plurality of data elements stored in the array to the output based on the read assignment, is provided. Memory.

2. The first sequence differs from the second sequence, and the first sequence order of the multiple data elements in the input differs from the second sequence order of the multiple data elements in the output. The memory according to claim 1.

3. The input is a parallel input of a first width, and the output is a parallel output of a second width. Preferably, the first width and the second width are the same. The memory according to claim 1 or claim 2.

4. The memory access logic is configured to be reprogrammed to generate different write and read assignments. The memory according to claim 1.

5. The multiple data elements in the input and output are either multiple single bits of a data word or multiple multi-bit words of a data string. The memory according to claim 1.

6. The most significant bit to the least significant bit of each single bit, or the most significant word to the least significant word of each multi-bit word, are mapped to the input or read in parallel to the output. The memory according to claim 5.

7. The write assignment maps the input to a first subset of each of the plurality of memory cells in the array in a first subset order, and the read assignment reads a second subset of each of the plurality of memory cells to the output in a second subset order. The memory according to claim 1.

8. Each of the first subsets includes a first arrangement of each of the plurality of memory cells in the array, and each of the second subsets includes a second arrangement of each of the plurality of memory cells in the array. The memory according to claim 7.

9. Each of the aforementioned first arrangements differs from each of the aforementioned second arrangements. The memory according to claim 8.

10. Each of the first arrangements has a width equal to the first width of the input and the second width of the output. The memory according to claim 8.

11. Each of the first arrangements and each of the second arrangements has a width equal to the first width of the input and the second width of the output. The memory according to claim 8.

12. The first subset order is different from the second subset order. The memory according to claim 7.

13. Each of the first subsets described above constitutes a row or column of multiple memory cells in the array, The memory according to claim 7.

14. Each of the aforementioned second subsets constitutes a row or column of multiple memory cells in the array. The memory according to claim 7.

15. Each first subset of the array's multiple memory cells is adjacent, the input is mapped to each first subset of the adjacent memory cells in the array, each second subset of the array's multiple memory cells is adjacent, and the output is read from each second subset of the adjacent memory cells in the array. The memory according to claim 7.

16. The plurality of data elements in the input and the output are either a plurality of single bits of a data word or a plurality of multi-bit words of a data string, The memory according to claim 7, wherein each single bit or each multi-bit word is mapped to a first subset of adjacent memory cells in the array, and each single bit or each multi-bit word is read to the output from a second subset of adjacent memory cells in the array.

17. The second subset order of the plurality of memory cells of the array read in the output is a predetermined shift of the first subset order of the plurality of memory cells of the array. The memory according to claim 7.

18. The second subset order of the array's multiple memory cells read in the output is a rotation of the first subset order of the array's multiple memory cells. The memory according to claim 7.

19. The first subset order is the butterfly transpose of the multiple data elements in the input. The memory according to claim 7.

20. Each first subset of the plurality of memory cells in the array and each second subset of the plurality of memory cells in the array both include at least one single bit from each data word in the input or at least one multi-bit word from each data string. The memory according to claim 7.

21. The memory according to claim 15, wherein each row or column of the plurality of memory cells in the array of the first subset includes a plurality of multibit words of one data string from a plurality of data strings in the input, and each second subset of the plurality of memory cells in the array includes at least one multibit word from each of the plurality of data strings in the input.

22. The memory access logic includes read logic and write logic, wherein the read logic generates the read allocation, and the write logic generates the write allocation. The memory according to claim 1.

23. The memory access logic includes a read state controller and a write state controller. The memory according to claim 1.

24. The memory interface further includes a memory interface configured to transfer a plurality of data elements of the input to a plurality of memory cells of the array, and to transfer a plurality of data elements stored in the plurality of memory cells of the array to the output. The memory according to claim 1.

25. The memory interface includes a read data bus and a write data bus, and the read data bus and the write data bus are configured to transfer instructions for programming the memory access logic to the memory access logic. The memory according to claim 24.

26. The read data bus and the write data bus are configured to supply a read counter, a write counter, and status control to the memory access logic. The memory according to claim 24.

27. ​​The memory access logic includes a read state controller and a write state controller, The memory according to claim 26, wherein the read state controller and the write state controller are configured to set, reset, read, or write both data counters and sequence counters in the memory access logic using the read counter, the write counter, and the status control.

28. The system further includes a data allocator switch fabric configured to connect the plurality of memory cells to the memory access logic and the memory controller. The memory according to claim 1.

29. The data allocator switch fabric includes a switch fabric, a read data allocator, and a write data allocator, wherein the read data allocator and the write data allocator are configured to decode the address of the array corresponding to the read assignment or the write assignment. The memory according to claim 28.

30. The aforementioned switch fabric is mapped to the bus size according to the bit number of each data. The memory according to claim 29.

31. The plurality of memory cells in the array are divided into a first memory cell subgroup and a second memory cell subgroup. The input includes a first input frame and a second input frame, The first input frame includes a first data element and a second data element, The second input frame includes a third data element and a fourth data element, The write assignment involves mapping the first data element to the first memory cell in the first memory cell subgroup, the second data element to the first memory cell in the second memory cell subgroup, the third data element to the second memory cell in the first memory cell subgroup, and the fourth data element to the second memory cell in the second memory cell subgroup. The memory according to claim 1.

32. The conversion relationship between the positions of the first memory cell and the second memory cell within the first memory cell subgroup corresponds to or is identical to the conversion relationship between the positions of the first memory cell and the second memory cell within the second memory cell subgroup. The memory according to claim 31.

33. The aforementioned conversion relationship is a translational or rotational relationship, and optionally, the conversion relationship is a rotation or translation by a single memory cell from one memory cell to an adjacent memory cell. The memory according to claim 32.

34. The order of the first data elements in the first input frame corresponds to the order of the third data elements in the second input frame, and the order of the second data elements in the first input frame corresponds to the order of the fourth data elements in the second input frame. The memory according to claim 31.

35. The read assignment includes mapping a plurality of memory cells of the array to an output that includes a first output frame containing the first data element and the third data element, and a second output frame containing the second data element and the fourth data element. The memory according to claim 31.

36. The order of the first data elements in the first output frame matches the order of the second data elements in the second output frame. The memory according to claim 35.

37. The order of the third data elements in the first output frame matches the order of the fourth data elements in the second output frame. The memory according to claim 35.

38. Each of the first and second input frames includes data corresponding to the light intensity values ​​detected on the output surface of the optical Fourier transform stage. The memory according to claim 31.

39. Each of the first and second data elements corresponds to a light intensity value detected at one of multiple ports in an array on the output surface of the optical Fourier transform stage, and each of the third and fourth data elements corresponds to a light intensity value detected at one of multiple ports in an array on the output surface of the same or a different optical Fourier transform stage. The memory according to claim 31.

40. The relative order of the first and second data elements in the first input frame, and the relative order of the third and fourth data elements in the second input frame, correspond to the relative positions of one of the multiple ports in the array on the output surface of each optical Fourier transform stage, and optionally, the relative order is an adjacent or subsequent position in the order, and the relative position is an adjacent position of the multiple ports in the array. The memory according to claim 39.

41. The first data element corresponds to a first detection intensity at a first port among a plurality of ports in the array on the output surface of the optical Fourier transform stage, the third data element corresponds to a second detection intensity at the first port, and optionally, the second data element corresponds to a third detection intensity at a second port among a plurality of ports in the array, and the fourth data element corresponds to a fourth detection intensity at the second port. The memory according to claim 31.

42. In the memory access logic, a first sequence generates a write assignment that maps an input to multiple memory cells in an array of memory cells, and a second sequence generates a read assignment that maps the memory cells in the array to outputs. Based on the write assignment, write the multiple data elements in the input to the array. Includes reading a plurality of data elements stored in the array to the output based on the read assignment, method.

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