Vector x matrix multiplication array with analog output

Abstract

Numerous examples of artificial neural networks with vector x matrix multiplication arrays utilizing analog outputs are disclosed. In one example, a system includes a vector x matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns, and an output circuit for receiving respective neuron currents from respective columns of the vector x matrix multiplication array and generating respective output voltages, the output circuit including a neuron scaler for generating scaled currents from the respective received neuron currents, and a current-to-voltage converter for converting the scaled currents to respective output voltages.

Description

[Technical field]

[0001] (Priority Claim) This application claims priority to U.S. Provisional Patent Application No. 63 / 328,473, filed April 7, 2022, entitled "Artificial Neural Network Comprising Vector-By-Matrix Multiplication Arrays Utilizing Analog Inputs and Analog Outputs," and U.S. Provisional Patent Application No. 17 / 847,491, filed June 23, 2022, entitled "Vector-By-Matrix-Multiplication Array Utilizing Analog Outputs."

[0002] FIELD OF THEINVENTION Numerous examples of artificial neural networks with vector-by-matrix multiplication arrays that utilize analog outputs have been disclosed. [Background technology]

[0003] Artificial neural networks mimic biological neural networks (the central nervous systems of animals, specifically the brain) and are used to estimate or approximate functions that can depend on multiple inputs and are generally unknown. Artificial neural networks typically contain layers of interconnected "neurons" that exchange messages between each other.

[0004] FIG. 1 illustrates an artificial neural network, where the circles represent inputs or layers of neurons. The connections (called synapses) are represented by arrows and have numerical weights that can be tuned based on experience. This allows the neural network to adapt to the inputs and learn. Typically, a neural network contains multiple layers of inputs. There are typically one or more hidden layers of neurons, and an output layer of neurons that provides the output of the neural network. Neurons at each level make decisions, individually or collectively, based on the data they receive from the synapses.

[0005] One of the main challenges in the development of artificial neural networks for high-performance information processing is the lack of suitable hardware technologies. Indeed, practical neural networks rely on a very large number of synapses, which allows high connectivity between neurons and therefore a very high degree of parallelization of computation. In principle, such complexity can be achieved by digital supercomputers or dedicated graphic processing unit clusters. However, in addition to high costs, these approaches also suffer from poor energy efficiency compared to biological networks, which mainly perform low-precision analog calculations and therefore consume much less energy. CMOS analog circuits have been used for artificial neural networks, but the synapses of most CMOS implementations are too large considering the large number of neurons and synapses.

[0006] Applicant previously disclosed an artificial (analog) neural network utilizing one or more non-volatile memory arrays as synapses in U.S. Patent Application Publication No. 2017 / 0337466(A1), which is incorporated by reference. The non-volatile memory array operates as an analog neural memory and comprises non-volatile memory cells arranged in rows and columns. The neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, each of which includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending therebetween, a floating gate insulated and disposed above a first portion of the channel region, and a non-floating gate insulated and disposed above a second portion of the channel region. Each of the plurality of memory cells stores a weight value corresponding to a number of electrons in the floating gate. The plurality of memory cells multiply the first plurality of inputs by the stored weight values ​​to generate the first plurality of outputs. <Non-volatile memory cells>

[0007] Non-volatile memories are well known. For example, U.S. Pat. No. 5,029,130 ​​("the '130 patent"), incorporated herein by reference, discloses an array of split-gate non-volatile memory cells, which are a type of flash memory cell. Such a memory cell 210 is shown in FIG. 2. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 between the source region 14 and the drain region 16. A floating gate 20 is formed over and insulated from a first portion of the channel region 18 (and controls the conductivity of the first portion of the channel region 18) and over a portion of the source region 14. A word line terminal 22 (typically coupled to a word line) has a first portion disposed over and insulated from a second portion of the channel region 18 (and controls the conductivity of the second portion of the channel region 18) and a second portion extending upwardly above the floating gate 20. A floating gate 20 and a wordline terminal 22 are insulated from the substrate 12 by a gate oxide. A bitline 24 is coupled to the drain region 16.

[0008] The memory cell 210 is erased (electrons are removed from the floating gate) by applying a high positive voltage to the word line terminal 22, which causes electrons in the floating gate 20 to pass via Fowler-Nordheim (FN) tunneling from the floating gate 20 to the word line terminal 22 through the insulator between them.

[0009] The memory cell 210 is programmed by source side injection (SSI) of hot electrons (electrons are added to the floating gate) by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14. Electrons flow from the drain region 16 towards the source region 14. The electrons accelerate and heat up when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons are injected into the floating gate 20 through the gate oxide due to electrostatic attraction from the floating gate 20.

[0010] The memory cell 210 is read by applying a positive read voltage to the drain region 16 and the word line terminal 22 (turning on the portion of the channel region 18 below the word line terminal). When the floating gate 20 is positively charged (i.e., erased with electrons), the portion of the channel region 18 below the floating gate 20 is also turned on and current flows through the channel region 18, which is sensed as the erased or "1" state. When the floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel region below the floating gate 20 is mostly or completely off and no (or very little) current flows through the channel region 18, which is sensed as the programmed or "0" state.

[0011] Table 1 shows typical voltage / current ranges that may be applied to the terminals of memory cell 210 to perform read, erase, and program operations. Table 1: Operation of the Flash Memory Cell 210 of FIG. 2 [Table 1]

[0012] Other split-gate memory cell configurations are known, as are other types of flash memory cells. For example, FIG. 3 shows a four-gate memory cell 310 including a source region 14, a drain region 16, a floating gate 20 above a first portion of a channel region 18, a select gate 22 (typically coupled to a word line WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Pat. No. 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates, except for the floating gate 20, are non-floating gates, i.e., they are electrically connected or connectable to a voltage source. Programming is performed by heated electrons injecting themselves from the channel region 18 into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0013] Table 2 shows typical voltage / current ranges that may be applied to the terminals of memory cell 310 to perform read, erase, and program operations. Table 2: Operation of the Flash Memory Cell 310 of FIG. [Table 2]

[0014] Figure 4 shows another type of flash memory cell, a three-gate memory cell 410. Memory cell 410 is identical to memory cell 310 of Figure 3, except that memory cell 410 does not have a separate control gate. Erase and read operations (where erasure occurs through the use of an erase gate) are similar to those of Figure 3, except that no control gate bias is applied. Programming operations are also performed without a control gate bias, and as a result, a higher voltage is applied to the source line during a program operation to compensate for the lack of control gate bias.

[0015] Table 3 shows typical voltage / current ranges that may be applied to the terminals of memory cell 410 to perform read, erase, and program operations. Table 3: Operation of Flash Memory Cell 410 of FIG. [Table 3]

[0016] Figure 5 shows another type of flash memory cell, a stacked gate memory cell 510. The memory cell 510 is similar to the memory cell 210 of Figure 2, except that the floating gate 20 extends over the entire channel region 18, and the control gate 22 (where it is coupled to a word line) extends over the floating gate 20, separated by an insulating layer (not shown). Erasing is done by FN tunneling of electrons from the FG to the substrate, programming is done by channel hot electron (CHE) injection in the region between the channel 18 and the drain region 16, and read operations are done by electrons flowing from the source region 14 towards the drain region 16, similar to the read operation of the memory cell 210, which has a higher control gate voltage.

[0017] Table 4 shows typical voltage ranges that may be applied to the terminals of memory cell 510 and substrate 12 to perform read, erase, and program operations. Table 4: Operation of Flash Memory Cell 510 of FIG. [Table 4]

[0018] The methods and means described herein may be applied to other non-volatile memory technologies such as, but not limited to, FINFET split-gate flash or stack-gate flash memory, NAND flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge traps in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge traps in nitride), ReRAM (resistive ram), PCM (phase change memory), MRAM (magnetic ram), FeRAM (ferroelectric ram), CT (charge trap) memory, CN (carbon-tube) memory, OTP (one time programmable, bi-level or multi-level one-time programmable) and CeRAM (correlated electron ram).

[0019] In order to utilize a memory array containing one of the non-volatile memory cell types in an artificial neural network as described above, two modifications are made: First, as explained further below, the lines are configured so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory state of other memory cells in the array; Second, a continuous (analog) programming of the memory cells is provided.

[0020] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed from a fully erased state to a fully programmed state, and vice versa, independently and continuously with minimal disturbance to other memory cells. This means that the cell storage is essentially analog, or can at a minimum store one of a number of discrete values ​​(such as 16 or 64 different values), making every memory cell in the memory array very precisely and individually tunable, and making the memory array ideal for storage and for fine tuning adjustments to the synaptic weights of neural networks. <Neural network using non-volatile memory cell array>

[0021] 6 conceptually illustrates a non-limiting example of a neural network utilizing the present example non-volatile memory array. The example uses the non-volatile memory array neural network for a face recognition application, although other suitable applications can be implemented using the non-volatile memory array based neural network.

[0022] S0 is the input layer, which in this example is a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, each pixel with 5-bit precision). Synapse CB1 going from input layer S0 to layer C1 scans the input image with overlapping filters (kernels) of 3x3 pixels, applying different sets of weights to some instances and shared weights to other instances, and shifts the filters by one pixel (or two or more pixels depending on the model). Specifically, the values ​​of the nine pixels in the 3x3 part of the image (i.e., referred to as filters or kernels) are provided to synapse CB1, which multiplies these nine input values ​​by the appropriate weights and, after adding the outputs of the multiplication, determines a single output value, which is given by the first synapse of CB1 to generate one pixel of the feature map of layer C1. The 3x3 filter is then shifted by one pixel to the right in the input layer S0 (i.e., adding a column of 3 pixels to the right and dropping a column of 3 pixels on the left), so that the 9 pixel values ​​of this newly positioned filter are provided to synapse CB1, where they are multiplied by the same weights as above to determine a second single output value by the associated synapse. This process continues until the 3x3 filter scans the entire 32x32 pixel image of the input layer S0 for all three colors and all bits (precision values). The process is then repeated using different sets of weights to generate different feature maps of layer C1 until all feature maps of layer C1 have been calculated.

[0023] In this example, in layer C1, there are 16 feature maps, each with 30x30 pixels. Each pixel is a new feature pixel extracted from the multiplication of the input with a kernel, and thus each feature map is a two-dimensional array, and thus in this example layer C1 constitutes 16 layers of two-dimensional arrays (note that layers and arrays referred to herein are logical, not necessarily physical, relationships, i.e., arrays are not necessarily oriented in a physical two-dimensional array). Each of the 16 feature maps in layer C1 is generated by one of 16 different synaptic weight sets applied to the filter scans. The C1 feature maps can all target different aspects of the same image feature, such as boundary identification. For example, a first map (generated using a first set of weights shared by all scans used to generate this first map) can identify circular edges, a second map (generated using a second set of weights different from the first set of weights) can identify rectangular edges or the aspect ratio of a particular feature, and so on.

[0024] Before going from layer C1 to layer S1, an activation function P1 (pooling) is applied that pools values ​​from non-overlapping, consecutive 2x2 regions in each feature map. The purpose of the pooling function P1 is to average nearby positions (or a max function can be used), e.g., to reduce edge position dependency, and to reduce data size before going to the next stage. In layer S1, there are 16 15x15 feature maps (i.e., 16 different arrays of 15x15 pixels each). The synapse CB2 going from layer S1 to layer C2 scans the maps in layer S1 with a 4x4 filter with a filter shift of 1 pixel. In layer C2, there are 22 12x12 feature maps. Before going from layer C2 to layer S2, an activation function P2 (pooling) is applied that pools values ​​from non-overlapping, consecutive 2x2 regions in each feature map. In layer S2, there are 22 6x6 feature maps. At synapse CB3 going from layer S2 to layer C3, an activation function (pooling) is applied, where all neurons in layer C3 connect to all maps in layer S2 through respective synapses in CB3. There are 64 neurons in layer C3. Synapse CB4 going from layer C3 to output layer S3 fully connects C3 to S3, i.e. all neurons in layer C3 connect to all neurons in layer S3. The output at S3 contains 10 neurons, where the neuron with the highest output determines the class. This output can indicate, for example, the identification or classification of the content of the original image.

[0025] Each layer of the synapse is implemented using an array or a portion of an array of non-volatile memory cells.

[0026] FIG. 7 is a block diagram of an array that can be used for that purpose. A vector-by-matrix multiplication (VMM) array 32 contains non-volatile memory cells and is used as a synapse between one layer and the next (such as CB1, CB2, CB3, and CB4 in FIG. 6). Specifically, the VMM array 32 includes an array of non-volatile memory cells 33, an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, which decode the respective inputs to the non-volatile memory cell array 33. Inputs to the VMM array 32 can come from the erase gate and word line gate decoder 34 or from the control gate decoder 35. The source line decoder 37 in this example also decodes the output of the non-volatile memory cell array 33. Alternatively, the bit line decoder 36 can decode the output of the non-volatile memory cell array 33.

[0027] The non-volatile memory cell array 33 serves two purposes. First, the non-volatile memory cell array 33 stores the weights used by the VMM array 32. Second, the non-volatile memory cell array 33 effectively multiplies the inputs by the weights stored in the non-volatile memory cell array 33 and adds them for each output line (source line or bit line) to generate an output that becomes the input to the next layer or the input to the last layer. With the non-volatile memory cell array 33 performing the multiplication and addition functions, the need for separate multiplication and addition logic circuits is eliminated and in-memory computation is also more power efficient.

[0028] The outputs of the non-volatile memory cell array 33 are fed to a differential summer (such as a summing op-amp or a summing current mirror) 38, which sums the outputs of the non-volatile memory cell array 33 to create a single value for the convolution. The differential summer 38 is arranged to perform a summation of the positive and negative weights.

[0029] The summed output value of the differential summer 38 is then fed to an activation function block 39 that normalizes the output. The activation function block 39 may provide a sigmoid, tanh, or ReLU function. The normalized output value of the activation function block 39 becomes an element of a feature map as the next layer (e.g., C1 in FIG. 6) and is then applied to the next synapse to generate the next feature map layer or the last layer. Thus, in this example, the non-volatile memory cell array 33 constitutes a number of synapses (receiving inputs from a previous layer of neurons or from an input layer such as an image database), and the summing op-amps 38 and the activation function block 39 constitute a number of neurons.

[0030] The inputs to the VMM array 32 of FIG. 7 (WLx, EGx, CGx, and optionally BLx and SLx) may be analog levels, binary levels, or digital bits (in which case a DAC is provided to convert the digital bits to the appropriate input analog levels), and the outputs may be analog levels, binary levels, or digital bits (in which case an output ADC is provided to convert the output analog levels to digital bits).

[0031] FIG. 8 is a block diagram illustrating the use of multiple layers of VMM array 32, labeled in the figure as VMM arrays 32a, 32b, 32c, 32d, and 32e. As shown in FIG. 8, an input (denoted Inputx) is converted from digital to analog by a digital-to-analog converter 31 and provided to input VMM array 32a. The converted analog input can be a voltage or a current. The first layer input D / A conversion can be done by using a function or a look up table (LUT) that maps the input Inputx to the appropriate analog level of the matrix multiplier of input VMM array 32a. The input conversion can also be done by an analog to analog (A / A) converter to convert an external analog input to the mapped analog input to input VMM array 32a.

[0032] The output generated by the input VMM array 32a is provided as input to the next VMM array (hidden level 1) 32b, which generates an output that is provided as input to the next input VMM array (hidden level 2) 32c, and so on. The various layers of the VMM arrays 32 function as layers of synapses and neurons of a convolutional neural network (CNN). Each VMM array 32a, 32b, 32c, 32d, and 32e may be a stand-alone physical non-volatile memory array, or the multiple VMM arrays may utilize different portions of the same physical non-volatile memory array, or the multiple VMM arrays may utilize overlapping portions of the same physical non-volatile memory array. 8 includes five layers (32a, 32b, 32c, 32d, 32e): one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). Those skilled in the art will appreciate that this is merely an example and that the system may instead include more than two hidden layers and more than two fully connected layers. <Vector × Matrix Multiplication (VMM) Array>

[0033] 9 shows a neuron VMM array 900 that is particularly suited for the memory cells 310 shown in FIG. 3 and is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 900 includes a memory array 901 of non-volatile memory cells and a reference array 902 of non-volatile reference memory cells (located at the top of the array). Alternatively, a separate reference array can be located at the bottom.

[0034] In the VMM array 900, control gate lines such as control gate line 903 run vertically (so that the row-wise reference array 902 is orthogonal to control gate line 903) and erase gate lines such as erase gate line 904 run horizontally. Here, the input to the VMM array 900 is provided on the control gate lines (CG0, CG1, CG2, CG3) and the output of the VMM array 900 appears on the source lines (SL0, SL1). In one example, only the even rows are used, and in another example, only the odd rows are used. The current in each source line (SL0, SL1 respectively) performs the function of summing all the currents from the memory cells connected to that particular source line.

[0035] As described herein for neural networks, the non-volatile memory cells of the VMM array 900, i.e., the memory cells 310 of the VMM array 900, may be configured to optionally operate in the sub-threshold region.

[0036] The non-volatile reference memory cells and non-volatile memory cells described herein are biased in weak inversion (sub-threshold region) as follows: Ids = Io x e (Vg-Vth) / nVt = w × Io × e (Vg) / nVt , In the formula, w=e (-Vth) / nVt and where Ids is the drain-source current, Vg is the gate voltage of the memory cell, Vth is the threshold voltage of the memory cell, Vt is the thermal voltage = k × T / q, k is the Boltzmann constant, T is the temperature in Kelvin, q is the electron charge, n is the slope coefficient = 1 + (Cdep / Cox), Cdep = capacitance of the depletion layer, and Cox is the capacitance of the gate oxide layer, Io is the memory cell current at a gate voltage equal to the threshold voltage, Io is (Wt / L) × u ​​× Cox × (n-1) × Vt 2 where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0037] When using an IV-log converter that uses memory cells (such as reference or peripheral memory cells) or transistors to convert the input current to an input voltage: Vg = n × Vt × log [Ids / wp × Io] where wp is the w of the reference or periphery memory cell.

[0038] For a memory array used as a vector x matrix multiplier VMM array with current inputs, the output current is: Iout = wa × Io × e (Vg) / nVt , i.e. Iout = (wa / wp) × Iin = W × Iin W=e (Vthp-Vtha) / nVt where wa=w of each memory cell in the memory array. Vthp is the effective threshold voltage of the peripheral memory cells and Vtha is the effective threshold voltage of the main (data) memory cells. Note that the threshold voltage of a transistor is a function of the substrate body bias voltage, which is designated Vsb, and can be modulated to compensate for various conditions at such temperature. The threshold voltage Vth can be expressed as: Vth=Vth0+gamma(SQRT|Vsb-2×φF)-SQRT|2×φF|) where Vth0 is the threshold voltage with zero substrate bias, φF is the surface potential, and gamma is the body effect parameter.

[0039] The word line or control gate can be used as the input of the memory cell for an input voltage.

[0040] Alternatively, the flash memory cells of the VMM arrays described herein can be configured to operate in the linear region. Ids=beta×(Vgs-Vth)×Vds, beta=u×Cox×Wt / L W = α(Vgs-Vth) That is, the weight W in the linear region is proportional to (Vgs-Vth).

[0041] The word line or control gate or bit line or source line can be used as the input of a memory cell operating in the linear region. The bit line or source line can be used as the output of the memory cell.

[0042] For an IV linear converter, memory cells (such as reference or peripheral memory cells) or transistors operating in the linear region can be used to linearly convert the input and output currents to input and output voltages.

[0043] Alternatively, the memory cells of the VMM arrays described herein can be configured to operate in the saturation region. Ids=1 / 2×beta×(Vgs-Vth) 2 , beta=u×Cox×Wt / L Wα(Vgs-Vth) 2 , that is, the weight W is (Vgs-Vth) 2 is proportional to.

[0044] The word lines, control gates, or erase gates can be used as inputs for memory cells operating in the saturation region, and the bit lines or source lines can be used as outputs for output neurons.

[0045] Alternatively, the memory cells of the VMM arrays described herein may be used in all regions or combinations thereof (sub-threshold, linear, or saturation) for each layer or layers of a neural network.

[0046] Other examples for the VMM array 32 of Figure 7 are described in U.S. Patent No. 10,748,630, which is incorporated herein by reference. As described in that application, the source lines or bit lines can be used as neuron outputs (current sum outputs).

[0047] FIG. 10 shows a neuron VMM array 1000, which is particularly suitable for the memory cells 210 shown in FIG. 2 and is used as a synapse between an input layer and the next layer. The VMM array 1000 includes a memory array 1003 of non-volatile memory cells, a reference array 1001 of a first non-volatile reference memory cell, and a reference array 1002 of a second non-volatile reference memory cell. The reference arrays 1001 and 1002 arranged in the columns of the array function to convert the current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second non-volatile reference memory cells are diode-connected through a multiplexer 1014 (only partially shown) with the current inputs flowing into them. The reference cells are tuned (e.g., programmed) to a target reference level. The target reference level is provided by a reference mini-array matrix (not shown).

[0048] The memory array 1003 serves two purposes. First, it stores the weights in each memory cell that are used by the VMM array 1000. Second, it effectively multiplies the inputs (i.e., the current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which the reference arrays 1001 and 1002 convert to input voltages and provide to the word lines WL0, WL1, WL2, and WL3) by the weights stored in the memory array 1003, and then adds all the results (memory cell currents) to generate an output for each bit line (BL0-BLN), which is the input to the next layer or the input to the last layer. By performing the multiplication and addition functions, the memory array 1003 eliminates the need for separate multiplication and addition logic circuits and is also power efficient. Here, voltage inputs are provided to word lines WL0, WL1, WL2, and WL3, and outputs appear on respective bit lines BL0-BLN during a read (inference) operation. The current on each of the bit lines BL0-BLN performs the function of summing the currents from all the non-volatile memory cells connected to that particular bit line.

[0049] Table 5 shows the operating voltages and currents for the VMM array 1000. The columns in the table show the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cells, the bit lines of the unselected cells, the source lines of the selected cells, and the source lines of the unselected cells. The rows show the operations of read, erase, and program. Table 5: Operation of VMM Array 1000 in Figure 10 [Table 5]

[0050] FIG. 11 shows a neuron VMM array 1100 that is particularly suited for the memory cells 210 shown in FIG. 2 and is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 1100 includes a memory array 1103 of non-volatile memory cells, a reference array 1101 of first non-volatile reference memory cells, and a reference array 1102 of second non-volatile reference memory cells. The reference arrays 1101 and 1102 run in the row direction of the VMM array 1100. The VMM array is similar to the VMM 1000, except that the word lines run vertically in the VMM array 1100. Here, inputs are provided to the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3) and outputs appear on the source lines (SL0, SL1) during a read operation. The current of each source line performs the function of summing all the currents from the memory cells connected to that particular source line.

[0051] Table 6 shows the operating voltages and currents for VMM array 1100. The columns in the table show the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cells, the bit lines of the unselected cells, the source lines of the selected cells, and the source lines of the unselected cells. The rows show the read, erase, and program operations. Table 6: Operation of VMM Array 1100 in FIG. 11 [Table 6]

[0052] 12 shows a neuron VMM array 1200, which is particularly suited for the memory cells 310 shown in FIG. 3 and is used as part of synapses and neurons between the input layer and the next layer. The VMM array 1200 includes a memory array 1203 of non-volatile memory cells, a reference array 1201 of a first non-volatile reference memory cell, and a reference array 1202 of a second non-volatile reference memory cell. The reference arrays 1201 and 1202 function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In practice, the first and second non-volatile reference memory cells are diode-connected through a multiplexer 1212 (only a portion of which is shown), with the current inputs flowing through BLR0, BLR1, BLR2, and BLR3. Each of the multiplexers 1212 includes a respective multiplexer 1205 and cascoding transistor 1204 to ensure that the respective bit lines (e.g., BLR0) of the first and second non-volatile reference memory cells are at a constant voltage during a read operation. The reference cells are tuned to a target reference level.

[0053] The memory array 1203 serves two purposes. First, it stores the weights used by the VMM array 1200. Second, it effectively multiplies the weights stored in the memory array by the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which the reference arrays 1201 and 1202 convert to input voltages and provide to the control gates (CG0, CG1, CG2, and CG3)) and then adds all the results (cell currents) to produce an output that appears on BL0-BLN and is the input to the next layer or the input to the last layer. Having the memory array perform the multiplication and addition functions eliminates the need for separate multiplication and addition logic circuits and is also power efficient, where the inputs are provided to the control gate lines (CG0, CG1, CG2, and CG3) and the outputs appear on the bit lines (BL0-BLN) during read operations. The current on each bit line performs the function of adding together all the currents from the memory cells connected to that particular bit line.

[0054] VMM array 1200 performs one-way tuning of the non-volatile memory cells in memory array 1203. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. If too much charge is added to the floating gate (causing an incorrect value to be stored in the cell), the cell is erased and the series of partial programming operations starts over. As shown, two rows that share the same erase gate (e.g., EG0 or EG1) are erased together (known as a page erase), and then each cell is partially programmed until the desired charge on the floating gate is reached.

[0055] Table 7 shows the operating voltages and currents of the VMM array 1200. The columns in the table show the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector than the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows show the read, erase, and program operations. Table 7: Operation of the VMM array 1200 of FIG. 12 [Table 7]

[0056] FIG. 13 shows a neuron VMM array 1300, which is particularly suitable for the memory cells 310 shown in FIG. 3 and is used as part of synapses and neurons between the input layer and the next layer. The VMM array 1300 comprises a memory array 1303 of non-volatile memory cells, a reference array 1301 or a first non-volatile reference memory cell, and a reference array 1302 of a second non-volatile reference memory cell. The EG lines EGR0, EG0, EG1, and EGR1 run vertically, and the CG lines CG0, CG1, CG2, and CG3 and the SL lines WL0, WL1, WL2, and WL3 run horizontally. The VMM array 1300 is similar to the VMM array 1400, except that the VMM array 1300 implements bidirectional tuning, and each individual cell can be fully erased, partially programmed, and partially erased as needed to reach a desired amount of charge on the floating gate through the use of individual EG lines. As shown, reference arrays 1301 and 1302 convert input currents at terminals BLR0, BLR1, BLR2 and BLR3 into control gate voltages CG0, CG1, CG2 and CG3 (through the action of diode-connected reference cells via multiplexer 1314) which are applied to the memory cells in the row direction. The current outputs (neurons) are in bit lines BL0-BLN, each of which sums all the currents from the non-volatile memory cells connected to that particular bit line.

[0057] Table 8 shows the operating voltages and currents for VMM array 1300. The columns in the table show the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector than the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows show the read, erase, and program operations. Table 8: Operation of VMM Array 1300 in FIG. 13 [Table 8]

[0058] 22 shows a neuron VMM array 2200 that is particularly suited for the memory cells 210 shown in FIG. 2 and is used as part of the synapses and neurons between the input layer and the next layer. In the VMM array 2200, the input INPUT 0. , ... , INPUT N are bit lines BL0, ..., BL N and outputs OUTPUT1, OUTPUT2, OUTPUT3, and OUTPUT4 are generated on source lines SL0, SL1, SL2, and SL3, respectively.

[0059] 23 illustrates a neuron VMM array 2300 that is particularly suited for memory cells 210 shown in FIG. 2 and that is utilized as part of the synapses and neurons between an input layer and the next layer. In this example, inputs INPUT0, INPUT1, INPUT2, and INPUT3 are received on source lines SL0, SL1, SL2, and SL3, respectively, and outputs OUTPUT0, ..., OUTPUT N are bit lines BL0, ..., BL N is generated.

[0060] 24 shows a neuron VMM array 2400 that is particularly suited for the memory cells 210 shown in FIG. 2 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the word lines WL0, ..., WL M Received at OUTPUT0, ..., OUTPUT N are bit lines BL0, ..., BL N is generated.

[0061] 25 shows a neuron VMM array 2500 that is particularly suited for the memory cells 310 shown in FIG. 3 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT Mare the word lines WL0, ..., WL M Received at OUTPUT0, ..., OUTPUT N are bit lines BL0, ..., BL N is generated.

[0062] 26 shows a neuron VMM array 2600 that is particularly suited for the memory cells 410 shown in FIG. 4 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT n are the vertical control gate lines CG0, ..., CG N and outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0063] 27 shows a neuron VMM array 2700 that is particularly suited for the memory cells 410 shown in FIG. 4 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT N are bit lines BL0, ..., BL N , 2701-(N-1) and 2701-N, which are coupled to the gates of the bit line control gates 2701-1, 2701-2, ..., 2701-(N-1) and 2701-N. Exemplary outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0064] 28 shows a neuron VMM array 2800 that is particularly suitable for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the word lines WL0, ..., WL M Received at OUTPUT0, ..., OUTPUT N are bit lines BL0, ..., BL N is generated.

[0065] 29 shows a neuron VMM array 2900 that is particularly suitable for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the control gate lines CG0, ..., CG M The outputs are OUTPUT0, ..., OUTPUT N are the vertical source lines SL0, ..., SL N , and each source line SL i is coupled to the source lines of all memory cells in column i.

[0066] 30 shows a neuron VMM array 3000 that is particularly suitable for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the control gate lines CG0, ..., CG M The outputs are OUTPUT0, ..., OUTPUT N are the vertical bit lines BL0, ..., BL N , and each bit line BL i is coupled to the bit lines of all memory cells in column i. <Long and short-term memory>

[0067] Prior art includes a concept known as long short-term memory (LSTM). LSTM units are often used within neural networks. LSTM allows a neural network to store information for any given period of time and use that information in subsequent operations. A traditional LSTM unit includes a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell, and the period of time that information is stored within the LSTM. VMMs are particularly useful in LSTM units.

[0068] 14 illustrates an example LSTM 1400. The LSTM 1400 in this example includes cells 1401, 1402, 1403, and 1404. Cell 1401 receives an input vector x0 and generates an output vector h0 and a cell state vector c0. Cell 1402 receives an input vector x1, an output vector (hidden state) h0 from cell 1401, and 、 Cell 1403 receives input vector x2, output vector (hidden state) h1 from cell 1402, and cell state c1 from cell 1402, and generates output vector h2 and cell state vector c2. Cell 1404 receives input vector x3, output vector (hidden state) h2 from cell 1403, and cell state c2 from cell 1403, and generates output vector h3. Additional cells are possible, and an LSTM with four cells is merely an example.

[0069] Figure 15 shows an example implementation of an LSTM cell 1500 that can be used for cells 1401, 1402, 1403, and 1404 in Figure 14. The LSTM cell 1500 receives an input vector x(t), a cell state vector c(t-1) from a previous cell, and an output vector h(t-1) from a previous cell, and produces a cell state vector c(t) and an output vector h(t).

[0070] LSTM cell 1500 includes sigmoid function devices 1501, 1502, and 1503, each of which applies a number between 0 and 1 to control the degree to which each component of the input vector contributes to the output vector. LSTM cell 1500 also includes tanh devices 1504 and 1505 for applying a hyperbolic tangent function to the input vector, multiplier devices 1506, 1507, and 1508 for multiplying two vectors, and an adder device 1509 for adding the two vectors. The output vector h(t) can be provided to the next LSTM cell in the system or can be accessed for other purposes.

[0071] FIG. 16 shows an example of an implementation of the LSTM cell 1500, the LSTM cell 1600. For the convenience of the reader, the same numbering scheme from the LSTM cell 1500 is used in the LSTM cell 1600. The sigmoid function devices 1501, 1502, and 1503, and the tanh device 1504 each include a plurality of VMM arrays 1601 and activation function blocks 1602. Thus, the VMM array proves to be particularly useful in the LSTM cell used in certain neural network systems. The multiplier devices 1506, 1507, and 1508, and the summing device 1509 are implemented in a digital or analog manner. The activation function block 1602 can be implemented in a digital or analog manner.

[0072] An alternative example of LSTM cell 1600 (and another example of an implementation of LSTM cell 1500) is shown in Figure 17. In Figure 17, sigmoid function devices 1501, 1502 and 1503, and tanh device 1504 share the same physical hardware (VMM array 1701 and activation function block 1702) in a time-multiplexed manner. The LSTM cell 1700 also includes a multiplier device 1703 for multiplying two vectors, an addition device 1708 for adding two vectors, a tanh device 1505 (including an activation function block 1702), a register 1707 for storing a value i(t) when i(t) is output from the sigmoid function block 1702, a register 1704 for storing a value f(t)×c(t−1) when that value is output from the multiplier device 1703 via a multiplexer 1710, a register 1705 for storing a value i(t)×u(t) when that value is output from the multiplier device 1703 via the multiplexer 1710, a register 1706 for storing a value o(t)×ĉ(t) when that value is output from the multiplier device 1703 via the multiplexer 1710, and a multiplexer 1709.

[0073] Whereas LSTM cell 1600 includes multiple sets of VMM arrays 1601 and respective activation function blocks 1602, LSTM cell 1700 includes only one set of VMM arrays 1701 and activation function blocks 1702, which are used to represent multiple layers in the example of LSTM cell 1700. LSTM cell 1700 requires less space than LSTM cell 1600 because LSTM cell 1700 requires ¼ the space for the VMMs and activation function blocks compared to LSTM cell 1600.

[0074] It can be further appreciated that an LSTM unit typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as adder and activation function blocks and high voltage generation blocks. Providing separate circuit blocks for each VMM array would require a significant amount of space within a semiconductor device and would be somewhat inefficient. Thus, the example described below reduces the circuitry required outside the VMM array itself. <Gated Recurrent Unit>

[0075] Analog VMM implementations can be used for gated recurrent unit (GRU) systems. GRUs are the gating mechanism in recurrent neural networks. GRUs are similar to LSTMs, except that GRU cells generally contain fewer components than LSTM cells.

[0076] 18 illustrates an exemplary GRU 1800. The GRU 1800 in this example includes cells 1801, 1802, 1803, and 1804. Cell 1801 receives input vector x0 and generates output vector h0. Cell 1802 receives input vector x1 and output vector h0 from cell 1801 and generates output vector h1. Cell 1803 receives input vector x2 and output vector (hidden state) h1 from cell 1802 and generates output vector h2. Cell 1804 receives input vector x3 and output vector (hidden state) h2 from cell 1803 and generates output vector h3. Additional cells may be used, and a GRU with four cells is merely an example.

[0077] FIG. 19 illustrates an example implementation of a GRU cell 1900 that may be used for cells 1801, 1802, 1803, and 1804 of FIG. 18. GRU cell 1900 receives an input vector x(t) and an output vector h(t-1) from a preceding GRU cell and generates an output vector h(t). GRU cell 1900 includes sigmoid function devices 1901 and 1902, each of which applies a number from 0 to 1 to the output vector h(t-1) and components from the input vector x(t). GRU cell 1900 also includes a tanh device 1903 for applying a hyperbolic tangent function to the input vector, multiple multiplier devices 1904, 1905, and 1906 for multiplying two vectors, an addition device 1907 for adding the two vectors, and a complement device 1908 for subtracting the input from 1 to generate an output.

[0078] FIG. 20 shows a GRU cell 2000, which is an example of the implementation of the GRU cell 1900. For the convenience of the reader, the same numbering method from the GRU cell 1900 is used in the GRU cell 2000. As can be seen from FIG. 20, the sigmoid function devices 1901 and 1902 and the tanh device 1903 each include a plurality of VMM arrays 2001 and activation function blocks 2002. Therefore, it can be seen that the VMM array is particularly used in the GRU cell used in a specific neural network system. The multiplier devices 1904, 1905, 1906, the summing device 1907, and the complementary device 1908 are implemented in a digital or analog manner. The activation function block 2002 can be implemented in a digital or analog manner.

[0079] An alternative example of GRU cell 2000 (and another example implementation of GRU cell 1900) is shown in Figure 21. In Figure 21, GRU cell 2100 utilizes a VMM array 2101 and an activation function block 2102, which, when configured as a sigmoid function, applies a number between 0 and 1 to control how much each component of the input vector contributes to the output vector. In Figure 21, sigmoid function devices 1901 and 1902, and tanh device 1903 share the same physical hardware (VMM array 2101 and activation function block 2102) in a time-multiplexed manner. The GRU cell 2100 also includes a multiplier device 2103 for multiplying two vectors, an addition device 2105 for adding the two vectors, a complementation device 2109 for subtracting an input from one to generate an output, a multiplexer 2104, a register 2106 for holding the value h(t-1)×r(t) as it is output from the multiplier device 2103 via the multiplexer 2104, a register 2107 for holding the value h(t-1)×z(t) as it is output from the multiplier device 2103 via the multiplexer 2104, and a register 2108 for holding the value h^(t)×(1-z(t)) as it is output from the multiplier device 2103 via the multiplexer 2104.

[0080] Whereas GRU cell 2000 includes multiple sets of VMM arrays 2001 and activation function blocks 2002, GRU cell 2100 includes only one set of VMM arrays 2101 and activation function blocks 2102, which are used to represent multiple tiers in the example of GRU cell 2100. GRU cell 2100 requires less space than GRU cell 2000 because GRU cell 2100 requires one-third the space for the VMM and activation function blocks compared to GRU cell 2000.

[0081] It can be further appreciated that a GRU system typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as adder and activation function blocks and high voltage generation blocks. Providing separate circuit blocks for each VMM array would require a significant amount of space within a semiconductor device and would be somewhat inefficient. Thus, the example described below reduces the circuitry required outside the VMM array itself.

[0082] The input to the VMM array can be an analog level, a binary level, a pulse, a time modulated pulse, or a digital bit (in this case a DAC is required to convert the digital bit to the appropriate input analog level), and the output can be an analog level, a binary level, a timing pulse, a pulse, or a digital bit (in this case an output ADC is required to convert the output analog level to a digital bit).

[0083] Typically, for each memory cell in the VMM array, each weight W can be provided by a single memory cell, or by a differential cell, or by two blended memory cells (average of two cells). In the case of a differential cell, two memory cells are needed to provide the weight W as a differential weight (W=W+-W-). In the case of two blended memory cells, two memory cells are needed to provide the weight W as the average of two cells.

[0084] FIG. 31 illustrates a VMM system 3100. In some examples, the weights W stored in the VMM array are stored as a differential pair, W+ (positive weight) and W− (negative weight), where W=(W+)−(W−). In the VMM system 3100, half of the bit lines are designated as W+ lines, i.e., bit lines that connect to memory cells that will store a positive weight W+, and the other half of the bit lines are designated as W− lines, i.e., bit lines that connect to memory cells that provide a negative weight W−. The W− lines are interspersed alternately among the W+ lines. The subtraction operation is performed by summing circuits, such as summing circuits 3101 and 3102, that receive currents from the W+ and W− lines. The output of the W+ lines and the output of the W− lines are combined together to effectively provide W=W+−W− for each pair of (W+, W−) cells of every pair of (W+, W−) lines. Although described thus far with respect to W- lines interspersed alternatingly among W+ lines, in other examples the W+ and W- lines may be arbitrarily positioned anywhere within the array.

[0085] 32 shows another example. In a VMM system 3210, positive weights W+ are provided in a first array 3211 and negative weights W− are provided in a second array 3212 that is separate from the first array, and the resulting weights are appropriately combined together by a summing circuit 3213.

[0086] FIG. 33 shows a VMM system 3300. The weights W stored in the VMM array are stored as a differential pair, W+ (positive weight) and W- (negative weight), where W=(W+)-(W-). The VMM system 3300 comprises an array 3301 and an array 3302. Half of the bit lines in each of the arrays 3301 and 3302 are designated as W+ lines, i.e., bit lines that connect to memory cells that store a positive weight W+, and the other half of the bit lines in each of the arrays 3301 and 3302 are designated as W- lines, i.e., bit lines that connect to memory cells that provide a negative weight W-. The W- lines are interspersed alternately among the W+ lines. Subtraction operations are performed by adder circuits, such as adder circuits 3303, 3304, 3305, and 3306, that receive current from the W+ and W- lines. The output of the W+ line and the output of the W- line from each array 3301, 3302, respectively, are combined together to effectively give W=W+-W- for each pair of (W+,W-) cells of every pair of (W+,W-) lines. In addition, the W values ​​from each array 3301 and 3302 may be further combined via summing circuits 3307 and 3308, meaning that each W value is the result of subtracting the W value from array 3302 from the W value from array 3301, and the final result from summing circuits 3307 and 3308 is one of two difference values.

[0087] Each non-volatile memory cell used in an analog neural memory system is erased and programmed to hold a very specific and precise amount of charge, i.e., number of electrons, in its floating gate. For example, each floating gate should hold one of N different values, where N is the number of different weights that can be represented by each cell. Examples of N include 16, 32, 64, 128, and 256.

[0088] As artificial neural network applications become more complex, there is an increasing need to increase speed while maintaining accuracy. Prior art VMM systems utilize digital inputs and digital outputs that require analog-to-digital and digital-to-analog conversion at various stages.

[0089] What is needed is an architecture for a VMM system that operates in the analog domain where the output is in analog form. Summary of the Invention

[0090] A number of examples are described for providing an artificial neural network system with a vector by matrix multiplication array that utilizes analog outputs.

[0091]

[0092]

[0093]

[0094]

[0095]

[0096]

[0097]

[0098]

[0099]

[0100]

[0101]

[0102]

[0103]

[0104]

[0105]

[0106]

[0107]

[0108]

[0109]

[0110]

[0111]

[0112]

[0113]

[0114]

[0115]

[0116]

[0117]

[0118]

[0119]

[0120]

[0121]

[0122]

[0123]

[0124]

[0125]

[0126]

[0127]

[0128]

[0129]

[0130]

[0131]

[0132]

[0133]

[0134]

[0135]

[0136]

[0137]

[0138]

[0139]

[0140]

[0141]

[0142]

[0143]

[0144] [Brief description of the drawings]

[0145] [Figure 1] FIG. 1 illustrates an artificial neural network. [Diagram 2] 1 shows a prior art split-gate flash memory cell. [Diagram 3] 1 illustrates another prior art split-gate flash memory cell. [Figure 4] 1 illustrates another prior art split-gate flash memory cell. [Diagram 5] 1 illustrates another prior art split-gate flash memory cell. [Figure 6] FIG. 1 illustrates various levels of an exemplary artificial neural network that utilizes one or more non-volatile memory arrays. [Figure 7] FIG. 1 is a block diagram illustrating a VMM system. [Figure 8] FIG. 1 is a block diagram illustrating an example artificial neural network utilizing one or more VMM systems. [Figure 9] 2 illustrates another example of a VMM system. [Figure 10] 2 illustrates another example of a VMM system. [Figure 11] 2 illustrates another example of a VMM system. [Figure 12]2 illustrates another example of a VMM system. [Figure 13] 2 illustrates another example of a VMM system. [Figure 14] 1 shows a prior art long-term and short-term memory system. [Figure 15] An exemplary cell for use in a long- and short-term memory system is shown. [Figure 16] 16 illustrates an exemplary implementation of the cell of FIG. 15. [Figure 17] 16 illustrates another exemplary embodiment of the cell of FIG. 15. [Figure 18] 1 shows a prior art gated recurrent unit system. [Figure 19] 1 shows an exemplary cell for use in a gated recurrent unit system. [Figure 20] 20 illustrates an exemplary implementation of the cell of FIG. 19. [Figure 21] 20 illustrates another exemplary embodiment of the cell of FIG. 19. [Figure 22] 2 illustrates another example of a VMM system. [Diagram 23] 2 illustrates another example of a VMM system. [Figure 24] 2 illustrates another example of a VMM system. [Diagram 25] 2 illustrates another example of a VMM system. [Figure 26] 2 illustrates another example of a VMM system. [Figure 27] 2 illustrates another example of a VMM system. [Figure 28] 2 illustrates another example of a VMM system. [Figure 29] 2 illustrates another example of a VMM system. [Diagram 30] 2 illustrates another example of a VMM system. [Diagram 31] 2 illustrates another example of a VMM system. [Diagram 32] 2 illustrates another example of a VMM system. [Diagram 33] 2 illustrates another example of a VMM system. [Diagram 34] 2 illustrates another example of a VMM system. [Figure 35A] An analog voltage input circuit is shown. [Figure 35B] An analog voltage input circuit is shown. [Figure 35C] An analog voltage input circuit is shown. [Diagram 36] An analog voltage input circuit is shown. [Figure 37] An analog voltage input circuit is shown. [Figure 38] 2 illustrates another example of a VMM system. [Figure 39] 2 illustrates another example of a VMM system. [Diagram 40] 2 illustrates another example of a VMM system. [Diagram 41] 2 illustrates another example of a VMM system. [Figure 42A] An example of a VMM system is shown. [Figure 42B] An example of a VMM system is shown. [Diagram 43] 2 illustrates another example of a VMM system. [Diagram 44] 2 illustrates another example of a VMM system. [Figure 45A] 1 illustrates an example current-to-voltage converter. [Figure 45B] 4 illustrates another example current-to-voltage converter. [Figure 46A] 4 illustrates another example current-to-voltage converter. [Figure 46B] 4 illustrates another example current-to-voltage converter. [Figure 47] 4 illustrates another example current-to-voltage converter. [Figure 48] 1 illustrates an exemplary current-to-pulse converter. [Figure 49] 1 shows an example activation circuit. [Figure 50] 4 illustrates another exemplary activation circuit. [Figure 51] 1 illustrates an example average current pooling circuit. [Figure 52] 1 illustrates an example maximum voltage pooling circuit. [Diagram 53] 1 illustrates an example minimum voltage pooling circuit.

Best Mode for Carrying Out the Invention

[0146] <Structure of VMM System> FIG. 34 shows a block diagram of a VMM system 3400. The VMM system 3400 includes a VMM array 3401, a row decoder 3402, a high-voltage decoder 3403, a column decoder 3404, a bit-line driver 3405, an input circuit 3406, an output circuit 3407, control logic 3408, and a bias generator 3409. The VMM system 3400 further includes a high-voltage generation block 3410 including a charge pump 3411, a charge pump regulator 3412, and a high-voltage analog precision level generator 3413. The VMM system 3400 further includes a (program / erase, or weight adjustment) algorithm controller 3414, an analog circuit 3415, a control engine 3416 (which may include special functions such as arithmetic functions, startup functions, embedded microcontroller logic, etc., without limitation), and test control logic 3417.

[0147] As will be described in more detail below, the input circuit 3406 can include circuits such as an AAC (analog-to-analog converter such as a current-voltage converter or a logarithmic converter), a PAC (pulse-to-analog level converter), or any other type of converter. The input circuit 3406 can implement one or more of normalization, linear or non-linear up / down scaling functions, or arithmetic functions. The input circuit 3406 can implement a temperature compensation function for the input level. The input circuit 3406 can execute an activation function such as a rectified linear activation function (ReLU) or a sigmoid.

[0148] As described in more detail below, the output circuit 3407 may include circuits such as, for example, AAC (e.g., analog-to-analog converters, such as current-to-voltage converters or logarithmic converters), APC (e.g., analog-to-pulse converters or analog-to-time modulated pulse converters), or any other type of converter. The output circuit 3407 may implement activation functions, such as, for example, ReLU or sigmoid. The output circuit 3407 may implement one or more of statistical normalization, regularization, up / down scaling / gain functions, statistical rounding, or arithmetic functions (e.g., add, subtract, divide, multiply, shift, log) of the neuron output. The output circuit 3407 may implement temperature compensation functions for the neuron output or array output (e.g., bit line output) to keep the power consumption of the array approximately constant over temperature changes, or to increase the accuracy of the array (neuron) output, such as by keeping the slope of the IV approximately the same over temperature changes. The output circuitry 3407 may include output temperature compensation circuitry for output circuits such as ADC circuits, such as by keeping the full-scale input range of the ADC circuit approximately constant over different array output current ranges.

[0149] Further details regarding an example of input circuit 3406 are now provided.

[0150] Table 8 shows various types of functions that can be performed by the input circuit 3406 in the analog domain. Table 8: Exemplary Functions Performed by Input Circuit 3406 [Table 9]

[0151] FIG. 35A shows an analog voltage input circuit 3500 that can be used to implement Example 1 (neuron currents to analog voltages) of Table 8. The input circuit 3500 receives n neuron input currents Ineu[n:0], scaled or unscaled, and converts the n neuron input currents to respective analog voltages in a linear fashion. The input circuit 3500 includes blocks 3501-0, 3501-1, ..., 3501(n-1), 3501-n, each coupled to one of the n+1 rows in a VMM array (such as VMM array 3401 of FIG. 34). Block 3501-0 includes a row decoder 3502-0, a switch 3503-0, a capacitor 3504-0, and a buffer 3505-0. The row decoders 3502-0 to 3502-n receive respective row addresses, and their respective outputs are asserted if the received row address is the address of the corresponding row. For example, an individual row, such as row 0, may be asserted, or multiple rows, such as row 0 through row 512, may be asserted. Referring to block 3501-0 as an example, the asserted output signal of each row decoder 3052-0 closes switch 3503-0 in response to a pulse received with a pulse width of tp for a predetermined time tp, which then passes current Ineu[n:0] to charge one terminal of capacitor 3504-0 to generate a voltage that is effectively a sampled and held voltage VCGSH_0 of the current Ineu_0 provided to voltage buffer 3505-0, which maintains voltage VCG0 at its output even after switch 3503-0 is opened after the predetermined time. The other terminal of capacitor 3504-0 is connected to a common potential, such as ground. Thus, row decoder 3052-0 enables application of current Ineu[n:0] to capacitor 3504 for a predetermined time tp. Block 3501-0 performs a sample and hold function. Voltage VCG0 is then applied to the control gate line of row 0 in the VMM array. Each block 3501-1,...,3501(n-1),3501-n contains identical components as block 3501-0 and operates in the same manner.In the illustrated example, switch 3503-1 also receives a pulse with pulse width tp, but switches 3503-(n-1) and 3503-n do not receive the pulse.

[0152] FIG. 35B illustrates an analog voltage input circuit 3550 that can be used to implement Example 2 (analog current to analog voltage) of Table 8. Input circuit 3550 receives neuron input voltage Vneu[n:0] and converts it to an analog voltage in a linear fashion. Input circuit 3550 includes blocks 3551-0, 3551-1, ..., 3551(n-1), 3551-n, each coupled to a respective one of n+1 rows in a VMM array (such as VMM array 3401 of FIG. 34). Block 3551-0 includes row decoder 3552-0, switch 3553-0, capacitor 3554-0, and buffer 3555-0. Row decoders 3552-0 to 3552-n receive a row address, and an output is asserted if the row address is the address of the corresponding row. For example, an individual row, such as row 0, may be asserted, or multiple rows, such as row 0 through row 512, may be asserted. The asserted output signal closes switch 3553-0 (in response to a received pulse (not shown) of pulse width tp) for a predetermined time tp, which then passes voltage Vneu_0, effectively charging one terminal of capacitor 3554-0 to a voltage that is the sampled and held voltage VCGSH_0, which is provided to buffer 3555-0, which functions as a voltage buffer, maintaining voltage VCG0 at its output even after switch 3553-0 is opened after the predetermined time. The other terminal of capacitor 3554-0 is connected to a common potential, such as ground. Thus, row decoder 3552-0 enables application of Vneu_0 to capacitor 3554. In this manner, block 3551-0 performs a sample and hold function. Voltage VCG0 is then applied to the control gate lines of row 0 in the VMM array. Each block 3551-1, ..., 3551(n-1), 3551-n contains identical components as block 3551-0 and operates in the same manner.

[0153] Figure 35C shows an analog voltage input circuit 3580 that can be used to implement Example 2 (analog current to analog voltage) of Table 8. In this diagram, the input neuron voltages are directly enabled (passed) by row decoders 3551-0, 3552-1, ...., 3552-(n-1), 3552-n with the appropriate addresses and applied to the VCG0 voltage of the corresponding row by switches 3552-0, 3552-1, ..., 3552-(n-1), 3552-n. VCG0 is applied to the control gates of the VMM array.

[0154] FIG. 36 illustrates an analog voltage input circuit 3600 that can be used to implement examples 3 and 4 of Table 8 in an input circuit 3406 to convert an input including one or more pulses to a voltage in a linear fashion. Input circuit 3600 includes blocks 3601-0, 3601-1, ..., 3601(n-1), 3601-n, each respective block coupled to one of n+1 rows in a VMM array (such as VMM array 3401 of FIG. 34). Block 3601-0 includes row decoder 3602-0, switch 3603-0, capacitor 3604-0, switch 3607-0, input signal 3608-0, current source 3609-0, and buffer 3605-0. Row decoder 3602-0 receives a row address, and an output is asserted if the row address is the address of the corresponding row. For example, an individual row, such as row 0, may be asserted, or multiple rows, such as row 0 through row 512, may be asserted. The asserted output signal of row decoder 3602-0 closes switch 3607-0, which closes switch 3603-0 enabling input signal 3608-0, a pulse having a pulse width tp0 representing time, to be passed for the time of pulse width tp0, and the closed switch 3603-0 passes current from a respective current source 3609-0 to generate a pulse current, which charges one terminal of capacitor 3604-0 to generate voltage VCGSH_0, which is provided to buffer 3605-0, which acts as a voltage buffer and maintains voltage VCO0 at its output even after switch 3603-0 opens at the end of pulse width tp0. The other terminal of capacitor 3604-0 is connected to a common potential, such as ground. Each pulse input 3608-0 may be a single pulse with a variable pulse width tp, as shown by tp0 for row 0, or one or more pulses with no variable width but varying number of pulses, as shown by two pulses of constant width tp1 for row 1, where the variability in pulse width or number of pulses reflects the activation value applied to a particular row. For example, the activation value may range from 0 to 256 for an 8-bit activation value.Thus, block 3601-0 converts the pulse input signal into a sampled and held voltage VCG0. Voltage VCG0 is then applied to the control gate lines of row 0 in the VMM array. Each block 3601-1,...,3601(n-1),3601-n contains identical components as block 3601-0 and operates in the same manner.

[0155] FIG. 37 shows an analog voltage input circuit 3700. Using this analog voltage input circuit 3700, Example 5 in Table 8 can be executed in the input circuit 3406 to convert the scaled neuron input current Ineu_scaled into a pulse signal. Note that the width of the pulse signal is proportional to the magnitude of Ineu_scaled. The input circuit 3700 includes blocks 3701-0, 3701-1,..., 3701(n-1), 3701-n, and each block is coupled to one of n+1 rows in the VMM array (such as the VMM array 3401 in FIG. 34). Block 3701-0 includes a row decoder 3702-0, a switch 3703-0, a capacitor 3704-0, and a voltage-to-pulse (VtP) converter 3705-0. The row decoder 3702-0 receives a row address, and EN, which is the output of the row decoder 3702-0, is asserted for a predetermined time tp when the row address is the address of row 0, generating a pulse with a pulse width of tp. The asserted output signal closes the switch 3703-0. When the switch 3703-0 is closed, it allows the signal Ineu_scaled to pass through, charging one terminal of the capacitor 3704-0 for a time period of tp to generate a voltage VCGSH_0, and the voltage VCGSH_0 is provided to the voltage-to-pulse converter 3705-0. The other terminal of the capacitor 3704-0 is connected to a common potential such as ground. The voltage-to-pulse converter 3705-0 includes a comparator 3706-0, and the comparator 3706-0 compares the generated voltage VCGSH_0 with a reference voltage VRAMP that slopes upward as shown in the graph. Control_0, which is the output of the comparator, is high when VCGSH_0 > VRAMP. When Control_0 is high, Control_0 closes the switch 3707-0 to generate a voltage VCG0 equal to the voltage Vsource, for example, 1.5V. When VCGSH_0 < VRAMP, Control_0 switches to low, opens the switch 3707-0, sets VCG0 low, and effectively ends the pulse. In this way, block 3701-0 converts the input current Ineu_scaled into a pulse VCG0 of a constant voltage. Note that the width of the pulse is proportional to the magnitude of the input current.A pulse VCG0 is then applied to the control gate line of row 0 in the VMM array. Each block 3701-1, ..., 3701(n-1), 3701-n contains identical components as block 3701-0 and operates in the same manner.

[0156] VtP block 3705-0 can be applied equally to FIGS. 35A / 35B / 35C to convert the sampled and held voltages into pulses to be applied to the VMM array to implement Example 7 of Table 8.

[0157] Further details regarding an example of output circuit 3407 of FIG. 34 will now be provided.

[0158] Table 9 shows various types of functions that can be performed by the output circuit 3407 in the analog domain. Table 9: Exemplary functions performed by output circuit 3407 [Table 10]

[0159] 38 shows a VMM system 3800 including a VMM array 3401 and an output circuit 3407 including an Ineuron scaler 3801 for implementing Example 1 of Table 9. The Ineuron scaler 3801 receives output from the VMM array 3401 in the form of a neuron current Ineu. The Ineuron scaler 3801 converts the neuron current Ineu to a scaled neuron current Ineu_scaled. The Ineuron scaler 3801 can scale the current using, for example, a current mirror ratio circuit.

[0160] 39 shows a VMM system 3900 including a VMM array 3401 and an output circuit 3407 including an Ineuron scaler 3801 and a current-to-voltage converter (ItV) 3901 for implementing Example 2 of Table 9. The Ineuron scaler 3801 receives output from the VMM array 3401 in the form of a neuron current Ineu. The Ineuron scaler 3801 converts the neuron current Ineu to a scaled neuron current Ineu_scaled. The current-to-voltage converter 3901 receives the scaled neuron current Ineu_scaled and converts the current to a voltage Vout according to a linear or logarithmic function.

[0161] 40 shows a VMM system 4000 including a VMM array 3401 and an output circuit 3407 including a current-to-pulse width (ItPW) converter 4001 for implementing Example 3 of Table 9. The current-to-pulse width converter 4001 receives output in the form of neuron current Ineu from the columns of the VMM array 3401.

[0162] The current-to-pulse width converter 4001 converts the neuronal current Ineu into a signal Pulse_width, which is a signal containing a single pulse whose width is proportional to the magnitude of Ineu.

[0163] 41 shows a VMM system 4100 including a VMM array 3401 and an output circuit 3407 including a current-to-pulse count (ItPC) converter 4101 for implementing Example 4 of Table 9. The current-to-pulse count converter 4101 receives output in the form of neuron current Ineu from the columns of the VMM array 3401. The current-to-pulse count converter 4101 converts the neuron current Ineu into a signal Pulse_count that includes one or more pulses of uniform width, where the number of pulses is proportional to the magnitude of Ineu.

[0164] Figures 42A, 42B, 43, and 44 show VMM systems 4200, 4250, 4300, and 4400, respectively, which are similar to the VMM systems of Figures 39-41, except that an activation circuit 4201 has been added to the output circuit 3407. The activation circuit 4201 performs an activation function such as, but not limited to, ReLU, sigmoid, or tanh.

[0165] In FIG. 42A, output circuit 3407 includes Ineuron scaler 3801, activation circuit 4201, and current-to-voltage converter 3901. Ineuron scaler 3801 receives output from VMM array 3401 in the form of a neuron current Ineu. Ineuron scaler 3801 converts the neuron current Ineu to a scaled neuron current Ineu_scaled. Activation circuit 4201 receives the scaled neuron current Ineu_scaled and performs a function on it to generate I_active. Current-to-voltage converter 3901 receives I_active and converts it to a voltage Vout according to a linear or logarithmic function.

[0166] Alternatively, the activation can be placed after the current-to-voltage converter, as shown in FIG. 42B.

[0167] In Figure 43, output circuit 3407 comprises Ineuron scaler 3801, activation circuit 4201, and current-to-pulse width converter 4001. Ineuron scaler 3801 receives output from VMM array 3401 in the form of a neuron current Ineu. Ineuron scaler 3801 converts the neuron current Ineu to a scaled neuron current Ineu_scaled. Activation circuit 4201 receives the scaled neuron current Ineu_scaled and performs a function on it to generate I_active. Current-to-pulse width converter 4001 converts I_active to a signal Pulse_width, which is a signal that includes a single pulse whose width is proportional to the magnitude of I_active.

[0168] In FIG. 44, output circuit 3407 includes Ineuron scaler 3801, activation circuit 4201, and current-to-pulse number converter 4101. Ineuron scaler 3801 receives output from VMM array 3401 in the form of neuron current Ineu. Ineuron scaler 3801 converts neuron current Ineu to a scaled neuron current Ineu_scaled. Activation circuit 4201 receives the scaled neuron current Ineu_scaled and performs a function on it to generate I_active. Current-to-pulse number converter 4101 converts I_active to a signal Pulse_count, which is a signal including one or more pulses of uniform width, where the number of pulses is proportional to the magnitude of I_active.

[0169] 45 to 51 show exemplary circuits for implementing the functions of the output circuit 3407 described in FIGS.

[0170] 45A shows a current-to-voltage converter 4500 that can be used for the current-to-voltage converter (logarithmic) 3901. The current-to-voltage converter 4500 comprises an exemplary block 4501 coupled to the bit line BLR0 and identical blocks for the other bit lines. The current-to-voltage converter 4500 also comprises switches 4506, 4507, 4508, and 4509, and a controller 4510. The block 4501-0 includes a reference cell 4502-0, an op-amp (operational amplifier) ​​4504-0, and a switch 4505-0. The controller 4510 controls the operation of the switch 4505-0, as well as the switches 4506, 4507, 4508, and 4509.

[0171] During operation of the current-to-voltage converter, the controller 4510 closes switch 4505-0 and opens switches 4506, 4507, 4508, and 4509. Block 4501-0 receives an input current I0 on bit line BLR0, which may be a current from the VMM array 3401 that is a contribution to Ineu from column 0 in the array. Opamp 4504-0 forces the voltages at its inputs to be equal through feedback from the output of opamp 4504-0 to the control gate of reference cell 4502-0, which forces a constant voltage VREF on bit line BLR0. The current of reference cell 4502-0 is adjusted by its control gate (the output of opamp 4504-0) so that the current is equal to the input current I0. The output of op-amp 4504-0 is the same as the control gate voltage Vout-0 of reference cell 4502-0, which is a voltage signal that is a logarithmic function of the input current I0 received at BLR0 for a reference cell operating in the sub-threshold region. For a cell operating in the sub-threshold region, VCG is a logarithmic function of the cell current Icell. A block identical to block 4501-0 is coupled to each array output from the VMM array 3401.

[0172] FIG. 45B shows a current-to-voltage converter 4550 that can be used for current-to-voltage converter (logarithmic) 3901. The current-to-voltage converter 4550 comprises an exemplary block 4551 coupled to bit line BLR0 and identical blocks for the other bit lines. The current-to-voltage converter 4550 also comprises switches 4558, 4559, 4560, and 4561, and a controller 4562. Block 4551-0 comprises a reference cell 4552-0, an op-amp (operational amplifier) ​​4554-0, a switch 4555-0, a capacitor 4556-0, and a buffer 4557-0. The controller 4562 controls 4558, 4559, 4560, and 4561.

[0173] In operation, block 4551-0 receives a current I0 from the output of VMM array 3401 that is an inverted version of the current from bit line BLR0. The bit line current is inverted so that the current flows from Vdd (high power supply) to low (to this circuit). Optionally, the current may be scaled before being supplied to this circuit.

[0174] The (array output) current is provided to reference cells 4552-0, which also receive a voltage Vsweep at their control gate terminals when their respective switches are closed. Vsweep is a varying voltage (such as a ramp signal) that charges capacitor 4556-0 during a sweep operation when switch 4550-0 is closed. When a change in Vsweep causes the output of comparator 4554-0 to change, switch 4555-0 opens, thereby sampling Vsweep onto capacitor 4556-0, and the voltage of Vsweep at that instant may be held on capacitor 4556-0. Note that the held voltage represents the output voltage that causes the reference cell to conduct the same current as the array. That voltage is provided to buffer 4557-0 and output as voltage Vout-0. Vout-0 is a voltage signal that is a logarithmic function of the current I0 received on BL0, which is due to the cell operating in the sub-threshold region, i.e., VCG is a function of log(Icell). A block identical to block 4551-0 is coupled to the array current output of the VMM array 3401.

[0175] FIG. 46A illustrates a current-to-voltage converter 4600 that may be used for current-to-voltage converter (logarithmic) 3901. The current-to-voltage converter 4600 includes a reference memory cell 4601, a switch 4602, an opamp 4603, and a controller 4604 arranged as shown. The reference memory cell 4601 receives a current BLR from a bit line in the VMM array, which is the contribution to the Ineuron for that particular column in the VMM array. The opamp 4603 outputs a voltage VNEUOUT, and the switch 4602 is closed by the controller 4604 to apply that voltage to the control gate terminal of the reference memory cell 4601. This feedback loop moves VNEUOUT to a value that causes the voltage applied to the inverting terminal of the opamp 4603 to be equal to the voltage VREF applied to the non-inverting terminal of the opamp 4603. In this manner, the current-to-voltage converter 4600 converts the received current BLR to a voltage VNEUOUT according to a logarithmic function for cells in the sub-threshold region and according to a linear function for cells in the linear region.

[0176] FIG. 46B illustrates a current-to-voltage converter 4550 that may be used for current-to-voltage converter (logarithmic) 3901 in FIG. 39. The current-to-voltage converter 4650 includes a reference memory cell 4651, a switch 4652, a comparator 4653, a switch 4654, a capacitor 4655, a buffer 4656, and a controller 4657 arranged as shown. The reference memory cell 4650 receives a current IBL from a bit line in the VMM array, which is the contribution to the Ineuron for that particular column in the VMM array. The opamp 4653 outputs a voltage COMPOUT, and switches 4654 and 4652 are closed by the controller 4657 to apply that voltage to the control gate terminal of the reference memory cell 4651. This feedback loop moves COMPOUT to a value that causes the voltage applied to the inverting terminal of the opamp 4653 to be equal to the voltage VREF applied to the non-inverting terminal of the opamp 4653. The voltage of the capacitor 4655 is also COMPOUT and holds that voltage. That voltage is input to the buffer 4656 and output as VNEUOUT. In this manner, the current-to-voltage converter 4650 converts the received current IBL into a voltage VNEUOUT according to a logarithmic function.

[0177] FIG. 47 illustrates a current-to-voltage converter 4700 that can be used by current-to-voltage converter 3901 to convert a current to a voltage in a linear fashion. Specifically, current-to-voltage converter 3901 includes an instance of current-to-voltage converter 4700 for each bit line output in VMM array 3401. Current-to-voltage converter 4700 comprises a PMOS transistor 4701 and an operational amplifier 4702 arranged as shown. One terminal of PMOS transistor 4701 is attached to a voltage source. Another terminal of PMOS transistor 4701 is attached to the gate of PMOS transistor 4701 and is coupled to a bit line in VMM array 401 and a non-inverting terminal of operational amplifier 4702. The inverting terminal of operational amplifier 4702 is connected to the output of operational amplifier 4702. The current drawn by bit line I_BL results in a voltage V_IBL being output from operational amplifier 4702. The operational amplifier 4702 acts as a buffer, and V_IBL maintains its level, which reflects the current drawn by the bit line I_BL, regardless of any load it may be attached to. Optionally, the current-to-voltage converter 4700 can also be used in a bit line current mirror buffer. In such an example, the voltage V_IBL is fed to the gate of a similar PMOS (not shown), and the current in this PMOS is the mirror current of PMOS 4701. FIG. 48 shows a current-to-pulse converter 4800, which can be used for the current-to-pulse width converter 4001 or the current-to-pulse number converter 4101 to convert a current into one or more pulses. The current-to-pulse converter 4800 receives the neuron current I_BL and the enable signal EN, and comprises a capacitor 4801, a comparator 4802, and a gate 4806. In operation, the capacitor 4801 is charged by I_BL. Initially, the voltage of the capacitor 4801 is lower than VREF, and the output COMPOUT is high. When the voltage on capacitor 4801 exceeds VREF, the output COMPOUT of comparator 4802 changes from high to low. COMPOUT is input to AND gate 4806 along with enable signal EN, and the output of AND gate 4806 is a pulse VNEU_PW whose pulse width is proportional to the magnitude of I_BL. This is shown in graphs 4803 and 4804.

[0178] Optionally, an AND gate 4807 can be used instead of AND gate 4806. AND gate 4807 takes COMPOUT, EN, and a clock signal as inputs and outputs VNEU_PC. VNEU_PC includes a series of pulses with the frequency and phase of CLK, where a pulse begins when COMPOUT and EN are high, and a pulse ends when COMPOUT or EN goes low. This converts the current I_BL into a series of uniform pulses, where the number of pulses is proportional to the magnitude of I_BL.

[0179] 49 shows an activation circuit 4900, which is an exemplary implementation of the tanh activation circuit 4201. The activation circuit 4900 comprises a current-to-voltage converter 4901, PMOS transistors 4902 and 4903 (forming a current mirror), NMOS transistors 4904 and 4905, and NMOS transistor 4906 arranged as shown. The activation circuit 4900 receives a current input I_input and generates a current output Iout according to a sigmoid function implemented using a differential pair as follows: Iout=I1-I2=Ibias×tanh(K×(V1-V2) / 2). Thus, the activation circuit 4900 converts I_input to Iout according to a sigmoid function. A graph 4907 shows IO as a function of I_input.

[0180] 50 shows an activation circuit 5000, which is an example implementation of the activation circuit 4201. The activation circuit 5000 includes an NMOS transistor 5001, an operational amplifier 5002, and an NMOS transistor 5003 arranged as shown. The activation circuit 5000 receives a current input I_In and generates a voltage output OUT according to a ReLu function, as shown by graph 5004.

[0181] FIG. 51 shows an average current pooling circuit 5100, which may optionally be part of the output circuit 3407, to perform the averaging function. The average current pooling circuit 5100 comprises N current sources 5101-1, ..., 5101-N (each representing a current from a bit line in the VMM array), an NMOS transistor 5102, and an NMOS transistor 5103. The NMOS transistor 5102 sums all of the currents received from the current sources 5101-1, ..., 5101-N. The NMOS transistors 5102 and 5103 are arranged in a current mirror configuration. However, the widths of the NMOS transistors 5102 and 5103 differ by a factor of N, so that the current Iout drawn through the NMOS transistor 5103 is 1 / N of the current drawn by the NMOS transistor 5102, which effectively produces an average of the currents received from all N bit lines.

[0182] FIG. 52 shows a maximum voltage pooling circuit 5200, which may optionally be part of the output circuit 3407. The maximum voltage pooling circuit 5200 receives n voltages (VIN1, ..., VINn) and outputs the maximum of the voltages as VOUT. It does this by comparing pairs of voltages (VIN1 and VIN2, ..., VINn-1 and VINn), outputting the larger of the two, and then comparing the resulting pairs, continuing the process until only one voltage VOUT remains. The comparison is done using a circuit 5201, which comprises a comparator 5202, an NMOS transistor 5203, an inverter 5204, and an NMOS transistor 5205. The circuit 5201 receives two voltages, such as VIN1 and VIN2, and outputs the larger of the two voltages as OUT. In particular, comparator 5202 outputs a high signal when VIN1 is greater than VIN2, which turns on NMOS transistor 5203 to pass VIN1 to OUT and turns off NMOS transistor 5205 through inverter 5204. Similarly, comparator 5202 outputs a low signal when VIN2 is greater than VIN1, which turns off NMOS transistor 5203 and turns on NMOS transistor 5205 through inverter 5204 to pass VIN2 to OUT.

[0183] FIG. 53 shows a minimum voltage pooling circuit 5300, which may optionally be part of the output circuit 3407. The minimum voltage pooling circuit 5300 receives n voltages (VIN1, ..., VINn) and outputs the minimum of the voltages as VOUT. It does this by comparing pairs of voltages (VIN1 and VIN2, ..., VINn-1 and VINn), outputting the smaller of the two, then comparing the resulting pairs and continuing the process until only one voltage VOUT remains. The comparison is done using a circuit 5301, which comprises a comparator 5302, an NMOS transistor 5303, an inverter 5304, and an NMOS transistor 5305. The circuit 5301 receives two voltages, such as VIN1 and VIN2, and outputs the smaller of the two voltages as OUT.

[0184] In particular, comparator 5302 outputs a high signal when VIN1 is less than VIN2, which turns on NMOS transistor 5203 to pass VIN1 to OUT and turns off NMOS transistor 5205 through inverter 5204. Similarly, comparator 5202 outputs a low signal when VIN2 is less than VIN1, which turns off NMOS transistor 5203 and turns on NMOS transistor 5205 through inverter 5204 to pass VIN2 to OUT.

[0185] It should be noted that, as used herein, both the terms "over" and "on" are inclusive of "directly" (with no intermediate material, element, or gap disposed between them) and "indirectly" (with an intermediate material, element, or gap disposed between them). Similarly, the term "adjacent" includes "directly adjacent" (with no intermediate material, element, or gap disposed between them) and "indirectly adjacent" (with an intermediate material, element, or gap disposed between them), "attached" includes "directly attached" (with no intermediate material, element, or gap disposed between them) and "indirectly attached" (with an intermediate material, element, or gap disposed between them), and "electrically coupled" includes "directly electrically coupled" (without an intermediate material or element disposed between them that electrically connects the elements together) and "indirectly electrically coupled" (with an intermediate material or element disposed between them that electrically connects the elements together). For example, forming an element "above a substrate" can include forming the element directly on the substrate, with no intermediate materials / elements between them, and forming the element indirectly on the substrate, with one or more intermediate materials / elements between them.

Claims

1. 1. A system comprising: a vector x matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns; an output circuit for receiving a respective neuron current from each column of the vector x matrix multiplication array and generating a respective output voltage, the output circuit comprising: a neuron scaler for generating scaled currents from each of the received neuron currents; a current-to-voltage converter for converting the scaled currents to the respective output voltages.

2. 2. The system of claim 1, wherein the current-to-voltage converter converts the received current to the output voltage according to a linear function applied to the received current.

3. 2. The system of claim 1, wherein the current-to-voltage converter converts the received current to the output voltage according to a logarithmic function applied to the received current.

4. The system of claim 1 , wherein the plurality of non-volatile memory cells comprises stacked gate flash memory cells.

5. The system of claim 1 , wherein the plurality of non-volatile memory cells comprises split-gate flash memory cells.

6. 1. A system comprising: a vector x matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns; an output circuit for receiving a respective neuron current from each said column of the vector x matrix multiplication array and generating a respective output voltage, the output circuit comprising: a neuron scaler for generating scaled currents from each of the received neuron currents; an activation circuit for performing an activation function on the scaled current to generate an activation current; a current-to-voltage converter for converting the activation current to the respective output voltage.

7. The system of claim 6 , wherein the activation function comprises a sigmoid function.

8. The system of claim 6 , wherein the activation function comprises a tanh function.

9. The system of claim 6 , wherein the activation function comprises a normalized linear activation function.

10. 1. A system comprising: a vector x matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns; an output circuit for receiving a respective neuron current from each said column of the vector x matrix multiplication array and generating a respective output voltage, the output circuit comprising: a neuron scaler for generating scaled currents from each of the received neuron currents; a current-to-voltage converter for converting the scaled current into a converted voltage; an activation circuit for performing an activation function on the converted voltages to generate the respective output voltages.

11. The system of claim 10 , wherein the activation function comprises a sigmoid function.

12. The system of claim 10 , wherein the activation function comprises a tanh function.

13. The system of claim 10 , wherein the activation function comprises a normalized linear activation function.

14. 1. A system comprising: a vector x matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns; an output circuit for receiving the neuron currents from the columns of the vector x matrix multiplication array and generating an output voltage, the output circuit comprising: A system comprising: a current to pulse width converter for converting the neuronal current into a pulse, the width of the pulse being based on the neuronal current.

15. 1. A system comprising: a vector x matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns; an output circuit for receiving a respective neuron current from each column of the vector x matrix multiplication array and generating a respective output voltage, the output circuit comprising: a neuron scaler for generating a scaled current from each said neuron current; 11. A system comprising: an activation circuit, the activation circuit performing an activation function on the scaled current to generate an activation current; and a current-to-pulse width converter for converting the activation current into a pulse, the width of the pulse being based on the activation current.

16. The system of claim 15 , wherein the activation function comprises a sigmoid function.

17. The system of claim 15 , wherein the activation function comprises a tanh function.

18. The system of claim 15 , wherein the activation function comprises a normalized linear activation function.

19. 20. The system of claim 15, wherein the plurality of non-volatile memory cells comprises stacked gate flash memory cells.

20. 20. The system of claim 15, wherein the plurality of non-volatile memory cells comprises split-gate flash memory cells.

21. 1. A system comprising: a vector x matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns; an output circuit for receiving the neuron currents from the columns of the vector x matrix multiplication array and generating an output voltage, the output circuit comprising: a current-to-pulse converter for converting the neuronal current into a series of pulses, the number of pulses in the series of pulses being based on a magnitude of the neuronal current;

22. 1. A system comprising: a vector x matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns; an output circuit for receiving the neuron currents from the columns of the vector x matrix multiplication array and generating an output voltage, the output circuit comprising: a neuron scaler for generating a scaled current from the neuron current; an activation circuit that performs an activation function on the scaled current to generate an activation current; a current-to-pulse converter for converting the activation current into a series of pulses, the number of pulses in the series of pulses being based on a magnitude of the activation current;

23. 23. The system of claim 22, wherein the activation function comprises a sigmoid function.

24. 23. The system of claim 22, wherein the activation function comprises a tanh function.

25. 23. The system of claim 22, wherein the activation function comprises a normalized linear activation function.

26. 23. The system of claim 22, wherein the plurality of non-volatile memory cells comprises stacked gate flash memory cells.

27. 23. The system of claim 22, wherein the plurality of non-volatile memory cells comprises split-gate flash memory cells.

Images