Wireless Power Transmission

Abstract

The power receiver 105 communicates with the power transmitter 101 using load-modulated data symbols modulated by a chip sequence that is a combination of two binary sequences. The power transmitter 101 comprises a data receiver 207 including a chip determiner 903 that determines the received chip sequence and two correlators 905, 907 that correlate this sequence with the two binary sequences. The two correlation results are combined into a single correlation value by the combiner 905. The detector 917 detects the received data symbol values ​​according to the combined correlation value. This approach may provide improved detection of data symbols and improved communication from the power receiver 105 to the power transmitter 101.

Description

[Technical field]

[0001] The present invention relates to wireless power transfer, and in particular, but not exclusively, to communication in power transfer systems such as the Qi wireless power transfer standard. [Background technology]

[0002] Most current electrical products require a dedicated electrical contact to be powered from an external source. However, this tends to be impractical, requiring the user to physically insert a connector or otherwise establish physical electrical contact. Typically, power requirements also vary widely, and currently most devices are provided with a dedicated power source, resulting in a typical user having a number of different power sources, each dedicated to a particular device. However, while the use of an internal battery may avoid the need for a wired connection to the power source during use, this only provides a partial solution, as the battery requires recharging (or replacement). Also, using a battery may substantially increase the weight and potential cost and size of the device.

[0003] To provide a significantly improved user experience, it is proposed to use a wireless power source where power is inductively transferred from a transmitter coil in the power transmitting device to a receiver coil in the individual devices.

[0004] Power transfer via magnetic induction is a well-known concept and is mostly applied in transformers with tight coupling between the primary transmitter inductor / coil and the secondary receiver coil. By separating the primary transmitter coil and the secondary receiver coil between the two devices, wireless power transfer between them becomes possible based on the principle of loosely coupled transformers.

[0005] Such a configuration allows for wireless power transmission to a device without the need for wires or physical electrical connections. Indeed, a device can simply be placed adjacent to or on the transmitter coil for external recharging or powering. For example, the power transmitter can be configured to have a horizontal surface onto which a device can simply be placed to provide power.

[0006] Moreover, such wireless power transmission configurations can be advantageously designed so that the power transmitter can be used with a range of power receiving devices. In particular, a wireless power transmission approach known as the Qi standard has been defined and is currently being further developed. This approach allows power transmitter devices that meet the Qi standard to be used with power receiver devices that meet the Qi standard without having to be from the same manufacturer or exclusive to each other. The Qi standard further includes several features to allow the operation to be adapted to a specific power receiving device (e.g., depending on a specific power drain).

[0007] The Qi standard has been developed by the Wireless Power Consortium and further information can be found, for example, on its website http: / / www.wirelesspowerconsortium.com / index.html, in particular the defined specifications.

[0008] Based on the Qi standard, an approach known as the Ki standard is being developed specifically for higher power applications, such as for kitchen appliances.

[0009] To support efficient wireless power transmission, wireless power transmission systems, such as Qi-based systems, utilize substantial communication between the power transmitter and the power receiver. Initially, Qi only supported communication from the power receiver to the power transmitter using load modulation of the power transmission signal. Thus, early Qi devices only supported one-way communication from the power receiver to the power transmitter.

[0010] However, the development of standards has introduced bidirectional communication, and many functions are supported by communication exchanges between the power receiver and the power transmitter. In many systems, communication from the power transmitter to the power receiver is achieved by modulating the power transmission signal.

[0011] Some systems have proposed using separate, dedicated communication capabilities, such as, for example, Bluetooth or NFC (near field communication) based communication. However, while such approaches tend to provide efficient operation in many scenarios, they are also associated with several drawbacks, including the need for dedicated, complex communication circuitry and potentially reducing the confidence that the power transmitter is communicating with the power receiver that is actually being powered. Also, backward compatibility with, for example, Qi-based devices, can be problematic for newer devices based on separate communication.

[0012] However, communicating using load modulation of a power transmission signal that transmits power to a power receiver tends to have several associated drawbacks. For example, load modulation tends to introduce some electrical noise, including both noise into the device's signal and radiated electromagnetic noise. Load modulation can increase electromagnetic interference to other devices, and maintaining sufficient or optimal electromagnetic compatibility has proven difficult.

[0013] It has also been found that in practice load modulation can introduce undesirable spurious oscillations into the drive signal and the power transmission signal. The power transmission paths in wireless power transmission systems tend to contain a significant amount of inductance and are prone to resonant behavior. Load modulation therefore tends to affect the power transmission path and indeed the communication path. Load modulation therefore also introduces noise and interference to the communication itself (self-interference). This is very different from other communication systems where random noise or interference from other transmissions is the main cause of bit errors.

[0014] Another drawback is that load modulation of the power transmission signal can result in acoustic noise. Such noise can result from the effect of the variations in the electromagnetic fields caused by the load modulation on mechanical elements, which can cause the mechanical elements to move and vibrate, potentially generating acoustic noise.

[0015] In some cases, for example, the load modulation communication used in early versions of the Qi standard may not be completely reliable and may cause some bit errors. For example, high levels of noise or self-interference may result in bit errors and / or may require an increase in the modulation depth, which may result in increased electrical or acoustic noise resulting from the load modulation.

[0016] In some methods, it may be desirable to maintain backward compatibility or change to a different communication approach that reduces the amount of changes required to existing designs and approaches, but this is a major challenge that often makes it unattractive. Summary of the Invention [Problem to be solved by the invention]

[0017] Therefore, improved approaches would be advantageous, particularly approaches that enable increased flexibility, reduced cost, reduced complexity, improved power transfer operation, increased reliability, reduced communication errors, improved backward compatibility, improved electromagnetic compatibility, reduced electrical and / or acoustic noise, improved communications, and / or improved performance. [Means for solving the problem]

[0018] Accordingly, the Invention seeks to preferably mitigate, reduce or eliminate one or more of the above mentioned disadvantages singly or in any combination.

[0019] According to one aspect of the present invention, there is provided a power transmitter for wirelessly supplying power to a power receiver via an electromagnetic power transmission signal, the power transmitter comprising: an output circuit including a transmit coil configured to generate a power transmission signal in response to a drive signal applied to the output circuit; a driver configured to generate the drive signal; and a data receiver configured to receive load modulated data symbols modulated by at least one modulation chip sequence, at least a first modulation chip sequence of the at least one modulation chip sequence being a combination of a first binary chip sequence and a second binary chip sequence, the receiver comprising: a load measurer configured to measure a load on the power transmission signal to generate a measured load value; a chip determiner configured to determine the received chip sequence from the measured load value; a first correlator configured to correlate the received chip sequence with the first binary chip sequence to generate a first correlation value; and a second correlator configured to correlate the received chip sequence with the second binary chip sequence to generate a second correlation value. A combiner configured to generate a combined correlation value as a function of the first correlation value and the second correlation value, and a detector configured to detect received data symbol values ​​in response to the combined correlation value.

[0020] The present invention may in many embodiments enable improved performance, and in particular may in many embodiments enable improved communication between a power receiver and a power transmitter, which may in many embodiments enable improved power transfer.

[0021] This approach can enable improved communication and, in many embodiments, can allow for improved tradeoffs between different parameters and operating characteristics. This approach can, for example, allow for reduced modulation depth to be used while still allowing reliable communication. This approach can reduce electrical noise and / or electromagnetic interference, allowing for improved electromagnetic compatibility. This approach can often reduce or prevent acoustic noise. Additionally, this approach can provide advantageous backward compatibility, allowing for relatively easy modification of existing approaches, such as those used by the Qi or Ki standards. This approach can often reuse many features from such existing approaches. This approach can provide very efficient performance while allowing for low complexity implementation. This communication approach can be particularly advantageous for use in power transfer systems, as bandwidth considerations may be less important in such systems.

[0022] This approach can enable improved tradeoffs between various parameters, including computational resource requirements, data detection accuracy, bit error rate, data rate, etc., in many scenarios.

[0023] This approach, in many embodiments, allows for improved and / or facilitated detection of load modulation data in the power transmitter.

[0024] In many scenarios, the communication of data from a power receiver to a power transmitter can be made less sensitive to time variations, noise, distortion, and especially self-interference.

[0025] A chip sequence is a sequence / pattern of chip values. Each chip value can be represented by a load modulation level or its pattern. Chip sequences for different data symbols have different sequences / patterns of chip values. The first binary chip sequence and the second binary chip sequence can be different chip sequences. The combined correlation value can be monotonically increasing for the first correlation value and monotonically increasing for the second correlation value. The combined correlation value can be increasing for increasing values ​​of the first correlation value and increasing for increasing values ​​of the second correlation value. In some embodiments, the combined correlation value can be a weighted combination / sum / multiplication of the first correlation value and the second correlation value. The weights for both the first correlation value and the second correlation value can be positive. Each modulation chip sequence can represent one data symbol.

[0026] In many embodiments, the length of the chip sequence is greater than or equal to 10 chips and less than or equal to 1024 chips.

[0027] The measured load value may be a sample of a signal indicative of a load on the power transmission signal.The measured load value may be a sample of a parameter of the drive signal.

[0028] The load measurer may be configured to measure the loading / loading of the power transmission signal (particularly by the power receiver) to determine a measured load value for a load time interval.

[0029] The function for generating the combined correlation value may be monotonically increasing for both the first and second correlation values. The first and second binary sequences may have the same length and may have the same length as the modulation chip sequence.

[0030] The correlator may be configured to generate correlation values ​​for different, possibly all, chip alignments between the received chip sequence and the first and second binary sequences. The detector and possibly the combiner may process the correlation value corresponding to the peak correlation in such a case. In some embodiments, the correlation value is a correlation value of the first and second binary sequences that are aligned with the modulated chip sequence / received chip sequence, and the alignment may be determined, for example, by peak detection of the correlation.

[0031] In accordance with an optional feature of the invention, the first modulation chip sequence includes at least three different chip values.

[0032] This can provide improved performance in many embodiments, and in many scenarios it can provide improved information related to the modulation chip sequence and how this relates to the first and second binary sequences, thereby providing additional symbol detection.

[0033] According to an optional feature of the invention, at least two chip values ​​of the first modulated chip sequence are represented by a modulation load change, the modulation load change being different for the at least two chip values, and the chip determiner is configured to determine the received chip sequence in response to the modulation load change.

[0034] This approach, in many embodiments, allows for improved and / or facilitated detection of load modulation data in a power transmitter. It can reduce or eliminate in many scenarios the need to determine an average or nominal load reference level to detect modulation load levels and variations. For example, in many embodiments, chip values ​​can be determined considering only the modulation load values ​​within the chip itself.

[0035] In many scenarios, the load modulation of the individual chips can not only indicate the chip value but also provide a reference load value for the determination of the chip value.

[0036] According to an optional feature of the invention, each chip time interval of the first modulated chip sequence is divided into at least two duty time intervals, at least two chip values ​​have different modulation loads for the at least two duty time intervals, a pattern of modulation loads is different for different chip values ​​of the at least two chip values, and a third chip value of the at least three different chip values ​​has a same modulation load in the at least two duty time intervals, the load measurer is configured to determine a measured load value as a measured load value of a duty time interval, and the chip determiner is configured to determine a chip value of the received chip sequence in response to a difference between the measured load values ​​of the different duty time intervals of each chip.

[0037] This allows for improved and / or easier detection of the load modulation data in the power transmitter.

[0038] In some embodiments, the load measurement device is configured to synchronize measurements of the load of the power transmission signal to cycles of the power transmission signal.

[0039] This may allow for improved performance and / or accelerated operation and / or reduced complexity, which may in particular allow for improved and / or facilitated determination of appropriate load values ​​for data symbol detection.

[0040] In some embodiments, each duty time interval has a duration of one cycle of the power transmission signal.

[0041] This may allow for improved performance and / or accelerated operation and / or reduced complexity, which in many scenarios allows for increased data rates.

[0042] In some embodiments, each duty time interval has a duration of multiple cycles of the power transmission signal.

[0043] This may allow for improved performance and / or expedited operation and / or reduced complexity, which in some embodiments may provide reduced sensitivity to synchronization errors.

[0044] In some embodiments, the stress measurer is configured to perform a single stress measurement per stress time interval.

[0045] This may allow for improved performance and / or accelerated operation and / or reduced complexity.

[0046] In some embodiments, the chip determiner is configured to determine a binary chip value for each chip as a function of the sign of the difference between the measured load values ​​during two modulated load time intervals of the chip.

[0047] This may allow for improved performance and / or accelerated operation and / or reduced complexity.

[0048] In some embodiments, the chip determiner is configured to determine the received chip sequence to include a soft-decision chip value depending on a magnitude of a difference between the measured load values ​​for two modulation load time intervals for the chip, and the correlator is configured to perform correlation with the first and second binary chip sequences, respectively, depending on the soft-decision chip value.

[0049] This may allow for improved performance and / or accelerated operation and / or reduced complexity.

[0050] In accordance with an optional feature of the invention, the first modulation chip sequence includes three different chip values.

[0051] This allows for particularly advantageous operation and / or performance in many embodiments.

[0052] In accordance with an optional feature of the invention, the first modulated chip sequence has a first value for aligned chips of the first binary sequence and the second binary sequence that both have a first binary value, a second value for aligned chips of the first binary sequence and the second binary sequence that both have a second binary value, and a third value for aligned chips of the first binary sequence and the second binary sequence that have a different aligned value.

[0053] This allows for particularly advantageous operation and / or performance in many embodiments. Aligned chips can be chips that are in the same consecutive position within their respective sequences.

[0054] In accordance with an optional feature of the invention, the chip determiner is configured to determine the received chip sequence as a binary chip sequence.

[0055] This allows for particularly advantageous operation and / or performance in many embodiments. This allows for efficient and / or low complexity implementation in many embodiments. It may, for example, allow for binary correlation. However, this approach allows for very accurate data symbol detection despite the binary received chip sequence representing a possibly non-binary modulation chip sequence.

[0056] According to an optional feature of the invention, the chip determiner and the first correlator are configured such that a contribution to the first correlation value for at least one chip value of the first modulated chip sequence is less than 10% of a contribution to the first correlation value for at least one other chip value of the modulated chip sequence.

[0057] This allows for particularly advantageous operation and / or performance in many embodiments.

[0058] According to an optional feature of the invention, the combiner is configured to generate a combined correlation value in response to multiplying the first correlation value and the second correlation value.

[0059] This allows for particularly advantageous operation and / or performance in many embodiments.

[0060] According to an optional feature of the invention, the chip determiner is configured to determine the received chip sequence to have chip values ​​which are possible chip values ​​for the first modulation chip sequence.

[0061] This allows for particularly advantageous operation and / or performance in many embodiments.

[0062] According to an optional feature of the invention, a cross-correlation between the first binary sequence and the first modulation chip sequence is greater than or equal to two-thirds of a length of the first binary sequence when the first binary sequence and the first modulation chip sequence are aligned and is less than or equal to one-third of a length of the first binary sequence when the first binary sequence and the first modulation chip sequence are not aligned.

[0063] According to one aspect of the present invention, there is provided a power receiver for wirelessly receiving power from a power transmitter via an electromagnetic power transmission signal, the power receiver comprising: an input circuit including a receive coil configured to extract power from the power transmission signal; and a data transmitter configured to transmit data symbols to the power transmitter by load modulating the power transmission signal, each data symbol being modulated by a sequence of modulation load values ​​corresponding to a chip sequence from a set of modulation chip sequences, wherein chip sequences from the set of chip sequences are linked to different data symbol values, and at least one modulation chip sequence from the set of modulation chip sequences is a combination of a first binary chip sequence and a second binary chip sequence and has at least three different chip values.

[0064] According to one aspect of the invention, there is provided a method of operating a power transmitter for wirelessly supplying power to a power receiver via an electromagnetic power transmission signal, the power transmitter having an output circuit including a transmit coil configured to generate a power transmission signal in response to a drive signal applied to the output circuit, a driver configured to generate the drive signal, and a data receiver configured to receive load modulated data symbols modulated by at least one modulation chip sequence, at least a first modulation chip sequence of the at least one modulation chip sequence being a combination of a first binary chip sequence and a second binary chip sequence, the method comprising the steps of: a receiver measuring a load on the power transmission signal to generate a measured load value, determining a received chip sequence from the measured load value, correlating the received chip sequence with the first binary chip sequence to generate a first correlation value, correlating the received chip sequence with the second binary chip sequence to generate a second correlation value, generating a combined correlation value as a function of the first correlation value and the second correlation value, and detecting a received data symbol value in response to the combined correlation value.

[0065] According to one aspect of the present invention, there is provided a method of operating a power receiver for wirelessly receiving power from a power transmitter via an electromagnetic power transmission signal, the power receiver having an input circuit including a receive coil configured to extract power from the power transmission signal, the method comprising: a data transmitter load modulating the power transmission signal to transmit data symbols to the power transmitter, each data symbol being modulated by a sequence of modulation load values ​​corresponding to a chip sequence from a set of modulation chip sequences, each chip sequence from the set of chip sequences being linked to different data symbol values, and at least one modulation chip sequence from the set of modulation chip sequences is a combination of a first binary chip sequence and a second binary chip sequence and has at least three different chip values.

[0066] According to one aspect of the present invention, a method of operation for a power receiver is provided.

[0067] These and other aspects, features and advantages of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. [Brief description of the drawings]

[0068] Embodiments of the present invention will now be described, by way of example only, with reference to the drawings in which: [Figure 1] FIG. 2 illustrates an example of elements of a power transfer system according to some embodiments of the present invention. [Diagram 2] 2 illustrates an example of elements of a power transmitter according to some embodiments of the present invention. [Diagram 3] FIG. 2 illustrates an example of a half-bridge inverter for a power transmitter. [Figure 4] FIG. 1 illustrates an example of a full bridge inverter for a power transmitter. [Diagram 5] FIG. 2 illustrates an example of elements of a power receiver according to some embodiments of the present invention. [Figure 6] FIG. 13 is a diagram showing an example of a chip sequence. [Figure 7]11 is a diagram showing an example of correlation values ​​for load communication in a wireless power transmission system; [Figure 8] FIG. 2 illustrates an example of elements of a power receiver according to some embodiments of the present invention. [Figure 9] 2 illustrates an example of elements of a power transmitter according to some embodiments of the present invention. [Figure 10] 11A and 11B are diagrams showing examples of simulation results of load modulation communication in a wireless power transmission system. [Figure 11] 11A and 11B are diagrams showing examples of simulation results of load modulation communication in a wireless power transmission system. [Figure 12] 11A and 11B are diagrams showing examples of simulation results of load modulation communication in a wireless power transmission system. [Figure 13] 1 illustrates an example of load communication in a wireless power transfer system according to some embodiments of the present invention. [Figure 14] 11A and 11B are diagrams showing an example of a simulation result of load modulation communication in a wireless power transmission system. [Figure 15] 1 shows an example of a simulation result of load modulation communication in a wireless power transmission system. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0069] The following description focuses on embodiments of the invention applicable to high power wireless power transfer systems utilizing power transfer approaches as known from the Qi or Ki standards, however, it will be appreciated that the invention is not limited to this application and may be applied to many other wireless power transfer systems.

[0070] 1 illustrates an example of a power transfer system according to some embodiments of the present invention. The power transfer system includes a power transmitter 101 including (or coupled to) a transmitter coil / inductor 103. The system further includes a power receiver 105 including (or coupled to) a receiver coil / inductor 107.

[0071] The system provides an inductive electromagnetic power transmission signal capable of inductively transmitting power from a power transmitter 101 to a power receiver 105. Specifically, the power transmitter 101 generates an electromagnetic signal, which is propagated as a magnetic flux by a transmitter coil or inductor 103. The power transmission signal can typically have a frequency between about 20 kHz and about 500 kHz, and in many practical systems can be about 120-150 kHz. The transmitter coil 103 and the receiver coil 107 are loosely coupled, and thus the receiver coil 107 picks up (at least a portion of) the power transmission signal from the power transmitter 101. Thus, power is transmitted from the power transmitter 101 to the power receiver 105 via wireless inductive coupling from the transmitter coil 103 to the receiver coil 107. The term power transmission signal is primarily used to refer to the induction signal / magnetic field (magnetic flux signal) between the transmitter coil 103 and the receiving coil 107, but it will be understood that equivalently it can also be considered and used to refer to an electrical signal supplied to the transmitter coil 103 or picked up by the receiving coil 107.

[0072] In an embodiment, power receiver 105 is specifically a power receiver that receives power via receiver coil 107. However, in other embodiments, power receiver 105 may include a metallic element, such as a metallic heating element, where the power transmission signal directly induces eddy currents that result in direct heating of the element.

[0073] The operation of the power transmitter 101 and the power receiver 105 is described below with specific reference to embodiments that generally comply with the Qi or Ki standards (except for any modifications or extensions described (or necessary) herein).

[0074] Many wireless power transfer systems utilize resonant power transfer, where the transmitter coil 103 is part of a resonant circuit, and typically the receiver coil 107 is also part of the resonant circuit. In many embodiments, the resonant circuit is a series resonant circuit, such that the transmitter coil 103 and the receiver coil 107 can be coupled in series with corresponding resonant capacitors. The use of a resonant circuit tends to provide more efficient power transfer.

[0075] Typically, wireless power transfer systems use a power control loop to steer the system towards a suitable operating point. This power control loop varies the amount of power transmitted from the power transmitter to the power receiver. The received power (or voltage or current) can be measured and, depending on the set power value, an error signal can be generated. The power receiver feeds this error signal to the power control function of the power transmitter, which reduces this static error, ideally to zero.

[0076] FIG. 2 shows elements of the power transmitter 101 of FIG. 1 in more detail.

[0077] The power transmitter 101 includes a driver 201 capable of generating a drive signal that is provided to a power transmitter coil 103, which in return generates an electromagnetic power transmission signal, thereby providing power transmission to a power receiver 105. The transmitter coil 103 is part of an output resonant circuit that includes the transmitter coil 103 and a capacitor 203. In this example, the output resonant circuit is a series resonant circuit, although it will be appreciated that in other embodiments the output resonant circuit can be a parallel resonant circuit. It will be appreciated that any suitable resonant circuit may be used, including those that use multiple inductors and / or capacitors.

[0078] The driver 201 generates the current and voltage that are supplied to the output resonant circuit and thus to the transmitter coil 103. The driver 201 is a drive circuit, typically in the form of an inverter, that generates an AC signal from a DC voltage. The output of the driver 201 is typically a switched bridge that generates the drive signal by appropriate switching of the switches of the switched bridge. Figure 3 shows a half-bridge switched bridge / inverter. Switches S1 and S2 are controlled so that they are never closed at the same time. Alternately, S1 is closed while S2 is open and S2 is closed while S1 is open. The switches are opened and closed at a desired frequency, thereby generating an AC signal at the output. Typically, the output of the inverter is connected to the transmitter inductor via a resonant capacitor. Figure 4 shows a full-bridge switched bridge / inverter. Switches S1 and S2 are controlled so that they are never closed at the same time. Switches S3 and S4 are controlled so that they are never closed at the same time. Alternately, switches S1 and S4 are closed while S2 and S3 are open, and switches S2 and S3 are closed while S1 and S4 are open, thereby producing a square wave signal at the output. The switches are opened and closed at the desired frequency.

[0079] The power transmitter 101 further includes a power transmitter controller 205 configured to control the operation of the power transmitter 101 according to a desired operating principle. In particular, the power transmitter 101 may include many of the functions required to perform power control according to the Qi or Ki standards.

[0080] The power transmitter controller 205 is particularly configured to control the generation of the drive signal by the driver 201 and is in particular able to control the power level of the drive signal and thus the level of the generated power transmission signal. The power transmitter controller 205 comprises a power loop controller that controls the power level of the power transmission signal in response to power control messages received from the power receiver 105 during the power transfer phase.

[0081] FIG. 5 illustrates some example elements of the power receiver 105.

[0082] In this example, the receiver coil 107 is coupled to the power receiver controller 501 via a capacitor 503 that forms an input resonant circuit with the receiver coil 107. Thus, the power transfer may be a resonant power transfer between the resonant circuits. In other embodiments, only one or neither of the power receiver and power transmitter may utilize a resonant circuit for power transfer.

[0083] The power receiver controller 501 couples the receiver coil 107 to the load 505 via a switch 507. The power receiver controller 501 includes a power control path that converts the power extracted by the receiver coil 107 to a supply suitable for the load 505. In some embodiments, the power receiver controller 501 can provide a direct power path that simply connects the input resonant circuit to the switch 507 or the load 505, i.e., the power path of the power receiver controller 501 can be implemented simply by two wires. In other embodiments, the power path can include, for example, a rectifier and possibly a smoothing capacitor to provide a DC voltage. In still other embodiments, the power path can include more complex functions such as, for example, a voltage control circuit, an impedance matching circuit, a current control circuit, etc. Similarly, it will be appreciated that the switch 507 may only be present in some embodiments, and in some embodiments the load 505 can be permanently coupled to the input resonant circuit.

[0084] Additionally, the power receiver controller 501 may include various power receiver controller functions required to perform power transfer, particularly functions required to perform power transfer according to the Qi or Ki standards.

[0085] The power receiver 105 is configured to transmit data to the power transmitter 101. Such data may include, among other things, a power control loop error message used to implement a feedback power loop for controlling the power level of the power transmission signal during power transmission, as known to those skilled in the art. The power receiver is capable, in many embodiments, of transmitting a variety of different messages that serve different purposes, as known to those skilled in the art. For example, a variety of different messages, such as those specified in the Qi standard, may be transmitted. A message may include one or more data bits / symbols.

[0086] The power receiver is configured to transmit a message to the power transmitter using load modulation.

[0087] As is well known to those skilled in the art, for load modulation, changes in the load of the power transmission signal can be introduced by the power receiver, where the changes depend on the data values ​​to be transmitted, and these changes can be detected by the power transmitter to decode the data from the power receiver.

[0088] Load modulation can be used as a method for the power receiver to communicate control messages or other data to the power transmitter, for example according to the Qi wireless power standard.

[0089] Typically, there are two main ways to perform load modulation: either directly modifying the resistive load / power extraction of the input circuit, and / or detuning the resonance of the input circuit, for example by modifying the reactive load of the input circuit (typically by switching a capacitor in / out in line with the data to be transmitted). A similar approach can be used by the power receiver to load modulate the power transmission signal.

[0090] Correspondingly, in the power transmitter, detection approaches such as those known for the Qi standard system can be used to detect load variations. For example, direct measurement of the power level or current amplitude of the drive signal can be used as an indication of the load and thus the load modulation variations introduced by the power receiver.

[0091] The power receiver 105 comprises a data transmitter 509 configured to transmit data to the power transmitter 101 by load modulating the power transmission signal. For example, the data transmitter 509 can be configured to switch in / out a communication capacitor (or other impedance), e.g., in parallel with the power receiver controller 501 or the resonant capacitor 503, thereby varying the resonant frequency and the loading of the power transmission signal.

[0092] The data transmitter 509 can be coupled to the power receiver controller 501 and can be configured to receive data from the power receiver controller 501 for transmission to the power transmitter.

[0093] For example, the data transmitter 509 may receive power error control data from the power receiver controller 501 and transmit corresponding power error control messages to the power transmitter 101 using load modulation. In operation, the system is typically configured to control the drive signal such that the power transmission signal achieves appropriate operating parameters / characteristics and the power transmission operates at an appropriate operating point. To do so, the power transmitter is configured to control parameters of the drive signal using a power control loop in which the power characteristics of the power transmission signal / drive signal are controlled in response to power control error messages received from the power receiver.

[0094] The data transmitter 509 is configured to transmit data symbols by load modulating the power transmission signal with a sequence of modulation load values ​​corresponding to the chip sequence. The data transmitter 509 can transmit the data symbols using an approach that modulates the data symbols using the chip sequence, similar to, for example, direct sequence spread spectrum (DSSS). The data symbols / bits are modulated by a bit sequence (which is typically pseudorandom), also called a spreading sequence. Each spreading sequence bit, known as a chip, has a much shorter duration (larger bandwidth) than the original message bit.

[0095] In this approach, load modulation is used, but each symbol is represented by a chip sequence containing multiple chips, typically a sequence containing 10 to 1023 chips. Thus, rather than simply varying the load according to each symbol or bit, the data transmitter 509 is configured to transmit a given symbol (typically a bit) by a series of load changes and variations, where the changes and variations are different for each symbol. Specifically, a chip sequence can be defined for each symbol, and when transmitting a given symbol, the data transmitter 509 can read the chip sequence for that particular symbol and proceed to load modulate the power transmission signal according to the chip sequence for that symbol.

[0096] Similarly, as will be described in more detail below, the power transmitter can detect load modulation by considering the entire chip sequence, and in particular can attempt to determine the received symbol as the symbol whose measured load variation chip pattern most closely matches the chip sequence pattern of that symbol.

[0097] Such an approach in particular allows the modulation depth, i.e. the magnitude of the load fluctuations, to be significantly reduced, which may, for example, reduce electromagnetic noise and interference, reduce acoustic noise, and reduce spurious vibrations. It may also result in many embodiments in an improved signal-to-noise ratio, resulting in, for example, significantly improved, more reliable communications, often with a lower bit error rate. Thus, an overall improved power transfer may be achieved.

[0098] Traditionally, such communications use binary sequences, such as the exemplary chip sequences shown in FIG. 6, which shows some examples of two possible chip sequences. Each chip sequence consists of a sequence of chips. Traditionally, the set of chip values ​​is two, corresponding to a binary chip sequence. However, as will be described in more detail below, current approaches may in many embodiments use at least one modulation chip sequence having non-binary chip levels. In many embodiments, the chips may have one of three different chip levels, and the chip sequence includes three different chip levels. The following description focuses on such an example, but it will be understood that in other embodiments, a binary chip sequence may be used, or indeed a chip sequence having four or more possible levels may be used.

[0099] The symbol time is divided into multiple chip intervals in the described approach, and the chip sequences of chips are different for different data symbols. Typically, each sequence contains at least 10 chips, and often significantly more. In many embodiments, each chip sequence is 2 N −1, where N is typically an integer greater than or equal to 4.

[0100] Each possible data symbol value can be linked / represented by one modulation chip sequence. Thus, for a given data symbol value to be transmitted, a corresponding / linked modulation chip sequence is determined and modulated onto the power transmission signal by load modulation. For example, if only two data symbols are possible, i.e., binary communication is implemented, the set of chip sequences can include only two chip sequences.

[0101] In many embodiments, one or more chip sequences can be represented by their relationship to another chip sequence. For example, in the case of binary communication, the data transmitter 509 can store a single modulated chip sequence that corresponds to one of the binary data values. The chip sequence for the other binary data value can be given as the inverse of the stored bit sequence, and thus can be represented by the same stored bit sequence. Thus, in many cases, a set of chip sequences utilizes complementary inverse chip sequences for pairs of data symbols, and thus only half of the chip sequences used are typically explicitly stored / determined in the data transmitter 509, while the remaining chip sequences are automatically and implicitly stored / determined as their inverses.

[0102] Thus, in some embodiments, the modulation chip sequence may include an inverse chip sequence. Equivalently, the same modulation chip sequence may be considered to represent two data symbol values, specifically two binary data symbol values.

[0103] A modulation chip sequence is selected from the set of modulation chip sequences for a given data symbol to be transmitted, in this example, the data transmitter 509 provides a set of modulation chip sequences, each chip sequence being linked to a data symbol value. Typically, the set of modulation chip sequences includes one modulation chip sequence for each possible data symbol value. For example, if binary communication is used, the first set of chip sequences may include only two chip sequences. It will be appreciated that the data transmitter 509 may store the chip sequences in any suitable form and need not store a complete sequence for each possible data symbol. For example, a given modulation chip sequence may be multiplied by a binary symbol value represented by values ​​1, -1. At the receiving end, i.e., the power transmitter, a data value may be determined by correlation with the given modulation chip sequence, and the determination of the corresponding binary data value depends on whether this is a positive or negative correlation.

[0104] Thus, in many embodiments, binary communication may be used, where only two data symbol values ​​are possible (corresponding to a "0" or "1" bit value). In such cases, one bit value may be represented by a given chip sequence, and the other bit value may be associated with the inverse bit sequence, i.e., the bit sequence resulting from changing each chip value to its opposite value. Thus, the two bit sequences are typically complementary, one resulting from multiplying the other by -1 (chip values ​​are represented by +1 and -1).

[0105] A particular advantage in such a case is that demodulation is particularly easy since a single correlation can be used to distinguish between bit values, since the magnitude of the correlation is the same for the chip sequence, but the sign of the correlation value is opposite.

[0106] It will be appreciated that it is equivalent to consider a data symbol represented by an inverse modulation chip sequence to be represented by one chip sequence or two chip sequences. It will be appreciated that such a binary approach, where two inverse chip sequences are used, is equivalent to considering two possible binary values ​​as modulated by the same chip sequence, but with data symbols having opposite data values ​​(e.g., +1 and -1).

[0107] When the power receiver 105 wishes to transmit a data symbol, that value is provided from the power receiver controller 501 to the data transmitter 509, which proceeds to determine the chip sequence that is linked to the data symbol value to be transmitted.

[0108] The data transmitter 509 is configured to modulate a chip sequence onto the power transmission signal, specifically, to switch a modulated load on and off along the chip, i.e., to change the load according to the modulated load value of the chip sequence.

[0109] The chip sequences in a set are typically (but not necessarily) of the same length. In the case of binary communication, the set of chip sequences may contain only a single modulated chip sequence (i.e., equivalent to two inverted chip sequences), as described above. The following description focuses on such binary communication, but it will be understood that the invention is not limited to only binary communication.

[0110] Load modulation can provide advantageous operation in many systems and applications, and tends to provide reliable, low-complexity operation suitable for power transmission systems in which a power transmission signal is generated for the purpose of transmitting power. Reusing the power transmission signal as a communications carrier typically reduces complexity and requires less circuitry, thereby reducing cost. The Qi standard was originally implemented using unidirectional communication from the power receiver to the power transmitter by using load modulation with a modulation symbol shape that allows easy distinction between binary data values.

[0111] However, load modulation, as used, for example, in the Qi system, may also have some associated drawbacks, which may relate to issues such as electromagnetic compatibility, communication quality (bit error rate), and audible noise.

[0112] Load modulation can generate additional components in the electromagnetic spectrum, causing additional electromagnetic interference and electrical noise. Thus, in contrast to typical conventional communication systems, where noise and interference are unrelated or independent noise caused by other noise or interference sources, load modulation in power transmission systems tends to result in a significant amount of self-interference. In particular, the power transmission path contains substantial inductances and resonances that cause load fluctuations that result in vibrations and other interference components. Thus, in contrast to conventional systems, interference tends to include components that are correlated to the actual modulation, rather than independent or random noise and interference.

[0113] It has also been found that in many cases, the electromagnetic field changes caused by load modulation can induce mechanical forces and movements that result in audible noise. It has also been found that strong load modulation can disturb the energy balance in wireless power systems and result in spurious oscillations in the communication carrier spectrum. In the presence of spurious oscillations, wireless power transmitters are often unable to properly demodulate the signal and must therefore interrupt the power supply to maintain safe operation.

[0114] Therefore, there are several challenges in communication in a wireless power transmission system.

[0115] This problem tends to get worse for higher power transmission levels. Indeed, as the power level of the power transmission signal increases, the load change due to the load modulation is typically required to increase as well. Typically, the load modulation is required to be a suitable percentage of the power level of the power transmission signal, or the maximum power level. For example, the load modulation caused by the load modulation may be required to have a magnitude of, for example, about 1% or more of the typical load of the power receiver (i.e., the load change of the receiver coil caused by the load modulation would be required to be 1% or more of the total load of the receiver coil 107). Qi was originally introduced for low power applications, less than about 5W. At such low power levels, the impact of the drawbacks of load modulation are relatively manageable or not very significant. However, the maximum power level of Qi has now been increased to a maximum of 15W, and work is underway to further increase this to a maximum level of 45W. However, at such power levels, the drawbacks mentioned above tend to become more pronounced, and these may be a major obstacle to further development of the Qi standard.

[0116] Although chip sequence-based load modulation communication offers great advantages, in particular allowing the reduction of the modulation depth of the load modulation, current approaches tend not to provide ideal performance. Indeed, in some cases, reducing the modulation depth may reduce detection accuracy and increase the bit error rate. Interference, specifically self-interference of the load modulation, may result in data symbols not being detected accurately. In some cases, correlation performed in the data receiver may not be detected correctly due to interference. For example, FIG. 7 shows an example of a correlator output between the received load sequence and the modulation chip sequence used to modulate the power transmission signal. The correlation peak is reduced by interference and noise, and the example peak 701 is not detected accurately.

[0117] Such issues and other problems can be addressed and mitigated in many scenarios by the approach used by the wireless power transfer systems of FIGS. 1, 2 and 5.

[0118] In this approach, a modulation chip sequence (in many embodiments having three or more levels) is generated by combining a first and a second binary chip sequence. The data symbols, specifically bits, to be transmitted are then encoded and typically multiplied by this (often three-level (or more)) modulation chip sequence. The resulting sequence is then modulated onto a power transmission signal.

[0119] In this approach, data symbols are then encoded using at least one modulation chip sequence that is a combination of a first binary chip sequence and a second binary chip sequence, and in many embodiments has at least three different chip values, with each data symbol being associated with a different modulation chip sequence and thus a different first and / or second binary sequence.

[0120] In the data receiving function of the power transmitter, the received loading sequence is not directly correlated with the (e.g., three-level) modulating chip sequence, but rather, two correlations are performed, i.e., with the first chip sequence and the second chip sequence, respectively, and the two resulting correlation values ​​are then combined into a combined correlation value, e.g., by multiplying the two correlation values, and the data symbols are detected based on the resulting combined correlation value.

[0121] This approach is explained in more detail with reference to FIGS.

[0122] 8 shows elements of a data transmitter 509. The data transmitter 509 in this example comprises a first sequence source 801 and a second sequence source 803. The first and second sequence sources 801, 803 each provide a binary chip sequence to a combiner 805, which combines the binary sequences into a modulated chip sequence. In many embodiments, the modulated chip sequence is generated as a three-level modulated chip sequence.

[0123] The first and second binary chip sequences are in many embodiments selected to be the same length, i.e., to contain the same number of chips. Furthermore, the combining is typically performed on a chip-by-chip basis, such that the combined modulated chip sequence has the same length / number of chips as the original chip sequences.

[0124] The length of the chip sequences, as previously mentioned, often includes at least 10 chips, and can often be significantly longer. In many embodiments, each chip sequence is 2 N −1, where N is typically an integer greater than or equal to 4.

[0125] The first and second binary chip sequences are typically selected to provide improved detection and communication characteristics by being selected to have a relatively high cross-correlation when the binary sequences are aligned in time / sequence, i.e., for a given offset, typically zero, but low cross-correlation values ​​when they are not aligned, i.e., for other time / sequence offsets.

[0126] The combination is further such that the correlation value for the modulation chip sequence maintains a relatively high cross-correlation with at least one, and typically both, of the first and second binary chip sequences when the sequences are aligned with the modulation chip sequence, but has a relatively low cross-correlation when they are not aligned.

[0127] In particular, the first and second binary chip sequences and combinations are designed such that a cross-correlation between the first and / or second binary sequences and the modulation chip sequence is greater than or equal to two-thirds the length of the first and / or second binary sequences when the first binary sequence and the modulation chip sequence are aligned, and is less than or equal to one-third the length of the first and / or second binary sequences when they are not aligned.

[0128] For example, the first sequence source 801 may be a polynomial x , which includes a set of 31 chips that can be expressed as -1 and 1. 5 +x 2 At the same time, the second sequence source 803 may provide a first binary chip sequence of degree 5 based on +1. For example, the second sequence source 803 may provide another polynomial x that includes another set of 31 chips that can be expressed as -1 and 1. 5 +x 4 +x 3 +x 2 A second binary sequence of order 5 using +1 can be generated. The autocorrelation and cross-correlation functions of these sequences are shown in FIG.

[0129] The combining by combiner 805 can use different approaches in different embodiments to generate a three-level (or higher) modulated chip sequence. Typically, chip-by-chip combining is performed.

[0130] As a specific example, the first and second binary chip sequences may be represented by values ​​−1 and 1, and the combination may follow the following rules for generating a combined modulated chip sequence, where the chips are represented by three possible values ​​(−1, 0, 1): If both binary sequences have chip values ​​of 1 in the same positions, then the resulting modulated chip sequence is set to a value of 1 in the corresponding positions. If both binary sequences have a chip value of -1 in the same position, then the resulting modulated chip sequence is set to a value of -1 in the corresponding position. If both sequences have different values ​​(-1 and 1) in the same position, the resulting modulated chip sequence is set to a value of 0.

[0131] By applying these rules to the first and second binary chip sequences, a three-state modulated chip sequence is obtained. Moreover, the resulting sequence is strongly correlated with both the first and second binary chip sequences. FIG. 11 shows the cross-correlation between each of the first and second binary chip sequences and the resulting modulated chip sequence. FIG. 11 further shows the result of multiplying two individual cross-correlations. As can be seen, the correlation peaks are clearer and more clearly determined in the multiplied result. In particular, this reflects that the probabilistic maxima (minima) are not aligned with respect to the individual cross-correlation functions (between the modulated sequence and the first or second binary chip sequence). Thus, the multiplication of the correlation results allows for improved detection of the correlation peaks.

[0132] The modulated chip sequence is provided to a modulator 807, which is further coupled to a data source 809. The data source provides the data symbols to be transmitted, and the modulator generates a corresponding chip sequence and controls the modulation of the chip sequence onto the power transmission signal.

[0133] In a particular example, the data symbols are binary data symbols represented by values ​​of -1 and 1, and the chip sequence to be modulated onto the power transmission signal can be generated by multiplying the modulation chip sequence (represented by (-1,0,1) levels / values) with the data symbol value. In other embodiments, other approaches can be used. For example, for each data symbol value, the stored modulation chip sequence (generated as a combination of two binary sequences) linked to that data symbol is read out and modulated onto the power transmission signal.

[0134] In this example, the chip sequence is modulated onto the power transmission signal by changing the modulation capacitance 811 of the power transmitter input resonant circuit. In this example, for example, a capacitor can be switched in / out of the resonant circuit depending on the chip value. It will be appreciated that the modulated chip sequence in many embodiments includes three (or more) levels, so that the load variation for a given chip can be represented by three (or more) load variations. Often, the modulator 807 can switch the capacitance between three different levels (e.g., using two different modulation capacitors and two switches). In some embodiments, a different modulation for each chip is used, in which case the modulation load varies within the chip depending on the chip value, and thus more values ​​can be represented, for example, using simple binary switching of the load / modulation capacitor 811. Such approaches are described in more detail below.

[0135] Then, the power receiver transmits data symbols to the power transmitter by load modulating the power transmission signal, where each data symbol is modulated by a sequence of modulation load values ​​corresponding to a chip sequence of the set of modulation chip sequences, where the modulation chip sequence is a combination of the first binary chip sequence and the second binary chip sequence and has at least three different chip values.

[0136] While in the example of FIG. 8 the modulation chip sequences are dynamically generated, it will be appreciated that in many embodiments the modulation chip sequences can be predetermined and, for example, stored in the data transmitter 509, and the appropriate modulation chip sequence for a given data symbol can be retrieved when that data symbol is to be transmitted.

[0137] FIG. 9 illustrates elements of a power transmitter data receiver 207 according to some exemplary embodiments of the present invention.

[0138] The data receiver 207 comprises a load meter 901 configured to measure the loading of the power transmission signal to determine a measured load value of the power transmission signal. The measured load value may be indicative of the loading of the power transmission signal by the power receiver and thus the modulation load applied to the power transmission signal by the power receiver 105.

[0139] The load measurement device 901 is coupled to a chip determination circuit 903 configured to determine a received chip sequence from a measured load value. The received chip sequence can specifically be a sequence of binary chip values ​​corresponding to estimated chip values ​​derived from the load measurements. The received chip sequence can in some embodiments be soft decision values ​​indicating not only the chip data values ​​but also the reliability of the chip data values. Thus, the received chip sequence is determined from a load variation determined by measuring the load of the power transmission signal.

[0140] The chip decision circuit 903 is coupled to first and second correlators 905, 907 which are fed with the received chip sequence from the chip decision circuit 903. The first correlator 905 is coupled to a first correlation chip sequence source 909 which feeds a first binary sequence to the first correlator 905. Similarly, the second correlator 907 is coupled to a second correlation chip sequence source 911 which feeds a second binary sequence to the second correlator 907. The first and second binary sequences used by the data receiver 207 and the correlators 905, 907 are the same as the first and second binary sequences used by the data transmitter 509 of the power receiver, i.e. their combination forms the modulated chip sequence. Thus, the data receiver 207 stores local replicas of the first and second binary sequences and correlates both of these with the received chip sequence to generate the first and second correlation values, respectively. Thus, the data receiver 207 generates first and second correlation values ​​corresponding to the correlation between the received chip sequence and the two binary sequences.

[0141] The correlators 905, 907 are coupled to a combiner 915 to which the first and second correlation values ​​are supplied. The combiner 915 is configured to generate a combined correlation value as a function of the first and second correlation values. This function may in particular be a monotonically increasing function of both the first and second correlation values. The function may be linear or possibly non-linear with respect to the first and / or second correlation values. In many embodiments, the combiner is configured to combine the two partial correlation values ​​from the first and second correlators 905, 907 by multiplying them together.

[0142] The combiner 915 is coupled to a detector 917 configured to determine a received data symbol value from the combined correlation values.

[0143] The detector 917 is configured to determine the data symbols received from the power receiver in response to a combined correlation value resulting from correlation with the stored first and second binary chip sequences (at least one of which is different for different symbols). Specifically, in some embodiments, the load detector 917 can perform a correlation operation for all possible data symbols by selecting the first and second binary chip sequences for each data symbol and determining the corresponding combined correlation value. In cases such as the described binary case where some sequences are inverse to each other, only one combined correlation value can be determined, with the sign of this value reflecting which of the two possible inverse modulation chip sequences was most likely to have been received (and therefore which binary value was most likely to have been received).

[0144] The detector 917 may then determine the data symbol as being linked to the first and second binary chip sequences with which the associated joint correlation value is high enough to exceed a given threshold. The threshold may in many embodiments be an adaptive threshold, e.g., the threshold may be set depending on the correlation value with other symbols. As a specific example, the threshold may be set as the value of the next highest correlation value (e.g., a minimum threshold is applied), so that the data symbol is selected as the data symbol with the highest correlation value (e.g., exceeding the minimum threshold).

[0145] Thus, the power receiver can transmit data to the power transmitter using load modulation with a relatively long chip sequence for each data symbol, and the power transmitter can be configured to receive this communication. The communication is based on using a modulation chip sequence for a given data symbol that is a combination of two binary sequences. The data receiver 207 is configured to determine the received symbol by a combination of two correlations with the two binary sequences, rather than directly correlating with the modulation chip sequence.

[0146] This approach can provide, in many embodiments, significantly improved communication and operation. In particular, significantly improved communication performance and reliability, in particular the symbol signal to noise ratio can be significantly increased. This approach is particularly advantageous in dealing with self-interference, where the interference is correlated with the load modulation itself. This approach allows the modulation depth, specifically the modulation load variation relative to the power transmission signal level / power transmission level, to be significantly reduced. This can reduce and mitigate many of the drawbacks of using load modulation, for example reducing electromagnetic interference, reducing electrical noise, reducing mechanical noise, and preventing or mitigating spurious vibrations.

[0147] In some embodiments, each chip can be represented by a constant modulation level, specifically a constant modulation load. In such embodiments, the modulation load changes only from chip to chip. However, in some embodiments, each chip can be modulated / represented as a difference or load transition parameter. For example, in many embodiments, a first chip value (e.g., -1) can be represented by a chip with a modulation load change in a first direction (e.g., an increase or decrease in load), a second chip value (e.g., +1) can be represented by a chip with a modulation load change in a second direction (e.g., the increase or decrease in load is the opposite of the transition of the first chip value), and a third chip value (e.g., 0) can be represented by no modulation load transition occurring during the chip interval.

[0148] Such an approach can facilitate and / or improve the determination of the received chip value. For example, using a constant modulation chip level approach, the chip value can be detected by comparing the measured load value to a threshold. For example, the load measurer 901 can be configured to measure one load per chip value, i.e., the load measurement can be a load measurement sample generated at one sample per chip.

[0149] For example, the load value (e.g., current and / or power) of the drive signal can be measured and sampled at time intervals corresponding to the chip intervals during the time that a message is (expected to) be received from the power receiver, and the received chip sequence is thus generated from the sampling of the output circuit's signal.

[0150] However, typically, the load variations caused by load modulation are relatively small, which makes it difficult to accurately detect the chip value. Furthermore, since certain operating conditions tend to vary significantly, a fixed, predetermined threshold is typically not ideal, or even feasible in some cases. Rather, an appropriate threshold can be determined based on the signal conditions, and in particular, the threshold can be derived to correspond to an average modulation load level.

[0151] Figure 12 shows an example of how the power transfer signal is load modulated by the chips of the chip sequence. In this example, the modulation is synchronized to the power transfer signal at a rate of one chip per two power signal cycles. The arrows in Figure 12 indicate the times when the load of the power transfer signal is measured / sampled. The sampling is synchronized with the power transfer signal, producing one sample for each chip.

[0152] To determine the (binary) chip value, the sampled load value is compared to the average level 1201. In a specific example, the load of the power transmission signal is determined as the peak cycle value of the measured signal (which can be specifically the current, voltage, phase or power of the power transmission signal), and the sampling is synchronized with the peak of the power transmission signal. Furthermore, the average level 1201 of the peak cycle value is first determined, and then the chip value is determined based on whether the measured sample value is above or below the average level 1201. In the case of a three-level modulated chip sequence, the load value can be divided into three intervals using two thresholds (so, for example, a -1 level is determined if the measurement value is below the lowest threshold, a +1 level is determined if the measurement value is above the highest threshold, and 0 is determined if the measurement value is between the thresholds).

[0153] However, while such an approach may provide a very useful communication link in many circumstances, it may be sensitive to noise, errors, etc., which may sometimes result in undesirably high bit error rates. In particular, it is important to determine the average level with adequate accuracy in the approach described with reference to Fig. 12. Deviations and errors may affect not only the individual chip values, but also the correlation results used to determine the data symbols themselves. This may result in reduced peak values, strong side lobes to the peaks, or even peaks with opposite signs, etc. This may therefore result in significant bit errors.

[0154] In some embodiments, chip-level modulation may be based on load transitions within a chip duration. This may provide improved performance and / or facilitated operation in many scenarios. Rather than requiring accurate average level determination, this approach may effectively embed a reference level into the modulation format itself. It may further provide a greater number of chip modulation levels, including providing efficient support for three (or, for example, four) level modulation chip sequences.

[0155] In this approach, each chip is divided into two (or more) load time intervals that may have different modulation loads. Thus, each chip has at least two load time intervals with potentially different modulation loads, and therefore the chip can be represented by at least two different modulation loads, specifically each chip is represented by a pattern of load modulation loads that may differ in at least two load time intervals for at least some chip values. Furthermore, the pattern of different modulation loads is specific to a given chip value. Thus, different chip values ​​are linked to different patterns of load modulation. In this approach, instead of considering the entire chip time interval to be one (constant) load time interval, the chip time interval is divided into multiple load time intervals (with the modulation load in the example being constant among them).

[0156] In some cases, the system may use a binary modulation load, i.e., the modulation load applied by the power receiver may have one of two possible load values. Such an approach is advantageous by allowing for low complexity implementation and easy operation. It typically facilitates load modulation operation for both transmit and receive functions, which tends to lead to efficient performance and reliable communication. It further allows more chip values ​​(e.g., three or four values) to be effectively represented while using only a binary modulation load.

[0157] As an example, the data transmitter 509 can typically control the switching of modulation load components, such as capacitors or resistors, and therefore can apply different modulation loads.

[0158] Thus, in many embodiments, binary load modulation can be used while allowing for non-binary chip values. In many embodiments, a chip time interval can be divided into two load time intervals, with one binary load value applied in one load time interval and the other load value applied in the other load time interval. The two binary chip values ​​can then be determined to correspond to two possible patterns / orders of the two modulation loads assigned to the two load time intervals. Specifically, in some embodiments, each transmitted chip can be divided into two halves to have opposite modulation loads in each of those halves, with these orders (i.e., which modulation load is assigned to the first half) depending on the binary chip value.

[0159] An example of this is shown in Figure 13, where the top signal 1301 shows the chip sequence and chip values, and the middle signal 1303 shows the modulation load value variation. As shown, each chip is divided into two load time intervals, one having, for example, a (higher) modulation load and one having a (lower) modulation load. Whether the first load time interval of a given chip is a high or low modulation load depends on the chip value.

[0160] Specifically, signal 1301 indicates the chips in the sequence, and signal 1303 indicates the modulation load switching by the data transmitter 509, i.e., the modulation load level within the load time interval. In this example, for a "1" chip, the data transmitter 509 switches the modulation load off (or low) in the first half and on (or high) in the second half. Conversely, for a "-1" chip, the data transmitter 509 switches the modulation load on (or high) in the first half and off (or low) in the second half.

[0161] In many embodiments, such binary chip values ​​can be expanded, for example, by including a third chip value represented by a modulation load that does not change over the chip interval (i.e., the modulation load is the same over the two load time intervals). In this way, additional chip values ​​and higher order chip value modulation can be achieved.

[0162] Thus, such an approach not only allows for chip value determination without the need for a precise threshold, but can also efficiently support modulation chip sequences with more than two possible chip values.

[0163] In this approach, the power transmitter is configured to determine the data symbol by considering the relative load variation within the chip. Specifically, the load measurement unit 901 is configured to measure the load of the power transmission signal to determine a measured load value during a load time interval. A measured load value / sample can be determined for each load time interval.

[0164] The chip determination circuit 903 is configured to determine an individual chip value in response to a difference between the measured load values ​​for at least two modulated load time intervals of an individual chip.

[0165] Specifically, the tip determination circuit 903 is configured to determine a difference between two load time intervals, e.g., the load value of a first load time interval can be subtracted from the load value of a second load time interval, and depending on the result, the tip determination circuit 903 can proceed to determine a tip value as a function of the difference.

[0166] In Fig. 13, signal 1305 represents a measurement of the drive signal / power transmission signal. Thus, each chip consists of a loaded time interval with a high signal level (high modulation loading) and a loaded time interval with a low signal level (low modulation loading), the order of which depends on the chip value. In this example, an increasing signal level (the level of the second loaded time interval is higher than that of the first loaded time interval) is decoded as a chip value of "1" and a decreasing signal level (the level of the first loaded time interval is higher than that of the second loaded time interval) is decoded as "-1". Furthermore, if the difference between the signal levels in the two time intervals is below a given (e.g., predefined) threshold, the chip value is set to 0.

[0167] The amplitude / level of the drive signal / power transfer signal in the first half of the chip (first load time interval) can serve as a reference level for measurements made in the second half of the chip (second load time interval), and vice versa. Thus, the reference for individual chip load modulation determination is embedded directly within the modulation format. Thus, chip value determination can be made without the need for average or reference levels to be estimated or determined. Rather, local, intra-chip relative measurements and comparisons can be used to determine chip values.

[0168] The chip values ​​are then used to generate a received chip sequence that is compared to the first and second binary chip sequences.

[0169] This approach can provide substantially improved performance and more reliable data communications.

[0170] In many embodiments, the tip determiner circuit 903 can be configured to determine the tip value as a binary tip value. The tip determiner circuit 903 can be specifically configured to select the binary tip value to correspond to the sign of the difference between the load values / measurements in the load time interval of the tip. For example, if the signal peak sample is higher in the first load time interval than in the second load time interval, the tip value can be determined as "1", while if the signal peak sample is lower in the first load time interval than in the second load time interval, the tip value can be determined as "-1" (or vice versa). In many embodiments, the tip determiner circuit 903 can determine the difference between the load values ​​in the load time interval and set the binary value to correspond to its sign. However, if the absolute difference is below a threshold, the tip value can be determined as "0".

[0171] Such an approach can provide a low-complexity yet accurate determination of the received chip sequence and is suitable for low-complexity correlation. For example, it can enable binary correlation operations with significantly lower complexity and resource requirements, since multiplications can be replaced by simple binary operations (e.g., simple binary XOR operations). In the case of a "0" value, correlation can simply be skipped.

[0172] In some embodiments, the chip determiner circuit 903 can be configured to determine the received chip sequence to include soft-decision chip values. Rather than a simple code value, the generated chip value can also indicate a confidence or confidence level of the chip value.

[0173] For example, in addition to the sign, the magnitude of the difference can be considered. For example, for a given nominal in the absence of noise, a nominal magnitude of the difference can be determined (or a nominal difference can be determined, for example, by averaging / down filtering multiple, typically many, chip differences). The deviation of a particular chip difference relative to this difference can then indicate the probability that the decision is the correct value. However, in most embodiments, the magnitude of the difference simply indicates confidence or reliability: the larger the measured difference, the more likely the sign is correct, i.e., the larger the magnitude of the difference, the more reliable the chip value.

[0174] The correlation with a chip sequence of the set of chip sequences may be performed in response to the soft-decision chip values, specifically, the correlation may be performed using the soft-decision values.

[0175] For example, in some embodiments, the correlation can be performed as a binary exclusive-or operation between the stored binary chip sequence and the received chip sequence formed by the determined difference sign, with the result of each exclusive-or operation being weighted (e.g., multiplied) by the magnitude of the difference (e.g., relative to a nominal difference) prior to summing the results. As another example, the stored chip sequence can be represented by chip values ​​of +1 and -1, and these values ​​can be directly multiplied by the corresponding chip load difference (corresponding to the received chip sequence). The correlation can then be determined by summing the multiplication results.

[0176] While such an approach may require more complex computations, it may provide improved performance in many embodiments and scenarios, and in particular may enable more accurate data symbol detection.

[0177] In many embodiments, the chip determiner 211 is configured to determine the received chip sequence as a binary chip sequence, specifically, to determine the received chip sequence as a binary sequence even if the modulation chip sequence is a sequence of more than two levels / values. The chip determiner 211 can specifically determine the received chip sequence as a binary chip sequence even if the modulation chip sequence is a sequence of more than two levels. For example, even if the modulation chip sequence is represented by three possible levels (-1, 0, 1) for each chip, the chip determiner 211 can be configured to simply determine that the chips of the received chip sequence have binary values ​​(-1, 1). The binary received chip sequence is then fed to a correlator for correlation with the first binary chip sequence and the second binary chip sequence, respectively. In this case, low-complexity correlation and calculations can be performed. Furthermore, this can achieve improved / reliable data symbol detection while maintaining reliable performance.

[0178] In some embodiments, the chip determiner 211 can determine the received chip sequence to have the same values ​​as possible / allowed for the modulated chip sequence. For example, in case of a three-level modulated chip sequence, the received chip sequence can be determined as a three-level modulated chip sequence. For example, the chip determiner 211 can determine the most likely chip value by selecting the closest possible value to the measured value. In such a case, the correlation is still performed with the first and second binary sequences, i.e., the correlation is between the three (or more) levels of the received chip sequence and the two binary sequences. This approach can provide improved performance in some cases and can achieve improved data symbol detection. Furthermore, this can often be achieved with low complexity and low resource usage, since the correlation with the binary sequence can be effectively implemented without the need for explicit multiplications, for example, using simple logic circuit comparison values.

[0179] In some embodiments, the chip determiner 211 may determine the chip value as a soft decision value. Such chip value may include a representation of the likelihood that the detected chip value is correct. An uncertainty index may be taken into account in the correlation, and in particular, a lower uncertainty index may result in a higher weight for that chip relative to the correlation value than for a higher uncertainty index.

[0180] For example, as described above, the chip values ​​of a three-level modulated chip sequence having three levels can be represented by a load change in one direction, a load change in the other direction, or no load change, respectively. The chip determiner 211 can be configured to determine the chip value by determining the difference between the load values ​​in the first and second halves of the chip. If the chip determiner 211 determines the received chip sequence as a binary chip value, the chip value can be set to the sign of the difference. In the case of a three-level received chip sequence, the chip determiner 211 can determine the chip value as the sign unless the absolute value is below a threshold, in which case the chip level can be set to a third value, such as a zero value. In the case of a soft decision chip determiner 211, the chip value can simply be set to the difference value (e.g., normalized to an appropriate reference level).

[0181] In many embodiments, the chip determiner 211 can determine the received chip sequence as a binary received chip sequence. In such a case, a first binary value of the received chip sequence can represent a first chip value of the modulated chip sequence, and a second binary value of the received chip sequence can represent a second chip value of the modulated chip sequence. For a modulated chip sequence having at least three possible values, the chip determiner 211 can be configured to determine the binary value as the first binary value or the second binary value such that the probability of differing is no more than 10%, or only 5%. The determination depends on the noise / interference, and the requirement can be met for symmetric noise and interference. Indeed, in most embodiments, the chip determiner 211 can be configured to determine a binary value for the binary received chip sequence with substantially equal probability for symmetric noise for at least one chip level of the modulated chip sequence.

[0182] In many embodiments, the chip determiner 211 may be configured to perform a symmetric decision between a first chip value and a second chip value for the received chip sequence for at least one chip value of the modulated chip sequence.

[0183] As a particular example, the modulation chip sequence may be configured to use chip values ​​-1, 0, 1, which are load modulated by a modulation load, where the modulation load for value 0 is intermediate between the modulation loads for -1 and +1. The chip determiner 211 may be configured to determine the received chip sequence as a binary sequence having values ​​-1 and +1, respectively. In that case, the binary chip value for a modulation chip sequence chip value of 0 may be determined as -1 or +1 with equal probability.

[0184] As another example, if differential / load transition modulation of chip values ​​is used, the chip determiner 211 may determine the load difference between the first and second time intervals and then determine the chip value as the sign of this difference. For chip values ​​of the modulated chip sequence (0) where no load transitions are introduced, the sign of the difference is random with a 50% variation of either value, and therefore there is a 50% probability that the received chip sequence will be determined as either binary value.

[0185] In many embodiments, the data receiver 207 is configured such that the contribution to the first and / or second correlation value for at least one chip value of the modulation chip sequence is less than 10% (or alternatively less than 5%, or less than 1%) of the contribution for at least one other chip value of the modulation chip sequence. The contribution may be the contribution in the absence of noise or interference, or may be taken as the average contribution, for example, in the presence of symmetric (with respect to the chip value) noise.

[0186] For example, when the binary chip value of the received chip sequence is determined as the first or second binary value with equal probability to one modulation chip sequence chip value (0), the average contribution to the first and second correlations will be zero. In some embodiments, the data receiver 207 can be configured to detect, for example, that a third chip level has been received and explicitly ignore it in the correlation. For example, in the case of a load transition approach, differences having an absolute level below a given threshold can be ignored or set to zero.

[0187] Such an approach can provide improved operation, and typically provide more accurate data detection in the presence of noise. This approach can take advantage of the fact that the correlation for the differential chip sequence combined with the modulation chip sequence may reflect different correlation properties that can be combined to provide an overall improved performance.

[0188] This approach may typically provide improved communication channel immunity to stochastic detection errors (miscorrelation peaks) and improved detectability of signals under severe interference (e.g., spurious oscillations in the system). Figure 14 shows the correlation output for a single correlation of the measured load transition / difference with the entire single chip sequence compared to the correlation value combining the two correlations with the first and second sequences. It can be observed that the ratio of the average correlation peak amplitude to the average output of the correlator is about 16db in the first case and about 36db in the second case. Another example is shown in Figure 15, where noise and interference are further taken into account. As can be seen in this example, the correlation peak around sample 257 is clearly detectable using the approach described above, but without using a simple single correlation.

[0189] The above description has focused on scenarios where the modulation chip sequence is a non-binary sequence where the chips can be one of three or more different levels. However, while such an approach may provide advantageous operation in many embodiments, in some embodiments it is also possible to determine the modulation chip sequence itself as a binary sequence.

[0190] In the above approach, a third level was selected for cases where the first and second binary sequences have different bit values. The third level was determined by the data receiver 207 as a certain binary value with equal probability, thereby reducing the average contribution to the correlation, ideally to zero. However, in some embodiments, the selection of the binary value can be performed at the data transmitter side. For example, the chip values ​​of the chips where the first and second binary sequences have different values ​​can be selected to alternate between being set to values ​​of the first binary sequence and values ​​of the second sequence. In such cases, the contribution of these values ​​to the first and second correlation values ​​can be reduced to typically insignificant values ​​(and possibly even to a zero contribution on average). Furthermore, such an approach can often maintain a balanced influence on the two individual correlations, providing improved detection accuracy.

[0191] It will be appreciated that other approaches for selecting a binary value in the case of different values ​​for the first and second binary values ​​may be used, such as randomly selecting from either sequence, alternating between either sequence, using an index into the sequences to select between either sequence, etc.

[0192] The chip time interval can typically be synchronized with a cycle of the power transmission signal. Similarly, the load time interval can typically be synchronized with a cycle of the power transmission signal. In many embodiments, the system can be configured to synchronize the load modulation communication (particularly the chip time interval and the load time interval) with the power transmission signal / drive signal.

[0193] In many embodiments, the data transmitter 509 can be specifically configured to synchronize the load modulation of the chip sequence and the duty time interval to the power transmission signal. The power transmission signal typically has an operating frequency in the range of 10 kHz to 500 kHz, and for Qi, is often around 100 kHz. The data transmitter 509 can adapt the timing of the chip time interval and the duty time interval to be synchronized to the oscillation and period of the power transmission signal. For example, in many embodiments, the data transmitter 509 can use chip durations / time intervals and / or duty time intervals (durations) that are multiples of the power transmission signal period. Thus, each duty time interval can have a duration that is a multiple of the period of the power transmission signal, i.e., the duration of the duty time interval can be N*T, where N is an integer and T is the duration of the period of the power transmission signal / drive signal.

[0194] In many embodiments, the data transmitter 509 not only synchronizes the duration of the duty time interval to the duration of the period of the power transmission signal, but also aligns the start and / or stop timing of the duty time interval to the timing of the power transmission signal. In particular, the transition times between modulation levels of the duty time interval can be synchronized to occur at the zero crossings of the power transmission signal or, for example, at a fixed offset relative to the zero crossings of the power transmission signal. It will be appreciated that the synchronization can be based on the timing of a signal induced in the receiver coil 107 by the power transmission signal.

[0195] Similarly, the power transmitter may be configured to generate the received chip sequence from samples / measurements of the load of the power transmission signal / drive signal (possibly after matched filtering has been applied).

[0196] The load measurement device 901 can sample signals of the output circuit corresponding to the power transmission signal, specifically the current and / or power of the drive signal, the relative phase between the current and voltage of the drive signal, the current through the transmitter coil 103, etc. The load modulation data receiver 207 can then generate the received chip sequence from the difference between such load measurements at a given sampling time belonging to different load time intervals of a given chip.

[0197] In many embodiments, the load measurer 901 is configured to synchronize sampling to the power transfer signal, and specifically this can be achieved by synchronizing it to the drive signal.

[0198] In many embodiments, the synchronization can be such that, for example, one sample is taken every load time interval (possibly after matched filtering). In particular, if the duration of the load time interval is equal to N times the period of the power transmission signal, the sampling can also be synchronized to be once every N times. Thus, in many embodiments, the synchronization can be such that the sampling rate is equal to the load time interval frequency of the load modulation.

[0199] In some embodiments, sampling can be a two-stage process in which several samples are generated at a higher frequency and then decimated to a given sample rate. For example, for a load time interval duration of 10 times the period of the power transmission signal, the sampler can take one sample per period. The averaging filter can then sum the last 10 samples, i.e. it can be a square window FIR filter that sums (with equal weights) the 10 most recent samples. The output of the sampling is then the sampled output of this filter, specifically the output every 10 periods, consistent with the filter being the sum of 10 periods within a single chip. Thus, sampling at synchronized instants can be effectively achieved by appropriately synchronized decimation at the output of the filter.

[0200] However, in most embodiments, only a single sample / measurement is performed per load time interval. In such situations, the timing of the samples can be synchronized to occur at the peak of the cycle of the signal / parameter being measured for each sample. If the load time interval and the samples are synchronized to the power transfer signal cycle, this can be accomplished by simply sampling / measuring at the center time of the load time interval.

[0201] In many embodiments, the operating frequency of the drive signal and the power transmission signal can be an integer multiple of the sampling rate of the sampling of the signal of the output circuit and / or an integer multiple of the load time interval and chip frequency of the load modulation. The multiple can specifically be 1. Indeed, in many embodiments, the integer multiple is advantageously relatively low to allow for efficient communication and higher data rates. In many embodiments, the integer is advantageously no more than 1, 3, 5, 10 or 20.

[0202] Synchronization of the load modulation to the power transmission signal may, in many practical implementations, allow a reduction in the amount of sampling that the power transmitter must perform, thus allowing an increase in the chip rate and / or bit rate. In the extreme case where the chip frequency is the same as the power transmission signal frequency, the power receiver may vary the load according to the chip sequence every cycle of the power transmission signal, and may vary the load every half cycle of the power transmission signal for two load time intervals. Alternatively, the power receiver may vary the load according to the chip sequence every N cycles of the power signal, reducing the chip frequency by a factor of N.

[0203] Synchronous modulation facilitates modulation detection at the power transmitter side by allowing it to apply synchronous sampling techniques and correlating the detected signal with the post-step modulation sequence. This approach can be significantly easier to implement while typically achieving efficient communication.

[0204] The length of the chip sequence can be selected to suit the particular preferences and requirements of an individual embodiment, and can be selected to provide a suitable compromise between communication reliability and performance (e.g., bit rate), data rate, bandwidth, modulation depth, associated drawbacks, etc. In most embodiments, a length of 8 chips or more and / or 128 chips or less provides suitable and advantageous performance, particularly for wireless power transfer systems such as the Qi system.

[0205] The particular chip sequences and patterns used may depend on the preferences and requirements of individual implementations. Typically, the sequences are selected to provide good correlation properties, specifically, the set of chip sequences is selected to consist of sequences with high autocorrelation and low cross-correlation values. In many embodiments, the chip sequences may be selected as maximum length sequences. For example, in many embodiments, the chip sequences may be selected as maximum length sequences generated from a polynomial, the order of the polynomial being selected by the power receiver according to the desired / selected modulation depth and the desired communication rate. In particular, pseudo-noise sequences developed for and used in direct sequence spread spectrum communication and code division multiple access systems tend to be well suited to the described approach.

[0206] As mentioned above, the set of sequences may include mirror image or inverted chip sequences, i.e., for a given binary chip sequence, the set of chip sequences may also include chip sequences in which all chips have complementary values. For example, if the load values ​​are represented by 1 and -1, the set of chip sequences may also include, for each chip sequence, a chip sequence resulting from multiplication by -1 (equivalent to a swap between 0 and 1 for all chips for chip sequences represented by values ​​of 1 and 0). Indeed, in some embodiments, the set of chip sequences may include only a chip sequence and its inverted chip sequence. It will be appreciated that in such embodiments, only a single representation needs to be stored to represent the pair of chip sequence and inverted chip sequence.

[0207] Such an approach is particularly suitable for many applications and may result in good performance and low complexity. For example, a single correlation between the received chip sequence and the reference chip sequence can provide correlation values ​​for both the reference chip sequence and the inverse chip sequence. Indeed, in the absence of noise, the correlation value of one of the reference chip sequences is +1, and the correlation value of the inverse reference chip sequence is -1. Thus, a single correlation value applicable to two symbol values / sequences can be determined and can be directly used to select between the two symbols.

[0208] It will be appreciated that the approach of using an inverted reference chip sequence can be considered equivalent to multiplying the binary data symbols with a single reference chip sequence (using values ​​of 1 and -1 to represent binary values).

[0209] In the above example for load transition modulation, each chip is divided into two load time intervals with different modulation loads. This allows for efficient operation with improved performance. In particular, it allows for low complexity and low resource usage while still providing significantly improved performance in many embodiments.

[0210] However, in some embodiments, each chip may be divided into three or more duty time intervals with different modulation duty.

[0211] For example, in some embodiments, each chip can be divided into three load time intervals, where the load level in the first load time interval is a reference level. The load in the second load time interval is higher than the reference level for the first binary chip value, and the load in the third load time interval is lower than the reference level. For other binary values, the load is lower than the reference level in the second load time interval and higher than the reference level in the third load time interval. Then, the chip determination circuit 903 can determine a chip value (e.g., binary) by detecting whether there are two load changes and in which direction they are changing in each load time interval. Such an approach allows for improved chip value determination in different scenarios. For example, it can reduce sensitivity to the direction of the load change.

[0212] In many embodiments, each duty time interval can have the duration of a single cycle of the power transfer signal, which is advantageous in many embodiments because it reduces the minimum time required per chip, thereby allowing higher data rates or, for example, longer chip sequences to be used.

[0213] However, in some embodiments, each load time interval can have a duration of multiple cycles of the power transmission signal. In some embodiments, each load time interval can have a duration of 2, 3, 5, 10 or more cycles of the power transmission signal. This is advantageous in many scenarios, for example, by facilitating or improving the measurement process. For example, while synchronization to the sample peak value of the power transmission signal / drive signal is relatively easy to achieve, synchronization between the set of cycles corresponding to each load time interval and the chip can be difficult. For example, the alignment between the cycle peaks and the load time intervals of the individual chips can be disrupted, resulting in the power transmitter assigning the load measurements to the wrong load time interval / chip.

[0214] For example, in many embodiments, the determination of the next power transfer signal cycle can be determined by detecting zero crossings of the power transfer signal. However, due to noise, etc., false additional zero crossings may be detected or zero crossings may not be found. If each load time interval has a duration of one power transfer signal cycle, this may result in misalignment between the cycle / measurement and the load time intervals of the individual chips, resulting in detection errors.

[0215] However, by having a duty time interval that is the duration of multiple cycles of the power transfer signal, such errors are mitigated.

[0216] A modulated load may be a load component of a power transmission signal / drive signal load that is caused / dependent / varying due to load modulation.

[0217] It will be appreciated that for clarity, the above description has described embodiments of the invention with reference to different functional circuits, units and processors. However, it will be apparent that any suitable distribution of functionality between different functional circuits, units or processors may be used without departing from the invention. For example, functionality shown to be performed by separate processors or controllers may be performed by the same processor or controller. Thus, references to specific functional units or circuits should not be regarded as indicative of a strict logical or physical structure or organization, but merely as references to suitable means for providing the described functionality.

[0218] The invention may be implemented in any suitable form including hardware, software, firmware or any combination of these. The invention may optionally be implemented at least partly as computer software running on one or more data processors and / or digital signal processors. The elements and components of the embodiments of the invention may be physically, functionally and logically implemented in any suitable way. Indeed functionality may be implemented in a single unit, in multiple units or as part of other functional units. Thus, the invention may be implemented in a single unit or may be physically and functionally distributed between different units, circuits and processors.

[0219] Although the present invention has been described in relation to several embodiments, it is not intended to be limited to the specific form set forth herein. Rather, the scope of the present invention is limited only by the appended claims. Moreover, although certain features may appear to be described in relation to a particular embodiment, those skilled in the art will recognize that various features of the described embodiments may be combined in accordance with the present invention. In the claims, the term "comprising" does not exclude the presence of other elements or steps.

[0220] Furthermore, although individually recited, a plurality of means, elements, circuits or method steps may be implemented by, for example, a single circuit, unit or processor. Moreover, although individual features may be included in different claims, these may in some cases be advantageously combined and the inclusion in different claims does not imply that the combination of features is not feasible and / or advantageous. Moreover, the inclusion of a feature in one category of claims does not imply a limitation to this category, but rather indicates that the feature is equally applicable to other claim categories, as appropriate. The inclusion of a feature in a dependent claim of an independent claim does not imply a limitation to this independent claim, but rather indicates that the feature is equally applicable to other independent claims, as appropriate. Moreover, the order of features in the claims does not imply a particular order in which the features must be operated, and in particular the order of individual steps in a method claim does not imply that the steps must be performed in this order. Rather, the steps may be performed in any suitable order. Moreover, a reference to the singular does not exclude a plurality. Thus, references to "a", "an", "first", "second", etc. do not exclude a plurality. Reference signs in the claims are provided merely as a clarifying example and shall not be construed as limiting the scope of the claims in any way.

Claims

1. A power transmitter for wirelessly supplying power to a power receiver via an electromagnetic power transmission signal, The output circuit includes a transmitter coil configured to generate the power transmission signal in response to a drive signal applied to the output circuit, A driver configured to generate the aforementioned drive signal, A data receiver configured to receive load-modulated data symbols modulated by one modulation chip sequence from a set of modulation chip sequences, wherein each modulation chip sequence in the set of modulation chip sequences represents one data symbol, and at least one first modulation chip sequence in the set of modulation chip sequences is a combination of a first binary chip sequence and a second binary chip sequence, wherein the first binary chip sequence and the second binary chip sequence are different chip sequences. The data receiver has, A load measuring device configured to measure the load of the power transmission signal and generate a measured load value, A chip determiner configured to determine the receiving chip sequence from the measured load value, A first correlator configured to generate a first correlation value by correlating the received chip sequence with the first binary chip sequence, A second correlator configured to generate a second correlation value by correlating the aforementioned receiving chip sequence with the second binary chip sequence, A coupler configured to generate a correlation value that is a function of the first correlation value and the second correlation value, A detector configured to detect received data symbol values ​​according to the combined correlation value, A power transmitter.

2. The power transmitter according to claim 1, wherein the first modulation chip sequence includes at least three different chip values.

3. The power transmitter according to claim 1, wherein at least two chip values ​​of the first modulation chip sequence are represented by a change in modulation load, the change in modulation load differs with respect to the at least two chip values, and the chip determiner is configured to determine the receiving chip sequence in accordance with the change in modulation load.

4. Each of the chip time intervals of the first modulation chip sequence is divided into at least two load time intervals, at least two chip values ​​have different modulation loads for the at least two load time intervals, the modulation load patterns differ for each of the at least two chip values, and the third chip value among the at least three different chip values ​​has the same modulation load for the at least two load time intervals. The load measuring device is configured to determine the measured load value as the load value measured during the load time interval, The power transmitter according to claim 2, wherein the chip determination unit is configured to determine the chip value of the received chip sequence according to the difference in the measured load values ​​of each chip at different load time intervals.

5. The power transmitter according to claim 1, wherein the first modulation chip sequence has three different chip values.

6. The power transmitter according to claim 5, wherein the first modulation chip sequence has a first value for aligned chips having a first binary value in both the first binary chip sequence and the second binary chip sequence, a second value for aligned chips having a second binary value in both the first binary chip sequence and the second binary chip sequence, and a third value for aligned chips having different aligned values ​​in the first binary chip sequence and the second binary chip sequence.

7. The power transmitter according to claim 1, wherein the chip decisioner is configured to determine the received chip sequence as a binary chip sequence.

8. The power transmitter according to claim 7, wherein the chip determiner and the first correlator are configured such that the contribution of the first correlation value to at least one chip value of the first modulation chip sequence is less than 10 percent of the contribution of the first correlation value to at least one other chip value of the modulation chip sequence.

9. The power transmitter according to claim 1, wherein the coupler is configured to generate a coupled correlation value in accordance with the multiplication of the first correlation value and the second correlation value.

10. The power transmitter according to claim 1, wherein the chip determiner is configured to determine the received chip sequence such that it has a chip value that is a possible chip value for the first modulation chip sequence.

11. The power transmitter according to claim 1, wherein the cross-correlation between the first binary chip sequence and the first modulation chip sequence is two-thirds or more of the length of the first binary chip sequence when the first binary chip sequence and the first modulation chip sequence are aligned, and one-third or less of the length of the first binary chip sequence when the first binary chip sequence and the first modulation chip sequence are not aligned.

12. A power receiver for wirelessly receiving power from a power transmitter via an electromagnetic power transmission signal, The input circuit includes a receiver coil configured to extract power from the power transmission signal, and the data transmitter transmits data symbols to the power transmitter by load modulation of the power transmission signal. Each data symbol is modulated by a sequence of modulation load values ​​corresponding to a chip sequence in a set of modulation chip sequences, each modulation chip sequence in the set of modulation chip sequences represents one data symbol, the chip sequences in the set of modulation chip sequences are linked to different data symbol values, at least one modulation chip sequence in the set of modulation chip sequences is a combination of a first binary chip sequence and a second binary chip sequence, having at least three different chip values, and the first binary chip sequence and the second binary chip sequence are different chip sequences, power receiver.

13. A method for operating a power transmitter that wirelessly supplies power to a power receiver via an electromagnetic power transmission signal, wherein the power transmitter is The output circuit includes a transmitter coil configured to generate the power transmission signal in response to a drive signal applied to the output circuit, A driver configured to generate the aforementioned drive signal, A data receiver configured to receive load-modulated data symbols modulated by one modulation chip sequence from a set of modulation chip sequences, wherein each modulation chip sequence in the set of modulation chip sequences represents one data symbol, and at least one first modulation chip sequence in the set of modulation chip sequences is a combination of a first binary chip sequence and a second binary chip sequence, wherein the first binary chip sequence and the second binary chip sequence are different chip sequences. The method includes, and the data receiver, The steps include measuring the load of the power transmission signal and generating a measured load value, The steps include determining the receiving chip sequence from the measured load value, The steps include: generating a first correlation value by correlating the received chip sequence with the first binary chip sequence; The steps include: generating a second correlation value by correlating the aforementioned received chip sequence with the second binary chip sequence; A step of generating a correlation value that is a combination of the first correlation value and the second correlation value, The steps include detecting the received data symbol value according to the combined correlation value, How to do it.

14. A method for operating a power receiver to wirelessly receive power from a power transmitter via an electromagnetic power transmission signal, The power receiver has an input circuit including a receiver coil configured to extract power from the power transmission signal, The method includes the step of a data transmitter transmitting data symbols to the power transmitter by load modulation of the power transmission signal, A method wherein each data symbol is modulated by a sequence of modulation load values ​​corresponding to a chip sequence in a set of modulation chip sequences, each modulation chip sequence in the set of modulation chip sequences represents one data symbol, the chip sequences in the set of modulation chip sequences are linked to different data symbol values, and at least one modulation chip sequence in the set of modulation chip sequences is a combination of a first binary chip sequence and a second binary chip sequence having at least three different chip values, the first binary chip sequence and the second binary chip sequence being different chip sequences.

15. A wireless power transmission system comprising a power transmitter according to claim 1 and a power receiver according to claim 12.

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