Display substrate and display device

Abstract

The display substrate includes a plurality of conductive layers, the plurality of conductive layers including a plurality of data lines, a plurality of connecting lines, and a plurality of fan-out lines. The connecting lines span at least one of the data lines and are insulated from the spanned data lines. The first fan-out lines are electrically connected to the connecting lines, and the second fan-out lines are electrically connected to ends of the second data lines close to the fan-out region. The first fan-out lines include a transfer line. The fan-out region includes a first fan-out region and a second fan-out region, and the transfer line is located in the second fan-out region. The transfer line is located in a different conductive layer from the plurality of second fan-out lines and spans at least one of the second fan-out lines, so that an arrangement order of the ends of the plurality of fan-out lines away from the display region in the first direction is the same as an arrangement order of the plurality of data lines in the first direction. Here, the transfer line includes a body portion and two connecting ends, and the body portion is located on a side of the two connecting ends close to the display region.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims priority from a Chinese patent application having application number 202210880462.1, filed on July 25, 2022, and a PCT international application having application number PCT / CN2022 / 089120, filed on April 25, 2022, the entire disclosures of which are incorporated herein by reference.

[0002] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. [Background technology]

[0003] Currently, organic light-emitting diode (OLED) display devices are widely used due to their characteristics of self-luminescence, fast response, high contrast, wide viewing angle, and the ability to be fabricated on a flexible base.

[0004] An OLED display device includes a number of sub-pixels, each of which includes a pixel driving circuit and a light-emitting element. The light-emitting element is driven to emit light via the pixel driving circuit, thereby realizing display. Summary of the Invention [Means for solving the problem]

[0005] In one embodiment, a display substrate is provided. The display substrate has a display area and a fan-out area, the fan-out area being adjacent to one side edge of the display area. The display substrate includes a base and a plurality of conductive layers. The conductive layers are located on the same side of the base. The conductive layers are arranged in a stacked manner. The conductive layers include a plurality of data lines, a plurality of connecting lines, and a plurality of fan-out lines. The data lines are spaced apart along a first direction, and the data lines all extend along a second direction, and the second direction crosses the first direction. The data lines include a plurality of first data lines and a plurality of second data lines, the first data lines being located in two edge regions along the first direction of the display area, and the second data lines being located in a central region along the first direction of the display area. A first end of a connecting line is located in the edge region and is electrically connected to the first data line, and a second end of the connecting line extends to a boundary between the central region and the fan-out region. At least one of the connecting lines spans at least one data line and is insulated from the data line spanned by it. A second end of the at least one of the connecting lines is located between two adjacent second data lines. The plurality of fan-out lines are located in the fan-out region. The plurality of fan-out lines include a plurality of first fan-out lines and a plurality of second fan-out lines, where the first fan-out lines are electrically connected to the second ends of the connecting lines, and the second fan-out lines are electrically connected to ends of the data lines that are not electrically connected to the connecting lines and that are closer to the fan-out region. Wherein, the display substrate further includes a bending region and a chip mounting region, which are sequentially spaced apart from the display region. The fan-out region includes a first fan-out region and a second fan-out region, where the first fan-out region is located between the display region and the bending region, and the second fan-out region is located between the bending region and the chip mounting region. The first fan-out line includes a transfer line, where the transfer line is located in the second fan-out region.The transfer line spans at least one of the second fan-out lines, such that an arrangement order of the ends of the fan-out lines away from the display area in the first direction is the same as an arrangement order of the data lines in the first direction, wherein the transfer line includes a main body and two connection ends, the main body being located on a side of the two connection ends closer to the display area.

[0006] In some embodiments, the display substrate further comprises a circuit test area located between the flex area and the chip mounting area, and the second fan-out area is located between the circuit test area and the chip mounting area.

[0007] In some embodiments, the transfer line is U-shaped or approximately U-shaped.

[0008] In some embodiments, a central axis extending along the second direction of the display substrate is defined as a first central axis. A region of the second fan-out region located on one side of the first central axis is one sub-fan-out region. In the sub-fan-out region, the transfer lines are radially arranged, and of two adjacent transfer lines, the transfer line located on the outer side is provided around the transfer line located on the inner side.

[0009] In some embodiments, two adjacent transfer lines are located on different conductive layers.

[0010] In some embodiments, a central axis extending along the second direction of the display substrate is defined as a first central axis. A region of the second fan-out region located on one side of the first central axis is one sub-fan-out region. In the sub-fan-out region, the first fan-out line further includes a first wiring segment and a second wiring segment that are sequentially separated from the display region and electrically connected to each other. The first wiring segment gradually approaches the first central axis from an end close to the display region to an end distant from the display region. The second wiring segment is parallel to the first central axis. The second fan-out line includes a third wiring segment and a fourth wiring segment that are sequentially separated from the display region and electrically connected to each other. The third wiring segment gradually approaches the first central axis from an end close to the display region to an end distant from the display region. The fourth wiring segment is parallel to the first central axis. Here, the connection end of the transfer line that is closer to the first central axis is electrically connected to an end of the second wiring segment that is distant from the first wiring segment.

[0011] In some embodiments, the first wiring segments and the third wiring segments are alternately arranged in the sub-fan-out region, and a fitting straight line defined by an end of the first wiring segment away from the display region and an end of the third wiring segment away from the display region gradually approaches the display region from an end away from the first central axis to an end close to the first central axis.

[0012] In some embodiments, in the sub-fan-out region, among the plurality of second wiring segments, directly adjacent second wiring segments are in the same group, and ends of the second wiring segments in the same group that are away from the display region are offset along the first direction.

[0013] In some embodiments, in the sub-fan-out region, of two adjacent second wiring segments, a length of the second wiring segment closer to the first central axis line is smaller than a length of the second wiring segment away from the first central axis line. Of two adjacent transfer lines, the connection end for connecting the second wiring segments of the transfer line closer to the first central axis line is closer to the display area than the connection end for connecting the second wiring segments of the transfer line away from the first central axis line.

[0014] In some embodiments, the body portion includes a first transfer segment connected to the connection end of the transfer line that connects the second wiring segment, such that an orthogonal projection of the first transfer segment at the base overlaps or nearly overlaps an orthogonal projection of the correspondingly connected second wiring segment at the base.

[0015] In some embodiments, the body further includes a second transfer segment connected to the first transfer segment and a third transfer segment connected to the second transfer segment. The conductive layers further include an isolation block, the isolation block being located on a side of the first wiring segment and the third wiring segment away from the base, and the isolation block covering the first wiring segment and the third wiring segment. Here, the transfer line is located on a side of the isolation block away from the base. An orthogonal projection of the second transfer segment on the base is located within an orthogonal projection of the isolation block on the base. An orthogonal projection of both the first transfer segment and the third transfer segment on the base is located outside an orthogonal projection of the isolation block on the base.

[0016] In some embodiments, the plurality of conductive layers includes at least two gate metal layers and at least two source / drain metal layers. The at least two source / drain metal layers are all located on the sides of the at least two gate metal layers that are away from the base. The first wiring segment, the second wiring segment, the third wiring segment, and the fourth wiring segment are located in the at least two gate metal layers. The isolation block is located in a source / drain metal layer of the at least two source / drain metal layers that is closer to the base. The transfer line is located in a source / drain metal layer of the at least two source / drain metal layers that is away from the base.

[0017] In another aspect, there is provided a display device, comprising a display panel according to any of the above embodiments. [Brief description of the drawings]

[0018] In order to more clearly describe the technical solutions according to the present disclosure, the drawings used in some embodiments of the present disclosure will be briefly described below. It is clear that the drawings in the following description are only some drawings of some embodiments of the present disclosure. Those skilled in the art can also obtain other drawings based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and do not limit the actual dimensions of the products, the actual flow of the methods, the actual timing of the signals, etc. according to the embodiments of the present disclosure. [Figure 1] 1 is a structural diagram of a display device according to some embodiments; [Diagram 2] 1 is a structural diagram of a display panel according to some embodiments. [Diagram 3] 1A to 1C are structural diagrams of a display substrate according to some embodiments. [Figure 4] 4 is a structural diagram of a connection structure between a light-emitting element in a sub-pixel and a pixel driving circuit. FIG. [Diagram 5] 11A to 11C are structural diagrams of a display substrate according to some other embodiments. [Figure 6]11A to 11C are structural diagrams of display substrates according to some other embodiments. [Figure 7] 11A to 11C are structural diagrams of display substrates according to some other embodiments. [Figure 8] 1A to 1C are partial structural diagrams of a display substrate according to some embodiments. [Figure 9] FIG. 9 is a structural diagram of the first gate metal layer, the second gate metal layer, and the first source / drain metal layer in FIG. 8. [Figure 10] FIG. 9 is a structural diagram of the second source-drain metal layer and the third source-drain metal layer in FIG. 8. [Figure 11] FIG. 9 is a partial structural diagram of region 001 in FIG. 8. [Figure 12] FIG. 12 is a structural diagram of each film layer in FIG. [Figure 13] FIG. 12 is a structural diagram of each film layer in FIG. [Figure 14] FIG. 12 is a structural diagram of each film layer in FIG. [Figure 15] FIG. 12 is a structural diagram of each film layer in FIG. [Figure 16] FIG. 12 is a structural diagram of each film layer in FIG. [Figure 17] FIG. 12 is a structural diagram of each film layer in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] Hereinafter, some embodiments of the present disclosure will be described clearly and completely with reference to the drawings. Of course, the embodiments described herein are only a part of the embodiments of the present disclosure, and are not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments that can be obtained by those skilled in the art shall be included in the protection scope of the present disclosure.

[0020] Unless otherwise indicated by the context, in the present specification and claims, the term "comprise" and other forms, such as the third person singular "comprises" and the present participle form "comprising" should be interpreted in an open, inclusive sense, i.e., "including but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "examples," "specific examples," "some examples," and the like, are intended to indicate that a particular feature, structure, material, or characteristic associated with this embodiment or the examples is included in at least one embodiment or example of the present disclosure. General expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, a particular feature, structure, material, or characteristic described may be included in any one or more embodiments or examples in any suitable manner.

[0021] In the following, the terms "first" and "second" are for descriptive purposes only and should not be understood as indicating or implying the relative importance or quantity of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more than two.

[0022] As used herein, "applied to" or "disposed to" is intended to be open and inclusive language that does not exclude devices that are adapted or configured to perform additional tasks or steps.

[0023] Additionally, the use of "based on" is meant to be open-ended and inclusive, as a process, step, calculation, or other action performed "based on" one or more recited conditions or values ​​may, in fact, be based on additional conditions or beyond the recited values.

[0024] When a layer or element is referred to as being on another layer or substrate, it is understood that the layer or element may be directly on the other layer or substrate, or there may be intermediate layers between the layer or element and the other layer or substrate.

[0025] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, thicknesses of layers and regions are exaggerated for clarity. Thus, variations in shape relative to the drawings due, for example, to manufacturing techniques and / or tolerances, can be expected. Thus, the exemplary embodiments are not limited to the shapes of regions shown herein, but should be construed to include deviations in shapes due to manufacturing or otherwise. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions shown in the drawings are exemplary in nature, and their shapes are not intended to represent the actual shape of a region of a device, nor are they intended to limit the scope of the exemplary embodiments.

[0026] FIG. 1 is a structural diagram of a display device according to some embodiments.

[0027] As shown in Fig. 1, some embodiments of the present disclosure provide a display device 200. It is understood that the display device 200 is a product having an image display function. Exemplarily, the display device 200 may be used to display still images such as pictures and photographs. The display device 200 may also be used to display moving images such as videos and game screens.

[0028] In some examples, the display device 200 may be a laptop, a mobile phone, a wireless device, a personal data assistant (PDA), a handheld or portable computer, a GPS receiver / navigator, a camera, an MP4 video player, a video camera, a game console, a watch, a clock, a calculator, a television monitor, a flat panel display, a computer monitor, an car display (e.g., a speedometer display, a distance meter display, etc.), a navigator, a cockpit controller and / or display, a display of a camera view (e.g., a rear view camera display in a vehicle), electronic photography, electronic signage or signs, projectors, packaging and aesthetic structures (e.g., a display of an image of a piece of jewelry), and the like.

[0029] The display device 200 includes a display panel 210. In some examples, the display panel 210 is an organic light-emitting diode display (OLED) or a quantum dot light-emitting diode display (QLED).

[0030] In addition, the display device 200 may be equipped with an under-screen camera and an under-screen fingerprint recognition sensor, etc., so that the display device can realize various different functions, such as photographing, video recording, fingerprint recognition, or face recognition.

[0031] FIG. 2 is a structural diagram of a display panel according to some embodiments.

[0032] The display panel 210 includes a display substrate 100. Exemplarily, as shown in Fig. 2, the display panel 210 may further include other functional film layers 211 located on the display side of the display substrate 100, such as a touch control functional layer, a reflection reducing layer, an anti-fingerprint layer, a hardening layer, and a package cover, so that the display panel 210 can achieve different functions.

[0033] The embodiment of the present disclosure does not further limit other functional layers 211 of the display panel 210. Hereinafter, the display substrate 100 will be described by way of example.

[0034] FIG. 3 is a structural diagram of a display substrate according to some embodiments.

[0035] In some examples, as shown in Fig. 3, the display substrate 100 includes a plurality of sub-pixels 101. The sub-pixels 101 are arranged in a plurality of columns along a first direction X and in a plurality of rows along a second direction Y. In some examples, the first direction X intersects with the second direction Y. Exemplarily, the first direction X is perpendicular to the second direction Y. In some examples, the first direction X is a horizontal direction and the second direction Y is a vertical direction.

[0036] It is understood that the sub-pixel 101 is the smallest unit for the display substrate 100 to display an image. Each sub-pixel 101 may display a single color, such as red, green, or blue. The display substrate 100 may include a plurality of red sub-pixels, a plurality of green sub-pixels, and a plurality of blue sub-pixels. By adjusting the brightness (gray scale) of the sub-pixels 101 of different colors, red light, green light, and blue light of different intensities can be obtained. By overlapping at least two of the red light, green light, and blue light of different intensities, more colors of light can be displayed, so that the full-color display of the display substrate 100 is realized.

[0037] 3, it can be understood that the display substrate 100 has a display area AA and a fan-out area BB, and the fan-out area BB is adjacent to one side edge of the display area AA. Here, the display area AA is used for displaying image information, and a number of sub-pixels 101 are located in the display area AA of the display substrate 100.

[0038] The fan-out region BB is adjacent to one side edge of the display region AA. That is, the edge of the fan-out region BB close to the display region AA overlaps with the edge of the display region AA close to the fan-out region BB. In the accompanying drawings of the present disclosure, taking FIG. 3 as an example, the edge of the fan-out region BB and the edge of the display region AA are separated from each other, but this is merely for the purpose of easily showing the display region AA and the fan-out region BB, and does not further limit the display region AA and the fan-out region BB.

[0039] In some examples, as shown in FIG. 3, the fan-out region BB is located on one side of the display area AA along the second direction Y.

[0040] 3, the fan-out region BB is adjacent to a lower edge of the display area AA. That is, the fan-out region BB is located below the display area AA along the second direction Y. Exemplarily, when the display device 200 is used in a state in which it is vertical or substantially vertical to the ground, the fan-out region BB is closer to the ground than the display area AA.

[0041] In some examples, each sub-pixel 101 includes a light-emitting element 300 and a pixel drive circuit that is electrically connected to the light-emitting element 300 and is used to drive the light-emitting element 300 to emit light.

[0042] FIG. 4 is a structural diagram of a connection structure between a light emitting element in a sub-pixel and a pixel driving circuit.

[0043] 4, the display substrate 100 includes a base 102 and a plurality of conductive layers 103. The plurality of conductive layers 103 are located on the same side of the base 102, and the plurality of conductive layers 103 are arranged in a stacked manner.

[0044] In some examples, the base 102 is a flexible material, thereby allowing the display substrate 100 to bend, thereby enabling the display panel 210 to achieve functions such as a curved display, a folding display, or a scrolling display. In some other examples, the base 102 is a rigid material.

[0045] For example, the material of the base 102 may be any one of polyimide (official English name: Polyimide, English abbreviation: PI), polycarbonate (official English name: Polycarbonate, English abbreviation: PC), or polyvinyl chloride (official English name: polyvinyl chloride, English abbreviation: PVC).

[0046] In some examples, multiple insulating layers (e.g., gate insulating layers and buffer layers, passivation layers, organic layers, etc.) may be provided between multiple conductive layers 103, serving to electrically isolate two adjacent conductive layers 103.

[0047] Exemplarily, the pixel driving circuit is provided in the plurality of conductive layers 103. In some examples, as shown in FIG. 4, the plurality of conductive layers 103 include an active film layer 1031, at least one gate metal layer Gate (e.g., a first gate metal layer Gate1, a second gate metal layer Gate2, and a third gate metal layer (not shown, may be located between the second gate metal layer Gate2 and the first source-drain metal layer SD1)), at least one source-drain metal layer (e.g., a first source-drain metal layer SD1, a second source-drain metal layer SD2, and a third source-drain metal layer (not shown, may be located between the second source-drain metal layer SD2 and the anode layer AND)), etc., which are arranged in sequence away from the base 102.

[0048] Exemplarily, the optional gate metal layer Gate may include a molybdenum material, and the optional source / drain metal layer may include a titanium / aluminum / titanium composite laminate structure.

[0049] The pixel driving circuit includes a plurality of thin film transistors (full English name: Thin Film Transistor, English abbreviation: TFT) and at least one capacitor. Exemplarily, the active film layer 1031 and the first gate metal layer Gate1 may be used to form a part of the plurality of thin film transistors (one or more). The active film layer 1031 and the second gate metal layer Gate2 may be used to form another part of the plurality of thin film transistors (one or more). The first gate metal layer Gate1 and the second gate metal layer Gate2 may be used to form at least one capacitor.

[0050] However, the number of active film layers 1031 is not limited. For example, some embodiments of the present disclosure may include only one active film layer 1031, and the material of the active film layer 1031 may include metal oxide and low-temperature polysilicon. Alternatively, some embodiments of the present disclosure may further include two active film layers 1031, where the material of one active film layer 1031 includes metal oxide and the material of the other active film layer includes low-temperature polysilicon.

[0051] As can be seen from the above several embodiments, the display substrate 100 further includes a light emitting element 300, and the pixel driving circuit is electrically connected to the light emitting element 300. Hereinafter, the light emitting element 300 will be described by way of example with continued reference to FIG.

[0052] In some examples, the light emitting element 300 is located on a side of the plurality of conductive layers 103 that is away from the base 102. Exemplarily, the light emitting element 300 includes an anode layer AND, an emission layer EML, and a cathode layer CTD that are sequentially provided in a direction away from the base 102.

[0053] In some examples, it is understood that the light-emitting layer EML includes a plurality of spaced apart effective light-emitting portions, and the effective light-emitting portions are used to emit light. Exemplarily, the effective light-emitting portions include an electroluminescent material. It is understood that electroluminescence refers to the phenomenon in which an organic semiconductor material, under the driving of an electric field, forms excitons through carrier injection, transport, and combination of electrons and holes, and then emits light through radiative recombination.

[0054] It is understood that among the multiple effective light-emitting portions, some are used to emit red light, others are used to emit green light, and still others are used to emit blue light. Exemplarily, different electroluminescent materials may be selected, so that the effective light-emitting portions emit light of different colors. It is understood that the number of the effective light-emitting portions that emit red light, the effective light-emitting portions that emit green light, and the effective light-emitting portions that emit blue light may be the same or different.

[0055] For example, the effective light-emitting portion emitting red light, the effective light-emitting portion emitting green light, and the effective light-emitting portion emitting blue light may be arranged in a mixed manner, and thus, by controlling the emission intensities of the different effective light-emitting portions, red light, green light, and blue light of different intensities can be obtained. By mixing the red light, green light, and blue light of different intensities, the display substrate 100 can display a color image.

[0056] It is understood that the pixel driving circuit may drive the emission of the emission layer EML. In some examples, one pixel driving circuit is electrically connected to one effective light-emitting section via the anode layer AND, so that each pixel driving circuit can provide a driving current to each effective light-emitting section via the anode layer AND, respectively, that is, make the effective light-emitting sections emit light independently, reduce mutual interference between the effective light-emitting sections, and improve the display effect of the display substrate 100. It is understood that the emission brightness of the effective light-emitting section may be adjusted by adjusting the magnitude of the driving current supplied by the pixel driving circuit to the effective light-emitting section.

[0057] In some examples, the anode layer AND is a metal material such as copper or silver. The cathode layer CTD is a transparent material such as transparent indium tin oxide (ITO) or transparent indium zinc oxide (IZO), so that the light emitted from the effective light-emitting part can be emitted through the cathode layer CTD, that is, in this case, the display substrate 100 is a top-emission display substrate.

[0058] In some other examples, the anode layer AND is a transparent material such as ITO or IZO, and the cathode layer CTD is a metallic material such as copper or silver, so that light emitted from the effective light-emitting area can be emitted through the anode layer AND, that is, in this case, the display substrate 100 is a bottom emission display substrate.

[0059] In some other examples, the anode layer AND and the cathode layer CTD are both transparent materials such as ITO or IZO, so that the light emitted from the effective light-emitting area can be emitted through the anode layer AND and the cathode layer CTD, that is, in this case, the display substrate 100 is a double-sided light-emitting display substrate.

[0060] In some examples, based on the work function, the material of the anode layer AND includes ITO or a stack of ITO-Ag-ITO, so that the anode layer AND can provide more holes. The material of the cathode layer CTD includes MgAg, so that the cathode layer CTD can provide more electrons. The cathode layer CTD is very thin and light transmissive, so that the display substrate 100 can achieve top emission.

[0061] In some examples, at least one of a hole injection layer (HIL), a hole transport layer (HTL), and an electron blocking layer (EBL) is provided between the anode layer AND and the effective light-emitting section along the direction from the anode layer AND to the effective light-emitting section. At least one of an electron injection layer (EIL), an electron transport layer (ETL), and a hole blocking layer (HBL) is provided between the cathode layer CTD and the effective light-emitting section along the direction from the cathode layer CTD to the effective light-emitting section. The above-mentioned installation method improves the light-emitting reliability of the effective light-emitting section.

[0062] FIG. 5 is a structural diagram of a display substrate according to some other embodiments.

[0063] 5, the display substrate 100 further includes a package layer 104. The package layer 104 may be located on the side of the light-emitting element 300 away from the base 102 and cover the light-emitting element 300, which serves to prevent water vapor and oxygen gas in the external environment from entering the light-emitting element 300 and protect the light-emitting element 300.

[0064] FIG. 6 is a structural diagram of a display substrate according to some other embodiments.

[0065] In some embodiments, as shown in Fig. 6, the conductive layers 103 further include a plurality of data lines 110 and a plurality of fan-out lines 130 in addition to the pixel driving circuits. It is understood that the data lines 110 are located in the display area AA and are electrically connected to a plurality of pixel driving circuits, and the pixel driving circuits may drive the light emitting elements 300 to emit light by transmitting driving signals to the pixel driving circuits, thereby realizing the display of different gray scales. The fan-out lines 130 are located in the fan-out area BB and are electrically connected to the data lines 110 in one-to-one correspondence.

[0066] 6, the data lines 110 are spaced apart along a first direction X, and all of the data lines 110 extend along a second direction Y. The second direction Y may intersect with the first direction X, and both the first direction X and the second direction Y may be parallel to the base 102.

[0067] In some examples, the first direction X is perpendicular or substantially perpendicular to the second direction Y. Illustratively, as shown in FIG 6, the first direction X is a horizontal direction and the second direction Y is a vertical direction.

[0068] As can be seen from the above, as shown in Fig. 3, the sub-pixels 101 are arranged in a plurality of columns along a first direction X and a plurality of rows along a second direction Y. That is, the pixel driving circuits of the sub-pixels 101 can be arranged in an array of a plurality of rows and a plurality of columns along the first direction X and the second direction Y. As shown in Fig. 6, the data lines 110 extend along the second direction Y, so that one data line 110 can be electrically connected to the pixel driving circuits of the sub-pixels 101 in one column arranged along the second direction Y to provide data voltages to the pixel driving circuits of the sub-pixels 101 in one column.

[0069] In some examples, the spacing distances of the multiple data lines 110 along the first direction X are the same or approximately the same.

[0070] As shown in FIG. 6, since the fan-out region BB is adjacent to one side edge of the display area AA along the second direction Y, it can be understood that the multiple data lines 110 are arranged to extend along the second direction Y, and the multiple data lines 110 may be electrically connected in one-to-one correspondence to the multiple fan-out lines 130 located within the fan-out region BB.

[0071] 6, the fan-out lines 130 located in the fan-out region BB are gradually converged and extend away from the display area AA of the fan-out region BB, facilitating electrical connection between the fan-out lines 130 and a driving chip (Integrated Circuit, IC) outside the display substrate 100. It is understood that the driving IC may input signals to each pixel driving circuit via the fan-out lines 130 and the data lines 110.

[0072] In some examples, the multiple fan-out lines 130 may be electrically connected to a driving IC by extending the side of the multiple fan-out lines 130 away from the display area AA to the edge of the fan-out area BB away from the display area AA.

[0073] However, the above implementation method increases the space occupied by the multiple fan-out lines 130 along the second direction Y, thereby increasing the width of the fan-out region BB, i.e., increasing the width of the side frame (e.g., the bottom frame) of the display panel 210, which is disadvantageous to achieving a narrow frame of the display panel 210 and affects the visual effect of the display panel 210.

[0074] In some examples, the fan-out lines 130 are located in at least one gate metal layer gate (e.g., the first gate metal layer gate1, the second gate metal layer gate2, and the third gate metal layer). The gate metal layer gate includes a molybdenum material, which has a relatively large resistance. Based on this, as shown in FIG. 6, the length of the fan-out lines 130 located at both end regions along the first direction X is relatively long, so that the resistance of the data lines 110 located at both end regions along the first direction X is relatively large, and the display brightness of the display substrate 100 at both end regions along the first direction X is easily reduced. In addition, as shown in FIG. 6 , the length of the fan-out lines 130 located at both end regions along the first direction X is obviously longer than the length of the fan-out lines 130 located at the middle region in the first direction X. Therefore, the resistance difference between the data lines 110 located at both end regions along the first direction X and the data lines 110 located at the middle region in the first direction X is also large. As a result, the display brightness of the middle region of the display substrate 100 along the first direction X is higher than the display brightness of the both end regions of the display substrate 100 along the first direction X, which affects the brightness uniformity of the display screen of the display substrate 100.

[0075] FIG. 7 is a structural diagram of a display substrate according to some other embodiments.

[0076] In some embodiments of the present disclosure, a display substrate 100 is provided, which includes a display area AA and a fan-out area BB, as shown in FIG. 7. The fan-out area BB is adjacent to one side edge of the display area AA. The display substrate 100 includes a base 102 and a plurality of conductive layers 103 (as shown in FIG. 4), where the plurality of conductive layers 103 are located on the same side of the base 102, and the plurality of conductive layers 103 are stacked. The plurality of conductive layers 103 includes a plurality of data lines 110. The plurality of data lines 110 are spaced apart along a first direction X, and the plurality of data lines 110 all extend along a second direction Y. The second direction Y intersects with the first direction X.

[0077] In addition, the above-mentioned embodiment of the present disclosure has already been described with examples for the display area AA, the fan-out area BB, the base 102, the conductive layers 103, and the data lines 110, and will not be repeated here. Also, referring to FIG. 7, the display substrate 100 may further include a plurality of scanning control signal lines 105. The plurality of scanning control signal lines 105 are spaced apart along the second direction Y, and all extend along the first direction. Thus, one scanning control signal line 105 is electrically connected to pixel driving circuits in one row of sub-pixels 101 arranged along the first direction X, and can thereby control the operation states of the pixel driving circuits in one row of sub-pixels 101.

[0078] Continuing to refer to FIG. 7, the display substrate 100 provided according to some embodiments of the present disclosure will now be described by way of example.

[0079] 7, the multiple data lines 110 include multiple first data lines 111 and multiple second data lines 112. The multiple first data lines 111 are located in two edge regions AA1 along the first direction X of the display area AA, and the multiple second data lines 112 are located in a central region AA2 along the first direction X of the display area AA.

[0080] For example, as shown in FIG. 7, the number of edge regions AA1 is two, the two edge regions AA1 are located on both sides of the display substrate 100 along the first direction X, and the central region AA2 is located between the two edge regions AA1 along the first direction X.

[0081] Exemplarily, the numbers of the first data lines 111 and the second data lines 112 may be the same or different, and the numbers of the first data lines 111 located in the two edge regions AA1 may be the same or different.

[0082] It should be noted that in each embodiment of the present disclosure, the first data line 111 and the second data line 112 are only used to distinguish the data lines 110 located in the edge region AA1 and the central region AA2, and do not further limit other locations of the data lines 110.

[0083] Exemplarily, the widths of the two edge regions AA1 of the display area AA along the first direction X are the same or approximately the same. In some examples, as shown in FIG. 7, the display area AA includes a rounded corner, i.e., two adjacent edges of the display area AA are connected in an arc-like or approximately arc-like manner. The rounded corner is located within the edge region AA1 of the display area AA. Exemplarily, the width dimension of the edge region AA1 in the first direction X may be equal to or greater than the width dimension of the rounded corner in the first direction X.

[0084] Exemplarily, the plurality of first data lines 111 and the plurality of second data lines 112 are located in the same conductive layer 103. For example, the plurality of first data lines 111 and the plurality of second data lines 112 are both located in the first source-drain metal layer SD1. Also, for example, the plurality of first data lines 111 and the plurality of second data lines 112 are both located in the second source-drain metal layer SD2. Furthermore, for example, the plurality of first data lines 111 and the plurality of second data lines 112 may be located in another conductive layer 103 (for example, a third source-drain metal layer) other than the first source-drain metal layer SD1 and the second source-drain metal layer SD2.

[0085] 7, the conductive layers 103 further include a plurality of connecting lines 120. A first end of one connecting line 120 (i.e., the end indicated by the arrow in FIG. 7) is located in the edge region AA1 of the display area AA, and is electrically connected to one first data line 111. A second end of the connecting line 120 (i.e., the end opposite to the end indicated by the arrow in FIG. 7) extends to the boundary between the central region AA2 of the display area AA and the fan-out region BB.

[0086] For example, as shown in FIG. 7, the second ends of any of the plurality of connection lines 120 extend to the central area AA2 of the display area AA.

[0087] As can be seen from the above, one side edge of the display area AA close to the fan-out area BB may overlap one side edge of the fan-out area BB close to the display area AA. The second end of the connection line 120 extends to the boundary between the central area AA2 and the fan-out area BB. It is understood that the second end of the connection line 120 may be located on the boundary line between the central area AA2 and the fan-out area BB, or may have a relatively small gap between the boundary line, such as a gap of several micrometers, in which case the second end of the connection line 120 may be located on the side of the boundary line close to the display area AA or on the side of the boundary line close to the fan-out area BB.

[0088] As shown in FIG. 7, at least one connecting line 120 spans at least one data line 110 (eg, the first data line 111 and / or the second data line 112) and is insulated from the data line 110 it spans.

[0089] It is understood that since the multiple data lines 110 are spaced apart along the first direction X, some connecting lines 120 need to span at least one data line 110 when their second ends extend to the boundary between the central area AA2 and the fan-out area BB. For example, at least one connecting line 120 may span the first data line 111 and the second data line 112 at the same time. For example, at least one connecting line 120 may only span the first data line 111 (not shown). For example, at least one connecting line 120 may only span the second data line 112 (not shown).

[0090] 7, the display substrate 100 may further include a connecting line 120 that does not cross any of the data lines 110. For example, in FIG. 7, the first connecting line 120 and the last connecting line 120 are arranged from left to right along the first direction X.

[0091] It is understood that the connecting line 120 spans at least one data line 110 , ie the orthogonal projection of the connecting line 120 on the base 102 intersects with the orthogonal projection of at least one data line 110 on the base 102 .

[0092] In some examples, the connecting lines 120 and the data lines 110 may be located on different conductive layers 103 such that the connecting lines 120 are insulated from the data lines 110 that they cross.

[0093] Exemplarily, the data line 110 is located in the first source-drain metal layer SD1, and the connection line 120 is located in the second source-drain metal layer SD2, or the data line 110 is located in the second source-drain metal layer SD2, and the connection line 120 is located in the third source-drain metal layer.

[0094] Exemplarily, when the connecting line 120 and the data line 110 are located in different conductive layers 103, the first end of the connecting line 120 may be electrically connected to the first data line 111 through a transfer hole. It is understood that the transfer hole may penetrate the insulating film layer between two adjacent conductive layers 103 along a direction perpendicular or substantially perpendicular to the base 102, thereby electrically connecting the different conductive layers 103, that is, electrically connecting the conductive wiring (e.g., the connecting line 120 and the data line 110) located in the different conductive layers 103. Exemplarily, when the two conductive layers 103 are not adjacent, the conductive wiring located in the different conductive layers 103 may be electrically connected through a plurality of transfer holes.

[0095] By way of example, for ease of explanation, a transfer hole electrically connected to the conductive wiring on the first source-drain metal layer SD1 and the conductive wiring on the second source-drain metal layer SD2 may be referred to as a PLN1 hole, and a transfer hole electrically connected to the conductive wiring on the second source-drain metal layer SD2 and the conductive wiring on the third source-drain metal layer may be referred to as a PLN2 hole.

[0096] That is, when the first data line 111 is located in the first source-drain metal layer SD1 and the connecting line 120 is located in the second source-drain metal layer SD2, a first end of the connecting line 120 is electrically connected to the first data line 111 through the PLN1 hole. When the first data line 111 is located in the second source-drain metal layer SD2 and the connecting line 120 is located in the third source-drain metal layer, a first end of the connecting line 120 is electrically connected to the first data line 111 through the PLN2 hole.

[0097] As can be seen from the above, in some examples, the connecting line 120 and the data line 110 are located on different conductive layers 103, so that the connecting line 120 can be insulated from the data line 110 that it crosses. In some other examples, the connecting line 120 includes a body portion and a jumper portion, where the body portion and the jumper portion can be electrically connected via a transfer hole. The body portion can be located on the same conductive layer 103 as the data line 110, but the jumper portion can be located on a different conductive layer 103 than the data line 110, so that the jumper portion can cross at least one data line and be insulated from the data line 110 that it crosses.

[0098] 7, the second end of at least one connecting line 120 is located between two adjacent second data lines 110. That is, the second end of one connecting line 120 may be disposed between two adjacent second data lines 112, or the second ends of two or more connecting lines 120 may be disposed between two adjacent second data lines 112.

[0099] It is understood that, as shown in Fig. 7, between any two adjacent second data lines 112 of a set, there may be one second end of the connecting line 120, two or more second ends of the connecting lines 120, or there may be no second end of the connecting line 120. The number of second ends of the connecting lines 120 between different two adjacent second data lines 112 may be the same or different.

[0100] As shown in FIG. 7, the second end of the connecting line 120 is disposed between two adjacent second data lines 112, so that the second end of the connecting line 120 can extend through the space between the two adjacent second data lines 112 to the boundary between the central region AA2 of the display area AA and the fan-out region BB.

[0101] It is understood that the number of the connection lines 120 and the number of the first data lines 110 may be the same or different. In some examples, the number of the connection lines 120 is the same as the number of the first data lines 110. The multiple connection lines 120 and the multiple first data lines 111 are connected in one-to-one correspondence. In some other examples, the number of the connection lines 120 is less than the number of the first data lines 111. In this case, all the connection lines 120 may be connected in one-to-one correspondence with some of the first data lines 111, but the other part of the first data lines 111 may not be connected to the connection lines 120.

[0102] In some examples, as shown in FIG. 7, the connection line 120 includes a first sub-connection line 121 and a second sub-connection line 122. One end of the first sub-connection line 121 is located in the edge region AA1 and is electrically connected to the first data line 111. The other end of the first sub-connection line 121 extends to the central region AA2. One end of the second sub-connection line 122 is electrically connected to an end of the first sub-connection line 121 away from the first data line 111, and the other end of the second sub-connection line 122 extends to the boundary between the central region AA2 and the fan-out region BB. Exemplarily, the first sub-connection line 121 extends along the first direction X, the second sub-connection line 122 extends along the second direction Y, and the first sub-connection line 121 is perpendicular or substantially perpendicular to the second sub-connection line 122.

[0103] As can be seen from the above, in some examples, the connecting line 120 includes a body portion and a jumper portion. Illustratively, as shown in FIG. 7, when the connecting line 120 includes a first sub-connecting line 121 and a second sub-connecting line 122, the second sub-connecting line 122 may be set as a body portion. The body portion is located on the same conductive layer 103 as the plurality of data lines 110, the first sub-connecting line 121 is a jumper portion, and the jumper portion is located on a different conductive layer 103 from the plurality of data lines 110. The first sub-connecting line 121 may span at least one data line 110 and be insulated from the spanned data line 110. Also, in some other examples, the second sub-connecting line 122 may be set as a body portion. The first sub-connecting line 121 includes a body portion and a jumper portion at the same time, where the jumper portion is used to span the data line 110.

[0104] In some examples, the jumper portion is further away from the base 102 relative to the multiple data lines 110, thereby reducing parasitic capacitance generated between the jumper portion and the gate metal layer Gate (e.g., the first gate metal layer Gate1, the second gate metal layer Gate2, and the third gate metal layer Gate3) and improving signal transmission reliability.

[0105] 7, the plurality of conductive layers 103 further includes a plurality of fan-out lines 130. The plurality of fan-out lines 130 are located in a fan-out region BB. The plurality of fan-out lines 130 include a plurality of first fan-out lines 131 and a plurality of second fan-out lines 132. The first fan-out lines 131 are electrically connected to the second end of the connection line 120, and the second fan-out lines 132 are electrically connected to an end of the second data line 112 close to the fan-out region BB.

[0106] Since both the data line 110 and the connection line 120 may be located in the display area AA, if the fan-out line 130 is provided in a layer different from the data line 110 (or the connection line 120) and is electrically connected to each other, the transfer positions of both may be located within the display area AA. In this case, the fan-out line 130 may still be considered to satisfy the condition that it is located in the fan-out area BB.

[0107] The number of the first fan-out lines 131 is the same as the number of the connection lines 120, so that the multiple first fan-out lines 131 may be electrically connected to the multiple connection lines 120 in one-to-one correspondence. The number of the second fan-out lines 132 may be the same as or different from the number of the second data lines 112.

[0108] For example, when all the first data lines 111 are electrically connected to the multiple connection lines 120 in one-to-one correspondence, the number of the second fan-out lines 132 is the same as the number of the second data lines 112, and the multiple second fan-out lines 132 are electrically connected to the multiple second data lines 112 in one-to-one correspondence.

[0109] When some of the first data lines 111 among all the first data lines 111 are electrically connected to the multiple connection lines 120 in one-to-one correspondence (i.e., when the number of the first data lines 111 is greater than the number of the connection lines 120), the number of the second fan-out lines 132 is different from the number of the second data lines 112. In this case, some of the second fan-out lines 132 (two or more) among the multiple second fan-out lines 132 may be electrically connected to the second data lines 112 in one-to-one correspondence, and the other some of the second fan-out lines 132 (two or more) may be electrically connected to the first data lines 111 that are not electrically connected to the connection lines 120 in one-to-one correspondence.

[0110] It is understood that the number of the above fan-out lines 130 (including the first fan-out line 131 and the second fan-out line 132) may be the same as the number of the data lines 110 (including the first data line 111 and the second data line 112). A signal outputted by the driving IC may be transmitted through one fan-out line 130 to one data line 110 electrically connected to the fan-out line 130, thereby realizing driving of one column of sub-pixels 101.

[0111] 7 , the central axis of the display substrate 100 along the second direction Y is defined as a first central axis Q. That is, the first central axis Q is located at the center of the display substrate 100 along the first direction X and is parallel to the base 102. It is understood that the first central axis Q is an imaginary reference line, and the first central axis Q is located within the central area AA2 of the display substrate 100.

[0112] As shown in FIG. 7, since the second end of the connecting line 120 extends to the boundary between the central region AA2 and the fan-out region BB, it can be understood that the multiple first fan-out lines 131 may be electrically connected to the second end of the connecting line 120 at a position closer to the first central axis Q of the display substrate 100.

[0113] By arranging in this manner, when the multiple fan-out lines 130 gather in the fan-out region BB and extend in a direction away from the display region AA, it is possible to reduce the space occupied along the second direction Y. This makes it possible to reduce the width of the fan-out region BB in the second direction Y, for example, to significantly reduce the width of the first fan-out region BB1 in the second direction Y. This makes it possible to reduce the width of the side frame (for example, the bottom frame) of the display panel 210, thereby enabling the display panel 210 to realize an ultra-narrow bottom frame, and improving the visual effect of the display panel 210.

[0114] Also, as can be seen from the above, the round corner is located within the edge area AA1 of the display area AA. Therefore, by adopting the above installation method, the first data line 111 at the round corner position can be electrically connected to the first fan-out line 131 through the connection line 120, and the first fan-out line 131 can be prevented from occupying the space of the fan-out area BB close to the round corner position, so that the frame width at the round corner can be reduced, and the display area AA of the display panel 210 can realize an extra-large round corner. In this way, the visual effect of the display panel 210 can be improved, while the installation convenience between the outer frame of the display panel 210 and the display panel 210 can be improved, the stress that the frame receives during installation can be reduced, and the possibility of wrinkles and cracks in the frame due to the installation stress can be reduced, and the processing convenience of the display device 200 can be improved, and the yield of the display device 200 can be further improved.

[0115] In addition, since the first data lines 111 located in the edge region AA1 can be electrically connected to the first fan-out lines 131 via the connection lines 120, it is advantageous to reduce the length of the first fan-out lines 131 electrically connected to the first data lines 111 (for example, in the solution shown in FIG. 7, the first fan-out lines 131 include first sub-fan-out lines 133, and the first to third first sub-fan-out lines 133 arranged from left to right along the first direction X are connected to the first data line 111 via the connection lines 130). When connected to the first data line 111, the shortening amount of the third first sub-fan-out line 133 is greater than that of the second first sub-fan-out line 133, which in turn is greater than that of the first first sub-fan-out line 133, which is advantageous for reducing the resistance of the first fan-out line 131, i.e., reducing the resistance on the first data line 111, and improving the brightness of the sub-pixels electrically connected to the first data line 111. Meanwhile, the length of the second fan-out line 132 does not change, i.e., the resistance is basically unchanged, and the length of the first fan-out line 131 is reduced so as to approach the length of the second fan-out line 132. Still referring to FIG. 7 , the second fan-out line 132 includes a third sub-fan-out line 136. Taking the above third first sub-fan-out line 133 as an example, the shortened length of the third first sub-fan-out line 133 is smaller than the length of the third sub-fan-out line 136 adjacent to the left side (in the illustrated direction), so the resistance of the third first sub-fan-out line 133 is smaller than the resistance of the third sub-fan-out line 136 adjacent to the left side. Based on this, the third first sub-fan-out line 133 is further connected to a connection line 120, and the connection line 120 is located in a source-drain metal layer SD (which may include a titanium / aluminum / titanium stacked structure) having a very small resistance, so that the total resistance of the third first sub-fan-out line 133 and the connection line 120 may be slightly smaller than or equal to the resistance of the third sub-fan-out line 136 adjacent to the left side of the third first sub-fan-out line 133.In other words, the resistance on the first data line 111 electrically connected to the third first sub-fan-out line 133 is slightly smaller than or equal to the resistance on the second data line 112 electrically connected to the third sub-fan-out line 136 adjacent to the left side (in the illustrated orientation) of the third first sub-fan-out line 133, which is also advantageous for the resistance difference between the first data line 111 and the second data line 112 and improves the brightness uniformity of the display screen.

[0116] In addition, the connecting line 120 is also added between the first fan-out line 131 and the first data line 111, but since the connecting line 120 is located in at least one source-drain metal layer SD, the source-drain metal layer SD includes a titanium / aluminum / titanium composite laminate structure, and the resistance is much smaller, for example, 1 / 10, compared with the gate metal layer Gate (including a molybdenum material). Therefore, when the connecting line 120 is increased, the resistance on the first data line 111 increases slightly, but the increased resistance is much smaller than the resistance decreased by shortening the first fan-out line 131. Therefore, in some of the above embodiments, it is also advantageous to reduce the resistance on the first data line 111 and balance the resistance difference between the first data line 111 and the second data line 112, thereby improving the luminance uniformity of the display screen.

[0117] For example, the fan-out method of increasing the number of connection lines 120 may be called FIAA (full English name: Fanout In AA) or FIP (full English name: Fanout In Panel).

[0118] As can be seen from the above, in some examples, the number of the connecting lines 120 may be set to be the same as the number of the first data lines 110, as shown in Fig. 7. In this case, the first data lines 111 are connected to the connecting lines 120 in one-to-one correspondence. Exemplarily, this setting manner may be referred to as a global FIAA.

[0119] In some other examples, some of the first data lines 111 may be connected to the connecting lines 120 in one-to-one correspondence, and other parts of the first data lines 111 may not be connected to the connecting lines 120. For example, similar to the second data lines 112, they may be directly drawn out through the second fan-out lines 132. Such an arrangement is advantageous for reducing the interval between the multiple data lines 110 and improving the pixel density of the display area AA, so that the display panel 210 can achieve a high PPI (English formal name: Pixels Per Inch). Exemplarily, this arrangement may be called partial FIAA.

[0120] As described above, by using the full FIAA or partial FIAA method, the display panel 210 can achieve a narrow frame on a high resolution. In some examples, the display panel may be a QHD (Quad High Definition) display panel.

[0121] 7, in some embodiments, any two adjacent connection lines 120 may be defined as a first connection line 120a and a second connection line 120b. It is understood that in this embodiment, the first connection line 120a and the second connection line 120b are used only to distinguish the two adjacent connection lines 120, and do not further limit the connection lines 120.

[0122] 7, the first data line 111 electrically connected to the first end of the first connecting line 120a is farther away from the first central axis Q of the display substrate 100 than the first data line 111 electrically connected to the first end of the second connecting line 120b. Also, the second end of the first connecting line 120a is closer to the first central axis Q of the display substrate than the second end of the second connecting line 120b. Exemplarily, the above connection manner may be referred to as reverse order FIAA.

[0123] In some other examples, the first data line 111 electrically connected to the first end of the first connection line 120a is closer to the first central axis Q of the display substrate 100 than the first data line 111 electrically connected to the first end of the second connection line 120b. Also, the second end of the first connection line 120a is closer to the first central axis Q of the display substrate 100 than the second end of the second connection line 120b. Exemplarily, the above connection method may be called the forward FIAA.

[0124] When the first data line 111 is electrically connected to the first fan-out line 131 via the connection line 120 (for example, using the reverse FIAA or forward FIAA as described above), the order in which the ends (for example, the ends electrically connected to the driving IC) of the plurality of fan-out lines 130 (including the first fan-out line 131 and the second fan-out line 132) that are away from the display area AA are arranged along the first direction X is different from the order in which the plurality of data lines 110 (including the first data line 111 and the second data line 112) are arranged along the first direction X. This is understood.

[0125] Exemplarily, one edge in the first direction X of the display substrate 100 may be defined as the first edge. It is understood that the first edge is any one of the two edges in the first direction X of the display substrate 100.

[0126] Exemplarily, a plurality of data lines 110 (including the first data line 111 and the second data line 112) arranged at intervals along the direction from the first edge of the display substrate 100 to the first central axis Q of the display substrate 100 may be defined as data line 1 to data line n. Here, data line 1 to data line m (m < n) are located in the edge region AA1, and data line m + 1 to data line n are located in the central region AA2. That is, data line 1 to data line m are the first data line 111, and data line m + 1 to data line n are the second data line 112.

[0127] As can be seen from the above, the first end of the connecting line 120 is electrically connected to the first data line 111, and the second end of at least one connecting line 120 is located between two adjacent second data lines 112. Exemplarily, the second end of the connecting line 120 electrically connected to the data line 1 can be located between the data line m+1 and the data line m+2 (forward FIAA), or the second end of the connecting line 120 electrically connected to the data line 1 can be located between the data line n-1 and the data line n (reverse FIAA). That is, the second end of the connecting line 120 is inserted between two adjacent second data lines 112 (e.g., data line m+1 and data line m+2).

[0128] In this way, when the first fan-out line 131 is electrically connected to the second end of the connection line 120 and the second fan-out line 132 is electrically connected to the end of the second data line 112 close to the fan-out region BB, at least one first fan-out line 131 is inserted between two adjacent second fan-out lines 132.

[0129] Exemplarily, a plurality of fan-out lines 130 (including a first fan-out line 131 and a second fan-out line 132) electrically connected to the data lines 1 to n in one-to-one correspondence may be defined as fan-out lines 1 to n. The fan-out line 1 is electrically connected to the data line 1, and the fan-out line 2 is electrically connected to the data line 2, as analogized above.

[0130] Since at least one first fan-out line 131 is inserted between two adjacent second fan-out lines 132, the ends of fan-out lines 1 to n away from the display area AA (i.e., the ends where the multiple fan-out lines 130 are electrically connected to the driving IC) cannot be arranged in sequence along the direction from the first edge to the first central axis Q.

[0131] As can be seen from the above, the data lines 1 to n are spaced apart from each other along the direction from the first edge to the first central axis Q. That is, if wiring is performed using the full FIAA or partial FIAA method, the arrangement order of the multiple fan-out lines 130 (including the first fan-out line 131 and the second fan-out line 132) in the first direction X at the end away from the display area AA will be different from the arrangement order of the multiple data lines 110 (including the first data line 111 and the second data line 112) in the first direction X.

[0132] For example, the driving IC has an output end, and the arrangement order of the output end of the driving IC along the first direction X is the same as the arrangement order of the multiple data lines 110 along the first direction X. It is understood that the arrangement order of the ends of the multiple fan-out lines 130 (including the first fan-out line 131 and the second fan-out line 132) away from the display area AA along the first direction line X is different from the arrangement order of the multiple data lines 110 (including the first data line 111 and the second data line 112) along the first direction X, so that the output end of the driving IC cannot output driving signals to the multiple data lines 110 in sequence, that is, the driving IC cannot drive the emission of the sub-pixels 101 in multiple columns in sequence. Meanwhile, redevelopment of the driving IC is relatively expensive, leading to an increase in the cost of the display panel 210.

[0133] In some embodiments, the display substrate 100 further includes a bending region CC, as shown in Fig. 7. The fan-out region BB includes a first fan-out region BB1 and a second fan-out region BB2, where the first fan-out region BB1 is closer to the display area AA than the second fan-out region BB2, and the bending region CC is located between the first fan-out region BB1 and the second fan-out region BB2.

[0134] Exemplarily, the base 102 is a flexible base. The base 102 and at least one of the plurality of conductive layers 103 are provided in the bending region CC. The base 102 and at least one of the plurality of conductive layers 103 are bendable in the bending region CC.

[0135] In some examples, the base 102 and the second source-drain metal layer SD2 are provided in the bending region CC. The bending region CC is located between the first fan-out region BB1 and the second fan-out region BB2, so that the second fan-out region BB2 can be bent to the rear surface of the portion located in the display region AA of the display substrate 100, and the second fan-out region BB2 can be prevented from occupying space on the display side of the display substrate 100, thereby further reducing the width of the side frame (e.g., the bottom frame) of the display panel 210 and improving the visual effect of the display panel 210.

[0136] In some embodiments, as shown in Figure 7, the display substrate 100 further includes a chip on panel (COP) area. The COP area is used to mount a driving IC. The second fan-out area BB2 is located between the bending area CC and the COP area.

[0137] In some examples, as shown in FIG. 7, the display substrate 100 further includes a cell test (CT) region. The CT region is used to test the display substrate 100. In this case, the second fan-out region BB2 may be located between the CT region and the COP region. In this case, the distance between the CT region and the bending region CC may be 0 (i.e., there may be no intermediate fan-out region BB0 shown in FIG. 7) or may not be 0 (i.e., there may be an intermediate fan-out region BB0 shown in FIG. 7).

[0138] Additionally, if intermediate fan-out region BB0 is included, intermediate fan-out region BB0 may be part of second fan-out region BB2 (not shown) or may not be part of second fan-out region BB2 (as shown in FIG. 7).

[0139] In some examples, the display substrate 100 further includes an ILB (Inner Lead Bonding) area (not shown) and a FOP (Flexible Printed Circuit On Panel) area (not shown). The ILB area and the FOP area are located on the side of the COP area away from the second fan-out area BB2. In some examples, some pins of the driving IC may be electrically connected to pins of the FOP area through wiring in the ILB area, and the pins of the FOP area may be used to connect an external flexible circuit board.

[0140] As can be seen from the above description, in the above-mentioned several embodiments of the present disclosure, when using the FIAA method to connect several data lines 110 to the driving IC, it may be full FIAA (i.e., all the first data lines 111 in the edge area AA1 are all drawn out through the connecting lines 120), or partial FIAA (i.e., some of the first data lines 111 in the edge area AA1 are drawn out through the connecting lines 120), and may be forward FIAA or reverse FIAA. In the following, several embodiments of the present disclosure will be described by taking the full FIAA and reverse FIAA methods shown in FIG. 7 as examples.

[0141] 7, the first fan-out line 131 includes a transfer line 134. The transfer line 134 is located in the second fan-out region BB2. The transfer line 134 is located in a different conductive layer 103 from the second fan-out lines 132, and the transfer line 134 spans at least one second fan-out line 132, so that the arrangement order of the ends of the fan-out lines 130 away from the display area AA in the first direction X is the same as the arrangement order of the data lines 110 in the first direction X.

[0142] In the embodiments of the present disclosure, it is understood that one wire "crosses" another wire when at least a portion of the wire is located on a different conductive layer 103 than the other wire, and when an orthogonal projection of at least a portion of the wire on the base 102 intersects with an orthogonal projection of the other wire on the base 102, thereby achieving the "crossing" of the other wire.

[0143] It is understood that the transfer line 134 spans at least one second fan-out line 132, i.e., an orthogonal projection of the transfer line 134 at the base 102 intersects an orthogonal projection of the at least one second fan-out line 132 at the base 102. By locating the transfer line 134 on a different conductive layer 103 than the plurality of second fan-out lines 132, the transfer line 134 can be insulated from the plurality of second fan-out lines 132.

[0144] In some examples, the multiple transfer lines 134 may be located in one conductive layer 103 or multiple conductive layers 103. Illustratively, when the multiple transfer lines 134 are located in multiple conductive layers 103, any one of the transfer lines 134 is located in a different conductive layer 103 than the multiple second fan-out lines 132.

[0145] In some examples, when the transfer lines 134 are located in multiple conductive layers 103, any two adjacent transfer lines 134 may be located in different conductive layers 103. In some examples, the transfer lines 134 may be located in the second source-drain metal layer SD2 and / or the third source-drain metal layer. Illustratively, when the transfer lines 134 are located in the second source-drain metal layer SD2 and the third source-drain metal layer, any two adjacent transfer lines 134 may be located in different source-drain metal layers SD (including the second source-drain metal layer SD2 or the third source-drain metal layer).

[0146] As shown in FIG. 7, by arranging the transfer line 134 across at least one second fan-out line 132 and insulated from the multiple second fan-out lines 132, the arrangement order of the multiple first fan-out lines 131 along the first direction X at their ends away from the display area AA can be adjusted by adjusting the extension direction, extension length, etc. of the transfer line 134.

[0147] That is, by arranging the transfer line 134 to span at least one second fan-out line 132, the arrangement order of the ends of the first fan-out line 131 away from the display area AA (i.e., the ends where the first fan-out line 131 is electrically connected to the driving IC) can be adjusted, and therefore the arrangement order of the ends of the multiple fan-out lines 130 away from the display area AA (i.e., the ends where the multiple fan-out lines 130 are electrically connected to the driving IC) can be adjusted. In this way, the ends of the fan-out lines 1 to n away from the display area AA can be arranged in sequence with intervals along the direction from the first edge to the first central axis Q, whereby the ends of the multiple fan-out lines 130 away from the display area AA can be arranged in the same order as the arrangement order of the multiple first data lines 110 along the first direction X.

[0148] As a result, the arrangement order of the output ends of the driving ICs in the first direction X, the arrangement order of the ends of the fan-out lines 130 away from the display area AA in the first direction X, and the arrangement order of the data lines 110 in the first direction X can be made the same, and the output ends of the driving ICs can provide driving signals to the data lines 110 in sequence, i.e., the driving ICs can drive the emission of the sub-pixels 101 in multiple columns in sequence. This eliminates the need to redevelop the driving ICs, enables the display substrate 100 to achieve a narrow frame, and reduces the cost of the display substrate 100.

[0149] In addition, locating the transfer line 134 in the second fan-out region BB2 prevents the transfer line 134 from occupying space in the first fan-out region BB1, and reduces the width of the first fan-out region BB1. Because the first fan-out region BB1 is located on the side of the bending region CC closer to the display area AA, reducing the width of the first fan-out region BB1 can further reduce the width of the bottom border of the display substrate 100, thereby improving the visual effect of the display panel 210.

[0150] In some examples, the first fan-out line 131 is electrically connected to the output end of the driving IC directly via the transfer line 134. In some other examples, the first fan-out line 131 further includes another part of wiring, and the first fan-out line 131 is electrically connected to the output end of the driving IC via the other part of wiring.

[0151] In some embodiments of the present disclosure, still referring to FIG. 7, the transfer line 134 includes a main body 1340 and two connection ends (G1, G2). The main body 1340 is located on the side of the two connection ends (G1, G2) closer to the display area AA. Hereinafter, for convenience of explanation, the connection end closer to the first central axis Q is defined as the first connection end G1, and the connection end away from the first central axis Q is defined as the second connection end G2.

[0152] For example, the first connection end G1 may be used to connect a portion of the first fan-out line 131 close to the display area AA, and the second connection end G2 may be used to connect a portion of the first fan-out line 131 close to the COP area.

[0153] 7 , the first fan-out line 131 further includes a first sub-fan-out line 133 and a second sub-fan-out line 135. The first connection end G1 is electrically connected to the first sub-fan-out line 133 and is electrically connected to the connection line 120 through the first sub-fan-out line 133. The second connection end G2 is electrically connected to the second sub-fan-out line 135 and is electrically connected to the driving IC through the second sub-fan-out line 135.

[0154] 7, the second fan-out line 132 includes a third sub-fan-out line 136 and a fourth sub-fan-out line 137. One end of the third sub-fan-out line 136 is electrically connected to the second data line 112, the other end of the third sub-fan-out line 136 is electrically connected to the fourth sub-fan-out line 137, and the end of the fourth sub-fan-out line 137 away from the third sub-fan-out line is electrically connected to a driving IC.

[0155] Exemplarily, along the first direction X, the third sub-fan-out lines 136 are alternately arranged with the first sub-fan-out lines 133. For example, four third sub-fan-out lines 136 may be arranged as one group, two first sub-fan-out lines 133 may be arranged as one group, and the lines may be alternately arranged between the groups (i.e., 4-insert-2 manner). Of course, the embodiment of the present disclosure is not limited thereto, and may be, for example, 3-insert-1 manner, 4-insert-3 manner, etc. Based on this, adjacent sub-fan-out lines (e.g., adjacent third sub-fan-out line 136 and first sub-fan-out line 133, or adjacent two third sub-fan-out lines 136, or adjacent two first sub-fan-out lines 133) may be located in different gate metal layers Gate. For example, one of them is located in the first gate metal layer Gate1, and the other is located in the second gate metal layer Gate2. This arrangement is advantageous for reducing signal crosstalk between adjacent sub-fan-out lines.

[0156] In some examples, by using the FIAA scheme, the crossing angle between the portions of the third sub-fan-out line 136 and the first sub-fan-out line 133 located in the first fan-out region BB1 and the first central axis Q tends to be smaller, i.e., to be parallel to the first central axis Q. Therefore, in the first fan-out region BB1, there may be more distance between the third sub-fan-out line 136 and the first sub-fan-out line 133, between the two third sub-fan-out lines 136, and between the two first sub-fan-out lines 133. Therefore, the portions of the third sub-fan-out line 136 and the first sub-fan-out line 133 located in the first fan-out region BB1 may be arranged to be located in the same source-drain metal layer SD, or to be located in different source-drain metal layers SD alternately along the first direction X. As a result, the third sub-fan-out line 136 and the first sub-fan-out line 133 can have a smaller resistance, i.e., the first data line 111 and the second data line 112 can have a smaller resistance, which is beneficial to improving the display brightness of the display substrate 100.

[0157] In addition, in order to reduce resistance, the portions of either the third sub-fan-out line 136 or the first sub-fan-out line 133 located in the bending region CC may be arranged to be located in a film layer other than the gate metal layer (e.g., any of the source / drain metal layers), and the embodiments of the present disclosure are not limited thereto.

[0158] 7, some of the wirings located in the second fan-out region BB2 of both the first sub-fan-out line 133 and the third sub-fan-out line 136 need to be arranged at an angle, thereby realizing further concentration and facilitating the subsequent electrical connection between the fourth sub-fan-out line 137 and the driving IC via the transfer line 134 and the second sub-fan-out line 135. Here, in the second direction Y, the width of the second fan-out region BB2 occupied by the some of the inclined wirings is greater than the width of the second fan-out region BB2 occupied by both the second sub-fan-out line 135 and the fourth fan-out line 137.

[0159] Based on this, when the body part 1340 is installed so as to be located on the side closer to the COP area of ​​the two connection ends (G1, G2), the width of the second fan-out region BB2 along the second direction needs to be further increased, in which case the length of the second sub-fan-out line 135 and the length of the fourth sub-fan-out line 137 increase, which increases the resistance of the plurality of data lines 110, thereby affecting the display brightness of the display substrate 100 and the display effect of a low grayscale screen.

[0160] In the above-mentioned several embodiments of the present disclosure, since the body portion 1340 is located on the side of the two connection ends (G1, G2) close to the display area AA, the body portion 1340 overlaps with the area where both the first sub-fan-out line 133 and the third sub-fan-out line 136 are located in the thickness direction of the base 102. By designing in this way, since the width of the second fan-out region BB2 occupied by the inclined wiring in the first sub-fan-out line 133 and the third sub-fan-out line 136 in the second direction Y is relatively large, there is no need to extend the first fan-out line 133 and the third fan-out line 136, which is advantageous for reducing the space occupied by the fan-out line 130 in the second direction Y of the second fan-out region BB2, and thus advantageous for reducing the width of the second fan-out region BB2 in the second direction Y. In addition, it is also advantageous to reduce the length of the second fan-out line 135 and the length of the fourth sub-fan-out line 137, i.e., it is advantageous to reduce the resistance of the multiple data lines 110 compared to the above-mentioned solution in which the body portion 1340 is located closer to the COP area of ​​the two connection ends (G1, G2), thereby being advantageous to improve the display brightness of the display substrate 100 and the display effect of low gray-scale screens.

[0161] 7, the display substrate 100 further includes an isolation block 140. The isolation block 140 separates the transfer line 134 from the first sub-fan-out line 133, and separates the transfer line 134 from the third sub-fan-out line 136.

[0162] Exemplarily, the first sub-fan-out line 133 and the third sub-fan-out line 136 are located in at least one gate metal layer Gate. The transfer line 134 is located in the second source-drain metal layer SD2 and / or the third source-drain metal layer SD3. The isolation block may be located in the first source-drain metal layer SD1.

[0163] In this embodiment, this arrangement is advantageous for reducing signal crosstalk between the transfer line 134 and the first sub-fan-out line 133, and for reducing signal crosstalk between the transfer line 134 and the third sub-fan-out line 136, thereby improving the brightness uniformity in the display area AA and making it less likely that multiple sub-pixels of the display substrate 100 will cause problems such as flickering and dark line defects.

[0164] 7, the isolation block 140 may be connected to a voltage signal line 141, i.e., the isolation block 140 may be configured to transmit a voltage signal. Exemplarily, the voltage signal line 141 may be any of signal lines such as, but not limited to, a Vdd signal line that provides a voltage to the anode of the light-emitting element 300, a Vss signal line that provides a voltage to the cathode of the light-emitting element 300, and the like.

[0165] By isolating the transfer line 134 from the first sub-fan-out line 133 and the transfer line 134 from the third sub-fan-out line 136 by the isolation block 140 configured to transmit a voltage signal, there is no need to install additional components, the manufacturing process is simplified, and the cost of the display substrate 100 is reduced.

[0166] Fig. 8 is a partial structural diagram of a display substrate according to some embodiments. Fig. 9 is a structural diagram of a first gate metal layer, a second gate metal layer, and a first source-drain metal layer of Fig. 8. Fig. 10 is a structural diagram of a second source-drain metal layer and a third source-drain metal layer of Fig. 8.

[0167] 8 to 10, an area located on one side of the first central axis Q of the second fan-out area BB2 is one sub-fan-out area BBZ. In the following, the wiring method in one sub-fan-out area BBZ will be mainly described. It is understood that the wiring methods in two sub-fan-out areas BBZ may be the same or different.

[0168] In some embodiments of the present disclosure, as shown in FIGS. 8 to 10, the display substrate 100 includes a first gate metal layer Gate1, a second gate metal layer Gate2, a first source-drain metal layer SD1, a second source-drain metal layer SD2, and a third source-drain metal layer SD3, which are arranged in order away from the base 102. The display substrate 100 also includes a first fan-out region BB1, a bending region CC, a middle fan-out region BB0 (optional), a CT region, a second fan-out region BB2, a COP region, an ILB region, and an FOP region, which are arranged in order away from the display region AA. Here, the portion of the bending region CC of the display substrate 100 located on the side away from the display region AA may be bent to the rear surface of the portion of the display substrate 100 located on the side away from the display region AA, thereby preventing the portion of the bending region CC of the display substrate 100 located on the side away from the display region AA from occupying the space on the display side of the display substrate 100, thereby reducing the width of the side frame (e.g., the bottom frame) of the display panel 210 and improving the visual effect of the display panel 210.

[0169] In some embodiments, as shown in Figures 8 and 10, the transfer line 134 is U-shaped or approximately U-shaped. The opening of the transfer line 134 faces the COP area.

[0170] It will be understood that a U-shaped or approximately U-shaped transfer line 134 may span at least one second fan-out line 132, thereby adjusting the arrangement order of the ends of the first fan-out lines 131 away from the display area AA in the first direction X, so that the ends of fan-out lines 1 to n away from the display area AA may be spaced apart in sequence along the direction from the edge to the first central axis Q, i.e., the arrangement order of the ends of the multiple fan-out lines 130 away from the display area AA in the first direction X may be the same as the arrangement order of the multiple first data lines 110 in the first direction X.

[0171] 9, the isolation block 140 is located on a side of the second gate metal layer Gate2 that is away from the first gate metal layer Gate1. For example, the isolation block 140 may be located on the first source-drain metal layer SD1.

[0172] Based on this, exemplarily, any of the first sub-fan-out line 133 and the third sub-fan-out line 136 is located in the first gate metal layer Gate1 and / or the second gate metal layer Gate2, and the transfer line 134 is located in the second source-drain metal layer SD2 and / or the third source-drain metal layer. Therefore, the isolation block 140 may be used to separate the transfer line 134 from the first sub-fan-out line 133 and to separate the transfer line 134 from the third sub-fan-out line 136. This is advantageous for reducing signal crosstalk between the transfer line 134 and the first sub-fan-out line 133 and between the transfer line 134 and the third sub-fan-out line 136, thereby improving the luminance uniformity of the display substrate 100 and making the display substrate 100 less susceptible to problems such as flickering and dark line defects.

[0173] Fig. 11 is a partial structural diagram of region 001 in Fig. 8. Figs. 12 to 17 are structural diagrams of each film layer in Fig. 11.

[0174] In some embodiments, multiple transfer lines 134 are radially arranged in one sub-fan-out region as shown in Fig. 11. Here, "radially arranged" refers to the arrangement of any two adjacent transfer lines 134, in which the outer transfer line 134 surrounds the inner transfer line 134, that is, for example, the arrangement shown in Fig. 11.

[0175] Illustratively, each transfer line 134 is U-shaped, with the inner transfer line 134 positioned generally within the outer transfer line 134 .

[0176] In this embodiment, of the two adjacent transfer lines 134, the outer transfer line 134 is arranged to surround the inner transfer line 134, which is advantageous for saving wiring space, increasing the distance between the transfer lines 134, and reducing signal crosstalk. It is also advantageous for reducing the dimension of the second fan-out region BB2 of the display substrate 100 along the second direction Y, and for making the bottom frame of the display substrate 100 narrower.

[0177] For example, adjacent transfer lines 134 may be substantially parallel to each other. In this manner, the intervals between adjacent transfer lines 134 can be substantially consistent, which is advantageous for reducing signal interference between the adjacent transfer lines 134 and improving the luminance uniformity of the display screen of the display substrate.

[0178] In some embodiments, two adjacent transmission lines are located in different conductive layers, as shown in Fig. 11. This arrangement is advantageous for further improving the signal interference problem between adjacent transmission lines 134, and thus for further improving the luminance uniformity of the display screen of the display substrate.

[0179] 12 and 13, in some embodiments, the first fan-out line 131 further includes a first wiring segment 1311 and a second wiring segment 1312 that are sequentially farther away from the display area AA and electrically connected to each other. That is, a first sub-fan-out line 133 in the first fan-out line 131 may include a first wiring segment 1311 and a second wiring segment 1312 that are sequentially farther away from the display area AA and electrically connected to each other. The first wiring segment 1311 gradually approaches the first central axis Q from an end closer to the display area AA to an end farther away from the display area AA. The second wiring segment 1312 is parallel to the first central axis Q.

[0180] The second fan-out line 132 includes a third wiring segment 1321 and a fourth wiring segment 1322 which are successively farther away from the display area AA and which are electrically connected to each other. That is, the third sub-fan-out line 136 in the second fan-out line 132 may include a third wiring segment 1321 and a fourth wiring segment 1322 which are successively farther away from the display area AA and which are electrically connected to each other. The third wiring segment 1321 gradually approaches the first central axis Q from the end closer to the display area AA to the end farther away from the display area AA. The fourth wiring segment 1322 is parallel to the first central axis Q.

[0181] 16 and 17, the transfer line 134 includes a connection end portion close to the first center axis Q (i.e., the first connection end portion G1) and a connection end portion away from the first center axis Q (i.e., the second connection end portion G2). Here, the connection end portion close to the first center axis Q (i.e., the first connection end portion G1) of the transfer line 134 may be electrically connected to the end portion a1 of the second wiring segment 1312 away from the first wiring segment 1311 in FIGS. 12 and 13.

[0182] The interlayer medium layer ILD shown in Fig. 14 includes a first contact hole 161 and a second contact hole 162. The first source-drain metal layer SD1 shown in Fig. 15 includes a first transfer portion M1 and a second transfer portion M2.

[0183] Two adjacent second wiring segments 1312 are respectively located on the first gate metal layer Gate1 and the second gate metal layer Gate2. Of the ends a1 of the two adjacent second wiring segments 1312, the end a1 of the second wiring segment 1312 located on the first gate metal layer Gate1 may be electrically connected to the first transfer unit M1 located on the first source-drain metal layer SD1 via the first connection hole 161, and the end a1 located on the second gate metal layer Gate2 may be directly electrically connected to the second transfer unit M2 located on the first source-drain metal layer SD1 via the second connection hole 162.

[0184] As can be seen from the above description, the transfer hole electrically connected to the conductive wiring on the first source-drain metal layer SD1 and the conductive wiring on the second source-drain metal layer SD2 may be called a PLN1 hole, and the transfer hole electrically connected to the conductive wiring on the second source-drain metal layer SD2 and the conductive wiring on the third source-drain metal layer may be called a PLN2 hole. Therefore, the first connection end G1 of the transfer line 134 in the second source-drain metal layer SD2 shown in FIG. 16 may be electrically connected to the second transfer section M2 through the PLN1 hole. Since the second transfer section M2 is electrically connected to the end a1 of one second wiring segment 1312, the first connection end G1 of the transfer line 134 in the second source-drain metal layer SD2 shown in FIG. 16 may be electrically connected to the end a1 of one second wiring segment 1312.

[0185] Based on this, the second source-drain metal layer SD2 shown in FIG. 16 may further include a third transfer portion M3. The first connection end G1 of the transfer line 134 in the third source-drain metal layer SD3 shown in FIG. 17 may be electrically connected to the third transfer portion M3 through the PLN2 hole, and the third transfer portion M3 may be electrically connected to the first transfer portion M1 through the PLN1 hole. Since the first transfer portion M1 is electrically connected to the end a1 of the other second wiring segment 1312, the first connection end G1 of the transfer line 134 in the third source-drain metal layer SD3 shown in FIG. 17 may be electrically connected to the end a1 of the other second wiring segment 1312.

[0186] In some embodiments, the second source-drain metal layer SD2 further includes a fourth transfer portion M4 as shown in Figure 16. The third source-drain metal layer SD3 further includes a fifth transfer portion M5 as shown in Figure 17.

[0187] The second connection end G2 of the transfer line 134 in the second source-drain metal layer SD2 may be electrically connected to the fifth transfer portion M5 in the third source-drain metal layer SD3 through a PLN2 hole, and the second connection end G2 of the transfer line 134 in the third source-drain metal layer SD3 may be electrically connected to the fourth transfer portion M4 in the second source-drain metal layer SD2 through a PLN2 hole. This arrangement is advantageous in balancing the difference in parasitic capacitance between adjacent transfer lines 134 located in different layers.

[0188] Based on this, as shown in FIG. 15, the first source-drain metal layer SD1 includes a first extension wiring N1 and a second extension wiring N2.

[0189] The second connection end G2 and the fourth transfer portion M4 of the transfer line 134 in the second source-drain metal layer SD2 may be electrically connected to different first extension wirings N1 via different PLN1 holes, respectively.

[0190] As shown in FIG. 12, the first gate metal layer Gate1 includes a seventh transfer section M7 and a second virtual transfer section M02. As shown in FIG. 13, the second gate metal layer Gate2 includes a sixth transfer section M6 and a first virtual transfer section M01. As shown in FIG. 14, the interlayer medium layer ILD further includes a third connection hole 163. The first extension wirings N1 are transferred to the first virtual transfer section M01 and the second virtual transfer section M02 via some of the third connection holes 163, and the second extension wirings N2 are transferred to the sixth transfer section M6 and the seventh transfer section M7 via other some of the third connection holes.

[0191] In the above manner, both the first fan-out line 131 and the second fan-out line 132 may be transferred to the first source-drain metal layer SD1. Also, by providing the first virtual transfer section M01 and the second virtual transfer section M02, it is possible to balance the difference in parasitic capacitance between the multiple fan-out lines 130 caused by the transfer between different layers.

[0192] 14, the interlayer medium layer ILD further includes a fourth connection hole 164. The first extension wiring N1 and the second extension wiring N2 may be transferred to a pin 150 located in the first gate metal layer Gate1 through the fourth connection hole 164. The pin 150 in the first gate metal layer Gate1 may be used to connect a driving IC. By locating all the pins for connecting the driving IC in the first gate metal layer Gate1, it is advantageous to improve the stability of the driving IC after welding.

[0193] 12, the first gate metal layer Gate1 further includes a third virtual transfer portion M03. As shown in FIG.

[0194] The first extension wiring N1 may be transferred to the third virtual transfer portion M03 located in the first gate metal layer Gate1 through the fifth connection hole 165. Such an arrangement is advantageous in balancing the difference in parasitic capacitance between the multiple fan-out lines 130 caused by transfer between different layers.

[0195] 11, in some examples, in the region 002 (i.e., the lattice-shaped rectangular region in FIG. 11), an insulating layer may not be provided between the first source-drain metal layer SD1 and the second source-drain metal layer SD1. That is, the first extension wiring N1 and the second extension wiring N2 provided here may be a stacked structure in which the first source-drain metal layer SD1 and the second source-drain metal layer SD2 are simultaneously located. Such an arrangement is advantageous for reducing the resistance on the first extension wiring N1 and the second extension wiring N2, and thus for improving the display effect of the display substrate 100.

[0196] In some embodiments, as shown in FIGS. 11, 12, and 13, the first wiring segments 1311 are alternately arranged with the third wiring segments 1321 in the sub-fan-out region BBZ.

[0197] 12 and 13, four adjacent third sub fan-out lines 136 may be divided into a first wiring group, two adjacent first sub-lines may be divided into a second wiring group, and the first wiring group and the second wiring group may be arranged alternately, that is, in a "4-insert-2" manner. In some other examples, wiring may be performed using a "3-insert-1" or "4-insert-3" manner, and may be flexibly arranged according to factors such as wiring space.

[0198] Referring to Figures 12 and 13, the fitting straight line L defined by the end of the first wiring segment 1311 away from the display area AA and the end of the third wiring segment 1321 away from the display area AA gradually approaches the display area AA from the end away from the first central axis Q to the end close to the first central axis Q.

[0199] With this arrangement, the arrangement range of the ends a1 of the second wiring segments 1312 away from the display area AA along the second direction Y may be increased, so that the positions of the ends a1 of different second wiring segments 1312 may be adjusted to achieve balancing of the resistance difference between the multiple first fan-out lines 131, which is also advantageous in balancing the resistance difference between the multiple first fan-out lines 131 and the multiple second fan-out lines 132. In this way, the resistance difference between the multiple first data lines 111 and the multiple second data lines 112 is reduced, and the brightness uniformity of the display substrate 100 is improved.

[0200] In some examples, as shown in FIG. 11, in a sub-fan-out region BBZ, among a plurality of second wiring segments 1312, at least two (e.g., two) directly adjacent second wiring segments 1312 are in the same group, and ends a1 of the second wiring segments 1312 in the same group that are away from the display region AA are offset along the first direction X.

[0201] In this example, the ends of the second wiring segments 1312 in the same group that are away from the display area AA are offset along the first direction, which is advantageous for saving wiring space and reducing signal crosstalk between adjacent second wiring segments, thereby improving the brightness uniformity of the display substrate 100.

[0202] In some examples, in the sub-fan-out region BBZ, of two adjacent second wiring segments 1312, the length of the second wiring segment 1312 closer to the first central axis Q is shorter than the length of the second wiring segment 1312 away from the first central axis Q. Of two adjacent transfer lines 134, the connection end for connecting the second wiring segment 1312 in the transfer line 134 closer to the first central axis Q (i.e., the first connection end G1) is closer to the display region AA than the connection end for connecting the second wiring segment 1312 in the transfer line 134 away from the first central axis Q (i.e., the second connection end G2).

[0203] In addition, for the reverse FIAA shown in Figure 7, the closer the first sub-fan-out line 133 is to the first central axis Q, the closer the connected first data line is to the edge along the first direction X of the display area, so that the connection line 120 connected to the first sub-fan-out line 133 closer to the first central axis Q becomes longer, and the total resistance between the first sub-fan-out line 133 closer to the first central axis Q and the connection line 120 to which it is connected becomes larger. Therefore, in some of the above examples of the present disclosure, in the sub-fan-out region BBZ, of two adjacent second wiring segments 1312, the length of the second wiring segment 1312 closer to the first central axis Q is made shorter than the length of the second wiring segment 1312 away from the first central axis Q, and of two adjacent transfer lines 134, the connection end (i.e., the first connection end G1) for connecting the second wiring segment 1312 of the transfer line 134 closer to the first central axis Q is located closer to the display region AA than the connection end (i.e., the second connection end G2) for connecting the second wiring segment 1312 of the transfer line 134 away from the first central axis Q, so that of the two adjacent first sub-fan-out lines 133, the reduction in length of the first sub-fan-out line 133 closer to the first central axis Q is greater than the reduction in length of the first sub-fan-out line 133 away from the first central axis Q. Therefore, the amount of resistance reduction of the first sub-fan-out lines 133 closer to the first central axis Q is greater than the amount of resistance reduction of the first sub-fan-out lines 133 away from the first central axis Q, so that the resistance differences between the multiple first sub-fan-out lines 133 can be more balanced, i.e., the resistance differences between the multiple first data lines 111 can be balanced, thereby improving the brightness uniformity of the display substrate 100.

[0204] In some examples, as shown in FIGS. 16 and 17, the body portion 1340 includes a first transfer segment 1341.

[0205] The first transfer segment 1341 is connected to a connection end (i.e., the first connection end G1) of the transfer line 134 that is connected to the second wiring segment 1312. The orthogonal projection of the first transfer segment 1341 at the base overlaps or nearly overlaps with the orthogonal projection of the second wiring segment 1312 at the base that is connected correspondingly.

[0206] In addition, since the first transfer segment 1341 and the second wiring segment 1312 are used to transmit the same signal, there is no problem of signal crosstalk between them. In addition, by providing both of them overlapping along the thickness direction of the base, it is advantageous to save wiring space.

[0207] In some examples, as shown in Figures 16 and 17, the main body portion 1340 further includes a second transfer segment 1342 connected to the first transfer segment 1341 and a third transfer segment 1343 connected to the second transfer segment 1342.

[0208] 11 and 12 to 17, for example, the isolation block 140 is located on the side away from the base of the first wiring segment 1311 and the third wiring segment 1321, and the isolation block 140 covers the first wiring segment 1311 and the third wiring segment 1321. The transfer line 134 is located on the side away from the base of the isolation block 140. The orthogonal projection of the second transfer segment 1342 at the base is located within the orthogonal projection of the isolation block 140 at the base. The orthogonal projections of both the first transfer segment 1341 and the third transfer segment 1343 at the base are both located outside the orthogonal projection of the isolation block 140 at the base.

[0209] By installing in this manner, it becomes easy to adjust the transfer position between the end a1 of the second wiring segment 1312 away from the display area AA and the transfer line 134, thereby balancing the resistance difference among the multiple data lines 110. It also becomes easy to use the isolation block 140 to separate the second transfer segment 1342 of the transfer line 134 from the first wiring segment 1311 of the first sub-fan-out line 133, and to separate the second transfer segment 1342 of the transfer line 134 from the third wiring segment 1321 of the third sub-fan-out line 136. This prevents crosstalk between the second transfer segment 1342 of the transfer line 134 and the first wiring segment 1311 of the first sub-fan-out line 133, and also prevents crosstalk between the second transfer segment 1342 of the transfer line 134 and the third wiring segment 1321 of the third sub-fan-out line 136, thereby improving the brightness uniformity of the display substrate 100.

[0210] 16 and 17, the dotted lines extending generally along the first direction X are partial boundaries of the isolation block 140. Exemplarily, the transfer line 134 may be divided into a first transfer segment 1341, a second transfer segment 1342, and a third transfer segment 1343 depending on the position of the partial boundary.

[0211] 16 and 17, the first transfer segment 1341 and the third transfer segment 1343 are both parallel to the first central axis Q, and the second transfer segment 1342 is U-shaped or approximately U-shaped. It is understood that in other examples, the boundary positions of the isolation block 140 are different, so the boundary positions of the first transfer segment 1341, the second transfer segment 1342, and the third transfer segment 1343 are also not fixed.

[0212] Illustratively, at least one of the second wiring segment 1312 and the fourth wiring segment 1322 may be configured to include serpentine or other irregular wiring, which may be advantageous in further balancing the resistance between the fan-out lines, which in turn balances the resistance between the data lines.

[0213] 11, 15, 16, and 17, the isolation block 140 includes a first boundary E1 and a second boundary E2, where the first boundary E1 is gradually separated from the display area AA along a direction approaching the first central axis Q, and the second boundary E2 is gradually approached to the display area AA along a direction approaching the first central axis Q.

[0214] In addition, either of the first boundary E1 and the second boundary E2 may be at least one straight line (for example, in the example of FIG. 15, the first boundary E1 is one straight line, and the second boundary E2 may be two connected straight lines, or at least one curved line, or at least one connected straight line and at least one curved line. In addition, in FIGS. 11, 15, 16, and 17, only a portion of the first boundary E1 and the second boundary E2 is shown, and a more complete first boundary E1 and second boundary E2 may refer to the isolation block 140 shown in FIG. 9. Exemplarily, the first boundary E1 and the second boundary E2 may be directly connected or indirectly connected.

[0215] 11 to 13, in some examples, the first boundary E1 overlaps or substantially overlaps with a fitting line L defined by an end of the first line segment 1311 away from the display area AA and an end of the third line segment 1321 away from the display area AA. Here, "substantially overlaps" means that there may be a relatively small gap, such as a gap of several microns, between the first boundary E1 and the fitting line L.

[0216] In this example, the area of ​​the isolation block 140 can be set to be relatively small, so as to reduce the space occupied by the second fan-out region BB, while realizing signal shielding between the first wiring segment 1311 and the transfer line 134, and signal shielding between the third wiring segment 1321 and the transfer line 134, thereby preventing the occurrence of signal crosstalk between the first wiring segment 1311 and the transfer line 134, and the occurrence of signal crosstalk between the third wiring segment 1321 and the transfer line 134, and improving the brightness uniformity of the display substrate 100.

[0217] 11 and 13, the second boundary E2 overlaps or substantially overlaps with a wiring segment that is farthest from the first central axis Q among all the first wiring segments 1311 and all the third wiring segments 1321 (e.g., one third wiring segment 1321 shown in the lower left corner of FIG. 13; it is understood that the embodiments of the present disclosure are not limited thereto, and that in some other embodiments, the wiring segment may be the first wiring segment 1311). Here, "substantially overlaps" means that there may be a relatively small gap, such as a gap of several microns, between the second boundary E2 and the wiring segment that is farthest from the first central axis Q.

[0218] In this example, the area of ​​the isolation block 140 can be set to be relatively small, so as to reduce the space occupied by the second fan-out region BB, while realizing signal shielding between the first wiring segment 1311 and the transfer line 134, and signal shielding between the third wiring segment 1321 and the transfer line 134, thereby preventing the occurrence of signal crosstalk between the first wiring segment 1311 and the transfer line 134, and the occurrence of signal crosstalk between the third wiring segment 1321 and the transfer line 134, and improving the brightness uniformity of the display substrate 100.

[0219] In some examples, the included angle between the first boundary E1 and the second boundary E2 is an obtuse angle. This arrangement is advantageous for allowing the isolation block 140 to more fully cover the first wiring segment 1311 and the third wiring segment 1321 that are arranged at an angle, and is therefore advantageous for preventing signal crosstalk between the transfer line 134 and the first wiring segment 1311 and between the transfer line 134 and the third wiring segment 1321.

[0220] In some examples, the orthogonal projection of the isolation block 140 at the base is a triangle or a roughly triangular shape. For example, referring to FIG. 9, the orthogonal projection of the isolation block 140 at the base shown in FIG. 9 is a regular triangle with a large corner missing at the left end and a small corner missing at the right end. In this case, the orthogonal projection shape may be considered roughly triangular. It is understood that in other examples, the orthogonal projection of the isolation block 140 at the base may be a triangle or other roughly triangular shape. Here, other roughly triangular shapes may include, for example, cases where the sides of the triangle are sawtooth or wavy.

[0221] In this example, the orthogonal projection of the isolation block 140 at the base is set to a triangular or other approximate triangular shape, which is advantageous for the isolation block 140 to more fully cover the first wiring segment 1311 and the third wiring segment 1321 that are provided at an angle, and prevents signal crosstalk between the transfer line 134 and the first wiring segment 1311 and between the transfer line 134 and the third wiring segment 1321. Furthermore, the area of ​​the isolation block 140 may be set to be relatively small, which reduces the space occupied by the second fan-out region BB.

[0222] In some examples, the first wiring segment 1311, the second wiring segment 1312, the third wiring segment 1321, and the fourth wiring segment 1322 are located in the at least two gate metal layers Gate (e.g., the first gate metal layer Gate1 and the second gate metal layer Gate2). The isolation block 140 is located in a source-drain metal layer (e.g., the first source-drain metal layer SD1) that is relatively close to the base 102 among the at least two source-drain metal layers SD, and the transfer line 134 is located in a source-drain metal layer (e.g., the second source-drain metal layer SD2 and the third source-drain metal layer SD3) that is relatively far from the base among the at least two source-drain metal layers SD.

[0223] For example, in one sub-fan-out region, any two adjacent wiring segments (e.g., the first wiring segment 1311 and the third wiring segment 1321, or the two first wiring segments 1311, or the two second wiring segments 1321) among the plurality of first wiring segments 1311 and the plurality of third wiring segments 1321 are located in different gate metal layers (e.g., the first gate metal layer Gate1 and the second gate metal layer Gate2). This arrangement is advantageous to reduce signal interference between adjacent wiring segments (e.g., the first wiring segment 1311 and the third wiring segment 1321, or the two first wiring segments 1311, or the two second wiring segments 1321), thereby advantageous to improve the luminance uniformity of the display substrate.

[0224] For example, in one sub-fan-out region, any two adjacent transfer lines 134 are located in different source-drain metal layers SD (e.g., the second source-drain metal layer SD2 and the third source-drain metal layer SD3). This arrangement is advantageous for reducing signal interference between the two adjacent transfer lines 134, and thus for improving the luminance uniformity of the display substrate.

[0225] The above are merely specific embodiments of the present disclosure, and the scope of protection of the present disclosure is not limited thereto, and all modifications or replacements that can be easily conceived by a person skilled in the art within the technical scope of the present disclosure are included within the technical scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be governed by the scope described in the claims.

Claims

1. A display substrate, a display region and a fan-out region, the fan-out region being adjacent to one edge of the display region, the display substrate comprising: With the base, A plurality of conductive layers disposed on the same side of the base and stacked thereon; Equipped with The plurality of conductive layers include a plurality of data lines spaced apart from one another along a first direction and all extending along a second direction, the second direction intersecting the first direction, the plurality of data lines including a plurality of first data lines and a plurality of second data lines, the plurality of first data lines being located in two edge regions along the first direction of the display area, and the plurality of second data lines being located in a central region along the first direction of the display area; a plurality of connecting lines, a first end of one connecting line being located in the edge region and electrically connected to a first data line, a second end of the connecting line extending to a boundary between the central region and the fan-out region, at least one of the connecting lines spanning at least one data line and insulated from the spanning data line, and a second end of at least one of the connecting lines being located between two adjacent second data lines; a plurality of fan-out lines located in the fan-out region, the fan-out lines including a plurality of first fan-out lines and a plurality of second fan-out lines, the first fan-out lines being electrically connected to second ends of the connection lines, and the second fan-out lines being electrically connected to ends of data lines that are not electrically connected to the connection lines and are closer to the fan-out region; the display substrate further includes a bending region and a chip mounting region separated from the display region in order, the fan-out region including a first fan-out region and a second fan-out region, the first fan-out region being located between the display region and the bending region, and the second fan-out region being located between the bending region and the chip mounting region; the first fan-out lines include transfer lines, the transfer lines are located in the second fan-out region, and the transfer lines span at least one of the second fan-out lines, such that an arrangement order of ends of the plurality of fan-out lines away from the display region in the first direction is the same as an arrangement order of the plurality of data lines in the first direction; the transfer line includes a main body and two connection ends, the main body being located on a side of the two connection ends closer to the display area; Display board.

2. the display substrate further comprises a circuit test area located between the bending area and the chip mounting area, and the second fan-out area is located between the circuit test area and the chip mounting area; The display substrate according to claim 1 .

3. the transfer line is U-shaped or approximately U-shaped; The display substrate according to claim 1 or 2.

4. a central axis of the display substrate extending along the second direction is defined as a first central axis, and a region located on one side of the first central axis of the second fan-out region is one sub-fan-out region; In the sub fan-out region, the transfer lines are arranged radially, and of two adjacent transfer lines, the outer transfer line is provided around the inner transfer line. The display substrate according to claim 1 .

5. Two adjacent transfer lines are located on different conductive layers. The display substrate according to claim 4 .

6. a central axis of the display substrate extending along the second direction is defined as a first central axis, and a region located on one side of the first central axis of the second fan-out region is one sub-fan-out region; In the sub-fan-out region, the first fan-out line further includes a first wiring segment and a second wiring segment which are sequentially separated from the display region and electrically connected to each other, the first wiring segment gradually approaches the first central axis from an end close to the display region to an end separated from the display region, and the second wiring segment is parallel to the first central axis; the second fan-out line includes a third wiring segment and a fourth wiring segment which are successively farther from the display area and electrically connected to each other, the third wiring segment gradually approaches the first medial axis from an end close to the display area to an end farther from the display area, and the fourth wiring segment is parallel to the first medial axis; the connection end of the transfer line proximate to the first central axis is electrically connected to an end of the second wiring segment away from the first wiring segment; The display substrate according to claim 1 .

7. In the sub-fan-out region, a plurality of the first wiring segments and a plurality of the third wiring segments are alternately arranged, and a fitting straight line defined by an end of the first wiring segment away from the display area and an end of the third wiring segment away from the display area gradually approaches the display area from the end away from the first central axis to the end close to the first central axis. The display substrate according to claim 6 .

8. In the sub-fan-out region, among the plurality of second wiring segments, directly adjacent second wiring segments belong to the same group, and ends of the second wiring segments in the same group that are away from the display area are shifted along the first direction. The display substrate according to claim 6 or 7.

9. In the sub-fan-out region, Of two adjacent second wiring segments, a length of the second wiring segment closer to the first center axis is shorter than a length of the second wiring segment farther from the first center axis; the connection end portion for connecting the second wiring segment of the transfer line closer to the first center axis of each of the two adjacent transfer lines is closer to the display area than the connection end portion for connecting the second wiring segment of the transfer line away from the first center axis; The display substrate according to any one of claims 6 to 8.

10. the body portion includes a first transfer segment; The first transfer segment is connected to the connection end portion of the transfer line that connects the second wiring segment, and an orthogonal projection of the first transfer segment at the base overlaps or substantially overlaps an orthogonal projection of the second wiring segment at the base that is connected to the first transfer segment. The display substrate according to any one of claims 6 to 9.

11. The main body further includes a second transfer segment connected to the first transfer segment and a third transfer segment connected to the second transfer segment, The plurality of conductive layers include an isolation block is further included, the isolation block being located on a side of the first wiring segment and the third wiring segment away from the base and covering the first wiring segment and the third wiring segment; the transfer line is located away from the base of the isolation block, and an orthogonal projection of the second transfer segment on the base is located within an orthogonal projection of the isolation block on the base; the orthogonal projections of both the first transfer segment and the third transfer segment at the base are both outside the orthogonal projection of the isolation block at the base; The display substrate according to claim 10.

12. The isolation block comprises: The isolation block is electrically connected to a voltage signal line; or the isolated block includes a first boundary that overlaps or substantially overlaps a fitting line defined by an end of the first line segment that is away from the display area and an end of the third line segment that is away from the display area; Alternatively, the isolation block includes a second boundary, and the second boundary overlaps or substantially overlaps a wiring segment that is farthest from the first central axis among all of the first wiring segments and all of the third wiring segments; Alternatively, the isolation block includes a first boundary and a second boundary, and an included angle between the first boundary and the second boundary is an obtuse angle; or in a manner such that an orthogonal projection of the isolation block on the base is triangular or approximately triangular. The display substrate according to claim 11.

13. The plurality of conductive layers include at least two gate metal layers; and at least two source / drain metal layers each located on a side of the at least two gate metal layers away from the base, the first wiring segment, the second wiring segment, the third wiring segment, and the fourth wiring segment are located in the at least two gate metal layers, the isolation block is located in a source / drain metal layer of the at least two source / drain metal layers that is relatively close to the base, and the transfer line is located in a source / drain metal layer of the at least two source / drain metal layers that is relatively far from the base. The display substrate according to claim 11 or 12.

14. A display substrate according to any one of claims 1 to 13, Display device.

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