Display panel and display device

Abstract

A display panel, comprising a base and a plurality of first pixel units. The plurality of first pixel units are located on one side of the base and are arranged in a plurality of rows and a plurality of columns. The first pixel unit includes a plurality of sub-pixels, each of which includes a pixel driving circuit and a light-emitting element. The light-emitting element is located on a side of the pixel driving circuit away from the base and is electrically connected to the pixel driving circuit. The pixel driving circuit includes a first reset transistor. The plurality of sub-pixels include a first sub-pixel, a second sub-pixel and a third sub-pixel, and an area of ​​the light-emitting element of the first sub-pixel is larger than an area of ​​the light-emitting element of the second sub-pixel and is larger than an area of ​​the light-emitting element of the third sub-pixel. An orthogonal projection of the first reset transistor of the second sub-pixel and / or the first reset transistor of the third sub-pixel on the base is located within an orthogonal projection of the light-emitting element of the first sub-pixel on the base.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims priority from a Chinese patent application having application number 202210468937.6, filed on April 29, 2022, the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. [Background technology]

[0003] At present, OLED (organic light-emitting diode) display devices are widely used due to their characteristics of self-luminescence, fast response, wide viewing angle, and the ability to be fabricated on a flexible base, etc. An OLED display device includes a number of sub-pixels, each of which includes a pixel driving circuit and a light-emitting element, and the light-emitting element is driven to emit light via the pixel driving circuit, thereby realizing display. Summary of the Invention [Means for solving the problem]

[0004] In one aspect, a display panel is provided, the display panel comprising a base and a plurality of first pixel units, the plurality of first pixel units being located on one side of the base and arranged in a plurality of rows and a plurality of columns, the first pixel units including a plurality of sub-pixels, the sub-pixels including a pixel driving circuit and a light emitting element, the light emitting element being located on a side of the pixel driving circuit away from the base and electrically connected to the pixel driving circuit, the pixel driving circuit including a first reset transistor.

[0005] The plurality of sub-pixels include a first sub-pixel, a second sub-pixel and a third sub-pixel, and an area of ​​a light-emitting element of the first sub-pixel is larger than an area of ​​a light-emitting element of the second sub-pixel and is also larger than an area of ​​a light-emitting element of the third sub-pixel.

[0006] The orthogonal projection on the base of the first reset transistor of the second sub-pixel and / or the first reset transistor of the third sub-pixel is located within the orthogonal projection on the base of the light-emitting element of the first sub-pixel.

[0007] In some embodiments, a first reset transistor of the first sub-pixel, a first reset transistor of the second sub-pixel, and a first reset transistor of the third sub-pixel are all located within a orthogonal projection of the base of the light emitting element of the first sub-pixel.

[0008] In some embodiments, at least two of the first reset transistor of the first sub-pixel, the first reset transistor of the second sub-pixel, and the first reset transistor of the third sub-pixel are the same transistor.

[0009] In some embodiments, the pixel driving circuit further includes a second reset transistor. The second reset transistor of the first subpixel, the second reset transistor of the second subpixel, and the second reset transistor of the third subpixel are the same transistor. An orthogonal projection of the base of the second reset transistor is located within an orthogonal projection of the base of the light emitting element of the first subpixel. The second reset transistor is connected in series with any of the first reset transistors.

[0010] The display panel further includes a reset signal line and an initialization signal line, a control electrode of each of the first reset transistors and a control electrode of the second reset transistor are both electrically connected to the reset signal line, a first electrode of the second reset transistor is electrically connected to the initialization signal line, and a second electrode of the second reset transistor is electrically connected to the first electrode of each of the first reset transistors.

[0011] The pixel driving circuits further include driving transistors, and a control electrode of the driving transistor of each of the pixel driving circuits is electrically connected to a second electrode of each of the first reset transistors.

[0012] In some embodiments, the second sub-pixel light emitting element and the third sub-pixel light emitting element are spaced apart along a column direction, the first sub-pixel light emitting element is located in a column adjacent to a column in which the second sub-pixel light emitting element and the third sub-pixel light emitting element are located, and the first sub-pixel light emitting element spans a gap region between the second sub-pixel light emitting element and the third sub-pixel light emitting element.

[0013] The pixel driving circuit further includes a circuit body, where an orthogonal projection of the circuit body of the first subpixel on the base is located within an orthogonal projection of the light-emitting element of the first subpixel on the base, an orthogonal projection of the circuit body of the second subpixel on the base is located within an orthogonal projection of the light-emitting element of the second subpixel on the base, and an orthogonal projection of the circuit body of the third subpixel on the base is located within an orthogonal projection of the light-emitting element of the third subpixel on the base.

[0014] In some embodiments, the second reset transistor, the first reset transistor of the third subpixel, and the first reset transistor of the second subpixel are located on a side of the first reset transistor of the first subpixel closer to the circuit body of the third subpixel and are sequentially further away from the circuit body of the third subpixel.

[0015] In some embodiments, the reset signal lines extend along the row direction, one of the reset signal lines is electrically connected to the control electrodes of the second reset transistors in the first pixel units in a row and the control electrodes of each of the first reset transistors, the initialization signal lines extend along the row direction, and one of the initialization signal lines is electrically connected to the first electrodes of the second reset transistors in the first pixel units in a row.

[0016] The orthogonal projections of the second reset transistor and each of the first reset transistors on the base are located between an orthogonal projection of an initialization signal line electrically connected to the second reset transistor on the base and an orthogonal projection of a circuit body of the third subpixel on the base. The orthogonal projection of the reset signal line on the base is located between an orthogonal projection of the initialization signal line on the base and an orthogonal projection of the circuit body of the third subpixel on the base.

[0017] In some embodiments, the base includes a first display area, and the first pixel units are located within the first display area.

[0018] The display panel further includes a plurality of signal lines located between the base and the light-emitting element. A portion of at least one of the signal lines located within the first display region includes a metal wiring and a transparent connecting wiring that are electrically connected to each other. An orthogonal projection of at least a portion of the metal wiring on the base is located within an orthogonal projection of the light-emitting element on the base.

[0019] In some embodiments, the display panel comprises a first gate metal layer and a first transparent wiring layer, the first gate metal layer and the first transparent wiring layer are both located between the base and the light-emitting element, and the first transparent wiring layer is located on the side of the first gate metal layer away from the base.

[0020] The at least one signal line includes a reset signal line, the reset signal line extends along a row direction, and one of the reset signal lines is electrically connected to a control electrode of the second reset transistor and a control electrode of each of the first reset transistors in one row of the first pixel units.

[0021] The metal wiring of the reset signal line is located in the first gate metal layer, and at least a part of the orthogonal projection of the metal wiring of the reset signal line on the base is located within the orthogonal projection of the base of the light-emitting element of the first sub-pixel. The transparent connecting wiring of the reset signal line is located in the first transparent wiring layer. The orthogonal projection of the transparent connecting wiring of the reset signal line on the base is outside the orthogonal projection of the light-emitting element of the second sub-pixel on the base and outside the orthogonal projection of the light-emitting element of the third sub-pixel on the base. The transparent connecting wiring of the reset signal line and the metal wiring of the reset signal line are connected through a via.

[0022] In some embodiments, the circuit body of the pixel driving circuit includes a writing transistor, a compensation transistor and a third reset transistor, and the at least one signal line further includes a scanning signal line, and one of the scanning signal lines is electrically connected to the control electrodes of the writing transistors, the control electrodes of the compensation transistors and the control electrodes of the third reset transistors of all the sub-pixels in the first pixel unit of one row.

[0023] The metal wiring of the scanning signal line is located in the first gate metal layer, and at least a part of the orthogonal projection of the metal wiring of the scanning signal line on the base is located within the orthogonal projection of the base of the light emitting element. The transparent connecting wiring of the scanning signal line is located in the first transparent wiring layer, and the transparent connecting wiring of the scanning signal line and the metal wiring of the scanning signal line are connected through vias.

[0024] In some embodiments, the circuit body of the pixel driving circuit further includes a first emission control transistor and a second emission control transistor, and the at least one signal line further includes an emission control signal line, and the one emission control signal line is electrically connected to the control electrodes of the first emission control transistors and the control electrodes of the second emission control transistors of all the sub-pixels in the first pixel unit of one row.

[0025] The metal wiring of the light emission control signal line is located in the first gate metal layer, and at least a part of the orthogonal projection of the metal wiring of the light emission control signal line on the base is located within the orthogonal projection of the base of the light emitting element. The transparent connecting wiring of the light emission control signal line is located in the first transparent wiring layer, and the transparent connecting wiring of the light emission control signal line and the metal wiring of the light emission control signal line are connected through vias.

[0026] In some embodiments, the display panel comprises a first source-drain metal layer and a first transparent wiring layer, the first source-drain metal layer and the first transparent wiring layer are both located between the base and the light-emitting element, and the first transparent wiring layer is located on the side of the first source-drain metal layer away from the base.

[0027] The at least one signal line further includes an initialization signal line, and one of the initialization signal lines is electrically connected to a first electrode of the second reset transistor in the first pixel unit in one row. The metal wiring of the initialization signal line is located in the first source-drain metal layer, and at least a part of an orthogonal projection of the metal wiring of the initialization signal line on the base is located within an orthogonal projection of the base of the light-emitting element of the first subpixel. The transparent connecting wiring of the initialization signal line is located in the first transparent wiring layer. The orthogonal projection of the transparent connecting wiring of the initialization signal line on the base is outside an orthogonal projection of the light-emitting element of the second subpixel on the base and outside an orthogonal projection of the light-emitting element of the third subpixel on the base. The transparent connecting wiring of the initialization signal line and the metal wiring of the initialization signal line are connected through a via.

[0028] In some embodiments, the display panel includes a second gate metal layer, a second source / drain metal layer, and a second transparent wiring layer, the second gate metal layer, the second source / drain metal layer, and the second transparent wiring layer are located between the base and the light emitting element, the second source / drain metal layer is located on a side of the second gate metal layer away from the base, and the second transparent wiring layer is located on a side of the second source / drain metal layer away from the second gate metal layer. The circuit body of the pixel driving circuit further includes a capacitor, and a first plate of the capacitor is located on the second gate metal layer.

[0029] The at least one signal line further includes a first power supply signal line, the first power supply signal line extends along a column direction, and one of the first power supply signal lines is electrically connected to a first plate of a capacitor of the second sub-pixel and a first plate of a capacitor of the third sub-pixel in one column of the first pixel unit.

[0030] The metal wiring of the first power supply signal line is located in the second source-drain metal layer, and at least a part of the orthogonal projection of the metal wiring of the first power supply signal line on the base is located within the orthogonal projection of the light emitting element of the second subpixel and the light emitting element of the third subpixel on the base. The transparent connecting wiring of the first power supply signal line is located in the second transparent wiring layer, and the transparent connecting wiring of the first power supply signal line and the metal wiring of the first power supply signal line are connected through a via.

[0031] In some embodiments, the at least one signal line further includes a second power supply signal line, the second power supply signal line extends along a column direction, and one of the second power supply signal lines is electrically connected to a first plate of a capacitor of the first sub-pixel in the first pixel unit in one column.

[0032] The metal wiring of the second power signal line is located in the second source-drain metal layer, and at least a part of the orthogonal projection of the metal wiring of the second power signal line on the base is located within the orthogonal projection of the base of the light emitting element of the first subpixel. The transparent connecting wiring of the second power signal line is located in the second transparent wiring layer, and the transparent connecting wiring of the second power signal line and the metal wiring of the second power signal line are connected through a via.

[0033] In some embodiments, the display panel further comprises a plurality of data lines extending along a column direction, the orthogonal projection at the base of a portion of the plurality of data lines located within the first display region is located outside the orthogonal projection at the base of a light-emitting element of any of the sub-pixels, and the portion of at least one data line located in the first display region is located in the second transparent wiring layer.

[0034] The circuit body of the pixel driving circuit includes a write transistor, and in one of the first pixel units, a first electrode of the write transistor of the first subpixel, a first electrode of the write transistor of the second subpixel, and a first electrode of the write transistor of the third subpixel are each connected to different data lines.

[0035] In some embodiments, the portion of the at least one data line located within the first display area is a transparent wiring segment.

[0036] In the first pixel unit of the same column, an orthogonal projection on the base of a transparent wiring segment of a data line electrically connected to the write transistor of the first subpixel is located on a side of an orthogonal projection on the base of a circuit body of the first subpixel away from an orthogonal projection on the base of a circuit body of the second subpixel, and an orthogonal projection on the base of a light-emitting element of the second subpixel and an orthogonal projection on the base of a light-emitting element of the third subpixel are located between an orthogonal projection on the base of a transparent wiring segment of a data line electrically connected to the write transistor of the second subpixel and an orthogonal projection on the base of a transparent wiring segment of a data line electrically connected to the write transistor of the third subpixel.

[0037] In some embodiments, the circuit body of the pixel driving circuit further includes a compensation transistor and a third reset transistor.

[0038] In one of the first pixel units, the write transistor, the compensation transistor, and the third reset transistor in the first sub-pixel are arranged in sequence away from the circuit body of the second sub-pixel, the write transistor, the compensation transistor, and the third reset transistor in the second sub-pixel are arranged in sequence along a first set direction, and the write transistor, the compensation transistor, and the third reset transistor in the third sub-pixel are arranged in sequence along a direction opposite to the first set direction.

[0039] In some embodiments, the light-emitting element comprises an anode, an emissive layer and a cathode, the anode being electrically connected to the pixel driving circuit, the emissive layer being located on a side of the anode away from the base, and the cathode being located on a side of the emissive layer away from the base. An orthogonal projection of the base of a first reset transistor of the second subpixel and / or a first reset transistor of the third subpixel is located within an orthogonal projection of the base of the anode of the first subpixel.

[0040] In some embodiments, the first subpixel is a blue subpixel, the second subpixel is a green subpixel, and the third subpixel is a red subpixel.

[0041] In some embodiments, the display panel comprises a first display region and a second display region. The first pixel unit is provided in the first display region. A plurality of second pixel units are provided in the second display region, and the plurality of second pixel units are arranged in a plurality of rows and a plurality of columns. The second pixel unit includes a plurality of sub-pixels, and a density of the sub-pixels in the first display region is equal to a density of the sub-pixels in the second display region. An area of ​​a light-emitting element of a sub-pixel in the first display region is 0.4 to 0.6 times an area of ​​a light-emitting element of a sub-pixel of the same color in the second display region.

[0042] In another aspect, there is provided a display device, comprising a display panel according to any of the above embodiments. [Brief description of the drawings]

[0043] In order to more clearly describe the technical solutions according to the present disclosure, the drawings used in some embodiments of the present disclosure will be briefly described below. It is clear that the drawings in the following description are only some drawings of some embodiments of the present disclosure. Those skilled in the art can also obtain other drawings based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and do not limit the actual dimensions of the products, the actual flow of the methods, the actual timing of the signals, etc. according to the embodiments of the present disclosure. [Figure 1A] 1 is a structural diagram of a display device according to some embodiments; [Figure 1B] 1 is a structural diagram of a display device according to some embodiments; [Figure 2A] 1 is a structural diagram of a display device according to some embodiments; [Figure 2B] 1 is a structural diagram of a display panel according to some embodiments. [Figure 3A] 1 is a structural diagram of a display panel according to some embodiments. [Figure 3B] 1 is a structural diagram of a display panel according to some embodiments. [Figure 4A] 2 is a structural diagram of a pixel driving unit according to some embodiments. [Figure 4B] 2 is a timing diagram of a pixel driving circuit according to some embodiments. [Figure 4C] 2 is a structural diagram of a pixel driving unit according to some embodiments. [Figure 4D] 2 is a structural diagram of a pixel driving unit according to some embodiments. [Figure 4E] 2 is a structural diagram of a pixel driving unit according to some embodiments. [Figure 4F] 2 is a structural diagram of a pixel driving unit according to some embodiments. [Figure 5A] 1 is a structural diagram of a display panel according to some embodiments. [Figure 5B] 1 is a structural diagram of a display panel according to some embodiments. [Figure 5C] 1 is a structural diagram of a display panel according to some embodiments. [Figure 5D] 1 is a structural diagram of a display panel according to some embodiments. [Figure 6A] 1 is a structural diagram of a display panel according to some embodiments. [Figure 6B] 1 is a structural diagram of a display panel according to some embodiments. [Figure 7A] 1 is a structural diagram of a display panel according to some embodiments. [Figure 7B] 1 is a structural diagram of a display panel according to some embodiments. [Figure 7C] 1 is a structural diagram of a display panel according to some embodiments. [Figure 8A] 1 is a structural diagram of a display panel according to some embodiments. [Figure 8B] 1 is a structural diagram of a display panel according to some embodiments. [Figure 9A] 1 is a structural diagram of a display panel according to some embodiments. [Figure 9B] 1 is a structural diagram of a display panel according to some embodiments. [Figure 9C] 1 is a structural diagram of a display panel according to some embodiments. [Figure 10A] 1 is a structural diagram of a display panel according to some embodiments. [Figure 10B] 1 is a structural diagram of a display panel according to some embodiments. [Figure 11A] 1 is a structural diagram of a display panel according to some embodiments. [Figure 11B] 1 is a structural diagram of a display panel according to some embodiments. [Figure 11C] 1 is a structural diagram of a display panel according to some embodiments. [Figure 11D] 1 is a structural diagram of a display panel according to some embodiments. [Figure 11E] 1 is a structural diagram of a display panel according to some embodiments. [Figure 12A] 1 is a structural diagram of a display panel according to some embodiments. [Figure 12B] 1 is a structural diagram of a display panel according to some embodiments. [Figure 12C] 1 is a structural diagram of a display panel according to some embodiments. [Figure 13A] 1 is a structural diagram of a display panel according to some embodiments. [Figure 13B] 1 is a structural diagram of a display panel according to some embodiments. [Figure 14] 1 is a structural diagram of a display panel according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0044] Hereinafter, some embodiments of the present disclosure will be described clearly and completely with reference to the drawings. Of course, the embodiments described herein are only a part of the embodiments of the present disclosure, and are not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments that can be obtained by those skilled in the art shall be included in the protection scope of the present disclosure.

[0045] Unless otherwise indicated by the context, in the present specification and claims, the term "comprise" and other forms, such as the third person singular "comprises" and the present participle form "comprising" should be interpreted in an open, inclusive sense, i.e., "including but not limited to." In the description of the specification, the terms "some embodiments," "examples," "some examples," and the like are intended to indicate that a particular feature, structure, material, or characteristic associated with this embodiment or the examples is included in at least one embodiment or example of the present disclosure. General expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, a particular feature, structure, material, or characteristic described may be included in any one or more embodiments or examples in any suitable manner.

[0046] In the following, the terms "first" and "second" are for descriptive purposes only and should not be understood as indicating or implying the relative importance or quantity of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more than two.

[0047] In describing some embodiments, the term "connected" and its derivatives may be used. For example, in describing some embodiments, the term "connected" may be used to indicate that two or more elements are in direct physical or electrical contact with each other.

[0048] "A and / or B" includes the three combinations of A only, B only, and a combination of A and B.

[0049] As used herein, the term "if" is arbitrarily interpreted to mean "when" or "when," depending on the context.

[0050] In this specification, the use of "disposed to" is intended to be open and inclusive language and does not exclude devices adapted or arranged to perform additional tasks or steps.

[0051] Additionally, the use of "based on" is meant to be open-ended and inclusive, as a process, step, calculation, or other action performed "based on" one or more recited conditions or values ​​may, in fact, be based on additional conditions or beyond the recited values.

[0052] In describing some embodiments, the phrases "the feature is provided below the anode" or "the feature is located below the anode" or "the feature is hidden below the anode" may be used to indicate that the orthogonal projection of the feature onto the base is located within the orthogonal projection of the anode onto the base.

[0053] In describing some embodiments, the term "area of ​​a particular structure" may be used to refer to the area of ​​the orthogonal projection of the particular structure onto the base.

[0054] As used herein, "approximately" or "approximate" includes the stated value and the average within an acceptable range of deviation of the particular value, where the acceptable range of deviation is determined by one of ordinary skill in the art considering the measurement and the error associated with the measurement of the particular quantity (i.e., limitations of the measurement system).

[0055] As used herein, "parallel", "perpendicular" and "equal" include the described situation and the situation that is approximate to the described situation, and the range of the approximate situation is within an acceptable deviation range, and the acceptable deviation range is determined by taking into consideration the measurement considered by a person skilled in the art and the error associated with the measurement of a particular quantity (i.e., the limit of the measurement system). For example, "parallel" includes true parallel and approximately parallel, where the acceptable deviation range of approximately parallel may be, for example, within 5°, and "perpendicular" includes true perpendicular and approximately perpendicular, where the acceptable deviation range of approximately perpendicular may be, for example, within 5°. "Equal" includes absolutely equal and approximately equal, where, within the acceptable deviation range of approximately equal, for example, the difference between the two that are equal is 5% or less.

[0056] When a layer or element is referred to as being on another layer or substrate, it is understood that the layer or element may be directly on the other layer or substrate, or there may be intermediate layers between the layer or element and the other layer or substrate.

[0057] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, thicknesses of layers and regions are exaggerated for clarity. Thus, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances, can be expected. Thus, the exemplary embodiments are not limited to the shapes of regions shown herein, but should be construed as including deviations in shape due to manufacturing or otherwise. For example, an etching region shown as a rectangle will typically have curved features. Thus, the regions shown in the drawings are exemplary in nature, and their shapes are not intended to represent the actual shape of the regions of the facility, nor are they intended to limit the scope of the exemplary embodiments.

[0058] Some embodiments of the present disclosure provide a display device. FIG. 1A and FIG. 1B are structural diagrams of a display device according to some embodiments. Referring to FIG. 1A and FIG. 1B, the display device 100 is a product having an image (including still images or moving images, where the moving images may be videos) display function. For example, the display device 100 may be any of a watch, a display, a television, a signboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a personal digital assistant (abbreviated as PDA), a digital camera, a portable video recorder, a viewfinder, a navigator, a vehicle, a large wall, a home appliance, an information inquiry device (for example, a business inquiry device for electronic government affairs, banks, hospitals, power, etc.), a monitor, etc.

[0059] Referring now to FIG. 2A, the display device 100 includes a display panel 200 and a sensor 300.

[0060] In some embodiments of the present disclosure, a display panel 200 is provided. FIG. 2B is a structural diagram of a display panel according to some embodiments. Referring to FIG. 2B, the display panel 200 includes a display area AA and a peripheral area BB disposed on at least one side of the display area AA. Here, the display area AA is used to display an image. In some examples, the peripheral area BB may be disposed on one or more sides of the display area AA. In some other examples, the peripheral area BB is disposed to surround the periphery of the display area AA.

[0061] Here, the display panel 200 may be an OLED (organic light-emitting diode) display panel, which has advantages such as a wide viewing angle, high contrast, fast response, low power consumption, foldability, and flexibility.

[0062] 2B, the display panel 200 includes a base 210 and a plurality of first pixel units 220, which are disposed on one side of the base 210 and arranged in a plurality of rows and a plurality of columns. The first pixel units 220 include a plurality of sub-pixels 230. The sub-pixels 230 are the smallest units for the display panel 200 to display an image, and each sub-pixel 230 may display a single color, such as red, green, or blue. By adjusting the brightness (grayscale) of the sub-pixels of different colors, the combination and superposition of colors can realize the display of multiple colors, thereby realizing the full-color display of the display panel 200.

[0063] In some embodiments, referring to Fig. 2B, the display area AA includes a first display area A1, and the plurality of first pixel units 220 are disposed in the first display area A1. Referring to Fig. 2A, the display panel 200 includes a backlight side 201 and a display side 202 disposed opposite to each other, where the display side 202 is used for displaying an image. The sensor 300 is disposed in the backlight side 201 of the display panel 200 and located in the first display area A1 of the display panel 200.

[0064] Here, the sensor 300 is, for example, an image sensor or an infrared sensor. The sensor 300 is configured to receive light rays from the display side 202 of the display panel 200, thereby performing operations such as image capture, distance detection, and light intensity detection. These light rays may be irradiated to the sensor 300 after passing through the first display area A1, and thus may be detected by the sensor 300.

[0065] By installing the sensor 300 in the first display area A1 of the display panel 200 and positioning it on the backlight side 201 of the display panel, it is possible to avoid drilling holes in the display screen, improve the screen occupancy rate relative to the outer frame, and provide a better visual experience.

[0066] 3A is a structural diagram of a first display area A1 of a display panel according to some embodiments. Referring to FIG. 3A, a sub-pixel 230 includes a pixel driving circuit 231 and a light-emitting element 232. The light-emitting element 232 is located on a side of the pixel driving circuit 231 away from the base 210 and is electrically connected to the pixel driving circuit 231. Here, the pixel driving circuit 231 is used to drive the light-emitting element 232 to emit light.

[0067] FIG. 3B is a structural diagram of a display panel according to some embodiments, and FIG. 3B shows the structure of one sub-pixel. Referring to FIG. 3B, the light-emitting element 232 includes an anode AND1, an emitting layer EL, and a cathode CTD1. Here, the anode AND1 is located on a side away from the base 210 of the pixel driving circuit 231, and is electrically connected to the pixel driving circuit 231. The emitting layer EL is located on a side away from the base 210 of the anode AND1, and the cathode CTD1 is located on a side away from the base 210 of the emitting layer EL. In some examples, the light-emitting element 232 further includes at least one layer or multiple layers of an electron transporting layer (abbreviated as ETL), an electron injection layer (abbreviated as EIL), a hole transporting layer (abbreviated as HTL), and a hole injection layer (abbreviated as HIL).

[0068] In some examples, the orthogonal projections of the anode AND1 on the base 210, the orthogonal projections of the emissive layer EL on the base 210, and the orthogonal projections of the cathode CTD1 on the base 210 at least partially overlap.

[0069] Referring to FIG. 3A, the sub-pixels 230 in one first pixel unit 220 include a first sub-pixel 230B, a second sub-pixel 230G and a third sub-pixel 230R.

[0070] In one first pixel unit 220, the area of ​​the light emitting element 232 of the first sub-pixel 230B is larger than that of the light emitting element 232 of the second sub-pixel 230G, and is larger than that of the light emitting element 232 of the third sub-pixel 230R. Correspondingly, referring to FIG. 3A, in one first pixel unit 220, the area of ​​the anode AND-B of the first sub-pixel 230B is larger than that of the anode AND-G of the second sub-pixel 230G, and is larger than that of the anode AND-R of the third sub-pixel 230R. Correspondingly, in one first pixel unit 220, the area of ​​the light emitting layer EL of the first sub-pixel 230B is larger than that of the light emitting layer EL of the second sub-pixel 230G, and is larger than that of the light emitting layer EL of the third sub-pixel 230R. Correspondingly, in one first pixel unit 220, the area of ​​the cathode CTD1 of the first sub-pixel 230B is larger than the area of ​​the cathode CTD1 of the second sub-pixel 230G, and is also larger than the area of ​​the cathode CTD1 of the third sub-pixel 230R.

[0071] The anodes AND1 are block-shaped, and the anodes AND1 of the different sub-pixels 230 are separated from each other. The light-emitting layers EL are block-shaped, and the light-emitting layers EL of the different sub-pixels 230 are separated from each other.

[0072] In some examples, the cathodes CTD1 of the subpixels 230 in the display panel 200 are connected to each other, and the cathodes CTD1 of the subpixels 230 are of a full-layer structure. In the examples, the area of ​​the cathode CTD1 of one subpixel 230 is equal to the area of ​​the light-emitting layer EL or the area of ​​the anode AND1. In the examples, the area of ​​the light-emitting layer EL or the anode AND1, whichever has a larger area, is the area of ​​the light-emitting element 232. Exemplarily, when the area of ​​the orthogonal projection of the anode AND1 on the base 210 is larger than the area of ​​the light-emitting layer EL on the base 210, the area of ​​the light-emitting element 232 is the area of ​​the anode AND1. Exemplarily, when the area of ​​the orthogonal projection of the light-emitting layer EL on the base 210 is larger than the area of ​​the orthogonal projection of the anode AND1 on the base 210, the area of ​​the light-emitting element 232 is the area of ​​the light-emitting layer EL.

[0073] In some other examples, the cathode CTD1 is block-shaped, and the cathodes CTD1 of the subpixels 230 in the display panel 200 are separated from each other. In this case, the largest area among the cathode CTD1, the light-emitting layer EL, and the anode AND1 is the area of ​​the light-emitting element 232. Exemplarily, when the area of ​​the cathode CTD1 is the largest among the three of the cathode CTD1, the light-emitting layer EL, and the anode AND1 of one subpixel 230, the area of ​​the light-emitting element 232 is the area of ​​the cathode CTD1. When the area of ​​the anode AND1 is the largest, the area of ​​the light-emitting element 232 is the area of ​​the anode AND1. When the area of ​​the light-emitting layer EL is the largest, the area of ​​the light-emitting element 232 is the area of ​​the light-emitting layer EL.

[0074] Exemplarily, in the first pixel unit 220, the first sub-pixel 230B is a blue sub-pixel, the second sub-pixel 230G is a green sub-pixel, and the third sub-pixel 230R is a red sub-pixel.

[0075] The light-emitting layer EL includes an effective light-emitting area. In some examples, in one first pixel unit 220, the area of ​​the light-emitting element 232 of the first sub-pixel 230B is larger than that of the light-emitting element 232 of the second sub-pixel 230G, and is larger than that of the light-emitting element 232 of the third sub-pixel 230R. Correspondingly, the area of ​​the effective light-emitting area of ​​the first sub-pixel 230B is larger than that of the effective light-emitting area of ​​the second sub-pixel 230G, and is larger than that of the effective light-emitting area of ​​the third sub-pixel 230R. Here, the light-emitting layer EL of the light-emitting element 232 includes a light-emitting material, and the efficiency of the light-emitting material of the blue sub-pixel is low. By maximizing the effective light-emitting area of ​​the blue sub-pixel, the color shift problem caused by the difference in light-emitting efficiency between the red sub-pixel, the green sub-pixel, and the blue sub-pixel can be reduced.

[0076] In one implementation, the area of ​​the light-emitting element 232 of the sub-pixel 230 is reduced and the pixel driving circuit 231 is hidden under the light-emitting element 232, thereby making it possible to reduce the area occupied by the sub-pixel 230 in the display panel 200, and thus to increase the area of ​​the light-transmitting region and improve the light transmittance of the first display region A1. Note that the area of ​​the light-emitting element 232 means the area covered by the orthogonal projection of the light-emitting element 232 on the base 210. Hiding the pixel driving circuit 231 under the light-emitting element 232 means that the pixel driving circuit 231 is located closer to the base 210 of the light-emitting element 232, and the orthogonal projection of the pixel driving circuit 231 on the base 210 is located within the orthogonal projection of the light-emitting element 232 on the base 210.

[0077] However, because the areas of the light emitting element 232 of the second sub-pixel 230G and the light emitting element 232 of the third sub-pixel 230R are relatively small, it is difficult to hide the pixel driving circuit 231-G of the second sub-pixel 230G under the light emitting element 232 of the second sub-pixel 230G, and it is also difficult to hide the pixel driving circuit 231-R of the third sub-pixel 230R under the light emitting element 232 of the third sub-pixel 230R. If the pixel driving circuit 231 is exposed to the outside of the light emitting element 232, the light transmittance of the first display region A1 will decrease and diffraction will become severe, which will be disadvantageous for imaging.

[0078] On this basis, the present disclosure provides a pixel driving unit 400. Referring to FIG. 4A, the pixel driving unit 400 includes a plurality of pixel driving circuits 231.

[0079] In some embodiments, the structure of the pixel driving circuit of the present disclosure may be various, and may be selected and installed according to actual needs. For example, the structure of the pixel driving circuit 231 may include "6T1C", "7T1C", "6T2C" or "7T2C", etc., where "T" is a thin film transistor, and the number before "T" indicates the number of thin film transistors. "C" is a storage capacitor C, and the number before "C" indicates the number of storage capacitors. The following description will be given by taking the pixel driving circuit of 7T1C mode as an example.

[0080] 4A, one pixel driving circuit 231 includes a driving transistor T3 and a second reset transistor T12. The second reset transistor T12 is electrically connected to a reset signal terminal Rst, an initialization signal terminal Vin and a control electrode of the driving transistor T3. The second reset transistor T12 is configured to transmit an initialization signal received at the initialization signal terminal Vin to the control electrode of the driving transistor T3 in response to a reset signal received at the reset signal terminal Rst, to reset the control electrode of the driving transistor T3.

[0081] Exemplarily, the control electrode of the second reset transistor T12 is electrically connected to the reset signal terminal Rst, the first electrode is electrically connected to the initialization signal terminal Vin, and the second electrode is electrically connected to the control electrode of the driving transistor T3.

[0082] Referring to FIG. 4A, in addition to the second reset transistor T12 and the driving transistor T3, the pixel driving circuit 231 further includes a compensation transistor T2, a writing transistor T4, a first emission control transistor T5, a second emission control transistor T6, a third reset transistor T7 and a capacitor Cst.

[0083] Here, the control electrode of the compensation transistor T2 is electrically connected to the scanning signal terminal Gt, the first electrode of the compensation transistor T2 is electrically connected to the second electrode of the driving transistor T3, and the second electrode of the compensation transistor T2 is electrically connected to the control electrode of the driving transistor T3.

[0084] A control electrode of the write transistor T4 is electrically connected to the scanning signal terminal Gt, a first electrode of the write transistor T4 is electrically connected to the data signal terminal Dt, and a second electrode of the write transistor T4 is electrically connected to the first electrode of the drive transistor T3.

[0085] A control electrode of the first light-emitting control transistor T5 is electrically connected to the light-emitting control signal terminal Em, a first electrode of the first light-emitting control transistor T5 is electrically connected to the first type power supply signal terminal Vdd, and a second electrode of the first light-emitting control transistor T5 is electrically connected to the first electrode of the driving transistor T3.

[0086] A control electrode of the second emission control transistor T6 is electrically connected to the emission control signal terminal Em, a first electrode of the second emission control transistor T6 is electrically connected to the second electrode of the driving transistor T3, and a second electrode of the second emission control transistor T6 is electrically connected to the anode of the light-emitting element 232. A cathode of the light-emitting element 232 is electrically connected to the second type power supply signal terminal Vss. Here, the voltage of the first type power supply signal received at the first type power supply signal terminal Vdd is greater than the voltage of the second type power supply signal received at the second type power supply signal terminal Vss.

[0087] The control electrode of the third reset transistor T7 is electrically connected to the scanning signal terminal Gt, the first electrode of the third reset transistor T7 is electrically connected to the initialization signal terminal Vin, and the second electrode of the third reset transistor T7 is electrically connected to the anode of the light-emitting element 232.

[0088] A first plate of the capacitor Cst is electrically connected to the first type power supply signal terminal Vdd, and a second plate of the capacitor Cst is electrically connected to the control electrode of the driving transistor T3.

[0089] In some examples, the second reset transistor T12, the compensation transistor T2, the driving transistor T3, the writing transistor T4, the first emission control transistor T5, the second emission control transistor T6, and the third reset transistor T7 may be P-type transistors or N-type transistors, where the N-type transistors are turned on when the gates receive a high-voltage signal, and the P-type transistors are turned on when the gates receive a low-voltage signal. It should be noted that the above "high voltage signal" and "low voltage signal" are common terms, and generally, the condition for an N-type transistor to be conductive is that the voltage difference between the gate and source is greater than its threshold voltage, i.e., when the gate voltage of an N-type transistor is greater than the sum of its source voltage and its threshold voltage, and the threshold voltage of an N-type transistor is a positive value, the gate voltage signal that makes the N-type transistor conductive is called a high voltage signal, and the condition for a P-type transistor to be conductive is that the absolute value of the voltage difference between the gate and source is greater than its threshold voltage, and the threshold voltage of a P-type transistor is a negative value, i.e., when the gate voltage of a P-type transistor is less than the sum of its source voltage and its threshold voltage, the gate voltage signal that makes the P-type transistor conductive is called a low voltage signal, and the high and low of "high voltage signal" and "low voltage signal" refer to the source voltage.

[0090] In some examples, referring to FIG. 4A, the second reset transistor T12, the compensation transistor T2, the driving transistor T3, the writing transistor T4, the first emission control transistor T5, the second emission control transistor T6 and the third reset transistor T7 may all be P-type transistors, and in this case, the timing diagram of the pixel driving circuit 231 is shown in FIG. 4B.

[0091] Hereinafter, the driving process of the pixel driving circuit 231 will be described based on the assumption that all the transistors in the pixel driving circuit 231 are P-type transistors.

[0092] The driving process of the pixel driving circuit 231 is such that one frame period includes a reset stage t1, a data refresh and compensation stage t2 and a light emitting stage t3.

[0093] In the reset stage t1, the reset signal is low, and the second reset transistor T12 is turned on and transmits an initialization signal to the control electrode of the driving transistor T3 to reset the control electrode of the driving transistor T3 and turn on the driving transistor T3. Meanwhile, the compensation transistor T2, the writing transistor T4, the first emission control transistor T5, the second emission control transistor T6 and the third reset transistor T7 are all in an off state, and the light emitting element 232 does not emit light.

[0094] In the data refresh and compensation stage t2, the reset signal received at the reset signal terminal Rst is high voltage, and the second reset transistor T12 is turned off, while the scanning signal received at the scanning signal terminal Gt is low voltage, and the third reset transistor T7 is turned on under the control of the scanning signal, and thus the initialization signal received at the initialization signal terminal Vin is written to the anode of the light-emitting element 232, thereby resetting the anode of the light-emitting element 232.

[0095] At the same time, under the control of the scanning signal, the write transistor T4 and the compensation transistor T2 are made conductive, and at the same time the driving transistor T3 maintains the conductive state of the reset stage t1, so that the data signal received at the data signal terminal Dt may be transmitted to the control electrode of the driving transistor T3 through the write transistor T4, the driving transistor T3 and the compensation transistor T2 in sequence, thereby causing the voltage of the control electrode of the driving transistor T3 to change until the voltage of the control electrode of the driving transistor T3 reaches the sum of the threshold voltage of the driving transistor T3 and the voltage of the data signal, thereby turning off the driving transistor T3.

[0096] In the data refresh and compensation stage T2, the threshold voltage of the driving transistor T3 is written to the control electrode of the driving transistor T3, thereby compensating for the threshold voltage drift of the driving transistor T3, and thus reducing the impact on the emission intensity of the light emitting element 232. In this stage, the first emission control transistor T5 and the second emission control transistor T6 are turned off under the control of the emission control signal.

[0097] In the light emitting stage t3, the second reset transistor T12, the compensation transistor T2, the write transistor T4 and the third reset transistor T7 are turned off. The capacitor Cst fixes the voltage of the control electrode of the driving transistor T3, so as to maintain the voltage of the control electrode of the driving transistor T3 at the voltage of the data refresh and compensation stage t2. At this time, the light emitting control signal is low, and the first light emitting control transistor T5 and the second light emitting control transistor T6 are turned on under the control of the light emitting control signal, so that the first type power signal received at the first type power signal terminal Vdd is written to the first electrode of the driving transistor T3, thereby making the driving transistor T3 conductive, forming a path between the first type power signal terminal and the light emitting element 232, and making the light emitting element 232 emit light.

[0098] In the pixel driving unit 400 provided by some embodiments of the present disclosure, referring to FIG. 4A , the second reset transistors T12 of at least two pixel driving circuits 231 are the same transistor, which can reduce the area of ​​the pixel driving unit 400 and is advantageous for hiding the pixel driving circuit 231 in the pixel driving unit 400 under the light-emitting element 232.

[0099] In some examples, the second reset transistors T12 of all pixel driving circuits 231 in one pixel driving unit 400 are the same transistor.

[0100] In some examples, in one pixel driving unit 400, the multiple pixel driving circuits 231 include a first pixel driving circuit 231B, a second pixel driving circuit 231G and a third pixel driving circuit 231R, where the second reset transistor T12 of the first pixel driving circuit 231B, the second reset transistor T12 of the second pixel driving circuit 231G and the second reset transistor T12 of the third pixel driving circuit 231R are the same transistor.

[0101] Here, the first pixel driving circuit 231B, the second pixel driving circuit 231G and the third pixel driving circuit 231R share the second reset transistor T12. One second reset transistor T12 may simultaneously reset the control electrodes of the driving transistors T3 in the pixel driving circuits 231B, 231G and 231G.

[0102] By sharing the second reset transistor T12, the number of transistors in one pixel driving unit 400 can be reduced, so that the area of ​​the pixel driving unit 400 can be reduced, which is advantageous for hiding the pixel driving circuit 231 in the pixel driving unit 400 under the light-emitting element 232.

[0103] In some examples, referring to FIG. 3A, the first sub-pixel 230B includes a first pixel driving circuit 231B and an anode AND-B. In this case, the first pixel driving circuit 231B is electrically connected to the anode AND-B. The second sub-pixel 230G includes a second pixel driving circuit 231G and an anode AND-G. In this case, the second pixel driving circuit 231G is electrically connected to the anode AND-G. The third sub-pixel 230R includes a third pixel driving circuit 231R and an anode AND-R. In this case, the third pixel driving circuit 231R is electrically connected to the anode AND-R.

[0104] 4A, in some embodiments, the pixel driving circuit 231 further includes a first reset transistor T11. In the same pixel driving circuit 231, the first reset transistor T11 is connected in series between the second reset transistor T12 and the control electrode of the driving transistor T3.

[0105] Here, the control electrode of the first reset transistor T11 is electrically connected to the reset signal terminal Rst, and the first reset transistor T11 and the second reset transistor T12 jointly reset the control electrode of the driving transistor T3, thereby achieving the effect of preventing leakage current.

[0106] In some examples, referring to FIGS. 4C to 4F, in one pixel driving unit 400, the first reset transistors T11 of at least two pixel driving circuits 231 are the same transistor.

[0107] Based on the embodiment in which the above-mentioned multiple pixel driving circuits 231 include a first pixel driving circuit 231B, a second pixel driving circuit 231G and a third pixel driving circuit 231R, in some embodiments, referring to Figures 4C to 4F, at least two of the first reset transistor T11-B of the first pixel driving circuit 231B, the first reset transistor T11-G of the second pixel driving circuit 231G and the first reset transistor T11-R of the third pixel driving circuit 231R are the same transistor.

[0108] In some examples, referring to FIG. 4C, the first reset transistor T11-B of the first pixel driving circuit 231B and the first reset transistor T11-G of the second pixel driving circuit 231G are the same transistor.

[0109] In some examples, referring to FIG. 4D, the first reset transistor T11-B of the first pixel driving circuit 231B and the first reset transistor T11-R of the third pixel driving circuit 231R are the same transistor.

[0110] In some examples, referring to FIG. 4E, the first reset transistor T11-G of the second pixel driving circuit 231G and the first reset transistor T11-R of the third pixel driving circuit 231R are the same transistor.

[0111] In some examples, referring to FIG. 4F, in one pixel driving unit 400, the first reset transistors T11 of the multiple pixel driving circuits 231 (i.e., all pixel driving circuits 231) are the same transistor. Based on the above embodiment in which the multiple pixel driving circuits 231 include the first pixel driving circuit 231B, the second pixel driving circuit 231G and the third pixel driving circuit 231R, in this case, the first reset transistor T11-B of the first pixel driving circuit 231B, the first reset transistor T11-G of the second pixel driving circuit 231G and the first reset transistor T11-R of the third pixel driving circuit 231R are the same transistor.

[0112] In one pixel driving unit 400, at least two of the multiple pixel driving circuits 231 share the first reset transistor T11, which can reduce the number of transistors in one pixel driving unit 400, and thus reduce the area of ​​the pixel driving circuit 231 in the pixel driving unit 400, and is advantageous for hiding the pixel driving circuit 231 in the pixel driving unit 400 under the light-emitting element 232.

[0113] In addition, in some other embodiments, referring to FIG. 4A, the first reset transistor T11-B of the first pixel driving circuit 231B, the first reset transistor T11-G of the second pixel driving circuit 231G, and the first reset transistor T11-R of the third pixel driving circuit 231R are all different transistors.

[0114] By providing a first reset transistor T11 in each pixel driving circuit 231, in different pixel driving circuits 231, different first reset transistors T11 reset the control electrodes of the driving transistors T3, thereby ensuring the reset effect on the control electrodes of the driving transistors T3.

[0115] The display device 100 provided by some embodiments of the present disclosure includes a pixel driving unit 400 provided by any of the above embodiments. Therefore, the display device 100 provided by some embodiments of the present disclosure has all the beneficial effects of the pixel driving unit 400 provided by any of the above embodiments, which will not be repeated here.

[0116] Some embodiments of the present disclosure further provide a display panel 200. Referring to Fig. 5A, in the display panel 200, the orthogonal projection on the base 210 of the first reset transistor T11-G of the second subpixel 230G and / or the first reset transistor T11-R of the third subpixel 230R is located within the orthogonal projection on the base 210 of the light-emitting element 232 of the first subpixel 230B.

[0117] In addition, when the area of ​​the light emitting element 232 is the area of ​​the anode AND1, the orthogonal projection of the light emitting element 232 on the base 210 overlaps with the orthogonal projection of the anode AND1 on the base 210. When the area of ​​the light emitting element 232 is the area of ​​the light emitting layer EL, the orthogonal projection of the light emitting element 232 on the base 210 overlaps with the orthogonal projection of the light emitting layer EL on the base 210. When the area of ​​the light emitting element 232 is the area of ​​the cathode CTD1, the orthogonal projection of the light emitting element 232 on the base 210 overlaps with the orthogonal projection of the cathode CTD1 on the base 210.

[0118] In some examples, in one first pixel unit 220, the area of ​​the light emitting element 232 of the first sub-pixel 230B is the largest, while the area of ​​the light emitting element 232 of the second sub-pixel 230G and the area of ​​the light emitting element 232 of the third sub-pixel 230R are all relatively small. Hiding the first reset transistor T11-G in the second sub-pixel 230G and / or the first reset transistor T11-R in the third sub-pixel 230R under the light emitting element 232 of the first sub-pixel 230B not only can shield the first reset transistor T11-G in the second sub-pixel 230G and / or the first reset transistor T11-R in the third sub-pixel 230R, but also, because the area of ​​the light emitting element 232 of the first sub-pixel 230B is large, the structure of the pixel driving circuit 231 under the light emitting element 232 of the first sub-pixel 230B is not too compact, and the space under the light emitting element 232 of the first sub-pixel 230B can be reasonably utilized.

[0119] In some examples, only the orthogonal projection on the base 210 of the first reset transistor T11-G of the second subpixel 230G may be located within the orthogonal projection on the base 210 of the light-emitting element 232 of the first subpixel 230B. Here, in one first pixel unit 220, the area of ​​the light-emitting element 232 of the second subpixel 230G is relatively small, and the first reset transistor T11-G in the second subpixel 230G is provided below the light-emitting element 232 of the first subpixel 230B, so that the number of transistors in the pixel driving circuit 231 located below the light-emitting element 232 of the second subpixel 230G can be reduced, and thus the area of ​​the pixel driving circuit 231 located below the light-emitting element 232 of the second subpixel 230G can be reduced, which is advantageous for the light-emitting element 232 of the second subpixel 230G to shield the driving circuit 231 located thereunder.

[0120] In some other examples, only the orthogonal projection on the base 210 of the first reset transistor T11-R of the third subpixel 230R may be located within the orthogonal projection on the base 210 of the light-emitting element 232 of the first subpixel 230B. By providing the first reset transistor T11-R of the third subpixel 230R below the light-emitting element 232 of the first subpixel 230B, the number of transistors in the pixel driving circuit 231 located below the light-emitting element 232 of the third subpixel 230R can be reduced, and thus the area of ​​the pixel driving circuit 231 located below the light-emitting element 232 of the third subpixel 230R can be reduced, which is advantageous for the light-emitting element 232 of the third subpixel 230R to shield the pixel driving circuit 231 located thereunder.

[0121] In some other embodiments, referring to FIG. 5A , the first reset transistor T11-B of the first subpixel 230B, the first reset transistor T11-G of the second subpixel 230G, and the first reset transistor T11-R of the third subpixel 230R are all located within a positive projection of the base 210 of the light-emitting element 232 of the first subpixel 230B.

[0122] Here, the first reset transistor T11-G of the second sub-pixel 230G and the first reset transistor T11-R of the third sub-pixel 230R are both disposed under the light-emitting element 232 of the first sub-pixel 230B, so that the area of ​​the pixel driving circuit 231 under the light-emitting element 232 of the second sub-pixel 230G can be reduced, and the area of ​​the pixel driving circuit 231 under the light-emitting element 232 of the third sub-pixel 230R can also be reduced, which is favorable for shielding the pixel driving circuit 231 in the second sub-pixel 230G and the pixel driving circuit 231 in the third sub-pixel 230R, and reducing the diffraction phenomenon. In addition, the first reset transistor T11-B of the first sub-pixel 230B is disposed under the light-emitting element 232 of the first sub-pixel 230B, so as to prevent the first reset transistor T11-B from occupying other space, and thus improve the light transmittance.

[0123] In some embodiments, referring to Figures 4C to 4F, at least two of the first reset transistor T11-B of the first subpixel 230B, the first reset transistor T11-G of the second subpixel 230G, and the first reset transistor T11-G of the third subpixel 230G are the same transistor.

[0124] Here, since the first reset transistors T11 of at least two sub-pixels 230 in one first pixel unit 220 are the same transistor, it is possible to reduce the number of first reset transistors T11 in the first pixel unit 220. When the first reset transistor T11-B of the first sub-pixel 230B, the first reset transistor T11-G of the second sub-pixel 230G, and the first reset transistor T11-R of the third sub-pixel 230R are all provided under the light-emitting element 232 of the first sub-pixel 230B, the reduction in the number of first reset transistors T11 can reduce the area of ​​the pixel driving circuit 231 under the light-emitting element 232 of the first sub-pixel 230B, and thus the area of ​​the light-emitting element 232 of the first sub-pixel 230B can be reduced, and the light transmittance of the first display region A1 can be improved.

[0125] In some examples, the material of the anode AND1 includes a transparent conductive oxide material and a metal material. Here, the transparent conductive oxide material is, for example, ITO and IZO, and the metal material is, for example, Au, Ag, Ni, and PT. Exemplarily, the anode layer AND may include a laminated composite structure, such as one layer of transparent conductive oxide, one layer of metal, and one layer of transparent conductive oxide. The structure may be expressed as transparent conductive oxide / metal / transparent conductive oxide. For example, the structure of one kind of anode layer AND is ITO / Ag / ITO. Here, the anode AND1 has low or no light transmittance.

[0126] 5A , in some embodiments, the orthogonal projection of the first reset transistor T11-G of the second subpixel 230G and / or the first reset transistor T11-R of the third subpixel 230R on the base 210 is located within the orthogonal projection of the anode AND-B of the first subpixel 230B on the base 210. In this case, the areas of the light-emitting element 232 and the anode AND1 may be equal or different. It is also understood that the orthogonal projection of the light-emitting element 232 on the base 210 may completely or partially overlap with the orthogonal projection of the anode AND1 on the base 210.

[0127] Here, the anode AND1 has low light transmittance or is opaque, and thus the anode AND1 can shield the pixel driving circuit 231 and signal lines located below the anode AND1, thereby reducing the exposure of the pixel driving circuit 231 and signal lines, thereby reducing diffraction when the sensor 300 transmits through the first display area A1 to capture an image, and at the same time increasing the light transmittance of the first display area A1.

[0128] In some examples, the orthogonal projections on the base 210 of the first reset transistor T11-B of the first subpixel 230B, the first reset transistor T11-G of the second subpixel 230G, and the first reset transistor T11-R of the third subpixel 230R are all located within the orthogonal projection on the base 210 of the anode AND-B of the first subpixel 230B.

[0129] In some embodiments, referring to FIGS. 5A and 5B, the display panel 200 further includes a reset signal line RST and an initialization signal line VIN.

[0130] Referring to FIG. 5A, the pixel driving circuit 231 further includes a second reset transistor T12. The second reset transistor T12 is connected in series with any of the first reset transistors T11. Combined with FIG. 5B, the control electrode of each of the first reset transistors T11 and the control electrode of the second reset transistor T12 are both electrically connected to a reset signal line RST. The first electrode of the second reset transistor T12 is electrically connected to the initialization signal line VIN, and the second electrode of the second reset transistor T12 is electrically connected to the first electrode of each of the first reset transistors T11. The pixel driving circuit 231 further includes a driving transistor T3, and the control electrode of the driving transistor T3 of each of the pixel driving circuits 231 is electrically connected to the second electrode of each of the first reset transistors T11.

[0131] The reset signal line RST is used to transmit a reset signal, and the initialization signal line VIN is used to transmit an initialization signal. If the first reset transistor T11 and the second reset transistor T12 are both P-type transistors, when the reset signal is a low-voltage signal, the first reset transistor T11 and the second reset transistor T12 are conductive, and the first reset transistor T11 and the second reset transistor T12 may transmit an initialization signal to the control electrode of the driving transistor T3, and thus reset the control electrode of the driving transistor T3. Here, the two transistors reset the control electrode of the driving transistor T3, thereby achieving the effect of preventing leakage current.

[0132] 5A , in some embodiments, the second reset transistor T12 of the first subpixel 230B, the second reset transistor T12 of the second subpixel 230G, and the second reset transistor T12 of the third subpixel 230R are the same transistor. The orthogonal projection of the base 210 of the second reset transistor T12 is located within the orthogonal projection of the base 210 of the light emitting element 232 of the first subpixel 230B.

[0133] Here, as shown in FIG. 5A , the second reset transistor T12 of the first subpixel 230B, the second reset transistor T12 of the second subpixel 230G, and the second reset transistor T12 of the third subpixel 230R are the same transistor, which can reduce the number of transistors under the light-emitting element 232 of the first subpixel 230B, thereby reducing the area of ​​the pixel driving circuit 231 under the light-emitting element 232 of the first subpixel 230B, which is advantageous for the light-emitting element 232 of the first subpixel 230B to shield the pixel driving circuit 231 located thereunder, thereby avoiding exposure of the pixel driving circuit 231, and thereby reducing the diffraction phenomenon.

[0134] At the same time, if the number of transistors under the light emitting element 232 of the first sub-pixel 230B is relatively small, the area of ​​the light emitting element 232 of the first sub-pixel 230B can be reduced, and thus the light transmittance can be increased.

[0135] 5A , the orthogonal projection of the second reset transistor T12 on the base 210 is located within the orthogonal projection of the anode AND-B of the first sub-pixel 230B on the base 210. Here, the anode AND-B of the first sub-pixel 230B is opaque and has a relatively good shielding effect on the second reset transistor T12, thereby reducing the diffraction phenomenon when the sensor 300 transmits and captures the first display area A1.

[0136] In some embodiments, referring to FIG. 5C, the light-emitting element 232 of the second sub-pixel 230G and the light-emitting element 232 of the third sub-pixel 230R are spaced apart from each other along the column direction Y. The direction indicated by the arrow Y is the column direction Y. Since the light-emitting element 232 of the second sub-pixel 230G and the light-emitting element 232 of the third sub-pixel 230R are sequentially arranged along the column direction Y, the light-emitting element 232 of the second sub-pixel 230G and the light-emitting element 232 of the third sub-pixel 230R in one column of the first pixel units 220 may be arranged in one column. The light-emitting element 232 of the first sub-pixel 230B in one column of the first pixel units 220 may be arranged in one column. Referring to FIG. 5B and FIG. 5C, the light-emitting element 232 of the first sub-pixel 230B is located in a column adjacent to the column in which the light-emitting element 232 of the second sub-pixel 230G and the light-emitting element 232 of the third sub-pixel 230R are located. And the light emitting element 232 of the first sub-pixel 230B spans the gap region between the light emitting element 232 of the second sub-pixel 230G and the light emitting element 232 of the third sub-pixel 230R.

[0137] 5B and 5C, the direction indicated by the arrow X is the row direction X. In some examples, the row direction X is perpendicular to the column direction Y. The light-emitting elements 232 of the third sub-pixels 230R in the first pixel units 220 in one row may be arranged in one row. The light-emitting elements 232 of the second sub-pixels 230G in the first pixel units 220 in one row may be arranged in one row. The light-emitting elements 232 of the first sub-pixels 230B in the first pixel units 220 in one row may be arranged in one row. Meanwhile, the gap region between the light-emitting element 232 of the second sub-pixel 230G and the light-emitting element 232 of the third sub-pixel 230R refers to the gap region between the light-emitting element 232 of the third sub-pixel 230R in the adjacent row and the light-emitting element 232 of the second sub-pixel 230G in the adjacent row.

[0138] The light-emitting element 232 of the first subpixel 230B spanning the gap region between the light-emitting element 232 of the second subpixel 230G and the light-emitting element 232 of the third subpixel 230R can further be understood as the projection in the row direction X of the light-emitting element 232 of the first subpixel 230B overlapping with either the light-emitting element 232 of the second subpixel 230G or the light-emitting element 232 of the third subpixel 230B.

[0139] The arrangement of the sub-pixels 230 disclosed in the above embodiments can be called a "REAL pixel arrangement". By using the REAL pixel arrangement, when the PPI (pixels per inch) of the display panel 200 is relatively low (e.g., lower than 400), the graininess can be reduced and the display effect can be improved. The above display panel 200 can be applied to a wristwatch device.

[0140] 5A, in some embodiments, the pixel driving circuit 231 further includes a circuit body 2311. Exemplarily, the circuit body 2311 of each subpixel 230 includes a compensation transistor T2, a driving transistor T3, a writing transistor T4, a first emission control transistor T5, a second emission control transistor T6, a third reset transistor T7, and a capacitor Cst.

[0141] The orthogonal projection of the circuit body 2311-B of the first subpixel 230B on the base 210 is located within the orthogonal projection of the light-emitting element 232 of the first subpixel 230B on the base 210, the orthogonal projection of the circuit body 2311-G of the second subpixel 230G on the base 210 is located within the orthogonal projection of the light-emitting element 232 of the second subpixel 230G on the base 210, and the orthogonal projection of the circuit body 2311-R of the third subpixel 230R on the base 210 is located within the orthogonal projection of the light-emitting element 232 of the third subpixel 230R on the base 210.

[0142] In one sub-pixel 230, the circuit body 2311 to which the light emitting element 232 is electrically connected is shielded, thereby preventing the circuit body 2311 from being exposed to the outside of the light emitting element 232, thereby reducing the diffraction phenomenon, and at the same time, further improving the light transmittance of the first display area A1.

[0143] 5A, the orthogonal projection of the circuit body 2311 of each subpixel 230 on the base 210 is located within the orthogonal projection of the anode AND1 of the subpixel 230B on the base 210. Exemplarily, the orthogonal projection of the circuit body 2311-B of the first subpixel 230B on the base 210 is located within the orthogonal projection of the anode AND-B of the first subpixel 230B on the base 210, the orthogonal projection of the circuit body 2311-G of the second subpixel 230G on the base 210 is located within the orthogonal projection of the anode AND-G of the second subpixel 230G on the base 210, and the orthogonal projection of the circuit body 2311-R of the third subpixel 230R on the base is located within the orthogonal projection of the anode AND-R of the third subpixel 230R on the base 210. Here, the anode AND1 of the sub-pixel 230B is opaque and has a relatively good shielding effect on the circuit bodies 2311, thereby reducing the diffraction phenomenon when the sensor 300 transmits and captures the first display area A1.

[0144] In some examples, referring to FIG. 5A , the direction in which the second subpixel 230G points to the third subpixel 230 is the second specified direction C2, the direction in which the arrow C2 points is the second specified direction C2, and the second specified direction C2 is parallel to the column direction Y.

[0145] 5D , in a row of the first pixel units 220, the second reset transistor T12 and the first reset transistors T11 are located on a side of the circuit body 2311-R of the third sub-pixel 230R that is away from the row in which the light emitting element 232 of the second sub-pixel 230G is located. In this case, the direction in which the circuit body 2311-R of the third sub-pixel 230R points the second reset transistor T12 and the first reset transistors T11 is the second designated direction C2.

[0146] In some embodiments, referring to FIG. 5D , the second reset transistor T12, the first reset transistor T11-R of the third subpixel 230R, and the first reset transistor T11-G of the second subpixel 230G are located on the side of the first reset transistor T11-B of the first subpixel 230B closer to the circuit body 2311-R of the third subpixel 230R, and are sequentially spaced apart from the circuit body 2311-R of the third subpixel 230R.

[0147] In some examples, in one first pixel unit 220, the direction in which the third sub-pixel 230R points to the first sub-pixel 230B is a first specified direction C1, the direction in which the arrow C1 points is the first specified direction C1, and the first specified direction C1 is parallel to the row direction X.

[0148] The second reset transistor T12, the first reset transistor T11-R of the third sub-pixel 230R, the first reset transistor T11-G of the second sub-pixel 230G, and the first reset transistor T11-B of the first sub-pixel 230B are arranged in sequence along the designated direction C1, which facilitates electrical connection between the first reset transistor T11-R of the third sub-pixel 230R and the driving transistor T3 of the third sub-pixel 230R, and also facilitates electrical connection between the first reset transistor T11-G of the second sub-pixel 230G and the driving transistor T3 of the second sub-pixel 230G.

[0149] 5B and 5C, in some embodiments, the reset signal lines RST extend along the row direction X, and one reset signal line RST is electrically connected to the control electrodes of the second reset transistors T12 and each of the first reset transistors T11 in one row of the first pixel units 220. Here, for the second reset transistors T12 not shown in Figures 5B and 5C, Figure 5A may be referred to.

[0150] Here, the pattern of the reset signal line RST may be a straight line pattern or an approximately straight line pattern. The above-mentioned "extending along the row direction X" of the reset signal line RST means that the reset signal line RST has a tendency to extend along the row direction X in which the main pattern of the reset signal line RST is located.

[0151] The second reset transistor T12 in the first pixel unit 220 in a row, the first reset transistor T11-B of the first sub-pixel 230B, the first reset transistor T11-G of the second sub-pixel 230G, and the first reset transistor T11-R of the third sub-pixel 230R receive the same reset signal, so that the control electrodes of the driving transistors T3 of each sub-pixel 230 in the first pixel unit 220 in a row are reset simultaneously.

[0152] 5B, the initialization signal lines VIN extend along the row direction X, and one initialization signal line VIN is electrically connected to the first electrodes of the second reset transistors T12 in one row of the first pixel units 220. Here, for the second reset transistors T12 not shown in FIG. 5B, reference may be made to FIG. 5A.

[0153] Among these, the pattern of the initialization signal line VIN may be a straight line pattern or an approximately straight line pattern. The above-mentioned "extending along the row direction X" of the initialization signal line VIN means that the main pattern of the initialization signal line VIN has a tendency to extend along a certain row direction X.

[0154] The initialization signal line VIN is used to transmit an initialization signal, which is transmitted to each first reset transistor T11 via the second reset transistor T12, and then transmitted to the control electrode of the driving transistor T3 of each sub-pixel 230 to reset the control electrode of the driving transistor T3.

[0155] 5A , the orthogonal projections of the second reset transistor T12 and each of the first reset transistors T11 on the base 210 are located between the orthogonal projections of the initialization signal line VIN electrically connected to the second reset transistor T12 on the base 210 and the orthogonal projections of the circuit body 2311-R of the third subpixel 230R on the base 210. The orthogonal projections of the reset signal line RST on the base 210 are located between the orthogonal projections of the initialization signal line VIN on the base 210 and the orthogonal projections of the circuit body 2311-G of the third subpixel 230R on the base 210.

[0156] For convenience of explanation, the second reset transistor T12 and each of the first reset transistors T11 are defined as a first type reset transistor.

[0157] Referring to FIG. 5A, the circuit body 2311-R of the third sub-pixel 230R, the first reset transistor, and the initialization signal line VIN are sequentially arranged along the second designated direction C2.

[0158] In the first pixel unit 220 in a row, the control electrodes of the second reset transistor T12 and each of the first reset transistors T11 are located on the reset signal line RST.

[0159] The location of the control electrode of the first reset transistor T11 will now be described with reference to the various film layers in the display panel 200.

[0160] 5D, the display panel 200 includes an active film layer 240 and a first gate metal layer Gate1 disposed on one side of a base 210. The active film layer 240 and the first gate metal layer Gate1 are both located between the base 210 and the light emitting element 232. The first gate metal layer Gate1 is located on a side of the active film layer 240 that is away from the base 210. In some examples, a first gate insulating layer is disposed between the active film layer 240 and the first gate metal layer Gate1.

[0161] The active film layer 240 includes an active layer of each transistor in the pixel driving circuit 231. Here, the active layer of the transistor includes a first electrode region, a second electrode region, and a channel region connecting the first electrode region and the second electrode region.

[0162] Exemplarily, referring to FIG. 6A, the active film layers 240 include an active layer T12-P of the second reset transistor T12 and an active layer T11-P of each first reset transistor T11.

[0163] 6A , the active layer T12-P of the second reset transistor T12 extends along the row direction X, and the active layers T11-P of each first reset transistor T11 extend along the column direction Y. An end of the active layer T12-P of the second reset transistor T12 away from the circuit body 2311-R of the third sub-pixel 230R is connected to an end of the active layer T11-P of each first reset transistor T11 away from the circuit body 2311-B of the first sub-pixel 230B.

[0164] Here, the active layer T11-RP of the first reset transistor T11-R of the third sub-pixel 230R, the active layer T11-GP of the first reset transistor T11-G of the second sub-pixel 230G, and the active layer T11-BP of the first reset transistor T11-B of the first sub-pixel 230B are arranged in sequence along the first designated direction C1.

[0165] 6B, the first gate metal layer Gate1 includes a reset signal line RST. The reset signal line RST is located on the side away from the base 210 of the active film layer 240. Here, referring to FIG. 5D, the overlapping portion of the reset signal line RST with the active layer T12-P of the second reset transistor T12 and the active layer T11-P of each first reset transistor T11 is used as the control electrode of the second reset transistor T12 and the control electrode of each first reset transistor T11.

[0166] In some embodiments, referring to Fig. 2B, the base 210 includes a first display area A1, and the first pixel units 220 are located in the first display area A1. The display panel 200 further includes a plurality of signal lines located between the base 210 and the light-emitting element 232. Note that the first display area A1 in the base 210 and the first display area A1 in the display panel 200 are the same area. Here, for the light-emitting element 232 not shown in Fig. 2B, reference may be made to Figs. 3A, 5A, 5B, etc.

[0167] 5B, a portion of at least one signal line located within the first display area A1 includes a metal wiring 250 and a transparent connecting wiring 260 that are electrically connected to each other. An orthogonal projection of at least a portion of the metal wiring 250 on the base 210 is located within an orthogonal projection of the light emitting element 232 on the base 210. Exemplarily, referring to FIG. 5C, the multiple signal lines in the display panel 200 include a reset signal line RST, a scanning signal line GT, a light emission control signal line EM, an initialization signal line VIN, a first power supply signal line VDD1, and a second power supply signal line VDD2.

[0168] In some examples, the orthogonal projections of all of the metal traces 250 on the base 210 lie within the orthogonal projections of the light emitting elements 232 on the base 210 .

[0169] In some other examples, referring to FIG. 5B , the orthogonal projections of some of the metal wiring 250 on the base 210 are located within the orthogonal projections of the light-emitting element 232 on the base 210, and the orthogonal projections of all of the remaining metal wiring 250 on the base 210 are located outside the orthogonal projections of the light-emitting element 232 on the base 210.

[0170] 5A and 5B, the end of the metal wiring 250 is provided with a metal connection portion 2501. Referring to FIG. 5B, the end of the transparent connection wiring 260 is provided with a transparent connection portion 2601, and the orthogonal projection of the metal connection portion 2501 on the base 210 at least partially overlaps with the orthogonal projection of the transparent connection portion 2601 on the base 210. In some examples, at least a part of the orthogonal projection of the metal connection portion 2501 on the base 210 is located within the orthogonal projection of the light-emitting element 232 on the base 210. In some other examples, the orthogonal projection of the metal connection portion 2501 on the base 210 is entirely outside the orthogonal projection of the light-emitting element 232 on the base 210.

[0171] The metal wiring 250 in one signal line may be connected via a transparent connecting wiring 260. At least a part of the transparent connecting wiring 260 is exposed to the outside of the light emitting element 232, and the transparent connecting wiring 260 is a transparent wiring that can transmit light. Therefore, connecting the metal wiring 250 via the transparent connecting wiring 260 can improve the light transmittance of the first display region A1.

[0172] In some other examples, referring to FIG. 5B, the orthogonal projection of at least a portion of the metal trace 250 on the base 210 lies within the orthogonal projection of the anode AND1 of the subpixel 230 on the base 210 .

[0173] The reset signal line RST, the scanning signal line GT, the light emission control signal line EM, the initialization signal line VIN, the first power supply signal line VDD1, and the second power supply signal line VDD2 will be described below in order.

[0174] 7A , in some embodiments, the display panel 200 includes a first transparent wiring layer 271. The first transparent wiring layer 271 is located between the base 210 and the light emitting element 232, and the first transparent wiring layer 271 is located on a side of the first gate metal layer Gate1 that is away from the base 210.

[0175] In some examples, the material of the first gate metal layer Gate1 is a metal, such as Al, Ag, Cu, Cr, etc. The material of the first transparent wiring layer 271 is a transparent conductive oxide material, such as ITO, IZO, etc.

[0176] 7B, the at least one signal line includes a reset signal line RST. The reset signal line RST includes a metal wiring 251 and a transparent connecting wiring 261. Here, the metal wiring 251 of the reset signal line RST is located in the first gate metal layer Gate1, and at least a part of the orthogonal projection of the metal wiring 251 of the reset signal line RST on the base 210 is located within the orthogonal projection of the light-emitting element 232 of the first sub-pixel 230B on the base 210. Here, for the light-emitting element 232 of the first sub-pixel 230B not shown in FIG. 7B, FIG. 5B may be referred to.

[0177] The single reset signal line RST includes multiple metal wirings 251. At least a portion of the single metal wiring 251 is located under the light-emitting element 232 of the first subpixel 230B. In some examples, the entire single metal wiring 251 is located under the light-emitting element 232 of the single first subpixel 230B. In some other examples, a portion of the single metal wiring 251 is located under the light-emitting element 232 of the single first subpixel 230B.

[0178] Referring to FIG. 6B, the metal wiring 251 in the reset signal line RST includes a main wiring segment 2511 and a connection wiring segment 2512. The main wiring segment 2511 extends along the row direction X, and overlaps with the active layer T11-P of each first reset transistor T11 at the base 210. Here, the control electrode of the first reset transistor T11 is located in the main wiring segment 2511. The connection wiring segment 2512 extends along the column direction Y and overlaps with the active layer T12-P of the second reset transistor T12. The overlapping portion of the connection wiring segment 2512 with the active layer T12-P of the second reset transistor T12 is the control electrode of the second reset transistor T12. That is, the control electrode of the second reset transistor T12 is located in the connection wiring segment 2512. Here, for the active layer T12-P of the second reset transistor T12 not shown in FIG. 6B, reference may be made to FIG. 5D and FIG. 6A.

[0179] 7B, the transparent connecting wire 261 of the reset signal line RST is located in the first transparent wiring layer 271. The transparent connecting wire 261 of the reset signal line RST and the metal wire 251 of the reset signal line RST are connected through a via.

[0180] Here, the orthogonal projection of the transparent connecting wire 261 of the reset signal line RST on the base 210 is located outside the orthogonal projection of the light emitting element 232 of the second sub-pixel 230G on the base 210, and is also located outside the orthogonal projection of the light emitting element 232 of the third sub-pixel 230R on the base 210. Therefore, the transparent connecting wire 261 of the reset signal line RST does not occupy the space below the light emitting element 232 of the second sub-pixel 230G and the light emitting element 232 of the third sub-pixel 230R, and thus the area of ​​the pixel driving circuit 231 below the light emitting element 232 of the second sub-pixel 230G and the light emitting element 232 of the third sub-pixel 230R becomes large, and the structure of the pixel driving circuit 231 below the light emitting element 232 of the second sub-pixel 230G and the light emitting element 232 of the third sub-pixel 230R is prevented from being combined due to being too compact. Here, for the light emitting element 232 of the third sub-pixel 230R not shown in FIG. 7B, reference may be made to FIG. 5A and FIG. 5B.

[0181] 7B, at least a part of the orthogonal projection of the metal wiring 251 of the reset signal line RST on the base 210 is located within the orthogonal projection of the anode AND-B of the first subpixel 230B on the base 210. The orthogonal projection of the transparent connecting wiring 261 of the reset signal line RST on the base 210 is located outside the orthogonal projection of the anode AND-G of the second subpixel 230G on the base 210, and outside the orthogonal projection of the anode AND-R of the third subpixel 230R on the base 210. Here, for the anode AND1 of each subpixel 230 not shown in FIG. 7B, reference may be made to FIG. 5B.

[0182] In some embodiments, referring to FIG. 5D, the circuit body 2311 of the pixel driving circuit 231 includes a writing transistor T4, a compensation transistor T2, and a third reset transistor T7.

[0183] The at least one signal line further includes a scanning signal line GT, which is electrically connected to the control electrodes of the writing transistors T4, the control electrodes of the compensation transistors T2 and the control electrodes of the third reset transistors T7 of all the sub-pixels 230 in the first pixel units 220 in one row.

[0184] The scanning signal line GT is used to transmit a scanning signal. All the sub-pixels 230 in the first pixel unit 220 in a row receive the same scanning signal. The writing transistor T4, the compensation transistor T2 and the third reset transistor T7 in the first pixel unit 220 in a row are turned on at the same time.

[0185] 7B, the metal wiring 252 of the scanning signal line GT is located in the first gate metal layer Gate1, and at least a part of the orthogonal projection of the metal wiring 252 of the scanning signal line GT on the base 210 is located within the orthogonal projection of the base 210 of the light emitting element 232. The transparent connecting wiring 262 of the scanning signal line GT is located in the first transparent wiring layer 271, and the transparent connecting wiring 262 of the scanning signal line GT and the metal wiring 252 of the scanning signal line GT are connected through vias.

[0186] 7B , the scanning signal line GT includes a plurality of metal wirings 252. At least a portion of the orthogonal projection of one metal wiring 252 on the base 210 is located within the orthogonal projection of one light-emitting element 232 on the base 210. In some examples, each of the metal wirings 252 is disposed below the light-emitting element 232. In some other examples, a portion of each of the metal wirings 252 is disposed below the light-emitting element 232.

[0187] In some other examples, referring to FIG. 7B, at least a portion of the orthogonal projection of the metal wiring 252 of the scanning signal line GT on the base 210 is located within the orthogonal projection of the anode AND1 of the subpixel 230 on the base 210.

[0188] In some examples, referring to FIG. 5D, one metal wiring 252 in the scanning signal line GT is electrically connected to the control electrode of the writing transistor T4, the control electrode of the compensation transistor T2, and the control electrode of the third reset transistor T7 in one subpixel 230.

[0189] In some examples, referring to FIG. 6A, the active film layers 240 include an active layer T4-P of the write transistor T4, an active layer T2-P of the compensation transistor T2, and an active layer T7-P of the third reset transistor T7.

[0190] 5D, an overlapping portion between one metal wiring 252 and the active layer T4-P of the write transistor T4 is also used as a control electrode of the write transistor T4. An overlapping portion between one metal wiring 252 and the active layer T2-P of the compensation transistor T2 is also used as a control electrode of the compensation transistor T2. An overlapping portion between one metal wiring 252 and the active layer T7-P of the third reset transistor T7 is also used as a control electrode of the third reset transistor T7. That is, the control electrode of the write transistor T4, the control electrode of the compensation transistor T2, and the control electrode of the third reset transistor T7 in one subpixel 230 are located on one metal wiring 252.

[0191] 4A and 5D, in some examples, the compensation transistor T2 of each subpixel 230 includes a first compensation transistor T21 and a second compensation transistor T22, where the first compensation transistor T21 and the second compensation transistor T22 are connected in series.

[0192] Here, the control electrode of the first compensation transistor T21 is electrically connected to the scanning signal line GT, the first electrode of the first compensation transistor T21 is electrically connected to the second electrode of the driving transistor T3 and the first electrode of the second light-emitting control transistor T6, and the second electrode of the first compensation transistor T21 is electrically connected to the first electrode of the second compensation transistor T22.

[0193] A control electrode of the second compensation transistor T22 is electrically connected to the scanning signal line GT, and a second electrode of the second compensation transistor T22 is electrically connected to the second electrode of the first reset transistor T11 and the control electrode of the driving transistor T3.

[0194] The compensation transistor T2 is configured as a first compensation transistor T21 and a second compensation transistor T22 connected in series, thereby achieving the effect of preventing leakage current.

[0195] 6B, based on an example in which the compensation transistor T2 includes a first compensation transistor T21 and a second compensation transistor T22, the metal wiring 252 of the scanning signal line GT includes a main wiring segment 2521 and a connection wiring segment 2522. The main wiring segment 2521 extends along the row direction X, the connection wiring segment 2522 extends along the column direction, and one end of the connection wiring segment 2522 is connected to the main wiring segment 2521. Here, the overlapping portion between the wiring segment 2522 and the active layer T2-P of the compensation transistor T2 is also used as the control electrode of the second compensation transistor T22. The overlapping portions between the main wiring segment 2521 and the active layer T4-P of the write transistor T4, the active layer T2-P of the compensation transistor T2, and the active layer T7-P of the third reset transistor T7 are also used as the control electrode of the write transistor T4, the control electrode of the first compensation transistor T21, and the control electrode of the third reset transistor T7, respectively. Reference may now be made to Figures 5D and 6A for the active layers of each transistor not shown in Figure 6B.

[0196] In some examples, referring to Fig. 7C, one scanning signal line GT includes a plurality of metal wirings 252 and a plurality of transparent connecting wirings 262. Here, the plurality of metal wirings 252 include a first segment metal wiring 252A, a second segment metal wiring 252B, and a third segment metal wiring 252C. Here, for the metal wirings 252 and the plurality of transparent connecting wirings 262 not shown in Fig. 7C, Fig. 7B may be referred to.

[0197] Here, at least a portion of the orthogonal projection of the first segment metal wiring 252A on the base 210 is located within the orthogonal projection of the light emitting element 232 of the first subpixel 230B on the base 210.

[0198] At least a portion of the orthogonal projection of the second segment metal wiring 252B on the base 210 is located within the orthogonal projection of the base 210 of the light-emitting element 232 of the second sub-pixel 230G.

[0199] At least a portion of the orthogonal projection of the third segment metal wiring 252C on the base 210 is located within the orthogonal projection of the base 210 of the light-emitting element 232 of the third sub-pixel 230R.

[0200] 7C , in some examples, the display panel 200 further includes a second transparent wiring layer 272. The second transparent wiring layer 272 is located on a side of the first transparent wiring layer 271 that faces away from the base 210 or a side of the first transparent wiring layer 271 that faces the base 210.

[0201] The multiple transparent connecting wires 262 in one scanning signal line GT include a first segment transparent connecting wire 262A, a second segment transparent connecting wire 262B, a third segment transparent connecting wire 262C, and a fourth segment transparent connecting wire 262D. Here, the first segment transparent connecting wire 262A, the second segment transparent connecting wire 262B, and the third segment transparent connecting wire 262C are located in the first segment transparent wiring layer 271. The fourth segment transparent connecting wire 262D is located in the second segment transparent wiring layer 272.

[0202] Here, the first segment metal wiring 252A electrically connected to the first sub-pixel 230B in each first pixel unit 220 and the third segment metal wiring 252C electrically connected to the third sub-pixel 230R are electrically connected by a first segment transparent connecting wiring 262A.

[0203] The first segment metal wiring 252A electrically connected to the first sub-pixel 230B in one first pixel unit 220 and the third segment metal wiring 252C electrically connected to the third sub-pixel 230R in the adjacent first pixel unit 220 in the row direction X are electrically connected by a second segment transparent connecting wiring 262B.

[0204] One end of the third segment transparent connecting wire 262C is electrically connected to one end of the second segment metal wire 252B away from the first sub-pixel 230B, and the other end is electrically connected to the fourth segment transparent connecting wire 262D. One end of the fourth segment transparent connecting wire 262D away from the third segment transparent connecting wire 262C is electrically connected to the second segment transparent connecting wire 262B.

[0205] 5D , in some embodiments, the circuit body 2311 of the pixel driving circuit 231 further includes a first emission control transistor T5 and a second emission control transistor T6. The at least one signal line further includes an emission control signal line EM. The emission control signal line EM is electrically connected to the control electrodes of the first emission control transistor T5 and the second emission control transistor T6 of all the sub-pixels 230 in the first pixel unit 220 in one row.

[0206] The light-emitting control signal line EM is used to transmit a light-emitting control signal. All the sub-pixels 230 in the first pixel unit 220 in a row receive the same light-emitting control signal. The first light-emitting control transistor T5 and the second light-emitting control transistor T6 in the first pixel unit 220 in a row are turned on at the same time.

[0207] 7B and 7C, the metal wiring 253 of the light-emitting control signal line EM is located in the first gate metal layer Gate1. At least a part of the orthogonal projection of the metal wiring 253 of the light-emitting control signal line EM on the base 210 is located within the orthogonal projection of the light-emitting element 232 on the base 210. The transparent connecting wiring 263 of the light-emitting control signal line EM is located in the first transparent wiring layer 271. The transparent connecting wiring 263 of the light-emitting control signal line EM and the metal wiring 253 of the light-emitting control signal line EM are connected via a via. Here, for the light-emitting element 232 not shown in FIGS. 7B and 7C, FIG. 5A may be referred to.

[0208] In some other examples, referring to FIG. 5A, at least a portion of the orthogonal projection of the metal wiring 253 of the light emission control signal line EM on the base 210 is located within the orthogonal projection of the anode AND1 of the subpixel 230 on the base 210.

[0209] 7B and 7C , the light emission control signal line EM includes a plurality of metal wires 253. At least a portion of an orthogonal projection of one metal wire 253 on the base 210 is located within an orthogonal projection of one light emitting element 232 on the base 210. In some examples, each of the metal wires 253 is disposed below the light emitting element 232. In some other examples, a portion of each of the metal wires 253 is disposed below the light emitting element 232.

[0210] In some examples, referring to FIG. 5A, one metal wiring 253 in the light emission control signal line EM is electrically connected to the control electrode of the first light emission control transistor T5 and the control electrode of the second light emission control transistor T6 in one subpixel 230.

[0211] In some examples, referring to FIG. 6A, the active film layer 240 includes an active layer T5-P of the first light-emitting control transistor T5 and an active layer T6-P of the second light-emitting control transistor T6.

[0212] 5D, an overlapping portion between one metal wiring 253 and the active layer T5-P of the first emission control transistor T5 is also used as the control electrode of the first emission control transistor T5. An overlapping portion between one metal wiring 253 and the active layer T6-P of the second emission control transistor T6 is also used as the control electrode of the second emission control transistor T6. That is, the control electrode of the first emission control transistor T5 and the control electrode of the second emission control transistor T6 in one subpixel 230 are located on one metal wiring 252.

[0213] In some examples, referring to FIG. 6A, the active film layer 240 further includes an active layer T3-P of the driving transistor T3. Referring to FIG. 6B, the first gate metal layer Gate1 further includes a second plate Cst2 of the capacitor Cst. Referring to FIG. 5D, the orthogonal projection of the second plate Cst2 on the base 210 partially overlaps with the orthogonal projection of the active layer T3-P of the driving transistor T3 on the base 210. Here, the overlapping portion between the second plate Cst2 and the active layer T3-P of the driving transistor T3 is the control electrode of the driving transistor T3.

[0214] In some examples, referring to Fig. 7C, one light emission control signal line EM includes a plurality of metal wirings 253 and a plurality of transparent connecting wirings 263. Here, the plurality of metal wirings 253 include a fourth segment metal wiring 253D, a fifth segment metal wiring 253E, and a sixth segment metal wiring 253F. Here, for the light emission control signal line EM, the metal wiring 253, and the transparent connecting wiring 263 not shown in Fig. 7C, Fig. 7B may be referred to.

[0215] Here, at least a part of the orthogonal projection of the fourth segment metal wiring 253D on the base 210 is located within the orthogonal projection of the light emitting element 232 of the first subpixel 230B on the base 210.

[0216] At least a portion of the orthogonal projection of the fifth segment metal wiring 253E on the base 210 is located within the orthogonal projection of the light emitting element 232 of the second subpixel 230G on the base 210.

[0217] At least a portion of the orthogonal projection of the sixth segment metal wiring 253F on the base 210 is located within the orthogonal projection of the light emitting element 232 of the third sub-pixel 230R on the base 210.

[0218] Referring to Figure 7B, the multiple transparent connecting wires 263 in one light emission control signal line EM include a fifth segment transparent connecting wire 263E, a sixth segment transparent connecting wire 263F and a seventh segment transparent connecting wire 263G, all of which are located in the first transparent wiring layer 271.

[0219] Referring to FIG. 7B, the fourth segment metal wiring 253D electrically connected to the first sub-pixel 230B in one first pixel unit 220 and the sixth segment metal wiring 253F electrically connected to the third sub-pixel 230R are electrically connected by a fifth segment transparent connecting wiring 263E.

[0220] The fourth segment metal wiring 253D electrically connected to the first sub-pixel 230B in one first pixel unit 220 and the sixth segment metal wiring 253F electrically connected to the third sub-pixel 230R in the adjacent first pixel unit 220 in the first specified direction C1 are electrically connected by a sixth segment transparent connecting wiring 263F.

[0221] One end of the seventh segment transparent connecting wiring 263G is electrically connected to one end of the fifth segment metal wiring 253E away from the first sub-pixel 230B, which is electrically connected to the second sub-pixel 230G, and the other end is electrically connected to the sixth segment transparent connecting wiring 263F.

[0222] In addition to the first gate metal layer Gate1, in some embodiments, referring to Figures 8A and 8B, the display panel 200 further includes a second gate metal layer Gate2. The second gate metal layer Gate2 is located between the active film layer 240 and the light-emitting element 232.

[0223] In some examples, the material of the second gate metal layer Gate2 is a metal, such as Al, Ag, Cu, Cr, etc.

[0224] 8A and 8B, the circuit body 2311 of the pixel driving circuit 231 includes a capacitor Cst. A first plate Cst1 of the capacitor Cst is located on the second gate metal layer Gate2.

[0225] 8B, in some examples, the second gate metal layer Gate2 is located on the side of the first gate metal layer Gate1 away from the base 210. Here, the orthogonal projection of the first plate Cst1 of the capacitor Cst on the base 210 at least partially overlaps with the orthogonal projection of the second plate Cst2 on the base 210.

[0226] In some embodiments, referring to FIG. 9A and FIG. 9B, the display panel 200 includes a first source-drain metal layer SD1. The first source-drain metal layer SD1 is located between the base 210 and the light-emitting element 232. The first source-drain metal layer SD1 is located on a side of the second gate metal layer Gate1 that faces away from the base 210. The first transparent wiring layer 271 is located on a side of the first source-drain metal layer SD1 that faces away from the base 210. The first transparent wiring layer 271 is located between the first source-drain metal layer SD1 and the light-emitting element 232. Referring to FIG. 9C, an interlayer medium layer ILD is provided between the second gate metal layer Gate1 and the first source-drain metal layer SD1. A plurality of vias ILDO are provided in the interlayer medium layer ILD. Here, the positions of the plurality of vias in the interlayer medium layer ILD are shown in FIG. 9C.

[0227] In some examples, the material of the first source-drain metal layer SD1 is a metal, such as Al, Ag, Cu, or Cr.

[0228] 7B and 7C, the at least one signal line further includes an initialization signal line VIN. The initialization signal line VIN is electrically connected to a first electrode of the second reset transistor T12 in the first pixel unit 220 in a row. Here, the metal wiring 254 of the initialization signal line VIN is located in the first source-drain metal layer SD1. Referring to FIG. 5A, at least a part of the orthogonal projection of the metal wiring 254 of the initialization signal line VIN on the base 210 is located within the orthogonal projection of the base 210 of the light-emitting element 232 of the first sub-pixel 230B.

[0229] In some examples, one initialization signal line VIN includes multiple metal wirings 254. One metal wiring 254 overlaps with the light emitting element 232 of one first sub-pixel 230B.

[0230] In some examples, one entire metal wiring 254 of the initialization signal line VIN is disposed under the light emitting element 232 of the first subpixel 230B.

[0231] In some other examples, a portion of one metal wiring 254 of the initialization signal line V IN is disposed under the light-emitting element 232 of the first subpixel 230B. In this case, a portion of the transparent connecting wiring 264 of the initialization signal line V IN is located under the light-emitting element 232 of the first subpixel 230B.

[0232] 7B, the transparent connecting wire 264 of the initialization signal line VIN is located in the first transparent wiring layer 271. The transparent connecting wire 264 of the initialization signal line VIN and the metal wiring 254 of the initialization signal line VIN are connected through a via. Here, the orthogonal projection of the transparent connecting wire 264 of the initialization signal line VIN on the base 210 is located outside the orthogonal projection of the light-emitting element 232 of the second subpixel 230G on the base 210, and is also located outside the orthogonal projection of the light-emitting element 232 of the third subpixel 230R on the base 210. Therefore, the transparent connecting wiring 264 of the initialization signal line VIN does not occupy the space below the light emitting element 232 of the second sub-pixel 230G and the light emitting element 232 of the third sub-pixel 230R, and thus the area of ​​the pixel driving circuit 231 below the light emitting element 232 of the second sub-pixel 230G and the light emitting element 232 of the third sub-pixel 230R becomes large, thereby avoiding the structure of the pixel driving circuit 231 below the light emitting element 232 of the second sub-pixel 230G and the light emitting element 232 of the third sub-pixel 230R from being too compact and being combined. Here, for the light emitting element 232 of the second sub-pixel 230G and the light emitting element 232 of the third sub-pixel 230R not shown in FIG. 7B, FIG. 5B may be referred to.

[0233] 5A , at least a portion of the orthogonal projection of the metal wiring 254 of the initialization signal line V IN on the base 210 is located within the orthogonal projection of the anode AND-B of the first subpixel 230B on the base 210. The orthogonal projection of the transparent connecting wiring 264 of the initialization signal line V IN on the base 210 is located outside the orthogonal projection of the anode AND-G of the second subpixel 230G on the base 210, and outside the orthogonal projection of the anode AND-R of the third subpixel 230R on the base 210.

[0234] 5A and 9A , in some examples, the metal wiring 254 in the initialization signal line VIN includes a main wiring segment 2541 and a connecting wiring segment 2542. Here, the main wiring segment 2541 extends along the row direction X, while the connecting wiring segment 2542 extends along the column direction Y. One end of the main wiring segment 2541 close to the third subpixel 230R is connected to the connecting wiring segment 2542.

[0235] 5A , an end of the active layer T12-P of the second reset transistor T12 close to the third subpixel 230R is connected through a via to a central portion of the connecting wiring segment 2542. An end of the connecting wiring segment 2542 away from the main wiring segment 2541 is connected to the active layer T7-P of the third reset transistor T7 in the first subpixel 230B through a via.

[0236] 7B , in some examples, the display panel 200 further includes a first transparent connecting line 281. The first transparent connecting line 281 is located in the first transparent wiring layer 271. One end of the first transparent connecting line 281 is electrically connected to one end of the connecting wiring segment 2542 away from the main wiring segment 2541, and the other end is electrically connected to the active layer T7-P of the third reset transistor T7 in the third sub-pixel 230R.

[0237] In some examples, referring to FIG. 7C , the display panel 200 further includes a second transparent connecting line 282 and a third transparent connecting line 283. Here, the second transparent connecting line 282 is located in the first transparent wiring layer 271, and the third transparent connecting line 283 is located in the second transparent wiring layer 272. Here, one end of the second transparent connecting line 282 is electrically connected to the active layer T7-P of the third reset transistor T7 of the second subpixel 230G, and the other end is electrically connected to the third transparent connecting line 283. One end of the third transparent connecting line 283 away from the second transparent connecting line 282 is connected to one end connected to the connecting wiring segment 2542 of the first transparent connecting line 281 through a via.

[0238] 7B, the display panel 200 further includes a fourth transparent connecting line 284 and a fifth transparent connecting line 285. Here, the fourth transparent connecting line 284 and the fifth transparent connecting line 285 are both located in the first transparent wiring layer 271.

[0239] One end of the fifth transparent connecting line 285 is electrically connected to the active layer T11-GP of the first reset transistor T11-G in the second subpixel 230G, and the other end is electrically connected to the control electrode of the driving transistor T3 in the second subpixel 230G, i.e., the second plate Cst2 of the capacitor Cst.

[0240] One end of the fourth transparent connecting line 284 is electrically connected to the active layer T11-RP of the first reset transistor T11-R in the third subpixel 230R, and the other end is electrically connected to the control electrode of the driving transistor T3 in the third subpixel 230R, i.e., the second plate Cst2 of the capacitor Cst.

[0241] In addition to the metal wiring 254 in the initialization signal line VIN, the first source-drain metal layer SD1 further includes a plurality of bridge patterns, which are connected to the active film layer 240, the first gate metal layer Gate1, and the second gate metal layer GaTe2 through vias.

[0242] 9A and 9B, in some examples, the multiple bridge patterns include a first bridge pattern 510. One end of the first bridge pattern 510 is connected to the active layer T6-P of the second light-emitting control transistor T6 through a via, and the other end is connected to the active layer T7-P of the third reset transistor T7 through a via.

[0243] 9A and 9B, in some examples, the multiple bridge patterns include a second bridge pattern 520. One end of the second bridge pattern 520 is connected to the control electrode of the driving transistor T3, i.e., the second plate Cst2 of the capacitor Cst, through a via, and the other end is connected to the active layer T2-P of the compensation transistor T2 through a via.

[0244] 9A and 9B, in some examples, the multiple bridge patterns include a third bridge pattern 530. One end of the third bridge pattern 530 is connected to the first plate Cst1 of the capacitor Cst through a via, and the other end is connected to the active layer T5-P of the first light-emitting control transistor T5 through a via.

[0245] In some other examples, the orthogonal projections on the base 210 of the multiple bridge patterns also lie within the orthogonal projection on the base 210 of the anode AND1.

[0246] 10A and 10B, in some embodiments, the display panel 200 includes a second source-drain metal layer SD2. The second source-drain metal layer SD2 is located between the base 210 and the light emitting element 232, and the second source-drain metal layer SD2 is located on a side of the second gate metal layer Gate2 that is away from the base 210.

[0247] 11A and 11B, the display panel 200 further includes a second transparent wiring layer 272. The second transparent wiring layer 272 is located between the base 210 and the light emitting element 232, and the second transparent wiring layer 272 is located on the side of the second source-drain metal layer SD2 away from the second gate metal layer Gate2.

[0248] In some examples, the second source-drain metal layer SD2 is located on the side of the first source-drain metal layer SD1 away from the base 210. The material of the second source-drain metal layer SD2 is a metal, such as Al, Ag, Cu, Cr, etc. The material of the second transparent wiring layer 272 is a transparent conductive oxide material, such as ITO, IZO, etc.

[0249] When the display panel 200 further includes a first source-drain metal layer SD1 and a first transparent wiring layer 271, in some examples, the first source-drain metal layer SD1, the second source-drain metal layer SD2, the first transparent wiring layer 271 and the second transparent wiring layer 272 are arranged in order on the side of the second gate metal layer Gate2 away from the base 210.

[0250] In some other examples, the first source-drain metal layer SD1, the first transparent wiring layer 271, the second source-drain metal layer SD2, and the second transparent wiring layer 272 are provided in this order on the side of the second gate metal layer Gate2 that is away from the base. Referring to FIG. 11C, a passivation layer PVX is provided between the first source-drain metal layer SD1 and the first transparent wiring layer 271, and a plurality of vias PVXO are provided in the passivation layer PVX. Referring to FIG. 11D, a first planarization layer PLN1 is provided between the first transparent wiring layer 271 and the second source-drain metal layer SD2, and a plurality of vias PLNO1 are provided in the first planarization layer PLN1. Referring to FIG. 11E, a second planarization layer PLN2 is provided between the second source-drain metal layer SD2 and the second transparent wiring layer 272, and a plurality of vias PLNO2 are provided in the second planarization layer PLN2.

[0251] 11B, the at least one signal line further includes a first power supply signal line VDD1. The first power supply signal line VDD1 extends along the column direction Y. The one first power supply signal line VDD1 is electrically connected to the first electrode plate Cst1 of the capacitor Cst of the second sub-pixel 230G and the first electrode plate Cst1 of the capacitor Cst of the third sub-pixel 230R in one column of the first pixel unit 220.

[0252] Here, the first power supply signal line VDD1 extending along the column direction Y means that the main pattern of the first power supply signal line VDD1 has a tendency to extend along a certain column direction Y. The pattern of the first power supply signal line VDD1 may be a straight line pattern or an approximately straight line pattern.

[0253] Here, the first power supply signal line VDD1 is used to transmit a first type power supply signal. The first power supply signal line VDD1 is electrically connected to the first electrode plate Cst1 of the capacitor Cst to transmit the first type power supply signal to the first electrode plate Cst1.

[0254] Referring to FIG. 11B, the metal wiring 255 of the first power supply signal line VDD1 is located in the second source-drain metal layer SD2. At least a part of the orthogonal projection of the metal wiring 255 of the first power supply signal line VDD1 on the base 210 is located within the orthogonal projection of the light emitting element 232 of the second subpixel 230G and the light emitting element 232 of the third subpixel 230R on the base 210. The transparent connecting wiring 265 of the first power supply signal line VDD1 is located in the second transparent wiring layer 272. The transparent connecting wiring 265 of the first power supply signal line VDD1 is connected to the metal wiring 255 of the first power supply signal line VDD1 through a via. Here, for the light emitting element 232 of the second subpixel 230G and the light emitting element 232 of the third subpixel 230R not shown in FIG. 11B, FIG. 5C may be referred to.

[0255] 11B, at least a part of the orthogonal projection of the metal wiring 255 of the first power supply signal line VDD1 on the base 210 is located within the orthogonal projection of the anode AND-G of the second subpixel 230G and the anode AND-R of the third subpixel 230R on the base 210. For the anode AND-G of the second subpixel 230G and the anode AND-R of the third subpixel 230R that are not shown in FIG. 11B, FIG. 5C may be referred to.

[0256] 11B, in some examples, the first power supply signal line VDD1 includes a plurality of metal wirings 255. Here, the plurality of metal wirings 255 in the first power supply signal line VDD1 includes a seventh segment metal wiring 255G and an eighth segment metal wiring 255H.

[0257] In some examples, the entire orthogonal projection of the seventh segment metal wire 255G on the base 210 is located within the orthogonal projection of the light-emitting element 232 of the second subpixel 230G on the base 210. The entire orthogonal projection of the eighth segment metal wire 255H on the base 210 is located within the orthogonal projection of the light-emitting element 232 of the third subpixel 230R on the base 210. In this case, the seventh segment metal wire 255G and the eighth segment metal wire 255H are electrically connected by the transparent connecting wire 265. The transparent connecting wire 265 extends to below the light-emitting element 232 of the third subpixel 230R and below the light-emitting element 232 of the second subpixel 230G.

[0258] In some other examples, a portion of the orthogonal projection of the seventh segment metal wire 255G on the base 210 is located within the orthogonal projection of the light-emitting element 232 of the second subpixel 230G on the base 210, and the remaining portion is located outside the orthogonal projection of the light-emitting element 232 of the second subpixel 230G on the base 210. A portion of the orthogonal projection of the eighth segment metal wire 255H on the base 210 is located within the orthogonal projection of the light-emitting element 232 of the third subpixel 230R on the base 210, and the remaining portion is located outside the orthogonal projection of the light-emitting element 232 of the third subpixel 230R on the base 210.

[0259] 11B, in some examples, the first power supply signal line VDD1 includes a plurality of transparent connecting wires 265. The plurality of transparent connecting wires 265 includes an eighth segment transparent connecting wire 265H and a ninth segment transparent connecting wire 265I.

[0260] In one first pixel unit 220, the seventh segment metal wiring 255G electrically connected to the second sub-pixel 230G and the eighth segment metal wiring 255H electrically connected to the third sub-pixel 230R are electrically connected by an eighth segment transparent connecting wiring 265H.

[0261] The eighth segment metal wiring 255H electrically connected to the third sub-pixel 230R in one first pixel unit 220 and the seventh segment metal wiring 255G electrically connected to the second sub-pixel 230G in the adjacent first pixel unit 220 in the second specified direction C2 are electrically connected by a ninth segment transparent connecting wiring 265I.

[0262] In some examples, referring to FIG. 12A , the seventh segment metal wiring 255G of the first power supply signal line VDD1 is connected to the third bridge pattern 530 located under the light-emitting element 232 of the second subpixel 230G through a via, thereby transmitting the first type of power supply signal line to the first plate Cst1 of the capacitor Cst and the active layer T5-P of the first light-emitting control transistor T5 in the second subpixel 230G through the third bridge pattern 530.

[0263] In some examples, referring to FIG. 12B , the 8th segment metal wiring 255H of the first power supply signal line VDD1 is connected to the third bridge pattern 530 located under the light-emitting element 232 of the third subpixel 230R through a via, thereby transmitting the first type of power supply signal line to the first plate Cst1 of the capacitor Cst and the active layer T5-P of the first light-emitting control transistor T5 in the third subpixel 230R through the third bridge pattern 530.

[0264] 11B, in some embodiments, the at least one signal line further includes a second power supply signal line VDD2. The second power supply signal line VDD2 extends along the column direction Y. The one second power supply signal line VDD2 is electrically connected to the first plate Cst1 of the capacitor Cst of the first sub-pixel 230B in the first pixel unit 220 in one column.

[0265] Here, the second power supply signal line VDD2 extending along the column direction Y means that the main pattern of the second power supply signal line VDD2 has a tendency to extend along a certain column direction Y. The pattern of the second power supply signal line VDD2 may be a straight line pattern or an approximately straight line pattern.

[0266] Here, the second power supply signal line VDD2 is used to transmit a first type power supply signal and is electrically connected to the first electrode plate Cst1 of the capacitor Cst of the first sub-pixel 230B to transmit the first type power supply signal to the first electrode plate Cst1 of the first sub-pixel 230B.

[0267] Referring to FIG. 11B, the metal wiring 256 of the second power supply signal line VDD2 is located in the second source-drain metal layer SD2. At least a part of the orthogonal projection of the metal wiring 256 of the second power supply signal line VDD2 on the base 210 is located within the orthogonal projection of the light emitting element 232 of the first pixel 230B on the base 210. The transparent connecting wiring 266 of the second power supply signal line VDD2 is located in the second transparent wiring layer 272. The transparent connecting wiring 266 of the second power supply signal line VDD2 is connected to the metal wiring 256 of the second power supply signal line VDD2 through a via. Here, FIG. 5C may be referred to for the light emitting element 232 of the first sub-pixel 230B not shown in FIG. 11B.

[0268] In some examples, the entire orthogonal projection of the metal wiring 256 of the second power supply signal line VDD2 on the base 210 is located within the orthogonal projection of the light emitting element 232 of the first subpixel 230B on the base 210. In this case, the orthogonal projection of the transparent connecting wiring 266 of the second power supply signal line VDD2 on the base 210 partially overlaps with the orthogonal projection of the light emitting element 232 of the first subpixel 230B on the base 210.

[0269] In some other examples, a portion of the orthogonal projection of the metal wiring 256 of the second power supply signal line VDD2 on the base 210 is located within the orthogonal projection of the light emitting element 232 of the first subpixel 230B on the base 210.

[0270] In some other examples, at least a portion of the orthogonal projection of the metal wiring 256 of the second power supply signal line VDD2 on the base 210 is located within the orthogonal projection of the base 210 of AND-B of the first subpixel 230B.

[0271] In some examples, referring to FIG. 12C , the metal wiring 256 of the second power signal line VDD2 is connected through a via to a third bridge pattern 530 located under the light-emitting element 232 of the first subpixel 230B, thereby transmitting the first type of power signal to the first plate Cst1 of the capacitor Cst and the active layer T5-P of the first light-emitting control transistor T5 in the first subpixel 230B through the third bridge pattern 530.

[0272] Above, the reset signal line RST, the scanning signal line GT, the emission control signal line EM, the first power supply signal line VDD1, and the second power supply signal line VDD2 in the display panel 200 have been described. In addition to the above several signal lines, the display panel 200 further includes a data line DT. In some embodiments, referring to FIG. 11B, the display panel 200 further includes a plurality of data lines DT, which extend along the column direction Y.

[0273] Here, the data lines DT extending along the column direction Y means that the main patterns of the data lines DT have a tendency to extend along a certain column direction Y. The pattern of the data lines DT may be a straight line pattern or an approximately straight line pattern.

[0274] 11B, the orthogonal projection of the portion of the plurality of data lines DT located in the first display region A1 on the base 210 is outside the orthogonal projection of the light emitting element 232 of any of the sub-pixels 230 on the base 210. As shown in FIG.

[0275] Therefore, the data line DT does not occupy the space below the light-emitting element 232, and thus the space occupied by the pixel driving circuit 231 below the light-emitting element 232 becomes large, which prevents the structure of the pixel driving circuit 231 below the light-emitting element 232 from becoming too compact.

[0276] Here, a portion of at least one data line DT located in the first display region A1 is located in the second transparent wiring layer 272. Here, the portion of the data line DT located in the first display region A1 is provided in the second transparent wiring layer 272, and the portion of the data line DT located in the first display region A1 does not block light, so that the light transmittance of the first display region A1 in the display panel 200 can be improved.

[0277] 7C, the circuit body 2311 of the pixel driving circuit 231 includes a write transistor T4. In one first pixel unit 220, the first electrode of the write transistor T4 of the first sub-pixel 230B, the first electrode of the write transistor T4 of the second sub-pixel 230G, and the first electrode of the write transistor T4 of the third sub-pixel 230R are connected to different data lines DT. Here, for the write transistor T4 of the first sub-pixel 230B, the first electrode of the write transistor T4 of the second sub-pixel 230G, and the write transistor T4 of the third sub-pixel 230R, which are not shown in FIG. 7C, FIG. 5D may be referred to.

[0278] The data line DT is used to transmit a data signal. In each sub-pixel 230, the first electrode of the writing transistor T4 is electrically connected to the data line DT, so that the data signal is transmitted to the first electrode of the writing transistor T4. In one first pixel unit 220, the sub-pixels 230 are respectively connected to different data lines DT, and the voltages of the data signals on the different data lines DT may be different, so that the light-emitting elements 232 in the different sub-pixels 230 can have different gray scales.

[0279] In addition, in some of the above embodiments, in one first pixel unit 220, the first reset transistor T11 and the second reset transistor T12 in the multiple sub-pixels 230 are turned on at the same time, so that the pixel driving circuits 231 in the multiple sub-pixels 230 are simultaneously in the reset stage. The compensation transistor T2, the writing transistor T4, and the third reset transistor T7 are turned on at the same time, so that the pixel driving circuits 231 in the multiple sub-pixels 230 are simultaneously in the data refresh and compensation stage t2. In the data refresh and compensation stage t2, the data signal is written to the control electrode of the driving transistor T3 through the writing transistor T4 and the compensation transistor T2, so that the data signal is simultaneously written to the pixel driving circuit 231 in one first pixel unit 220. The first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on at the same time, so that the pixel driving circuits 231 in the multiple sub-pixels 230 are simultaneously in the light-emitting stage t3. As described above, in one first pixel unit 220, the multiple sub-pixels 230 emit light at the same time.

[0280] In some embodiments, referring to FIG. 7C, a portion of at least one data line DT located in the first display area A1 is a transparent line segment 27.

[0281] The transparent wiring segment 27 is located in the second transparent wiring layer 272. In addition to the transparent wiring segment 27, the second transparent wiring layer 272 further includes a transparent connecting pattern 2701. Here, the transparent connecting pattern 2701 extends approximately along the row direction X. One end of the transparent connecting pattern 2701 is connected to the transparent wiring segment 27, and the other end is electrically connected to the active layer T4-P of the write transistor T4.

[0282] In some examples, referring to FIG. 9A, the first source-drain metal layer SD1 further includes a fourth bridge pattern 540. The first transparent wiring layer 271 and the second source-drain metal layer SD2 are both provided with transfer patterns. One end of the transparent connection pattern 2701 away from the transparent wiring segment 27 is via-connected to the transfer pattern in the second source-drain metal layer SD2 through a via, the transfer pattern in the second source-drain metal layer SD2 is via-connected to the transfer pattern in the first transparent wiring layer 271 through a via, the transfer pattern in the first transparent wiring layer 271 is connected to the fourth bridge pattern 540 through a via, and the fourth bridge pattern 540 is connected to the active layer T4-P of the write transistor T4 through a via, so that the data signal is transmitted to the first electrode of the write transistor T4. Here, by providing the fourth bridge pattern 540 and a plurality of transfer patterns in the transparent connection pattern 2701 and the active layer T4-P of the write transistor T4, the depth of the via can be reduced. Deeper vias have higher resistance, so in some examples of the present disclosure, resistance can be reduced.

[0283] In some examples, the portions of each data line DT located in the first display region A1 are all located in the second transparent wiring layer 272 , that is, each data line DT includes a transparent wiring segment 27 .

[0284] Referring to FIG. 11B, in the first pixel unit 220 of the same column, the orthogonal projection on the base 210 of the transparent wiring segment 27-B of the data line DT-B electrically connected to the write transistor T4 of the first subpixel 230B is located on the side away from the orthogonal projection on the base 210 of the circuit body 2311-B of the first subpixel 230B of the first subpixel 230G of the circuit body 2311-G of the second subpixel 230G.

[0285] The orthogonal projection on the base 210 of the light-emitting element 232 of the second subpixel 230G and the orthogonal projection on the base 210 of the light-emitting element 232 of the third subpixel 230R are located between the orthogonal projection on the base 210 of the transparent wiring segment 27-G of the data line DT-G electrically connected to the write transistor T4 of the second subpixel 230G and the orthogonal projection on the base 210 of the transparent wiring segment 27-R of the data line DT-R electrically connected to the write transistor T4 of the third subpixel 230G.

[0286] Here, the transparent wiring segment 27-G electrically connected to the second subpixel 230G and the transparent wiring segment 27-R electrically connected to the third subpixel 230G are respectively provided on both sides of the columns in which the second subpixel 230G and the third subpixel 230G are located.

[0287] In some examples, referring to FIGS. 11A and 11B, the transparent wiring segment 27-R, the transparent wiring segment 27-G and the transparent wiring segment 27-B are arranged in sequence along the first designated direction C1.

[0288] In some other examples, the transparent wiring segment 27-G, the transparent wiring segment 27-R, and the transparent wiring segment 27-B are arranged in sequence along the first designated direction C1.

[0289] 5D, in one first pixel unit 220, the third reset transistor T7, the compensation transistor T2, and the write transistor T4 in the first subpixel 230B are sequentially separated from the circuit body 2311-G of the second subpixel 230G. That is, the third reset transistor T7, the compensation transistor T2, and the write transistor T4 in the first subpixel 230B are sequentially separated from the column in which the second subpixel 230G and the third subpixel 230R are located, so that the transparent wiring segment 27-B electrically connected to the first subpixel 230B is located on the side of the first subpixel 230B that is away from the column in which the second subpixel 230G and the third subpixel 230R are located.

[0290] 5D, in one first pixel unit 220, the third reset transistor T7, the compensation transistor T2, and the write transistor T4 in the second sub-pixel 230G are sequentially arranged along the first set direction, and the third reset transistor T7, the compensation transistor T2, and the write transistor T4 in the third sub-pixel 230R are sequentially arranged along the opposite direction to the first set direction.

[0291] Now, referring to FIG. 11B and combining with FIG. 5D, the transparent wiring segment 27 is electrically connected to the active layer T4-P of the write transistor T4. In one of the second subpixel 230G and the third subpixel 230R, the write transistor T4 is located on the side of the compensation transistor T2 that is farther from the first subpixel 230B. In the other subpixel 230, the write transistor T4 is located on the side of the compensation transistor T2 that is closer to the first subpixel 230B. Therefore, the transparent wiring segment 27-G electrically connected to the second subpixel 230G and the transparent wiring segment 27-R of the third subpixel 230R can be disposed on both sides of the column in which the second subpixel 230G and the third subpixel 230R are located, respectively, and the transparent wiring segment 27-R can be easily connected to the write transistor T4 of the third subpixel 230R, and the transparent wiring segment 27-G can be easily connected to the write transistor T4 of the second subpixel 230G.

[0292] In some examples, referring to FIG. 11B, the first set direction D is opposite to the first specified direction C1, in which case the transparent wiring segment 27-R electrically connected to the third sub-pixel, the transparent wiring segment 27-G electrically connected to the second sub-pixel 230G, and the data line 27-B electrically connected to the first sub-pixel 230B are sequentially arranged along the first specified direction C1.

[0293] In some other examples, the first set direction D is the same as the first specified direction C1, and the transparent wiring segment 27-G electrically connected to the second sub-pixel 230G, the transparent wiring segment 27-R electrically connected to the third sub-pixel 230R, and the data line 27-B electrically connected to the first sub-pixel 230B are sequentially arranged along the first specified direction C1.

[0294] 13A and 13B, the display panel 200 further includes an anode layer AND. The anode layer AND includes a plurality of anodes AND1, such as an anode AND-B of the first sub-pixel 230B, an anode AND-G of the second sub-pixel 230G, and an anode AND-R of the third sub-pixel 230R.

[0295] 2B , in addition to the first display area A1, the display panel 200 further includes a second display area A2. The first display area A1 includes a first pixel unit 220. The second display area A2 includes a plurality of second pixel units 290, which are arranged in a number of rows and a number of columns. The second pixel unit 290 includes a plurality of sub-pixels 291. The sub-pixels 291 include a first sub-pixel 291B, a second sub-pixel 291G, and a third sub-pixel 291R.

[0296] Here, the second display area A2 is located on at least one side of the first display area A1. In some examples, the second display area A2 may be located on one or more sides of the first display area A1. In some other examples, the second display area A2 may be located so as to surround the first display area A1. In FIG. 2B, the area surrounded by a relatively small dashed frame is the first display area A1, the relatively large dashed frame is located outside the relatively small dashed frame, and the area between the relatively small dashed frame and the relatively large dashed frame is the second display area A2, and the first display area A1 and the second display area A2 together constitute the display area AA.

[0297] 14, the sub-pixel 291 of the second pixel unit 290 includes a light emitting element 232. The area of ​​the light emitting element 232 of the first sub-pixel 291B of the second pixel unit 290 is larger than the area of ​​the light emitting element 232 of the second sub-pixel 291G of the second pixel unit 290, and is also larger than the area of ​​the light emitting element 232 of the third sub-pixel 291R of the second pixel unit 290.

[0298] Here, the light-emitting element 232 includes an anode AND1. In some examples, the area of ​​the anode AND1 of the first sub-pixel 291B of the second pixel unit 290 is larger than the area of ​​the anode AND1 of the second sub-pixel 291G of the second pixel unit 290, and is larger than the area of ​​the anode AND1 of the third sub-pixel 291R of the second pixel unit 290.

[0299] In some embodiments, the area of ​​the light emitting element 232 of the sub-pixel 230 in the first display region A1 is 0.4 to 0.6 times the area of ​​the light emitting element 232 of the sub-pixel 291 of the same color in the second display region A2.

[0300] In some examples, in the second display area A2, the first sub-pixel 291B of the second pixel unit 290 may be a blue sub-pixel, the second sub-pixel 291G may be a green sub-pixel, and the third sub-pixel 291R may be a red sub-pixel.

[0301] As can be seen from the above, in some examples, in the first display area A1, the first sub-pixel 230B of the first pixel unit 220 is a blue sub-pixel, the second sub-pixel 230G is a green sub-pixel, and the third sub-pixel 230R is a red sub-pixel.

[0302] In some examples, the area of ​​the light-emitting element 232 of the first sub-pixel 230B of the first pixel unit 220 is 0.4 to 0.6 times the area of ​​the light-emitting element 232 of the first sub-pixel 291B of the second pixel unit 290, thereby preventing the light transmittance of the first display region A1 from being reduced due to the area of ​​the light-emitting element 232 of the first sub-pixel 230B of the first pixel unit 220 being too large (for example, greater than 0.6 times the area of ​​the light-emitting element 232 of the first sub-pixel 291B). In addition, the area of ​​the light-emitting element 232 of the first sub-pixel 230B of the first pixel unit 220 is too small (e.g., smaller than 0.4 times the area of ​​the light-emitting element 232 of the first sub-pixel 291B), which can avoid the area occupied by the pixel driving circuit 231 located under the light-emitting element 232 of the first sub-pixel 230B of the first pixel unit 220 becoming small, thereby making the structure in the pixel driving circuit 231 of the light-emitting element 232 of the first sub-pixel 230B of the first pixel unit 220 too compact, resulting in coupling between the structures.

[0303] Exemplarily, the area of ​​the light emitting element 232 of the first sub-pixel 230B of the first pixel unit 220 is 0.5 times that of the light emitting element 232 of the first sub-pixel 291B of the second pixel unit 290.

[0304] Referring to FIG. 14, the area of ​​the light-emitting element 232 of the second sub-pixel 230G of the first pixel unit 220 is 0.4 to 0.6 times the area of ​​the light-emitting element 232 of the second sub-pixel 291G of the second pixel unit 290, thereby preventing the light transmittance of the first display region A1 from being reduced due to the area of ​​the light-emitting element 232 of the second sub-pixel 230G of the first pixel unit 220 being too large (for example, greater than 0.6 times the area of ​​the light-emitting element 232 of the second sub-pixel 291G). In addition, the area of ​​the light-emitting element 232 of the second subpixel 230G of the first pixel unit 220 is too small (e.g., smaller than 0.4 times the area of ​​the light-emitting element 232 of the second subpixel 291G), which can avoid the area occupied by the circuit body 2311-G of the second subpixel 230G under the light-emitting element 232 of the second subpixel 230G of the first pixel unit 220 being small, thereby making the structure in the circuit body 2311-G of the second subpixel 230G of the first pixel unit 220 too compact, resulting in coupling between the structures.

[0305] Exemplarily, the area of ​​the light emitting element 232 of the second sub-pixel 230G of the first pixel unit 220 is 0.5 times that of the light emitting element 232 of the second sub-pixel 291G of the second pixel unit 290.

[0306] 14, the area of ​​the light emitting element 232 of the third sub-pixel 230R of the first pixel unit 220 is 0.4 to 0.6 times the area of ​​the light emitting element 232 of the third sub-pixel 291R of the second pixel unit 290. This makes it possible to prevent the light transmittance of the first display region A1 from being reduced due to the area of ​​the light emitting element 232 of the third sub-pixel 230R of the first pixel unit 220 being too large (for example, larger than 0.6 times the area of ​​the light emitting element 232 of the third sub-pixel 291R). In addition, the area of ​​the light-emitting element 232 of the third subpixel 230R of the first pixel unit 220 is too small (e.g., smaller than 0.4 times the area of ​​the light-emitting element 232 of the third subpixel 291R), which can avoid the area occupied by the circuit body 2311-R of the third subpixel 230R under the light-emitting element 232 of the third subpixel 230R of the first pixel unit 220 being small, which can cause the structure in the circuit body 2311-R of the third subpixel 230R to become too compact, resulting in coupling between the structures.

[0307] Exemplarily, the area of ​​the light emitting element 232 of the third sub-pixel 230R of the first pixel unit 220 is 0.5 times that of the light emitting element 232 of the third sub-pixel 291R of the second pixel unit 290.

[0308] In some examples, the subpixel density of the first display area A1 is equal to the subpixel density of the second display area A2. Note that the subpixel density of the first display area A1 refers to the number of subpixels 230 per unit area in the first display area A1. The subpixel density of the second display area A2 refers to the number of subpixels 291 per unit area in the second display area A2.

[0309] Here, the area of ​​the light-emitting element 232 of the sub-pixel 291 in the second display region A2 is larger than the area of ​​the light-emitting element 232 of the sub-pixel 230 of the same color in the first display region A1, but since the density of the sub-pixels in the first display region A1 is equal to the density of the sub-pixels in the second display region A2, the display difference between the first display region A1 and the second display region A2 can be reduced.

[0310] In addition, the light transmittance of the first display area A1 is greater than that of the second display area A2, ensuring that the sensor 300 can detect sufficient light.

[0311] Here, the structure of the light-emitting element 232 of the subpixel 291 is the same as that of the light-emitting element 232 of the subpixel 230 described above, and will not be repeated here. Here, it is understood that, among the three elements of the cathode CTD1, the light-emitting layer EL, and the anode AND1 of one subpixel 291, when the area of ​​the cathode CTD1 is the largest, the area of ​​the light-emitting element 232 of the subpixel 291 is the area of ​​the cathode CTD1. When the area of ​​the anode AND1 is the largest, the area of ​​the light-emitting element 232 of the subpixel 291 is the area of ​​the anode AND1. When the area of ​​the light-emitting layer EL is the largest, the area of ​​the light-emitting element 232 of the subpixel 291 is the area of ​​the light-emitting layer EL.

[0312] The display device 100 provided by some embodiments of the present disclosure includes the display panel 200 provided by any of the above embodiments. Therefore, the display device 100 provided by some embodiments of the present disclosure has all the beneficial effects of the display panel 200 provided by any of the above embodiments, which will not be repeated here.

[0313] The above are merely specific embodiments of the present disclosure, and the scope of protection of the present disclosure is not limited thereto, and all modifications or replacements that can be easily conceived by a person skilled in the art within the technical scope of the present disclosure are included within the technical scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be governed by the scope described in the claims.

Claims

1. With the base, a plurality of first pixel units located on one side of the base and arranged in a plurality of rows and a plurality of columns, each of the first pixel units including a plurality of sub-pixels, each of the sub-pixels including a pixel driving circuit and a light-emitting element, the light-emitting element being located on a side of the pixel driving circuit away from the base and electrically connected to the pixel driving circuit, the pixel driving circuit including a first reset transistor; Equipped with the plurality of sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel, and an area of ​​a light-emitting element of the first sub-pixel is larger than an area of ​​a light-emitting element of the second sub-pixel and is also larger than an area of ​​a light-emitting element of the third sub-pixel; a positive projection of the base of the first reset transistor of the second sub-pixel and / or the first reset transistor of the third sub-pixel is located within a positive projection of the base of the light-emitting element of the first sub-pixel; Display panel.

2. orthogonal projections of the base of the first reset transistor of the first sub-pixel, the first reset transistor of the second sub-pixel, and the first reset transistor of the third sub-pixel are all located within orthogonal projections of the base of the light-emitting element of the first sub-pixel; The display panel according to claim 1 .

3. at least two of the first reset transistor of the first sub-pixel, the first reset transistor of the second sub-pixel, and the first reset transistor of the third sub-pixel are the same transistor; 3. The display panel according to claim 1 or 2.

4. the pixel driving circuit further includes a second reset transistor, wherein the second reset transistor of the first sub-pixel, the second reset transistor of the second sub-pixel, and the second reset transistor of the third sub-pixel are the same transistor, a plane orthogonal projection of the base of the second reset transistor is located within a plane orthogonal projection of the base of the light-emitting element of the first sub-pixel, and the second reset transistor is connected in series with any of the first reset transistors; the display panel further includes a reset signal line and an initialization signal line, wherein a control electrode of each of the first reset transistors and a control electrode of each of the second reset transistors are electrically connected to the reset signal line, a first electrode of each of the second reset transistors is electrically connected to the initialization signal line, and a second electrode of each of the second reset transistors is electrically connected to a first electrode of each of the first reset transistors; the pixel driving circuit further includes a driving transistor, and a control electrode of the driving transistor of each of the pixel driving circuits is electrically connected to the second electrode of each of the first reset transistors; The display panel according to claim 1 .

5. the light emitting element of the second sub-pixel and the light emitting element of the third sub-pixel are disposed at an interval along a column direction, the light emitting element of the first sub-pixel is located in a column adjacent to a column in which the light emitting element of the second sub-pixel and the light emitting element of the third sub-pixel are located, and the light emitting element of the first sub-pixel spans a gap region between the light emitting element of the second sub-pixel and the light emitting element of the third sub-pixel; the pixel driving circuit further includes a circuit body, the circuit body including the driving transistor, wherein an orthogonal projection of the circuit body of the first sub-pixel on the base is located within an orthogonal projection of the light-emitting element of the first sub-pixel on the base, an orthogonal projection of the circuit body of the second sub-pixel on the base is located within an orthogonal projection of the light-emitting element of the second sub-pixel on the base, and an orthogonal projection of the circuit body of the third sub-pixel on the base is located within an orthogonal projection of the light-emitting element of the third sub-pixel on the base; the second reset transistor, the first reset transistor of the third sub-pixel, and the first reset transistor of the second sub-pixel are located on a side of the first reset transistor of the first sub-pixel that is closer to the circuit body of the third sub-pixel and are spaced apart in order from the circuit body of the third sub-pixel; The display panel according to claim 4 .

6. the reset signal lines extend along a row direction, and one reset signal line is electrically connected to a control electrode of the second reset transistor and a control electrode of each of the first reset transistors in one row of the first pixel units; the initialization signal lines extend along a row direction, and one initialization signal line is electrically connected to a first electrode of the second reset transistor in one row of the first pixel units; an orthogonal projection of the base of each of the second reset transistor and each of the first reset transistors is located between an orthogonal projection of the base of an initialization signal line electrically connected to the second reset transistor and an orthogonal projection of the base of a circuit body of the first subpixel, and an orthogonal projection of the base of the reset signal line is located between an orthogonal projection of the base of the initialization signal line and an orthogonal projection of the base of the circuit body of the first subpixel. The display panel according to claim 5 .

7. the base includes a first display area, and the plurality of first pixel units are located within the first display area; the display panel further includes a plurality of signal lines located between the base and the light-emitting elements; a portion of at least one signal line located within the first display area includes a metal wiring and a transparent connecting wiring electrically connected to each other, and an orthogonal projection of at least a portion of the metal wiring on the base is located within an orthogonal projection of the light-emitting element on the base; 7. The display panel according to claim 5 or 6.

8. a first gate metal layer and a first transparent wiring layer, both of which are located between the base and the light emitting element, and the first transparent wiring layer is located on a side of the first gate metal layer away from the base; the at least one signal line includes a reset signal line, the reset signal line extends along a row direction, and one reset signal line is electrically connected to a control electrode of the second reset transistor and a control electrode of each first reset transistor in one row of the first pixel units; a metal wiring of the reset signal line is located in the first gate metal layer, and at least a part of an orthogonal projection of the metal wiring of the reset signal line on the base is located within an orthogonal projection of the base of the light-emitting element of the first sub-pixel; a transparent connecting wiring of the reset signal line is located in the first transparent wiring layer, an orthogonal projection of the transparent connecting wiring of the reset signal line on the base is located outside an orthogonal projection of the light-emitting element of the second sub-pixel on the base and outside an orthogonal projection of the light-emitting element of the third sub-pixel on the base, and the transparent connecting wiring of the reset signal line and the metal wiring of the reset signal line are connected through a via. The display panel according to claim 7 .

9. the circuit body of the pixel driving circuit further includes a writing transistor, a compensation transistor and a third reset transistor; the at least one signal line further includes a scanning signal line, wherein one scanning signal line is electrically connected to the control electrodes of the writing transistors, the control electrodes of the compensation transistors, and the control electrodes of the third reset transistors of all the sub-pixels in one row of the first pixel units; the metal wiring of the scanning signal line is located on the first gate metal layer, and at least a part of the orthogonal projection of the metal wiring of the scanning signal line on the base is located within the orthogonal projection of the base of the light emitting element; the transparent connecting wiring of the scanning signal line is located in the first transparent wiring layer, and the transparent connecting wiring of the scanning signal line and the metal wiring of the scanning signal line are connected through vias; The display panel according to claim 8 .

10. the circuit body of the pixel driving circuit further includes a first light-emitting control transistor and a second light-emitting control transistor; the at least one signal line further includes a light-emitting control signal line, and one of the light-emitting control signal lines is electrically connected to control electrodes of first light-emitting control transistors and control electrodes of second light-emitting control transistors of all of the sub-pixels in one row of the first pixel units; the metal wiring of the light-emitting control signal line is located on the first gate metal layer, and at least a part of the orthogonal projection of the metal wiring of the light-emitting control signal line on the base is located within the orthogonal projection of the base of the light-emitting element; the transparent connection wiring of the light emission control signal line is located in the first transparent wiring layer, and the transparent connection wiring of the light emission control signal line and the metal wiring of the light emission control signal line are connected through vias; 10. The display panel according to claim 8 or 9.

11. a first source / drain metal layer and a first transparent wiring layer, both of which are located between the base and the light emitting element, and the first transparent wiring layer is located on a side of the first source / drain metal layer that is away from the base; the at least one signal line includes an initialization signal line, and one of the initialization signal lines is electrically connected to first electrodes of the second reset transistors in the first pixel units of one row; a metal wiring of the initialization signal line is located in the first source-drain metal layer, and at least a part of an orthogonal projection of the metal wiring of the initialization signal line on the base is located within an orthogonal projection of the base of the light-emitting element of the first sub-pixel; a transparent connecting wiring of the initialization signal line is located in the first transparent wiring layer, an orthogonal projection of the transparent connecting wiring of the initialization signal line on the base is located outside an orthogonal projection of the light-emitting element of the second sub-pixel on the base and outside an orthogonal projection of the light-emitting element of the third sub-pixel on the base, and the transparent connecting wiring of the initialization signal line and the metal wiring of the initialization signal line are connected through a via. The display panel according to claim 7 .

12. a second gate metal layer, a second source / drain metal layer, and a second transparent wiring layer, the second gate metal layer, the second source / drain metal layer, and the second transparent wiring layer are all located between the base and the light emitting element, the second source / drain metal layer is located on a side of the second gate metal layer that is away from the base, and the second transparent wiring layer is located on a side of the second source / drain metal layer that is away from the second gate metal layer; the circuit body of the pixel driving circuit further includes a capacitor, a first electrode of the capacitor being located on the second gate metal layer; the at least one signal line includes a first power supply signal line, the first power supply signal line extends along a column direction, and one of the first power supply signal lines is electrically connected to a first electrode plate of a capacitor of the second sub-pixel and a first electrode plate of a capacitor of the third sub-pixel in one column of the first pixel unit; a metal wiring of the first power supply signal line is located in the second source-drain metal layer, and at least a part of an orthogonal projection of the metal wiring of the first power supply signal line on the base is located within an orthogonal projection of the base of the light emitting element of the second sub-pixel and the light emitting element of the third sub-pixel; the transparent connecting wiring of the first power signal line is located in the second transparent wiring layer, and the transparent connecting wiring of the first power signal line and the metal wiring of the first power signal line are connected through vias; The display panel according to claim 7 .

13. the at least one signal line further includes a second power supply signal line, the second power supply signal line extends along a column direction, and one of the second power supply signal lines is electrically connected to a first electrode plate of a capacitor of the first sub-pixel in the first pixel unit in one column; a metal wiring of the second power supply signal line is located in the second source-drain metal layer, and at least a part of an orthogonal projection of the metal wiring of the second power supply signal line on the base is located within an orthogonal projection of the base of the light-emitting element of the first sub-pixel; the transparent connecting wiring of the second power signal line is located in the second transparent wiring layer, and the transparent connecting wiring of the second power signal line and the metal wiring of the second power signal line are connected through vias; The display panel according to claim 12.

14. the plurality of data lines extending along a column direction, wherein an orthogonal projection of a portion of the plurality of data lines located within the first display region on the base is outside an orthogonal projection of a light-emitting element of any of the sub-pixels on the base, and a portion of at least one of the data lines located within the first display region is located on the second transparent wiring layer; the circuit body of the pixel driving circuit further includes a write transistor, and in one of the first pixel units, a first electrode of the write transistor of the first sub-pixel, a first electrode of the write transistor of the second sub-pixel, and a first electrode of the write transistor of the third sub-pixel are connected to different data lines; The display panel according to claim 12 or 13.

15. a portion of the at least one data line located within the first display area is a transparent wiring segment; In the first pixel unit of the same column, an orthogonal projection on the base of a transparent wiring segment of a data line electrically connected to a write transistor in the first subpixel is located on a side away from an orthogonal projection on the base of a circuit body of the first subpixel, and an orthogonal projection on the base of a light-emitting element of the second subpixel and an orthogonal projection on the base of a light-emitting element of the third subpixel are located between an orthogonal projection on the base of a transparent wiring segment of a data line electrically connected to a write transistor of the second subpixel and an orthogonal projection on the base of a transparent wiring segment of a data line electrically connected to a write transistor of the third subpixel. The display panel according to claim 14.

16. the circuit body of the pixel driving circuit further includes a compensation transistor and a third reset transistor; In one of the first pixel units, the writing transistor, the compensation transistor, and the third reset transistor in the first sub-pixel are spaced apart from the circuit body of the second sub-pixel in order, the third reset transistor, the compensation transistor, and the writing transistor in the second sub-pixel are arranged in order along a first set direction, and the writing transistor, the compensation transistor, and the third reset transistor in the third sub-pixel are arranged in order along a direction opposite to the first set direction. The display panel according to claim 15.

17. the light-emitting element includes an anode, a light-emitting layer, and a cathode, the anode being electrically connected to the pixel driving circuit, the light-emitting layer being located on a side of the anode away from the base, and the cathode being located on a side of the light-emitting layer away from the base; an orthogonal projection of the base of the first reset transistor of the second sub-pixel and / or the first reset transistor of the third sub-pixel is located within an orthogonal projection of the base of the anode of the first sub-pixel; The display panel according to claim 1 .

18. the first sub-pixel is a blue sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a red sub-pixel; The display panel according to claim 1 .

19. a first display region and a second display region, the first display region including the first pixel unit; the second display area includes a plurality of second pixel units, the plurality of second pixel units are arranged in a plurality of rows and a plurality of columns, and the second pixel units include a plurality of sub-pixels, and the density of the sub-pixels in the first display area is equal to the density of the sub-pixels in the second display area; an area of ​​a light-emitting element of a sub-pixel in the first display region is 0.4 to 0.6 times the area of ​​a light-emitting element of a sub-pixel of the same color in the second display region; The display panel according to claim 1 .

20. A display panel comprising the display panel according to claim 1. Display device.

Images