Display substrate and display device

Abstract

The present disclosure relates to a display technology field, and provides a display substrate and a display device that can reduce the frame width of the display substrate and reduce the cost of the display substrate. The display substrate includes a plurality of conductive layers, each of which includes a plurality of data lines, a plurality of connecting lines, and a plurality of fan-out lines. The connecting lines span at least one data line and are insulated from the data line they span. The first fan-out line is electrically connected to the connecting line, and the second fan-out line is electrically connected to an end of the second data line that is close to the fan-out region. The first fan-out line includes a transfer line. The fan-out region includes a first fan-out region and a second fan-out region, and the transfer line is located in the second fan-out region. The transfer line is located on a different conductive layer from the plurality of second fan-out lines and spans at least one second fan-out line, so that the arrangement order of the ends of the plurality of fan-out lines that are farther from the display region in the first direction is the same as the arrangement order of the plurality of data lines in the first direction. The display substrate provided by the present disclosure can be used in a display device.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims priority from a PCT international patent application having application number PCT / CN2022 / 089120, filed on April 25, 2022, and a Chinese patent application having application number 202210876068.0, filed on July 25, 2022, the entire disclosures of which are incorporated herein by reference.

[0002] The present disclosure relates to the field of display technology, and more particularly to a display substrate and a display device. [Background technology]

[0003] Currently, organic light-emitting diode (OLED) display devices are widely used due to their characteristics of self-luminescence, fast response, high contrast, wide viewing angle, and the ability to be fabricated on a flexible base.

[0004] An OLED display device includes a number of sub-pixels, each of which includes a pixel driving circuit and a light-emitting element. The light-emitting element is driven to emit light via the pixel driving circuit, thereby realizing display. Summary of the Invention [Means for solving the problem]

[0005] An object of the present disclosure is to provide a display substrate and a display device that can reduce the cost of the display substrate while narrowing the frame of the display substrate.

[0006] In one aspect, a display substrate is provided. The display substrate has a display area and a fan-out area. The fan-out area is adjacent to one edge of the display area. The display substrate comprises a base and a plurality of conductive layers. The conductive layers are located on the same side of the base. The conductive layers are arranged in a stacked manner. The conductive layers include a plurality of data lines, a plurality of connecting lines, and a plurality of fan-out lines. The data lines are spaced apart along a first direction, and the data lines all extend along a second direction. The second direction intersects with the first direction. The data lines include a plurality of first data lines and a plurality of second data lines. The first data lines are located in two edge areas along the first direction of the display area, and the second data lines are located in a center area along the first direction of the display area. A first end of the one connecting line is located in an edge region along a first direction of the display area and is electrically connected to one first data line, and a second end of the connecting line extends to a position close to the fan-out region in a central region of the display area. The connecting line spans at least one data line and is insulated from the spanned data line. The second end of the at least one connecting line is located between two adjacent second data lines. The multiple fan-out lines are located in the fan-out region. The multiple fan-out lines include multiple first fan-out lines and multiple second fan-out lines. The first fan-out lines are electrically connected to the second ends of the connecting lines, and the second fan-out lines are electrically connected to ends of the second data lines close to the fan-out region. The display substrate further has a bending region. The fan-out region includes a first fan-out region and a second fan-out region, the first fan-out region is closer to the display area than the second fan-out region, and the bending region is located between the first fan-out region and the second fan-out region. The first fan-out lines include transfer lines located in the second fan-out region, and the transfer lines are located in a different conductive layer from the second fan-out lines and span at least one of the second fan-out lines, such that an arrangement order of ends of the fan-out lines away from the display area in the first direction is the same as an arrangement order of the data lines in the first direction.

[0007] In some embodiments, the plurality of connecting lines are electrically connected to the plurality of first data lines in one-to-one correspondence, and the plurality of second fan-out lines are electrically connected to the plurality of second data lines in one-to-one correspondence.

[0008] In some embodiments, the plurality of first data lines include a plurality of first type first data lines and a plurality of second type first data lines. The plurality of second fan-out lines include a plurality of first type second fan-out lines and a plurality of second type second fan-out lines. The plurality of first type first data lines are electrically connected to the plurality of connection lines in one-to-one correspondence. The plurality of first type second fan-out lines are electrically connected to the plurality of second data lines in one-to-one correspondence. The plurality of second type second fan-out lines are electrically connected to the plurality of second type first data lines in one-to-one correspondence.

[0009] In some embodiments, the display substrate further comprises a plurality of sub-pixels. The sub-pixels are arranged in a plurality of columns along a first direction and in a plurality of rows along a second direction. The sub-pixels in one column are electrically connected to one data line. Two first type first data lines are provided between two adjacent second type first data lines. Of the two first type first data lines, one first type first data line is electrically connected to first sub-pixels in one column, the first sub-pixels including a sub-pixel emitting red light and a sub-pixel emitting blue light. The second type first data line is electrically connected to the sub-pixels in one column emitting green light.

[0010] In some embodiments, the first fan-out line further includes a first sub-fan-out line, a plurality of adapters, and a first signal transmission line. The first sub-fan-out line is electrically connected to a second end of the connection line. The plurality of adapters include a first adapter located in a region proximate the bend region of the first fan-out region and a second adapter located in a region proximate the bend region of the second fan-out region. The first adapter is electrically connected to an end of the first sub-fan-out line away from the connection line. The transmission line is electrically connected to the second adapter. The first signal transmission line passes through the bend region and connects the first adapter and the second adapter.

[0011] In some embodiments, a centerline of the display substrate is located at the center of the display substrate along the first direction and is parallel to the base. A portion of the second fan-out line located in the first fan-out region is defined as a third sub-fan-out line. The third sub-fan-out line and the first sub-fan-out line are arranged along the first direction. For two adjacent fan-out lines of the third sub-fan-out line and the first sub-fan-out line, at least some line segments of the fan-out line that are away from the centerline are curved toward the fan-out line closer to the centerline.

[0012] In some embodiments, the second fan-out region includes a first sub-fan-out region and a second sub-fan-out region, the first sub-fan-out region being closer to the bending region than the second sub-fan-out region. At least a portion of the transfer line is located in the first sub-fan-out region. The display substrate further comprises an isolation portion. The isolation portion is located in the first sub-fan-out region, and the isolation portion is located between the transfer line and the plurality of second fan-out lines.

[0013] In some embodiments, the first fan-out line further includes a second signal transmission line, the second signal transmission line being connected between the second adapter and the transfer line, and an orthogonal projection of the second signal transmission line at a base is located between an orthogonal projection of the second signal transmission line at a base of the isolation portion and an edge of the first sub-fan-out region proximate to the bending region.

[0014] In some embodiments, the second signal transmission line gradually approaches the centerline of the display substrate from one end close to the display area to the other end away from the display area.

[0015] In some embodiments, the number of the second signal transmission lines is more than one. At least a portion of the second signal transmission lines, which are adjacent to each other and are away from the center line, are curved toward the second signal transmission line closer to the center line.

[0016] In some embodiments, the ends of the transfer lines remote from the first sub-fan-out line extend to a second sub-fan-out region.

[0017] In some embodiments, the first fan-out line further includes a second sub-fan-out line. The second sub-fan-out line is located in a different conductive layer than the transfer line. The isolation portion is located between the transfer line and the second sub-fan-out line. An end of the transfer line remote from the first sub-fan-out line is located around the isolation portion and is electrically connected to the second sub-fan-out line. An end of the second sub-fan-out line remote from the transfer line extends to the second sub-fan-out region.

[0018] In some embodiments, a position of the transfer line where the transfer line is connected to the second sub-fan-out line is a first connection point. An orthogonal projection of a portion of the transfer line close to the first connection point and beyond the isolation portion at a base thereof substantially overlaps with an orthogonal projection of a portion of the second sub-fan-out line close to the first connection point and beyond the isolation portion at a base thereof.

[0019] In some embodiments, the portions of the multiple transfer lines that are close to the first connection point and extend beyond the isolation portion are located on at least one side of the isolation portion along the first direction. The portions of the multiple transfer lines that are close to the first connection point and extend beyond the isolation portion and that are located on the same side of the isolation portion along the first direction are defined as first extension portions. The multiple first extension portions are sequentially arranged along the second direction, and in the second direction, the lengths of the multiple first extension portions gradually increase and then gradually decrease. Alternatively, the lengths of the multiple first extension portions gradually decrease and then gradually increase.

[0020] In some embodiments, an orthogonal projection of the transfer line at its base is U-shaped or approximately U-shaped with an opening towards the bend region. One end of the transfer line is electrically connected to the first sub-fan-out line and the other end of the transfer line is electrically connected to the second sub-fan-out line.

[0021] In some embodiments, the plurality of conductive layers includes at least one gate metal layer, a first source-drain metal layer, and a second source-drain metal layer, the first source-drain metal layer and the second source-drain metal layer being both located away from the base of the at least one gate metal layer, and the first source-drain metal layer being closer to the base than the second source-drain metal layer, the first sub-fan-out line, the second sub-fan-out line, and the plurality of second fan-out lines being located in the at least one gate metal layer, the isolation portion being located in the first source-drain metal layer, and the transfer line being located in the second source-drain metal layer.

[0022] In some embodiments, the isolation portion includes at least one power signal line.

[0023] In some embodiments, the second fan-out region includes a first sub-fan-out region and a second sub-fan-out region, the first sub-fan-out region is closer to the bend region than the second sub-fan-out region, and the transfer line is located in the second sub-fan-out region.

[0024] In some embodiments, the transfer line includes a first sub-transfer line and a second sub-transfer line. The first sub-transfer line is electrically connected to the first sub-fan-out line. The first sub-transfer line spans at least one second fan-out line. The second sub-transfer line is electrically connected to an end of the first sub-transfer line remote from the first sub-fan-out line. An orthogonal projection at a base of the at least one second sub-transfer line is located between orthogonal projections at bases of two adjacent second fan-out lines.

[0025] In some embodiments, the centerline of the display substrate is located at the center of the display substrate along the first direction and is parallel to the base. The second sub-fan-out region includes two first regions, the two first regions located on either side of the centerline. At least one first region includes a plurality of sub-regions, the plurality of sub-regions including a first sub-region, a second sub-region, and a third sub-region. The first sub-region, the second sub-region, and the third sub-region are arranged in order along a direction from an edge away from the centerline of the first region to the centerline. An end of the first sub-transmission line electrically connected to the first sub-fan-out line is located in at least one of the first sub-region, the second sub-region, and the third sub-region, and the second sub-transmission line is located in the first sub-region.

[0026] In some embodiments, ends of the plurality of first sub-transmission lines that are electrically connected to the first sub-fan-out line are located in different sub-regions of the first region.

[0027] In some embodiments, ends of the plurality of first sub-transmission lines electrically connected to the first sub-fan-out line are evenly distributed in the first sub-region, the second sub-region, and the third sub-region.

[0028] In some embodiments, the outline shape of the region in which the orthogonal projections of all the first sub-transfer lines in the first region are located is a trapezoid or a triangle.

[0029] In some embodiments, the second sub-fan-out region includes a second region and a third region, the second region being closer to the first sub-fan-out region than the third region. A length of an edge of the second region closer to the first sub-fan-out region is greater than a length of an edge of the second region away from the first sub-fan-out region. The first sub-transfer lines extend along a first direction and the second sub-transfer lines extend along a second direction. At least one first sub-transfer line is located in the second region and at least one second sub-transfer line extends from the second region to the third region.

[0030] In some embodiments, along a direction from the first sub-fan-out region to the second sub-fan-out region, a distance between at least two adjacent first sub-transmission lines gradually decreases.

[0031] In some embodiments, the first fan-out line further includes a second sub-fan-out line, the second sub-fan-out line being located in a different conductive layer than the transfer line, the second sub-fan-out line being located in the second sub-fan-out region and electrically connected to an end of the transfer line remote from the first sub-fan-out line.

[0032] In some embodiments, an orthogonal projection of the transfer line at its base is U-shaped or approximately U-shaped with an opening towards the bend region. One end of the transfer line is electrically connected to the first sub-fan-out line and the other end of the transfer line is electrically connected to the second sub-fan-out line.

[0033] In some embodiments, the plurality of conductive layers includes at least one gate metal layer, a first source-drain metal layer, and a second source-drain metal layer, the first source-drain metal layer and the second source-drain metal layer being both located away from the base of the at least one gate metal layer, and the first source-drain metal layer being closer to the base than the second source-drain metal layer, the first sub-fan-out line, the second sub-fan-out line, and the plurality of second fan-out lines being located in the at least one gate metal layer, and the transfer lines alternating between the first source-drain metal layer and the second source-drain metal layer.

[0034] In some embodiments, the at least one gate metal layer includes a first gate metal layer and a second gate metal layer, the first gate metal layer being closer to the base than the second gate metal layer. The first sub-fan-out lines, the second sub-fan-out lines, and the second fan-out lines are located in the first gate metal layer and the second gate metal layer. Any two adjacent fan-out lines of the first sub-fan-out lines and the second fan-out lines are located in different gate metal layers. Any two adjacent fan-out lines of the second sub-fan-out lines and the second fan-out lines are located in different gate metal layers.

[0035] In some embodiments, the plurality of conductive layers include a light shielding metal layer, at least one active layer, at least one source-drain metal layer, a plurality of gate metal layers, at least one transparent conductive layer, and an anode layer. The transfer line is located in at least one of the light shielding metal layer, the at least one active layer, the at least one source-drain metal layer, one of the plurality of gate metal layers, the at least one transparent conductive layer, and the anode layer. The plurality of second fan-out lines are located in at least one of the plurality of gate metal layers.

[0036] In another aspect, a display device is provided, comprising a display substrate as described above.

[0037] The display substrate and display device provided by the present disclosure have the following beneficial effects.

[0038] In the embodiment of the present disclosure, the second ends of the connecting lines are located in the central region and extend to a position close to the fan-out region of the central region, so that the first fan-out lines can be electrically connected to the second ends of the connecting lines at a position close to the center line of the display substrate. In this way, the gathering of the fan-out lines in the fan-out region and the space occupied along the second direction when extending along a direction away from the display region can be reduced, and thus the width of the fan-out region along the second direction can be reduced. That is, the width of the side frame (e.g., bottom frame) of the display panel can be reduced, so that the display panel can realize an ultra-narrow bottom frame and improve the visual effect of the display panel.

[0039] In addition, by adopting the above-mentioned installation method, the first data line at the round corner position can be electrically connected to the first fan-out line through the connection line, and the first fan-out line can be prevented from occupying the space of the fan-out area close to the round corner position, so that the frame width at the round corner can be reduced, and the display area of ​​the display panel can realize an extra-large round corner. On the one hand, the visual effect of the display panel can be improved, and on the other hand, the installation convenience between the outer frame of the display panel and the display panel can be improved, the stress on the frame during installation can be reduced, and the possibility of wrinkles and cracks on the frame due to the installation stress can be reduced, and the processing convenience of the display device can be improved, and the yield of the display device can be improved.

[0040] In addition, by arranging the first fan-out line to include a transfer line and spanning at least one second fan-out line, the transfer line can adjust the arrangement order of the ends of the multiple first fan-out lines away from the display area (i.e., the ends of the first fan-out lines electrically connected to the driving ICs), along the first direction, thereby adjusting the arrangement order of the ends of the multiple fan-out lines away from the display area, along the first direction.

[0041] Such an arrangement results in the same arrangement order of the output ends of the driving ICs (full English name: Integrated Circuit, English abbreviation: IC) in the first direction, the arrangement order of the ends of the multiple fan-out lines away from the display area in the first direction, and the arrangement order of the multiple data lines in the first direction, so that the output ends of the driving ICs can provide driving signals to the multiple data lines in sequence, i.e., the driving ICs can drive the emission of multiple columns of sub-pixels in sequence. This eliminates the need to redevelop the driving ICs to achieve a narrower frame on the display substrate, and reduces the cost of the display substrate.

[0042] In addition, the transfer lines are disposed in the second fan-out region, which prevents the transfer lines from occupying space in the first fan-out region and reduces the width of the first fan-out region in the second direction. Since the first fan-out region is located on the side of the curved region closer to the display region, reducing the width of the first fan-out region in the second direction can further reduce the width of the side frame (e.g., bottom frame) of the display substrate, thereby improving the visual effect of the display panel.

[0043] In another aspect, a display device is provided, the display device comprising a display substrate as described above.

[0044] The display device provided by the embodiment of the present disclosure includes the above-mentioned display substrate, and therefore has all the above-mentioned beneficial effects, which will not be repeated here. [Brief description of the drawings]

[0045] In order to more clearly describe the technical solutions according to the present disclosure, the drawings used in some embodiments of the present disclosure will be briefly described below. It is clear that the drawings in the following description are only some drawings of some embodiments of the present disclosure. Those skilled in the art can also obtain other drawings based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and do not limit the actual dimensions of the products, the actual flow of the methods, the actual timing of the signals, etc. according to the embodiments of the present disclosure. [Figure 1]1 is a structural diagram of a display device according to some embodiments; [Diagram 2] 1 is a structural diagram of a display panel according to some embodiments. [Diagram 3] 1A to 1C are structural diagrams of a display substrate according to some embodiments. [Figure 4] 4 is a schematic diagram of a connection structure between a light-emitting element in a sub-pixel and a pixel driving circuit. FIG. [Diagram 5] 11A to 11C are structural diagrams of a display substrate according to some other embodiments of the present disclosure. [Figure 6] 11A to 11C are structural diagrams of display substrates according to some other embodiments. [Figure 7] 11A to 11C are structural diagrams of display substrates according to some other embodiments. [Figure 8] 11A to 11C are structural diagrams of display substrates according to some other embodiments. [Figure 9] 11A to 11C are structural diagrams of display substrates according to some other embodiments. [Figure 10] 11A to 11C are structural diagrams of display substrates according to some other embodiments. [Figure 11] 1A to 1C are partial structural diagrams of a display substrate according to some embodiments. [Figure 12] FIG. 8 is a partial enlarged view of region 1C in FIG. [Figure 13] 11A to 11C are structural diagrams of display substrates according to some other embodiments. [Figure 14] 11A to 11C are structural diagrams of display substrates according to some other embodiments. [Figure 15] FIG. 14 is a partial enlarged view of region 1A in FIG. [Figure 16] FIG. 14 is a partial enlarged view of region 2A in FIG. [Figure 17] FIG. 14 is a partial enlarged view of region 3A in FIG. [Figure 18] FIG. 14 is a partial enlarged view of region 4A in FIG. [Figure 19] FIG. 14 is a partial enlarged view of region 5A in FIG. [Figure 20] FIG. 14 is a partial enlarged view of region 6A in FIG. [Figure 21] FIG. 14 is a partial enlarged view of region 7A in FIG. [Figure 22] 11A to 11C are structural diagrams of display substrates according to some other embodiments. [Diagram 23] 11A to 11C are partial structural views of a display substrate according to some other embodiments. [Figure 24] FIG. 24 is a partial enlarged view of region 1B in FIG. 23. [Diagram 25] FIG. 24 is a partial enlarged view of region 2B in FIG. 23. [Figure 26] FIG. 24 is a partial enlarged view of region 3B in FIG. 23. [Figure 27] 11A to 11C are partial structural diagrams of display substrates according to some other embodiments. [Figure 28] FIG. 28 is a partial enlarged view of region 1D in FIG. 27. [Figure 29] 11A to 11C are partial structural diagrams of display substrates according to some other embodiments. [Diagram 30] 11A to 11C are partial structural diagrams of display substrates according to some other embodiments. [Diagram 31] 11A to 11C are partial structural diagrams of display substrates according to some other embodiments. [Diagram 32] 11A to 11C are partial structural diagrams of display substrates according to some other embodiments. [Diagram 33] FIG. 33 is a partial enlarged view of region 1E in FIG. 32. [Diagram 34] FIG. 28 is a partial enlarged view of region 2D in FIG. 27. [Diagram 35] FIG. 35 is a partial enlarged view of region 1F in FIG. 34. [Diagram 36] FIG. 35 is a partial enlarged view of region 2F in FIG. 34. [Figure 37] FIG. 28 is a partial enlarged view of region 3D in FIG. 27. [Figure 38] FIG. 28 is a partial enlarged view of region 4D in FIG. [Figure 39] 11A to 11C are partial structural diagrams of display substrates according to some other embodiments. [Diagram 40] FIG. 35 is a partial enlarged view of region 3F in FIG. 34. [Diagram 41] 11A to 11C are partial structural diagrams of display substrates according to some other embodiments. [Diagram 42]FIG. 24 is a partial enlarged view of region 4B in FIG. 23. [Diagram 43] FIG. 24 is a partial enlarged view of region 5B in FIG. 23. [Diagram 44] FIG. 2 is a structural diagram of a transfer line according to some embodiments. [Diagram 45] 11A to 11C are partial structural diagrams of display substrates according to some other embodiments. [Figure 46] 11A to 11C are partial structural diagrams of display substrates according to some other embodiments. [Figure 47] FIG. 47 is a partial enlarged view of region 1H in FIG. 46. [Figure 48] FIG. 47 is a partial enlarged view of region 2H in FIG. 46. [Figure 49] 11A to 11C are partial structural diagrams of display substrates according to some other embodiments. [Figure 50] FIG. 50 is a partial enlarged view of region 3H in FIG. 49. [Figure 51] 11A to 11C are partial structural diagrams of display substrates according to some other embodiments. [Figure 52] 11A to 11C are partial structural diagrams of display substrates according to some other embodiments. [Figure 53] 11A to 11C are partial structural diagrams of display substrates according to some other embodiments. [Figure 54] 11A to 11C are partial structural diagrams of display substrates according to some other embodiments. [Figure 55] 11A to 11C are partial structural diagrams of display substrates according to some other embodiments. [Figure 56] 11A to 11C are partial structural diagrams of display substrates according to some other embodiments. [Figure 57] 11A to 11C are partial structural diagrams of display substrates according to some other embodiments. [Figure 58] 11A to 11C are partial structural diagrams of display substrates according to some other embodiments. [Figure 59] 11A to 11C are partial structural diagrams of display substrates according to some other embodiments. [Figure 60] FIG. 60 is a partial enlarged view of region 4H in FIG. 59. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0046] Hereinafter, some embodiments of the present disclosure will be described clearly and completely with reference to the drawings. Of course, the embodiments described herein are only a part of the embodiments of the present disclosure, and are not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments that can be obtained by those skilled in the art shall be included in the protection scope of the present disclosure.

[0047] Unless the context indicates otherwise, in this specification and claims, the term "comprise" and other forms thereof, such as the third person singular "comprises" and the present participle form "comprising," are to be interpreted in an open, inclusive sense, i.e., "including but not limited to."

[0048] In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with this embodiment or example is included in at least one embodiment or example of the disclosure. General expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, a particular feature, structure, material, or characteristic described may be included in any one or more embodiments or examples in any suitable manner.

[0049] In the following, the terms "first" and "second" are for descriptive purposes only and should not be understood as indicating or implying the relative importance or quantity of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more than two.

[0050] In describing some embodiments, the term "connected" and its derivatives may be used. For example, in describing some embodiments, the term "connected" may be used to indicate that two or more elements are in direct physical or electrical contact with each other.

[0051] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C," and all include combinations of A, B, and C, such as A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0052] In this specification, "applied to" or "disposed to" are intended to be open and inclusive language.

[0053] As used herein, "parallel", "perpendicular" and "equal" include the described situation and the situation approximating the described situation, the range of approximating situations being within an acceptable deviation range, the acceptable deviation range being determined by taking into consideration the measurement considered by a person skilled in the art and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes true parallel and approximately parallel, where the acceptable deviation range of approximately parallel may be, for example, within 5°, and "perpendicular" includes true perpendicular and approximately perpendicular, where the acceptable deviation range of approximately perpendicular may be, for example, within 5°. "Equal" includes absolutely equal and approximately equal, where, within the acceptable deviation range of approximately equal, for example, the difference between the two equals is 5% or less.

[0054] When a layer or element is referred to as being on another layer or substrate, it is understood that the layer or element may be directly on the other layer or substrate, or there may be an intermediate layer between the layer or element and another layer or substrate.

[0055] It is understood that in the embodiments of the present disclosure, an "electrical connection" may be a direct connection, or the electrical connection may be realized via other wiring (e.g., a signal transmission line).

[0056] In the embodiments of the present disclosure, it is understood that "two conductive wires are adjacent" may refer to the two conductive wires being located in the same conductive layer and being adjacent, or may refer to the two conductive wires being located in different conductive layers and the orthogonal projections at the bases of the two conductive wires being adjacent.

[0057] FIG. 1 is a structural diagram of a display device according to some embodiments.

[0058] As shown in Fig. 1, in some embodiments of the present disclosure, a display substrate 200 is provided. It is understood that the display device 200 is a product having an image display function. Exemplarily, the display device 200 may be used to display still images such as pictures and photographs. The display device 200 may be used to display moving images such as videos and game screens.

[0059] In some examples, the display device 200 may be a laptop, a mobile phone, a wireless device, a personal data assistant (PDA), a handheld or portable computer, a GPS receiver / navigator, a camera, an MP4 video player, a video camera, a game console, a watch, a clock, a calculator, a television monitor, a flat panel display, a computer monitor, an car display (e.g., a speedometer display, a distance meter display, etc.), a navigator, a cockpit controller and / or display, a display of a camera view (e.g., a rear view camera display in a vehicle), electronic photography, electronic signage or signs, projectors, packaging and aesthetic structures (e.g., a display of an image of a piece of jewelry), and the like.

[0060] The display device 200 includes a display panel 210. In some examples, the display panel 210 is an organic light-emitting diode display (OLED) or a quantum dot light-emitting diode display (QLED).

[0061] In addition, the display device 200 may be equipped with an under-screen camera and an under-screen fingerprint recognition sensor, etc., so that the display device 200 can realize various different functions, such as photographing, video recording, fingerprint recognition, or face recognition.

[0062] FIG. 2 is a structural diagram of a display panel according to some embodiments.

[0063] The display panel 210 includes a display substrate 100. Exemplarily, as shown in Fig. 2, the display panel 210 may further include other functional film layers 211 located on the display side of the display substrate 100, such as a touch control functional layer, a reflection reducing layer, an anti-fingerprint layer, a hardening layer, and a package cover, so that the display panel 210 can achieve different functions.

[0064] The embodiment of the present disclosure does not further limit other functional layers 211 of the display panel 210. The display substrate 100 will be described below by way of example.

[0065] FIG. 3 is a structural diagram of a display substrate according to some embodiments.

[0066] In some examples, as shown in Fig. 3, the display substrate 100 includes a plurality of sub-pixels 101. The sub-pixels 101 are arranged in a plurality of columns along a first direction X and in a plurality of rows along a second direction Y. In some examples, the first direction X intersects with the second direction Y. Exemplarily, the first direction X is perpendicular to the second direction Y. In some examples, the first direction X is a horizontal direction and the second direction Y is a vertical direction.

[0067] It is understood that the sub-pixel 101 is the smallest unit for the display substrate 100 to display an image. Each sub-pixel 101 may display a single color, such as red, green, or blue. The display substrate 100 may include a plurality of red sub-pixels, a plurality of green sub-pixels, and a plurality of blue sub-pixels. By adjusting the brightness (gray scale) of the sub-pixels 101 of different colors, different intensities of red light, green light, and blue light can be obtained. By overlapping at least two of the red light, green light, and blue light of different intensities, more colors of light can be displayed, so that the full-color display of the display substrate 100 is realized.

[0068] 3, it is understood that the display substrate 100 has a display area AA and a fan-out area BB, the fan-out area BB being adjacent to one edge of the display area AA, where the display area AA is used for displaying image information, and a number of sub-pixels 101 are located in the display area AA of the display substrate 100.

[0069] In addition, the fan-out region BB is adjacent to one edge of the display region AA. That is, the edge of the fan-out region BB close to the display region AA overlaps with the edge of the display region AA close to the fan-out region BB. In the accompanying drawings of the present disclosure, taking FIG. 3 as an example, the edge of the fan-out region BB and the edge of the display region AA are separated from each other, but this is merely for the purpose of easily showing the display region AA and the fan-out region BB, and does not further limit the display region AA and the fan-out region BB.

[0070] In some examples, as shown in FIG. 3, the fan-out region BB is located on one side of the display area AA along the second direction Y.

[0071] 3, the fan-out region BB is adjacent to a lower edge of the display area AA. That is, the fan-out region BB is located below the display area AA along the second direction Y. Exemplarily, when the display device 200 is used in a state in which it is vertical or substantially vertical to the ground, the fan-out region BB is closer to the ground than the display area AA.

[0072] In some examples, each sub-pixel 101 includes a light-emitting element 300 and a pixel drive circuit that is electrically connected to the light-emitting element 300 and is used to drive the light-emitting element 300 to emit light.

[0073] FIG. 4 is a schematic diagram of a connection structure between a light emitting element in a sub-pixel and a pixel driving circuit.

[0074] 4, the display substrate 100 includes a base 102 and a plurality of conductive layers 103. The plurality of conductive layers 103 are located on the same side of the base 102, and the plurality of conductive layers 103 are arranged in a stacked manner.

[0075] In some examples, the base 102 is a flexible material, thereby allowing the display substrate 100 to bend, so that the display panel 210 can achieve functions such as curved display, folding display, or scrolling. In some other examples, the base 102 is a rigid material.

[0076] For example, the material of the base 102 may be any one of polyimide (official English name: Polyimide, English abbreviation: PI), polycarbonate (official English name: Polycarbonate, English abbreviation: PC), or polyvinyl chloride (official English name: polyvinyl chloride, English abbreviation: PVC).

[0077] In some examples, an insulating layer (e.g., a gate insulating layer and a buffer layer, a passivation layer, an organic layer, etc.) may be provided between multiple conductive layers 103, which serves to electrically isolate two adjacent conductive layers 103.

[0078] Exemplarily, the pixel driving circuit is provided in the plurality of conductive layers 103. In some examples, as shown in FIG. 4, the plurality of conductive layers 103 include an active layer 1031, a first gate metal layer Gate1, a second gate metal layer Gate2, a first source-drain metal layer SD1, and a second source-drain metal layer SD2, which are arranged in sequence away from the base 102.

[0079] The pixel driving circuit includes a plurality of thin film transistors (full English name: Thin Film Transistor, English abbreviation: TFT) and at least one capacitor. Exemplarily, the active layer 1031 and the first gate metal layer Gate1 may be used to form a part of the plurality of thin film transistors (one or more). The active layer 1031 and the second gate metal layer Gate2 may be used to form another part of the plurality of thin film transistors (one or more). The first gate metal layer Gate1 and the second gate metal layer Gate2 may be used to form at least one capacitor.

[0080] It should be noted that the number of active layers 1031 is not limited. For example, some embodiments of the present disclosure may include only one active layer 1031, and the material of the active layer 1031 may include metal oxide and low-temperature polysilicon. Alternatively, some embodiments of the present disclosure may further include two active layers 1031, where the material of one active layer 1031 includes metal oxide and the material of the other active layer 1031 includes low-temperature polysilicon.

[0081] In some examples, the conductive layers 103 may further include a third gate metal layer (not shown). Exemplarily, the first gate metal layer Gate1, the second gate metal layer Gate2, the third gate metal layer, the first source-drain metal layer SD1, and the second source-drain metal layer SD2 may be stacked in order along a direction away from the base 102.

[0082] As can be seen from the above, the display substrate 100 further includes a light emitting element 300, and the pixel driving circuit is electrically connected to the light emitting element 300. Hereinafter, the light emitting element 300 will be described by way of example, still with reference to FIG.

[0083] In some examples, the light emitting element 300 is located on a side of the plurality of conductive layers 103 that is away from the base 102. Exemplarily, the light emitting element 300 includes an anode layer AND, an emission layer EML, and a cathode layer CTD that are sequentially provided in a direction away from the base 102.

[0084] In some examples, it is understood that the light-emitting layer EML includes a plurality of spaced apart effective light-emitting portions, and the effective light-emitting portions are used to emit light. Exemplarily, the effective light-emitting portions include an electroluminescent material. It is understood that electroluminescence refers to the phenomenon in which an organic semiconductor material, under the driving of an electric field, forms excitons through carrier injection, transport, and combination of electrons and holes, and then emits light through radiative recombination.

[0085] It is understood that among the multiple effective light-emitting portions, some are used to emit red light, others are used to emit green light, and still others are used to emit blue light. Exemplarily, different electroluminescent materials may be selected, so that the effective light-emitting portions emit light of different colors. It is understood that the number of the effective light-emitting portions that emit red light, the effective light-emitting portions that emit green light, and the effective light-emitting portions that emit blue light may be the same or different.

[0086] For example, the effective light-emitting section emitting red light, the effective light-emitting section emitting green light, and the effective light-emitting section emitting blue light may be arranged in a mixed manner, and thus, by controlling the emission intensities of the different effective light-emitting sections, red light, green light, and blue light of different intensities can be obtained. By mixing the red light, green light, and blue light of different intensities, a color image can be displayed on the display substrate 100.

[0087] It is understood that the pixel driving circuit may drive the emission of the emission layer EML. In some examples, one pixel driving circuit is electrically connected to one effective light-emitting section via the anode layer AND, so that each pixel driving circuit can respectively supply a driving current to each effective light-emitting section via the anode layer AND, that is, make the effective light-emitting sections emit light independently, reduce mutual interference between the effective light-emitting sections, and improve the display effect of the display substrate 100. It is understood that the emission brightness of the effective light-emitting section may be adjusted by adjusting the magnitude of the driving current supplied by the pixel driving circuit to the effective light-emitting section.

[0088] In some examples, the anode layer AND is a metal material such as copper or silver. The cathode layer CTD is a transparent material such as transparent indium tin oxide (ITO) or transparent indium zinc oxide (IZO), so that the light emitted from the effective light-emitting part can be emitted through the cathode layer CTD, that is, in this case, the display substrate 100 is a top-emission display substrate.

[0089] In some other examples, the anode layer AND is a transparent material such as ITO or IZO, and the cathode layer CTD is a metallic material such as copper or silver, so that light emitted from the effective light-emitting area can be emitted through the anode layer AND, that is, in this case, the display substrate 100 is a bottom emission display substrate.

[0090] In some other examples, the anode layer AND and the cathode layer CTD are both transparent materials such as ITO or IZO, so that the light emitted from the effective light-emitting area can be emitted through the anode layer AND and the cathode layer CTD, that is, in this case, the display substrate 100 is a double-sided light-emitting display substrate.

[0091] In some examples, based on the work function, the material of the anode layer AND includes ITO or a stack of ITO-Ag-ITO, so that the anode layer AND can supply more holes. The material of the cathode layer CTD includes MgAg, so that the cathode layer CTD can supply more electrons. The cathode layer CTD is very thin and light transmissive, so that the display substrate 100 can achieve top emission.

[0092] In some examples, at least one of a hole injection layer (HIL), a hole transport layer (HTL), and an electron blocking layer (EBL) is provided between the anode layer AND and the effective light-emitting portion along the direction from the anode layer AND to the effective light-emitting portion. At least one of an electron injection layer (EIL), an electron transport layer (ETL), and a hole blocking layer (HBL) is provided between the cathode layer CTD and the effective light-emitting portion along the direction from the cathode layer CTD to the effective light-emitting portion. The above-mentioned installation method improves the light-emitting reliability of the effective light-emitting portion.

[0093] FIG. 5 is a structural diagram of a display substrate according to some other embodiments.

[0094] 5, the display substrate 100 further includes a package layer 104. The package layer 104 may be located on the side of the light-emitting element 300 away from the base 102 and cover the light-emitting element 300, which serves to prevent water vapor and oxygen gas in the external environment from entering the light-emitting element 300 and protect the light-emitting element 300.

[0095] FIG. 6 is a structural diagram of a display substrate according to some other embodiments.

[0096] In some examples, as shown in Fig. 6, the conductive layers 103 further include a plurality of data lines 110 and a plurality of fan-out lines 130 in addition to the pixel driving circuit. It is understood that the data lines 110 are located in the display area AA and are electrically connected to a plurality of pixel driving circuits, and the pixel driving circuits may drive the light emission of the light-emitting elements 300 to realize different gray scales by transmitting driving signals to the pixel driving circuits. The fan-out lines 130 are located in the fan-out area BB and are electrically connected to the data lines 110 in one-to-one correspondence.

[0097] 6, the data lines 110 are spaced apart along a first direction X, and all of the data lines 110 extend along a second direction Y. The second direction Y may intersect with the first direction X, and both the first direction X and the second direction Y may be parallel to the base 102.

[0098] In some examples, the first direction X is perpendicular or substantially perpendicular to the second direction Y. Illustratively, as shown in FIG 6, the first direction X is a horizontal direction and the second direction Y is a vertical direction.

[0099] As can be seen from the above, as shown in Fig. 3, the sub-pixels 101 are arranged in a number of columns along the first direction X and in a number of rows along the second direction Y. That is, the pixel driving circuits of the sub-pixels 101 can be arranged in an array of rows and columns along the first direction X and the second direction Y. As shown in Fig. 6, the data lines 110 may extend along the second direction Y, such that one data line 110 is electrically connected to the pixel driving circuits of one column of the sub-pixels 101 arranged along the second direction Y.

[0100] In some examples, the spacing distances of the multiple data lines 110 along the first direction X are the same or approximately the same.

[0101] As shown in FIG. 6, since the fan-out region BB is adjacent to one edge of the display area AA along the second direction Y, it can be understood that the multiple data lines 110 are arranged to extend along the second direction Y, and the multiple data lines 110 may be electrically connected in one-to-one correspondence to the multiple fan-out lines 130 located within the fan-out region BB.

[0102] 6, the fan-out lines 130 located in the fan-out region BB are gradually converged and extend away from the display area AA of the fan-out region BB, facilitating electrical connection between the fan-out lines 130 and a driving chip (Integrated Circuit, IC) outside the display substrate 100. It is understood that the driving IC may input signals to each pixel driving circuit via the fan-out lines 130 and the data lines 110.

[0103] In some examples, the multiple fan-out lines 130 may be electrically connected to a driving IC by extending the side of the multiple fan-out lines 130 away from the display area AA to the edge of the fan-out area BB away from the display area AA.

[0104] However, the above implementation method increases the space occupied by the multiple fan-out lines 130 along the second direction Y, thereby increasing the width of the fan-out region BB, i.e., increasing the width of the side frame (e.g., the bottom frame) of the display panel 210, which is disadvantageous to achieving a narrow frame of the display panel 210 and affects the visual effect of the display panel 210.

[0105] 7 and 8 are structural diagrams of display substrates according to still other embodiments.

[0106] In order to reduce the width of the side frame (eg, bottom frame) of the display panel 210, a display substrate 100 is provided in some embodiments of the present disclosure, as shown in FIG.

[0107] The display substrate 100 includes a display area AA and a fan-out area BB. The fan-out area BB is adjacent to one edge of the display area AA. The display substrate 100 includes a base 102 and a plurality of conductive layers 103. The conductive layers 103 are located on the same side of the base 102. The conductive layers 103 are arranged in a stacked manner. The conductive layers 103 include a plurality of data lines 110. The data lines 110 are spaced apart along a first direction X, and all of the data lines 110 extend along a second direction Y. The second direction Y intersects with the first direction X.

[0108] It should be noted that the above embodiment of the present disclosure has already described the display area AA, the fan-out area BB, the base 102, the conductive layers 103, and the data lines 110, etc., by way of example, and will not be repeated here. Hereinafter, the display substrate 100 provided by the embodiment of the present disclosure will be described by way of example with reference to Figures 7 and 8.

[0109] 7, the multiple data lines 110 include multiple first data lines 111 and multiple second data lines 112. The multiple first data lines 111 are located in two edge regions AA1 along the first direction X of the display area AA, and the multiple second data lines 112 are located in a central region AA2 along the first direction X of the display area AA.

[0110] 7 and 8, there are two edge regions AA1, and the two edge regions AA1 are located on both sides of the display substrate 100 along the first direction X. The central region AA2 is located between the two edge regions AA1 along the first direction X.

[0111] Exemplarily, the numbers of the first data lines 111 and the second data lines 112 may be the same or different, and the numbers of the first data lines 111 located in the two edge regions AA1 may be the same or different.

[0112] It should be noted that in each embodiment of the present disclosure, the first data line 111 and the second data line 112 are only used to distinguish the data lines 110 located in the edge region AA1 and the central region AA2, and do not further limit the data lines 110.

[0113] Exemplarily, the widths of the two edge regions AA1 of the display area AA along the first direction X are the same or approximately the same. In some examples, as shown in FIG. 7, the display area AA includes a rounded corner, i.e., two adjacent edges of the display area AA are connected in an arc-like or approximately arc-like manner. The rounded corner is located within the edge region AA1 of the display area AA. Exemplarily, the width of the edge region AA1 in the first direction X may be equal to or greater than the width of the rounded corner in the first direction X.

[0114] Exemplarily, the plurality of first data lines 111 and the plurality of second data lines 112 are located in the same conductive layer 103. In some examples, the plurality of first data lines 111 and the plurality of second data lines 112 are both located in the first source-drain metal layer SD1. In some other examples, the plurality of first data lines 111 and the plurality of second data lines 112 are both located in the second source-drain metal layer SD2. In some other examples, the plurality of first data lines 111 and the plurality of second data lines 112 may be located in another conductive layer 103 other than the first source-drain metal layer SD1 and the second source-drain metal layer SD2.

[0115] 7 and 8, the conductive layers 103 further include a plurality of connecting lines 120. A first end of one connecting line 120 is located in an edge region AA1 of the display area AA and is electrically connected to one first data line 111. A second end of the connecting line 120 extends to a position close to the fan-out region BB in a central region AA2 of the display area AA.

[0116] For example, as shown in FIGS. 7 and 8, the second ends of any of the plurality of connection lines 120 extend to the central area AA2 of the display area AA.

[0117] As can be seen from the above, the edge of the display area AA close to the fan-out area BB overlaps with the edge of the fan-out area BB close to the display area AA. In some examples, the second end of the connection line 120 may extend to the boundary between the central area AA2 and the fan-out area BB. In some other examples, the second end of the connection line 120 may have a gap between the boundary between the central area AA2 and the fan-out area BB.

[0118] As shown in FIGS. 7 and 8, the connecting line 120 spans at least one data line 110 (eg, the first data line 111 and / or the second data line 112) and is insulated from the data line 110 it spans.

[0119] It is understood that since the multiple data lines 110 are spaced apart along the first direction, when the second end of the connecting line 120 extends to a position close to the fan-out region BB of the central region AA2, it is necessary to span at least one data line 110. Exemplarily, the at least one connecting line 120 may span both the first data line 111 and the second data line 112.

[0120] It is understood that the connecting line 120 spans at least one data line 110 if the orthogonal projection of the connecting line 120 on the base 102 intersects with the orthogonal projection of at least one data line 110 on the base 102 .

[0121] In some examples, the connecting lines 120 and the data lines 110 may be located on different conductive layers 103 such that the connecting lines 120 are insulated from the data lines 110 that they cross.

[0122] Exemplarily, the data line 110 is located in the first source-drain metal layer SD1, and the connection line 120 is located in the second source-drain metal layer SD2, or the data line 110 is located in the second source-drain metal layer SD2, and the connection line 120 is located in the second gate metal layer Gate2.

[0123] Exemplarily, when the connecting line 120 and the data line 110 are located in different conductive layers 103, the first end of the connecting line 120 may be electrically connected to the first data line 111 through a transfer hole. It is understood that the transfer hole may penetrate an insulating film layer between two adjacent conductive layers 103 along a direction perpendicular or substantially perpendicular to the base 102, thereby electrically connecting the different conductive layers 103, that is, electrically connecting conductive wiring (e.g., the connecting line 120 and the data line 110) located in the different conductive layers 103. Exemplarily, the conductive wiring located in two non-adjacent conductive layers 103 may be electrically connected through a plurality of transfer holes penetrating different insulating films. By way of example, and for ease of explanation, a transfer hole electrically connecting a conductive wiring in the first source-drain metal layer SD1 to a conductive wiring in the second source-drain metal layer SD2 may be referred to as a PLN hole, and a transfer hole electrically connecting a conductive wiring in the first gate metal layer Gate1 to a conductive wiring in the second gate metal layer Gate2 may be referred to as an ILD hole.

[0124] That is, when the first data line 111 is located in the first source-drain metal layer SD1 and the connecting line 120 is located in the second source-drain metal layer SD2, the first end of the connecting line 120 can be electrically connected to the first data line 111 through the PLN hole. When the first data line 111 is located in the second source-drain metal layer SD2 and the connecting line 120 is located in the second gate metal layer Gate2, the first end of the connecting line 120 is first electrically connected to the conductive wiring in the first gate metal layer Gate1 through the ILD hole, and then electrically connects the conductive wiring in the first gate metal layer Gate1 and the first data line 111 in the second source-drain metal layer SD2 through another transfer hole, so that the connecting line 120 can be electrically connected to the first data line 111.

[0125] As can be seen from the above, in some examples, the connecting line 120 and the data line 110 are located on different conductive layers 103, so that the connecting line 120 can be insulated from the data line 110 that it crosses. In some other examples, the connecting line 120 includes a body portion and a jumper portion, where the body portion and the jumper portion can be electrically connected via a transfer hole. The body portion can be located on the same conductive layer 103 as the data line 110, but the jumper portion can be located on a different conductive layer 103 than the data line 110, so that the jumper portion can cross at least one data line 110 and be insulated from the data line 110 that it crosses.

[0126] 7 and 8, the second end of at least one connecting line 120 is located between two adjacent second data lines 112. That is, the second end of one connecting line 120 may be disposed between two adjacent second data lines 112, or the second ends of two or more connecting lines 120 may be disposed between two adjacent second data lines 112.

[0127] It is understood that, as shown in Figures 7 and 8, between any two adjacent second data lines 112 of a set, there may be one second end of the connecting line 120, there may be two or more second ends of the connecting lines 120, or there may be no second end of the connecting line 120. The number of second ends of the connecting lines 120 between different two adjacent second data lines 112 may be the same or different.

[0128] As shown in Figures 7 and 8, the second end of the connecting line 120 is located between two adjacent second data lines 112, so that the second end of the connecting line 120 can extend through the space between the two adjacent second data lines 112 to a position close to the fan-out region BB of the central region AA2 of the display area AA.

[0129] It is understood that the number of connecting lines 120 and the number of first data lines 110 may be the same or different.

[0130] In some examples, the number of the connection lines 120 is the same as the number of the first data lines 110. The multiple connection lines 120 and the multiple first data lines 111 are connected in one-to-one correspondence. Exemplarily, such an installation method may be called FIAA (full English name: Fanout In AA) or FIP (full English name: Fanout In Panel).

[0131] In some other examples, the number of the connecting lines 120 is less than the number of the first data lines 111. In this case, all the connecting lines 120 may be connected to some of the first data lines 111 in one-to-one correspondence, while some of the other first data lines 111 may not be connected to the connecting lines 120. Illustratively, such an installation method may be referred to as partial FIAA.

[0132] In some examples, as shown in FIG. 7, the connection line 120 includes a first sub-connection line 121 and a second sub-connection line 122. One end of the first sub-connection line 121 is located in the edge region AA1 and is electrically connected to the first data line 111. The other end of the first sub-connection line 121 extends to the central region AA2. One end of the second sub-connection line 122 is electrically connected to an end of the first sub-connection line 121 away from the first data line 111, and the other end of the second sub-connection line 122 extends to a position close to the fan-out region BB in the central region AA2. Exemplarily, the first sub-connection line 121 extends along the first direction X, the second sub-connection line 122 extends along the second direction Y, and the first sub-connection line 121 is perpendicular or substantially perpendicular to the second sub-connection line 122.

[0133] As can be seen from the above, in some examples, the connecting line 120 includes a body portion and a jumper portion. Illustratively, as shown in FIG. 7, when the connecting line 120 includes a first sub-connecting line 121 and a second sub-connecting line 122, the second sub-connecting line 122 is a body portion and is located on the same conductive layer 103 as the plurality of data lines 110, and the first sub-connecting line 121 is a jumper portion and is located on a different conductive layer 103 from the plurality of data lines 110. The first sub-connecting line 121 may span at least one data line 110 and be insulated from the data line 110 that it spans.

[0134] In some examples, the first sub-connection line 121 is farther away from the base 102 than the multiple data lines 110, reducing parasitic capacitance between the first sub-connection line 121 and the conductive layer 103 (e.g., the first gate metal layer Gate1 and the second gate metal layer Gate2, etc.) and improving signal transmission reliability.

[0135] 7, the plurality of conductive layers 103 further includes a plurality of fan-out lines 130. The plurality of fan-out lines 130 are located in a fan-out region BB. The plurality of fan-out lines 130 include a plurality of first fan-out lines 131 and a plurality of second fan-out lines 132. The first fan-out lines 131 are electrically connected to the second end of the connection line 120, and the second fan-out lines 132 are electrically connected to an end of the second data line 112 close to the fan-out region BB.

[0136] It is understood that the number of the first fan-out lines 131 may be the same as the number of the connection lines 120, so that the multiple first fan-out lines 131 may be electrically connected to the multiple connection lines 120 in one-to-one correspondence. The number of the second fan-out lines 132 may be the same as or different from the number of the second data lines 112.

[0137] For example, when the multiple first data lines 111 are electrically connected to the multiple connection lines 120 in one-to-one correspondence (i.e., FIAA), the number of second fan-out lines 132 is the same as the number of second data lines 112, and the multiple second fan-out lines 132 are electrically connected to the multiple second data lines 112 in one-to-one correspondence.

[0138] When some of the first data lines 111 are electrically connected to the multiple connection lines 120 in one-to-one correspondence (partial FIAA, i.e., when the number of the first data lines 111 is greater than the number of the connection lines 120), the number of the second fan-out lines 132 is different from the number of the second data lines 112. In this case, among the multiple second fan-out lines 132, some of the second fan-out lines 132 (two or more) are electrically connected to the second data lines 112 in one-to-one correspondence, and the other some of the second fan-out lines 132 (two or more) are electrically connected to the first data lines 111 that are not electrically connected to the connection lines 120 in one-to-one correspondence.

[0139] It is understood that the number of the above fan-out lines 130 (including the first fan-out line 131 and the second fan-out line 132) may be the same as the number of the data lines 110 (including the first data line 111 and the second data line 112). A signal outputted by the driving IC may be transmitted through one fan-out line 130 to one data line 110 electrically connected to the fan-out line 130, thereby realizing driving of one column of sub-pixels 101.

[0140] 7 and 8, the center line Q of the display substrate 100 is located at the center of the display substrate 100 along the first direction X and is parallel to the base 102. It is understood that the center line Q is an imaginary reference line, and the center line Q is located within the central area AA2 of the display substrate 100.

[0141] As shown in FIG. 7, it can be understood that the second end of the connecting line 120 is located within the central region AA2 and extends to a position close to the fan-out region BB of the central region AA2, and thus the multiple first fan-out lines 131 may be electrically connected to the second end of the connecting line 120 at a position close to the center line Q of the display substrate 100.

[0142] By arranging in this manner, when the multiple fan-out lines 130 gather in the fan-out region BB and extend in a direction away from the display region AA, it is possible to reduce the space occupied along the second direction Y. This makes it possible to reduce the width of the fan-out region BB along the second direction Y, that is, to reduce the width of the side frame (e.g., bottom frame) of the display panel 210, thereby realizing an ultra-narrow bottom frame of the display panel 210 and improving the visual effect of the display panel 210.

[0143] Also, as can be seen from the above, the round corner is located within the edge area AA1 of the display area AA. Therefore, by adopting the above installation method, the first data line 111 at the round corner position can be electrically connected to the first fan-out line 131 through the connection line 120, and the first fan-out line 131 can be prevented from occupying the space of the fan-out area BB close to the round corner position, so that the frame width at the round corner can be reduced, and the display area AA of the display panel 210 can realize an extra-large round corner. In this way, the visual effect of the display panel 210 can be improved, and the installation convenience between the outer frame of the display panel 210 and the display panel 210 can be improved, the stress on the frame during installation can be reduced, and the possibility of wrinkles and cracks on the frame due to the installation stress can be reduced, and the processing convenience of the display device 200 can be improved, and the yield of the display device 200 can be further improved.

[0144] As can be seen from the above, in some examples, as shown in FIG. 8, among the multiple second data lines 112 arranged at a distance, the second end of at least one connecting line 120 is provided between some two adjacent second data lines 112, and the second end of the connecting line 120 is not provided between some other two adjacent second data lines 112.

[0145] Such an arrangement can reduce the spacing between the data lines 110 and improve the pixel density of the display area AA, thereby enabling the display panel 210 to achieve a high PPI (official English name: Pixels Per Inch).

[0146] As described above, by using the FIAA or partial FIAA method, the display panel 210 can achieve a narrow frame on a high resolution. In some examples, the display panel 210 may be a QHD (Quad High Definition) display panel.

[0147] 9 and 10 are structural diagrams of display substrates according to still other embodiments.

[0148] Hereinafter, the display substrate 100 will be described by way of example with reference to Figures 7 to 10. In some embodiments, as shown in Figures 7 to 10, any two adjacent connection lines 120 may be defined as a first connection line 120a and a second connection line 120b. It is understood that in the embodiments of the present disclosure, the first connection line 120a and the second connection line 120b are only used to distinguish the two adjacent connection lines 120, and do not further limit the connection lines 120.

[0149] 7 and 9, the first data line 111 electrically connected to the first end of the first connecting line 120a is farther away from the center line Q of the display substrate 100 than the first data line 111 electrically connected to the first end of the second connecting line 120b. And, the second end of the first connecting line 120a is closer to the center line Q of the display substrate 100 than the second end of the second connecting line 120b. Exemplarily, the above connection manner may be referred to as reverse order FIAA.

[0150] 8 and 10, the first data line 111 electrically connected to the first end of the first connecting line 120a is closer to the center line Q of the display substrate 100 than the first data line 111 electrically connected to the first end of the second connecting line 120b. Also, the second end of the first connecting line 120a is closer to the center line Q of the display substrate 100 than the second end of the second connecting line 120b. Exemplarily, the above connection manner may be referred to as forward order FIAA.

[0151] As shown in FIGS. 7 to 10, when the first data line 111 is electrically connected to the first fan-out line 131 via the connection line 120 (for example, using the reverse-order FIAA or forward-order FIAA described above), it is understood that the arrangement order along the first direction X of the ends (for example, the ends electrically connected to the driving IC) of the plurality of fan-out lines 130 (including the first fan-out line 131 and the second fan-out line 132) away from the display area AA is different from the arrangement order along the first direction X of the plurality of data lines 110 (including the first data line 111 and the second data line 112).

[0152] Exemplarily, one edge of the display substrate 100 in the first direction X may be defined as the first edge. It is understood that the first edge is either one of the two edges of the display substrate 100 in the first direction X.

[0153] Exemplarily, the plurality of data lines 110 (including the first data line 111 and the second data line 112) arranged at intervals along the direction from the first edge of the display substrate 100 to the center line Q of the display substrate 100 may be defined as the first data line 110 to the nth data line 110. Here, the first data line 110 to the mth data line 110 (m < n) are located in the edge region AA1, and the (m + 1)th data line 110 to the nth data line 110 are located in the center region AA2. That is, the first data line 110 to the mth data line 110 are the first data line 111, and the (m + 1)th data line 110 to the nth data line 110 are the second data line 112. It is understood that both m and n are positive integers.

[0154] As can be seen from the above, the first end of the connecting line 120 is electrically connected to the first data line 111, and the second end of at least one connecting line 120 is located between two adjacent second data lines 112. Exemplarily, the second end of the connecting line 120 electrically connected to the first data line 110 may be located between the (m+1)th data line 110 and the (m+2)th data line 110 (forward order FIAA), or the second end of the connecting line 120 electrically connected to the first data line 110 may be located between the (n-1)th data line 110 and the nth data line 110 (reverse order FIAA). That is, the second end of the connecting line 120 is inserted between two adjacent second data lines 112 (e.g., the (m+1)th data line 110 and the (m+2)th data line 110).

[0155] In this manner, when the first fan-out line 131 is electrically connected to the second end of the connection line 120 and the second fan-out line 132 is electrically connected to the end of the second data line 112 close to the fan-out region BB, at least one first fan-out line 131 is inserted between two adjacent second fan-out lines 132.

[0156] Exemplarily, a plurality of fan-out lines 130 (including a first fan-out line 131 and a second fan-out line 132) electrically connected in one-to-one correspondence with the first data line 110 to the nth data line 110 may be defined as the first fan-out line 130 to the nth fan-out line 130. The first fan-out line 130 is electrically connected to the first data line 110, and the second fan-out line 130 is electrically connected to the second data line 110, as analogized above.

[0157] At least one first fan-out line 131 is inserted between two adjacent second fan-out lines 132, and thus the ends of the first fan-out line 130 to the nth fan-out line 130 away from the display area AA (i.e., the ends where the multiple fan-out lines 130 are electrically connected to the driving ICs) cannot be arranged sequentially along the direction from the first edge to the center line Q.

[0158] As can be seen from the above, the first data line 110 to the nth data line 110 are spaced apart from each other along the direction from the first edge to the center line Q. That is, when wiring is performed using the FIAA or partial FIAA method, the arrangement order of the multiple fan-out lines 130 (including the first fan-out line 131 and the second fan-out line 132) in the first direction X at the end away from the display area AA is different from the arrangement order of the multiple data lines 110 (including the first data line 111 and the second data line 112) in the first direction X.

[0159] For example, the driving IC has an output end, and the arrangement order of the output end of the driving IC along the first direction X is the same as the arrangement order of the multiple data lines 110 along the first direction X. It is understood that the arrangement order of the ends of the multiple fan-out lines 130 (including the first fan-out line 131 and the second fan-out line 132) away from the display area AA along the first direction line X is different from the arrangement order of the multiple data lines 110 (including the first data line 111 and the second data line 112) along the first direction X, so that the output end of the driving IC cannot output driving signals to the multiple data lines 110 in sequence, that is, the driving IC cannot drive the emission of the sub-pixels 101 in multiple columns in sequence. Meanwhile, redevelopment of the driving IC is relatively expensive, leading to an increase in the cost of the display panel 210.

[0160] FIG. 11 is a partial structural diagram of a display substrate according to some embodiments of the present disclosure.

[0161] In some embodiments, the display substrate 100 further includes a bending region CC, as shown in Fig. 11. The fan-out region BB includes a first fan-out region BB1 and a second fan-out region BB2, where the first fan-out region BB1 is closer to the display area AA than the second fan-out region BB2, and the bending region CC is located between the first fan-out region BB1 and the second fan-out region BB2.

[0162] Exemplarily, the base 102 is a flexible base. The base 102 and at least one of the plurality of conductive layers 103 are provided in the bending region CC. The base 102 and at least one of the plurality of conductive layers 103 are bendable in the bending region CC.

[0163] In some examples, the base 102 and the second source-drain metal layer SD2 are provided in the bending region CC. The bending region CC is located between the first fan-out region BB1 and the second fan-out region BB2, so that the second fan-out region BB2 can be bent to the rear surface of the portion located in the display region AA of the display substrate 100, and the second fan-out region BB2 can be prevented from occupying space on the display side of the display substrate 100, thereby further reducing the width of the side frame (e.g., the bottom frame) of the display panel 210 and improving the visual effect of the display panel 210.

[0164] In some embodiments, the second fan-out region BB2 includes a first sub-fan-out region BB21 and a second sub-fan-out region BB22, as shown in Figure 11. The first sub-fan-out region BB21 is closer to the curve region CC than the second sub-fan-out region BB22.

[0165] 11, the display substrate 100 further includes a cell test (CT) area. The CT area is located between the first sub-fan-out area BB21 and the second sub-fan-out area BB22. It is understood that the CT area is used to test the display substrate 100.

[0166] In some examples, the display substrate 100 further includes a COP (Chip On Panel) region, an ILB (Inner Lead Bonding) region, and a FOP (Flexible Printed Circuit On Panel) region. The COP region, the ILB region, and the FOP region are located on the side of the second sub-fan-out region BB22 away from the bending region CC, in that order. In some examples, the driving IC is located in the COP region and is connected to the base 102 of the display substrate 100 by binding.

[0167] FIG. 12 is a partial enlarged view of region 1C of FIG.

[0168] 12, the first fan-out line 131 includes a transfer line 136. The transfer line 136 is located in the second fan-out region BB2. The transfer line 136 is located in a different conductive layer 103 from the second fan-out lines 132, and the transfer line 136 spans at least one second fan-out line 132, so that the arrangement order of the ends of the fan-out lines 130 away from the display area AA in the first direction X is the same as the arrangement order of the data lines 110 in the first direction X.

[0169] In the embodiments of the present disclosure, it is understood that one wire "crosses" another wire when at least a portion of the wire is located on a different conductive layer 103 than the other wire, and when an orthogonal projection of at least a portion of the wire on the base 102 intersects with an orthogonal projection of the other wire on the base 102, thereby achieving the "crossing" of the other wire.

[0170] It is understood that the transfer line 136 spans at least one second fan-out line 132 when an orthogonal projection of the transfer line 136 at the base 102 intersects with an orthogonal projection of the at least one second fan-out line 132 at the base 102. By locating the transfer line 136 on a different conductive layer 103 than the plurality of second fan-out lines 132, the transfer line 136 can be insulated from the plurality of second fan-out lines 132.

[0171] In some examples, the multiple transfer lines 136 may be located in one conductive layer 103 or multiple conductive layers 103. Illustratively, when the multiple transfer lines 136 are located in multiple conductive layers 103, any one of the transfer lines 136 is located in a different conductive layer 103 than the multiple second fan-out lines 132.

[0172] In some examples, when the transfer lines 136 are located in multiple conductive layers 103, any two adjacent transfer lines 136 may be located in different conductive layers 103. In some examples, the transfer lines 136 may be located in the second source-drain metal layer SD2 and / or the first source-drain metal layer SD1. Illustratively, when the transfer lines 136 are located in the second source-drain metal layer SD2 and the first source-drain metal layer SD1, any two adjacent transfer lines 136 are located in different source-drain metal layers SD (including the first source-drain metal layer SD1 or the second source-drain metal layer SD2).

[0173] As shown in FIG. 12, by arranging the transfer line 136 across at least one second fan-out line 132 and insulated from the multiple second fan-out lines 132, the arrangement order of the multiple first fan-out lines 131 along the first direction X at their ends away from the display area AA can be adjusted by adjusting the extension direction and / or length of the transfer line 136.

[0174] That is, by arranging the transfer line 136 to span at least one second fan-out line 132, the arrangement order of the ends of the first fan-out line 131 away from the display area AA (i.e., the ends electrically connected to the driving ICs of the first fan-out line 131) can be adjusted, and therefore the arrangement order of the ends of the multiple fan-out lines 130 away from the display area AA (i.e., the ends electrically connected to the driving ICs of the multiple fan-out wirings 130) can be adjusted, so that the ends of the first fan-out line 130 to the n-th fan-out line 130 away from the display area AA can be arranged at intervals in sequence along the direction from the first edge to the center line Q, and so that the arrangement order of the ends of the multiple fan-out lines 130 away from the display area AA in the first direction X can be the same as the arrangement order of the multiple first data lines 111 in the first direction X.

[0175] As a result, the arrangement order of the output ends of the driving ICs in the first direction X, the arrangement order of the ends of the fan-out lines 130 away from the display area AA in the first direction X, and the arrangement order of the data lines 110 in the first direction X can be the same, and the output ends of the driving ICs can sequentially provide driving signals to the data lines 110. That is, the driving ICs can sequentially drive the emission of the sub-pixels 101 in multiple columns, eliminating the need to redevelop the driving ICs, enabling the frame of the display substrate 100 to be narrowed and reducing the cost of the display substrate 100.

[0176] In addition, the placement of the transfer line 136 in the second fan-out region BB2 prevents the transfer line 136 from occupying space in the first fan-out region BB1, and reduces the width of the first fan-out region BB1. Since the first fan-out region BB1 is located on the side of the bending region CC closer to the display area AA, the width of the first fan-out region BB1 can be reduced, and the width of the bottom frame of the display substrate 100 can be further reduced, thereby improving the visual effect of the display panel 210.

[0177] In some examples, the end of the transfer line 136 away from the display area AA is electrically connected to an output end of the driving IC. In some other examples, the first fan-out line 131 further includes some other wiring (e.g., a second sub-fan-out line 138 shown in FIG. 12), one end of the second sub-fan-out line 138 is electrically connected to the end of the transfer line 136 away from the display area AA, and the other end of the second sub-fan-out line 138 is electrically connected to the output end of the driving IC.

[0178] Fig. 13 is a structural diagram of a display substrate according to some other embodiments. Fig. 14 is a structural diagram of a display substrate according to some other embodiments. Note that the difference between Fig. 13 and Fig. 14 is that, in order to make it easier to show the wiring, Fig. 14 only shows the wiring (e.g., fan-out line 130) in the second source-drain metal layer SD2 in the present technical solution, and does not show other structures or wiring in the second source-drain metal layer SD2.

[0179] 13 and 14, the plurality of first fan-out lines 131 include a first type first fan-out line 131a and a second type first fan-out line 131b. The connection line 120 includes a third connection line 120c and a fourth connection line 120d. As can be seen from the above, the connection line 120 is located in the display area AA. A first end of the connection line 120 is electrically connected to the first data line 111, and a second end of the connection line 120 extends to a position close to the fan-out area BB of the central area AA2. The first fan-out line 131 is located in the fan-out area BB and is electrically connected to the second end of the connection line 120.

[0180] It should be noted that the first type first fan-out line 131a and the second type first fan-out line 131b are used only to distinguish between two different first fan-out lines 131, and do not further limit the first fan-out lines 131. The third connection line 120c and the fourth connection line 120d are used only to distinguish between two different connection lines 120, and do not further limit the connection lines 120.

[0181] In some examples, the second type first fan-out line 131b is electrically connected to one first data line 111 via the fourth connection line 120d. The first type first fan-out line 131a is electrically connected to another first data line 111 via the third connection line 120c. Here, the first data line 111 electrically connected to the third connection line 120c is closer to the center line Q of the display substrate 100 than the first data line 111 electrically connected to the fourth connection line 120d.

[0182] Fig. 15 is a partial enlarged view of region 1A in Fig. 13. Fig. 16 is a partial enlarged view of region 2A in Fig. 13. Fig. 17 is a partial enlarged view of region 3A in Fig. 13. Fig. 18 is a partial enlarged view of region 4A in Fig. 13. Fig. 19 is a partial enlarged view of region 5A in Fig. 13. Fig. 20 is a partial enlarged view of region 6A in Fig. 13. Fig. 21 is a partial enlarged view of region 7A in Fig. 13.

[0183] 13 and 15, in the position of region 1A, the second data lines 112 are electrically connected to the second fan-out lines 132, so that the driving IC can provide driving signals to the second data lines 112 via the second fan-out lines 132. Exemplarily, the first fan-out lines 131 (including the first type first fan-out lines 131a and the second type first fan-out lines 131b) are not provided in the position of region 1A.

[0184] As shown in FIGS. 13 and 16, in the region 2A, the second end of the third connection line 120c is electrically connected to the first type first fan-out line 131a.

[0185] As shown in Figures 13 and 17, the first type first fan-out line 131a extends from region 2A to region 3A, and is transferred to another conductive layer 103 at the position of region 3A by a jumper method, so that the transfer line 136 in the first type first fan-out line 131a can be located in a conductive layer 103 different from the multiple second fan-out lines 132.

[0186] As shown in FIG. 13 and FIG. 18, the first type first fan-out line 131a extends from the region 3A to the region 4A. In some examples, the transfer line 136 of the first type first fan-out line 131a is transferred to another conductive layer 103 through a transfer hole at the position of the region 4A1. That is, in FIG. 18, the transfer line 136 of the first type first fan-out line 131a may be transferred to the first portion first fan-out line 131a2 through a transfer hole at the position of the region 4A1. It is understood that the first portion first fan-out line 131a2 is a portion of the first type first fan-out line 131a other than the transfer line 136, and the first portion first fan-out line 131a2 is located in a conductive layer 103 different from the transfer line 136. Exemplarily, the first portion first fan-out line 131a2 may be the second sub-fan-out line 138 shown in FIG. 12.

[0187] In some examples, the orthogonal projection of the transfer line 136 at the base 102 and the orthogonal projection of the first portion first fan-out line 131a2 at the base 102 at least partially overlap, thereby avoiding overlap between the orthogonal projection of the transfer line 136 at the base 102 and the orthogonal projection of other wirings (e.g., the second fan-out line 132) at the base 102, i.e., avoiding overlap between the transfer line 136 and other wirings, thereby reducing parasitic capacitance generated between the transfer line 136 and other wirings and improving signal transmission reliability.

[0188] 13 and 19, the first type first fan-out lines 131a extend from region 4A to region 5A and are electrically connected to the driving ICs in region 5A. It is understood that in region 5A, the first type first fan-out lines 131a are located in a different conductive layer 103 than the second type first fan-out lines 131b.

[0189] Similarly, as shown in Figures 13 and 20, the transfer line 136 in the second type first fan-out line 131b is transferred to another conductive layer 103 through a transfer hole at the position of region 6A1, so that the transfer line 136 in the second type first fan-out line 131b can be located in a conductive layer 103 different from the multiple second fan-out lines 132.

[0190] 13 and 21, the second type first fan-out line 131b extends from region 6A to region 7A and is electrically connected to the driving IC at the position of region 7A. It is understood that the transfer lines 136 in the second type first fan-out line 131b are transferred to another conductive layer 103 through transfer holes at the position of region 6A1, so that the transfer lines 136 of the intersecting second type first fan-out line 131b and the remaining parts of the second type first fan-out line 131b (parts other than the transfer lines 136 in the second type first fan-out line 131b) in region 7A can be located in different conductive layers 103.

[0191] By positioning the transfer line 136 of the first fan-out line 131 on a different conductive layer 103 from the multiple second fan-out lines 132 and arranging the transfer line 136 to span at least one second fan-out line 132, the arrangement order of the multiple first fan-out lines 131 in the first direction X at their ends away from the display area AA can be adjusted by adjusting the extension direction, extension length, etc. of the transfer line 136, i.e., the arrangement order of the transfer line 136 in the first direction at the ends of the multiple fan-out lines 130 away from the display area AA can be adjusted, so that the arrangement order of the ends of the multiple fan-out lines 130 away from the display area AA in the first direction can be made the same as the arrangement order of the multiple first data lines 111 in the first direction X.

[0192] That is, by arranging the transfer line 136 so as to span at least one second fan-out line 132, the arrangement order of the output ends of the driving IC in the first direction X, the arrangement order of the ends of the multiple fan-out lines 130 away from the display area AA (i.e., the ends of the multiple fan-out lines 130 electrically connected to the driving IC) in the first direction X, and the arrangement order of the multiple data lines 110 in the first direction X can be the same. As a result, the output end of the driving IC can sequentially provide driving signals to the multiple data lines 110, that is, the driving IC can sequentially drive the emission of the sub-pixels 101 in multiple columns, and there is no need to redevelop the driving IC, and the frame of the display substrate 100 can be narrowed, and the cost of the display substrate 100 can be reduced.

[0193] 10, the plurality of connection lines 120 are electrically connected to the plurality of first data lines 111 in one-to-one correspondence. The plurality of second fan-out lines 132 are electrically connected to the plurality of second data lines 112 in one-to-one correspondence.

[0194] It is understood that the number of connection lines 120 may be the same as the number of first data lines 111, such that the multiple connection lines 120 are electrically connected to the multiple first data lines 111 in one-to-one correspondence. The number of second fan-out lines 132 may be the same as the number of second data lines 112, such that the multiple second fan-out lines 132 are electrically connected to the multiple second data lines 112 in one-to-one correspondence.

[0195] By installing the display substrate 100 in this manner, the wiring of the display substrate 100 becomes more convenient and the manufacturing cost is reduced.

[0196] FIG. 22 is a structural diagram of a display substrate according to some other embodiments.

[0197] As can be seen from the above, in some embodiments, the plurality of connecting lines 120 are electrically connected to the plurality of first data lines 111 in one-to-one correspondence. The plurality of second fan-out lines 132 are electrically connected to the plurality of second data lines 112 in one-to-one correspondence.

[0198] In some other embodiments, the plurality of first data lines 111 includes a plurality of first type first data lines 111a and a plurality of second type first data lines 111b, as shown in Fig. 22. The plurality of second fan-out lines 132 includes a plurality of first type second fan-out lines 132a and a plurality of second type second fan-out lines 132b.

[0199] 22, the multiple first type first data lines 111a are electrically connected in one-to-one correspondence with the multiple connection lines 120. The multiple first type second fan-out lines 132a are electrically connected in one-to-one correspondence with the multiple second data lines 112. The multiple second type second fan-out lines 132b are electrically connected in one-to-one correspondence with the multiple second type first data lines 111b.

[0200] It should be noted that in the embodiment of the present disclosure, the plurality of first type first data lines 111a and the plurality of second type first data lines 111b are only used to distinguish the first data lines 111 electrically connected to the connection lines 120 or the plurality of second type second fan-out lines 132b, and do not further limit the first data lines 111. The plurality of first type second fan-out lines 132a and the plurality of second type second fan-out lines 132b are only used to distinguish the second data lines 112 or the second fan-out lines 132 electrically connected to the second type first data lines 111b, and do not further limit the second fan-out lines 132.

[0201] Exemplarily, the numbers of the first type first data lines 111a and the second type first data lines 111b may be the same or different, and the numbers of the first type second fan-out lines 132a and the second type second fan-out lines 132b may be the same or different.

[0202] Here, the multiple first type first data lines 111a may be understood as the aforementioned "some of the first data lines 111," and the multiple second type first data lines 111b may be understood as the aforementioned "other some of the first data lines 111."

[0203] It can be understood that by arranging the plurality of first type first data lines 111a to be electrically connected to the transfer lines 136 and the plurality of second type first data lines 111b to be electrically connected to the second type second fan-out lines 132b, the wiring flexibility of the display substrate 100 can be improved and different usage needs can be met.

[0204] Fig. 23 is a partial structural view of a display substrate according to some other embodiments. Fig. 24 is a partial enlarged view of region 1B in Fig. 23. Fig. 25 is a partial enlarged view of region 2B in Fig. 23. Fig. 26 is a partial enlarged view of region 3B in Fig. 23.

[0205] It is understood that, since the first type first data line 111a is electrically connected to the connection line 120, the end of the first type first data line 111a close to the fan-out region BB is not directly electrically connected to the fan-out line 130 (including the first fan-out line 131 and the second fan-out line 132) at the position of region 1B as shown in Figures 23 and 24. It is understood that the first type first data line 111a is electrically connected to the first fan-out line 131 via the connection line 120 (not shown in region 1B).

[0206] As shown in FIGS. 23 and 24, in the position of the region 1B, the end of the second type first data line 111b close to the fan-out region BB is electrically connected to the second type second fan-out line 132b.

[0207] In some examples, as shown in Figures 23 and 25, two connection lines 120 (the fifth connection line 120e and the sixth connection line 120F shown in Figure 24) are provided between two adjacent second type first data lines 111b at the position of the region 2B. Note that the fifth connection line 120e and the sixth connection line 120f are used only to distinguish two different connection lines 120, and do not further limit the connection lines 120.

[0208] As shown in FIG. 25, it will be understood that the first fan-out lines 131 are electrically connected to the connection lines 120 in a one-to-one correspondence, and the second type second fan-out lines 132b are electrically connected to the second type first data lines 111b in a one-to-one correspondence.

[0209] As shown in Figures 23 and 26, the first fan-out line 131 electrically connected to the first type first data line 111a via the transfer line 136, and the second type second fan-out line 132b directly and electrically connected to the second type first data line 111b are both electrically connected to the driving IC at the position of region 3B.

[0210] As can be seen from the above, the light emitting element 300 can emit light of different colors, such as red light, green light, blue light, etc. The sub-pixels 101 of the display substrate 100 are arranged in a plurality of columns along a first direction X and in a plurality of rows along a second direction Y. Here, the sub-pixels 101 in one column are electrically connected to one data line 110 (the first data line 111 or the second data line 112).

[0211] Exemplarily, two first type first data lines 111a are provided between two adjacent second type first data lines 111b. In some examples, one of the two first type first data lines 111a is electrically connected to one column of first sub-pixels. The first sub-pixels include a sub-pixel 101 that emits red light and a sub-pixel 101 that emits blue light. The second type first data line 111b is electrically connected to one column of sub-pixels 101 that emit green light.

[0212] 22, the first type first data line 111a is electrically connected to the first fan-out line 131 via the transfer line 136, and the end of the second type first data line 111b close to the fan-out region BB is electrically connected to the second type second fan-out line 132b. That is, the second type first data line 111b does not need to be transferred via the transfer line 136, but can be electrically connected to the second type second fan-out line 132b, so that the driving IC can provide a driving signal to the second type first data line 111b via the second type second fan-out line 132b.

[0213] The first sub-pixels include a sub-pixel 101 that emits red light and a sub-pixel 101 that emits blue light. That is, the driving IC provides driving signals to the sub-pixel 101 that emits red light and the sub-pixel 101 that emits blue light via the first fan-out line 131, the first type first data line 111a, and the transfer line 136, and provides driving signals to the sub-pixel 101 that emits green light via the second type second fan-out line 132b and the second type first data line 111b.

[0214] It can be understood that since the second type first data line 111b can be directly electrically connected to the second type second fan-out line 132b, no transfer or jumper is required, and changes in loading (full English name: Loading) due to the transfer or jumper process are avoided, thereby improving the reliability of the driving signal provided by the driving IC to the sub-pixel 101 that emits green light.

[0215] Since a change in loading has a relatively large effect on the sub-pixels 101 emitting green light, the first type first data line 111a is electrically connected to the sub-pixels 101 emitting red light and the sub-pixels 101 emitting blue light, and the second type first data line 111b is electrically connected to the sub-pixels 101 emitting green light. This reduces the space occupied by the fan-out lines 130 in the second direction Y, prevents the jumper or transfer process from affecting the sub-pixels 101 emitting green light, and improves the reliability of the driving signal provided by the driving IC to the sub-pixels 101 emitting green light, thereby improving the display performance of the display panel 210.

[0216] As can be seen from the above, the first fan-out line 131 includes a transmission line 136. In some embodiments, the first fan-out line 131 further includes a first sub-fan-out line 133, a plurality of adapters 134, and a first signal transmission line 135, as shown in FIG.

[0217] As shown in FIG. 12, the first sub-fan-out line 133 is electrically connected to a second end of the connection line 120 (not shown in FIG. 12). The adapter 134 includes a first adapter 1341 located in a region close to the bending region CC of the first fan-out region BB1 and a second adapter 1342 located in a region close to the bending region CC of the second fan-out region BB2. Here, the first adapter 1341 is electrically connected to an end of the first sub-fan-out line 133 away from the connection line 120. The first signal transmission line 135 passes through the bending region CC and connects the first adapter 1341 and the second adapter 1342. The transfer line 136 is electrically connected to the second adapter 1342.

[0218] In some examples, the multiple first sub-fan-out lines 133 are located in the first fan-out region BB1 and are located in different conductive layers 103. The first sub-fan-out lines 133 are electrically connected to a first adaptor 1341. Exemplarily, the first sub-fan-out lines 133 may be transferred to a second source-drain metal layer SD2 by the first adaptor 1341 and electrically connected to a first signal transmission line 135.

[0219] The first signal transmission line 135 electrically connects the first adaptor 1341 and the second adaptor 1342. Exemplarily, the first signal transmission line 135 may be transferred to another conductive layer 103 other than the second source-drain metal layer SD2 via the second adaptor 1342 and electrically connected to the transfer line 136.

[0220] 12 , a portion of the second fan-out line 132 located in the first fan-out region BB1 is defined as a third sub-fan-out line 1321. Exemplarily, a portion of the second fan-out line 132 located in the second fan-out region BB2 is defined as a fourth sub-fan-out line 1322.

[0221] In some examples, the third sub-fan-out lines 1321 are located in different conductive layers 103. The third sub-fan-out lines 1321 are electrically connected to the first adaptor 1341, so that the third sub-fan-out lines 1321 can be transferred to the second source-drain metal layer SD2 by the first adaptor 1341 and electrically connected to the first signal transmission line 135. The first signal transmission line 135 is transferred to another conductive layer 103 other than the second source-drain metal layer SD2 via the second adaptor 1342 and electrically connected to the fourth sub-fan-out line 1322.

[0222] 12 , it is understood that the first sub fan-out line 133 and the second fan-out line 132 are electrically connected to different first adapters 1341. The transfer line 136 and the fourth sub fan-out line 1322 are electrically connected to different second adapters 1342. It is understood that the different first adapters 1341 and the different second adapters 1342 are electrically connected via different first signal transmission lines 135.

[0223] In some examples, within the first fan-out region BB1, any two adjacent fan-out lines 130 (including the first sub-fan-out line 133 and the third sub-fan-out line 1321) among the multiple first sub-fan-out lines 133 and the multiple third sub-fan-out lines 1321 are located in different conductive layers 103.

[0224] In addition, among the multiple first sub-fan-out lines 133 and the multiple third sub-fan-out lines 1321, any two adjacent fan-out lines 130 refer to any two fan-out lines 130 (including the first sub-fan-out line 133 and the third sub-fan-out line 1321) whose orthogonal projections on the base 102 are adjacent.

[0225] By installing in this manner, the distance between two adjacent fan-out lines 130 (including the first sub-fan-out line 133 and the third sub-fan-out line 1321) whose orthogonal projections on the base 102 are formed can be reduced, thereby reducing the width of the first fan-out region BB1 and further reducing the width of the side frame (e.g., the bottom frame) of the display panel 210.

[0226] Exemplarily, any two adjacent fan-out lines 130 among the plurality of first sub-fan-out lines 133 and the plurality of third sub-fan-out lines 1321 are alternately located in the first gate metal layer Gate1 and the second gate metal layer Gate2.

[0227] 12 , the first fan-out line 131 includes a second sub-fan-out line 138. The second sub-fan-out line 138 is located in a second fan-out region BB2 and is electrically connected to an end of the transfer line 136 that is remote from the first sub-fan-out line 133.

[0228] Illustratively, within the second fan-out region BB2, any two adjacent fan-out lines 130 (including the second sub-fan-out line 138 and the fourth sub-fan-out line 1322) among the plurality of second sub-fan-out lines 138 and the plurality of fourth sub-fan-out lines 1322 are located in different conductive layers 103.

[0229] In addition, among the multiple second sub-fan-out lines 138 and the multiple fourth sub-fan-out lines 1322, any two adjacent fan-out lines 130 refer to any two fan-out lines 130 (including the second sub-fan-out line 138 and the fourth sub-fan-out line 1322) whose orthogonal projections on the base 102 are adjacent.

[0230] By installing in this manner, the orthogonal projection on the base 102 can reduce the distance between two adjacent fan-out lines 130 (including the second sub-fan-out line 138 and the fourth sub-fan-out line 1322), thereby reducing the width of the second fan-out region BB2 and further reducing the width of the side frame (e.g., the bottom frame) of the display panel 210.

[0231] Exemplarily, any two adjacent fan-out lines 130 among the plurality of second sub-fan-out lines 138 and the plurality of fourth sub-fan-out lines 1322 are alternately located in the first gate metal layer Gate1 and the second gate metal layer Gate2.

[0232] 27 is a partial structural view of a display substrate according to some other embodiments, and FIG 28 is a partial enlarged view of region 1D in FIG 27.

[0233] 27 and 28, the third sub-fan-out line 1321 and the first sub-fan-out line 133 are arranged along the first direction X. Exemplarily, the third sub-fan-out line 1321 and the first sub-fan-out line 133 may be arranged alternately along the first direction X.

[0234] In some examples, for two adjacent fan-out lines 130, the third sub-fan-out line 1321 and the first sub-fan-out line 133, at least a portion of the line segments of the fan-out lines 130 that extend away from the center line Q curve toward the fan-out line 130 closer to the center line Q.

[0235] 22, when no connection line 120 is provided between two adjacent second data lines 112, the distance between the fan-out lines 130 (third sub-fan-out line 1321) electrically connected to the two second data lines 112 is the first distance. When at least one connection line 120 is provided between two adjacent second data lines 112, the distance between the fan-out lines 130 (including the first sub-fan-out line 133 and the third sub-fan-out line 1321) electrically connected to the two second data lines 112 and the at least one connection line 120 is the second distance. It is understood that the first distance is greater than the second distance.

[0236] Since at least one connection line 120 is located between two adjacent second data lines 112, the first distance is greater than the second distance, so that the distances between the plurality of fan-out lines 130 (including the first sub-fan-out line 133 and the third sub-fan-out line 1321) are not consistent. It can be understood that the smaller the distance between two adjacent fan-out lines 130 (including the first sub-fan-out line 133 and the third sub-fan-out line 1321), the larger the space they occupy along the second direction Y when they approach and converge. Conversely, the larger the distance between two adjacent fan-out lines 130 (including the first sub-fan-out line 133 and the third sub-fan-out line 1321), the smaller the space they occupy along the second direction Y when they approach and converge.

[0237] Therefore, as shown in FIG. 28, for two adjacent fan-out lines 130, the third sub-fan-out line 1321 and the first sub-fan-out line 133, at least a portion of the line segments of the fan-out lines 130 (including the first sub-fan-out line 133 and the third sub-fan-out line 1321) that are away from the center line Q are installed so as to curve toward the fan-out line 130 (including the first sub-fan-out line 133 and the third sub-fan-out line 1321) that is closer to the center line Q.

[0238] That is, when the distance between two adjacent fan-out lines 130 (including the first sub-fan-out line 133 and the third sub-fan-out line 1321) is relatively large, at least some of the line segments of the fan-out lines 130 (including the first sub-fan-out line 133 and the third sub-fan-out line 1321) away from the center line Q curve toward the fan-out line 130 (including the first sub-fan-out line 133 and the third sub-fan-out line 1321) closer to the center line Q, thereby reducing the space occupied by the multiple fan-out lines 130 (including the first sub-fan-out line 133 and the third sub-fan-out line 1321) along the second direction Y as they approach and converge, i.e., the width of the first fan-out region BB1 can be reduced, thereby reducing the width of the side frame (e.g., the bottom frame) of the display panel 210.

[0239] In some examples, as shown in FIG. 28, when the distance between two adjacent fan-out lines 130 (including the first sub-fan-out line 133 and the third sub-fan-out line 1321) is relatively small, at least some of the line segments of the fan-out line 130 (including the first sub-fan-out line 133 and the third sub-fan-out line 1321) closer to the center line Q curve toward the fan-out line 130 (including the first sub-fan-out line 133 and the third sub-fan-out line 1321) away from the center line Q, thereby avoiding multiple fan-out lines 130 from influencing each other when they fan out together.

[0240] By installing them in this manner, at least some of the line segments of the first sub-fan-out line 133 and the third sub-fan-out line 1321 can be curved according to the distance between two adjacent fan-out lines 130 (including the first sub-fan-out line 133 and the third sub-fan-out line 1321), thereby reducing the width of the first fan-out region BB1 while avoiding multiple fan-out lines 130 (including the first sub-fan-out line 133 and the third sub-fan-out line 1321) from influencing each other when they gather and fan out.

[0241] In some examples, as shown in FIG. 28, at least some of the wiring in the first sub-fan-out line 133 and the third sub-fan-out line 1321 extend in a wavy or substantially wavy curved manner.

[0242] Fig. 29 is a partial structural view of a display substrate according to still other embodiments. Fig. 30 is a partial structural view of a display substrate according to still other embodiments. Fig. 31 is a partial structural view of a display substrate according to still other embodiments. Fig. 32 is a partial structural view of a display substrate according to still other embodiments. Fig. 33 is a partial enlarged view of region 1E in Fig. 32.

[0243] As can be seen from the above, as shown in FIGS. 29 and 30, the plurality of conductive layers 103 includes a first gate metal layer Gate1, a second gate metal layer Gate2, a first source-drain metal layer SD1, and a second source-drain metal layer SD2.

[0244] As can be seen from the above, the second fan-out region BB2 includes a first sub-fan-out region BB21 and a second sub-fan-out region BB22. The first sub-fan-out region BB21 is closer to the bending region CC than the second sub-fan-out region BB22.

[0245] In some examples, as shown in Fig. 31, at least some of the transfer lines 136 are located in the first sub-fan-out region BB21. Exemplarily, as shown in Fig. 32 and Fig. 33, the transfer lines 136 extend in a concentrated manner in a direction close to the center line Q.

[0246] 32, the display substrate 100 further includes an isolation portion 140. The isolation portion 140 is located in the first sub-fan-out region BB21. The isolation portion 140 is also located between the transfer line 136 and the plurality of second fan-out lines 132.

[0247] It is understood that the transfer line 136 and the multiple second fan-out lines 132 are located on different conductive layers 103, and the isolation portion 140 is located between the transfer line 136 and the multiple second fan-out lines 132, i.e., the isolation portion 140 is located on the conductive layer 103 between the multiple transfer lines 136 and the multiple second fan-out lines 132.

[0248] It will be appreciated that because the transfer line 136 spans at least one second fan-out line 132, the orthogonal projection of the transfer line 136 at the base 102 partially overlaps with the orthogonal projection of the second fan-out line 132 at the base 102. In this manner, parasitic capacitance is created between the transfer line 136 and the second fan-out line 132, affecting signal transmission.

[0249] Therefore, at least a portion of the transfer line 136 is installed in the first sub-fan-out region BB21, and the isolation section 140 is similarly located in the first sub-fan-out region BB21, and the isolation section 140 is located between the transfer line 136 and the multiple second fan-out lines 132. This allows the isolation section 140 to isolate the transfer line 136 from the multiple second fan-out lines 132, thereby reducing the parasitic capacitance formed between the transfer line 136 and the second fan-out lines 132, and improving the reliability of signal transmission.

[0250] Exemplarily, the isolation section 140 is located between the transfer line 136 and a fourth sub-fan-out line 1322 of the plurality of second fan-out lines 132 .

[0251] In some examples, the transfer line 136 is located in the second source-drain metal layer SD2, the second fan-out line 132 (fourth sub-fan-out line 1322) is located in the first gate metal layer Gate1 and / or the second gate metal layer Gate2, and the isolation portion 140 is located in the first source-drain metal layer SD1.

[0252] The first source-drain metal layer SD1 is closer to the first gate metal layer Gate1 and the second gate metal layer Gate2 than the second source-drain metal layer SD2, and thus, the isolation portion 140 can be located between the transfer line 136 and the multiple second fan-out lines 132, thereby isolating the transfer line 136 and the multiple second fan-out lines 132, reducing the parasitic capacitance formed between the transfer line 136 and the second fan-out lines 132, and improving the reliability of signal transmission.

[0253] Fig. 34 is a partial enlarged view of region 2D in Fig. 27. Fig. 35 is a partial enlarged view of region 1F in Fig. 34.

[0254] 34 and 35 , the second fan-out line 132 further includes a second signal transmission line 137. The second signal transmission line 137 is connected between the second adapter 1342 and the transfer line 136. Here, the orthogonal projection of the second signal transmission line 137 on the base 102 is located between the orthogonal projection of the isolation portion 140 on the base 102 and the edge of the first sub-fan-out region BB21 on the side closer to the bending region CC.

[0255] It is understood that the second signal transmission line 137 may be electrically connected to the second adapter 1342 and the transfer line 136 may be electrically connected to the end of the second signal transmission line 137 away from the second adapter 1342, thereby electrically connecting the transfer line 136 to the second adapter 1342 via the second signal transmission line 137.

[0256] In some examples, as shown in FIG. 35, the second signal transmission line 137 and the second fan-out line 132 (fourth sub-fan-out line 1322) are located in different conductive layers 103. Exemplarily, the plurality of second fan-out lines 132 (fourth sub-fan-out line 1322) are alternately located in the first gate metal layer Gate1 and the second gate metal layer Gate2. The second signal transmission line 137 is located in the source-drain metal layer SD, so that the second signal transmission line 137 and the plurality of second fan-out lines 132 can be located in different conductive layers 103. Exemplarily, the second signal transmission line 137 may be located in the first source-drain metal layer SD1 or the second source-drain metal layer SD2.

[0257] Since the second signal transmission line 137 and the multiple second fan-out lines 132 (fourth sub-fan-out lines 1322) are located on different conductive layers 103, after the second adapter 1342 alternately transfers the multiple second fan-out lines 132 (fourth sub-fan-out lines 1322) to the first gate metal layer Gate1 and the second gate metal layer Gate2, by not providing the second signal transmission line 137 between two adjacent second fan-out lines 132 (fourth sub-fan-out lines 1322), the multiple second fan-out lines 132 (fourth sub-fan-out lines 1322) can be electrically connected to the driving IC by the gate metal layer Gate (first gate metal layer Gate1 or second gate metal layer Gate2) transferred by the second adapter 1342.

[0258] That is, when the second adapter 1342 transfers the second fan-out line 132 to the first gate metal layer Gate1, the second fan-out line 132 may be electrically connected to the driving IC at the first gate metal layer Gate1. When the second adapter 1342 transfers the second fan-out line 132 to the second gate metal layer Gate2, the second fan-out line 132 may be electrically connected to the driving IC at the second gate metal layer Gate2.

[0259] By installing in this manner, the second fan-out line 132 can be connected to the driving IC without being transferred to another conductive layer 103 again after being transferred to the first gate metal layer Gate1 or the second gate metal layer Gate2 by the second adapter 1342. This reduces the sudden change in loading caused by the jumper, thereby improving the luminance uniformity of the display panel 210, while improving the convenience of processing and reducing the cost of the display panel 210.

[0260] On the other hand, by positioning the second signal transmission line 137 and the multiple second fan-out lines 132 on different conductive layers 103, the distance between two adjacent wirings (including the second fan-out line 132 and the second signal transmission line 137) whose orthogonal projections are on the base 102 can be reduced, thereby reducing the width of the first sub-fan-out region BB21.

[0261] FIG. 36 is a partial enlarged view of region 2F in FIG.

[0262] As can be seen from the above, in some examples, the second signal transmission line 137 and the second fan-out line 132 (the fourth sub-fan-out line 1322) are located on different conductive layers 103. In some other examples, as shown in FIG. 36 , at least some of the line segments of the second signal transmission line 137 and at least some of the line segments of the plurality of second fan-out lines 132 (the fourth sub-fan-out line 1322) are located on the same conductive layer 103.

[0263] Illustratively, the multiple second signal transmission lines 137 and the multiple second fan-out lines 132 (fourth sub-fan-out lines 1322) are alternately located in the first gate metal layer Gate1 and the second gate metal layer Gate2, and any two adjacent wirings (including the second signal transmission line 137 and the second fan-out line 132) are located in different gate metal layers Gate (including the first gate metal layer Gate1 and the second gate metal layer Gate2).

[0264] It is understood that the second adapter 1342 can transfer a plurality of second signal transmission lines 137 to the first gate metal layer Gate1 and the second gate metal layer Gate2, and the transfer lines 136 are electrically connected to the second signal transmission lines 137 located in the gate metal layer Gate (e.g., the first gate metal layer Gate1 and the second gate metal layer Gate2). The second signal transmission lines 137 do not need to be transferred to other conductive layers 103 (e.g., the source-drain metal layer SD), which simplifies the manufacturing process and improves production efficiency.

[0265] However, since the second adapter 1342 alternately transfers the multiple second signal transmission lines 137 and the multiple second fan-out lines 132 to the first gate metal layer Gate1 and the second gate metal layer Gate2, when the second signal transmission line 137 located between two adjacent second fan-out lines 132 is electrically connected to the transfer line 136, i.e., when the second signal transmission line 137 located between two adjacent second fan-out lines 132 is transferred to another conductive layer 103, the two adjacent second fan-out lines 132 (fourth sub-fan-out line 1322) are located on the same conductive layer 103, and crosstalk between the two adjacent second fan-out lines 132 (fourth sub-fan-out line 1322) is increased.

[0266] In order to reduce crosstalk between two adjacent second fan-out lines 132 (fourth sub-fan-out line 1322), in some examples, as shown in FIG. 36, after the second signal transmission line 137 located between the two adjacent second fan-out lines 132 (fourth sub-fan-out line 1322) is transferred to another conductive layer 103, at least a portion of the multiple second fan-out lines 132 can be transferred with a jumper through the transfer hole T, so that the multiple second fan-out lines 132 (fourth sub-fan-out line 1322) can be alternately located in the first gate metal layer Gate1 and the second gate metal layer Gate2, thereby reducing crosstalk between the two adjacent second fan-out lines 132 (fourth sub-fan-out line 1322) and improving the signal transmission reliability.

[0267] In some embodiments, as shown in FIG. 35, the second signal transmission line 137 gradually approaches the center line Q of the display substrate 100 from an end closer to the display area AA to an end farther from the display area AA.

[0268] By arranging them in this manner, the space occupied by the multiple second signal transmission lines 137 in the second direction Y can be reduced, the width of the first sub-fan-out region BB21 can be further reduced, and the area utilization rate of the first sub-fan-out region BB21 can be improved.

[0269] Fig. 37 is a partial enlarged view of region 3D in Fig. 27. Fig. 38 is a partial enlarged view of region 4D in Fig. 27.

[0270] In some examples, as shown in FIG. 37, the fourth sub-fan-out line 1322 gradually approaches the center line Q of the display substrate 100 from an end closer to the display area AA to an end farther from the display area AA.

[0271] By arranging them in this manner, the space occupied by the multiple fourth sub-fan-out lines 1322 in the second direction Y can be reduced, the width of the first sub-fan-out region BB21 can be further reduced, and the area utilization rate of the first sub-fan-out region BB21 can be improved.

[0272] In some examples, as shown in FIG. 37, the second signal transmission line 137 and the fourth sub-fan-out line 1322, which are located away from the center line Q of the display substrate 100, both gradually approach the center line Q of the display substrate 100 from the end close to the display area AA to the end away from the display area AA.

[0273] In some examples, the second signal transmission line 137 and the fourth sub-fan-out line 1322 that are close to the center line Q of the display substrate 100 extend along the second direction Y, as shown in FIG.

[0274] As can be seen from the above, in some examples, the second signal transmission line 137 and the second fan-out line 132 (the fourth sub-fan-out line 1322) are located on different conductive layers 103. In some embodiments, the number of the second signal transmission lines 137 is plural. Among two adjacent second signal transmission lines 137, at least a part of the line segment of the second signal transmission line 137 away from the center line Q is curved toward the second signal transmission line 137 closer to the center line Q.

[0275] For example, when the distance between two adjacent second signal transmission lines 137 is relatively large, at least a portion of the line segments of the two adjacent second signal transmission lines 137 that are away from the center line Q are curved toward the second signal transmission line 137 that is closer to the center line Q, thereby reducing the spacing between the multiple second signal transmission lines 137 and reducing the space occupied by the multiple second signal transmission lines 137 along the second direction Y, that is, the width of the first sub-fan-out region BB21 can be reduced.

[0276] In some examples, the second signal transmission line 137 and the multiple second fan-out lines 132 (the fourth sub-fan-out line 1322) are located on different conductive layers 103. In this case, when the distance between two adjacent second signal transmission lines 137 is relatively small, at least a portion of the line segment of the second signal transmission line 137 that is close to the center line Q of the two adjacent second signal transmission lines 137 curves toward the second signal transmission line 137 that is away from the center line Q, thereby avoiding mutual influence between the multiple second signal transmission lines 137.

[0277] In some examples, at least some of the line segments of the plurality of second signal transmission lines 137 extend in a wavy or approximately wavy curved manner.

[0278] In some other examples, at least some of the line segments of the second signal transmission line 137 and at least some of the line segments of the plurality of second fan-out lines 132 (the fourth sub-fan-out line 1322) are located on the same conductive layer 103. In this case, of any two adjacent fan-out lines 130 (including the second signal transmission line 137 and the fourth sub-fan-out line 1322), at least some of the line segments of the second signal transmission line 137 that are away from the center line Q are curved toward the second signal transmission line 137 that is closer to the center line Q.

[0279] For example, when the distance between two adjacent fan-out lines 130 (including the second signal transmission line 137 and the fourth sub-fan-out line 1322) is relatively large, at least a portion of the line segments of the two adjacent fan-out lines 130 (including the second signal transmission line 137 and the fourth sub-fan-out line 1322) that are away from the center line Q will bend toward the fan-out line 130 closer to the center line Q, thereby reducing the spacing between the multiple fan-out lines 130 (including the second signal transmission line 137 and the fourth sub-fan-out line 1322) and reducing the space occupied by the multiple fan-out lines 130 (including the second signal transmission line 137 and the fourth sub-fan-out line 1322) along the second direction Y, that is, the width of the first sub-fan-out region BB21 can be reduced.

[0280] In some examples, when the distance between two adjacent fan-out lines 130 (including the second signal transmission line 137 and the fourth sub-fan-out line 1322) is relatively small, at least a portion of the line segments of the fan-out line 130 closer to the center line Q of the two adjacent fan-out lines 130 curve toward the fan-out line 130 away from the center line Q, thereby avoiding mutual influence between multiple fan-out lines 130 (including the second signal transmission line 137 and the fourth sub-fan-out line 1322).

[0281] In some examples, at least some of the line segments in the multiple fan-out lines 130 (including the second signal transmission line 137 and the fourth sub-fan-out line 1322) extend in a wavy or approximately wavy curved manner.

[0282] FIG. 39 is a partial structural view of a display substrate according to some other embodiments.

[0283] When the transfer line 136 is located at least in the first sub-fan-out region BB21, in some examples, the end of the transfer line 136 away from the first sub-fan-out line 133 extends to the second sub-fan-out region BB22, as shown in Fig. 39. That is, in this case, the transfer line 136 is located not only in the first sub-fan-out region BB21 but also in the second sub-fan-out region BB22.

[0284] It is understood that the ends of the transfer lines 136 remote from the first sub-fan-out lines 133 may extend to the second sub-fan-out region BB22, such that the first data lines 111 may be electrically connected to the driving ICs via the ends of the transfer lines 136 remote from the first sub-fan-out lines 133. With this arrangement, when the transfer lines 136 are electrically connected to the driving ICs, they do not need to be transferred again to another conductive layer 103, which simplifies the manufacturing process and reduces the manufacturing cost.

[0285] In some examples, the transfer line 136 is located in the second source-drain metal layer SD2. It is understood that the first data line 111 is electrically connected to the first fan-out line 131 via the connecting line 120, and the second data line 112 is directly electrically connected to the second fan-out line 132. That is, a signal output by the driving IC is transmitted to the first data line 111 via the first fan-out line 131 and the connecting line 120, and transmitted to the second data line 112 via the second fan-out line 132.

[0286] For ease of explanation, the transmission path of the signal to the first data line 111 may be referred to as the first transmission path a, and the transmission path of the signal to the second data line 112 may be referred to as the second transmission path b. It is understood that the first transmission path a includes the first fan-out line 131, the connection line 120, and the first data line 111, and the second transmission path b includes the second fan-out line 132 and the second data line 112.

[0287] As can be seen from the above, the length of the first transmission path a is longer than the length of the second transmission path b. In some examples, because the length of the first transmission path a is longer than the length of the second transmission path b, the signal delay (full English name: Loading) of the first transmission path a becomes larger than the signal delay of the second transmission path b, and the loading difference between different transmission paths increases, affecting signal transmission.

[0288] Based on this, in some examples, the transfer line 136 is provided in the second source-drain metal layer SD2, and as shown in FIG. 39, the transfer line 136 located in the second source-drain metal layer SD2 is arranged to extend to the second sub-fan-out region BB22, so that the end of the transfer line 136 away from the display area AA can be directly electrically connected to the driving IC.

[0289] Since the resistance of the second source-drain metal layer SD2 is relatively small, the loading of the first transmission path a can be compensated, the loading difference between different transmission paths (the first transmission path a and the second transmission path b) can be reduced, abrupt changes in loading due to different transmission paths can be avoided, and the consistency of loading among multiple transmission paths can be improved, thereby improving the brightness uniformity of the display panel 210.

[0290] As can be seen from the above, in some embodiments, the end of the transfer line 136 away from the first sub-fan-out line 133 extends to the second sub-fan-out region BB22. In some other embodiments, as shown in FIG. 12 , the first sub-fan-out line 131 further includes a second sub-fan-out line 138. The second sub-fan-out line 138 is located in a different conductive layer 103. The isolation portion 140 is located between the transfer line 136 and the second sub-fan-out line 138. That is, the isolation portion 140 is located in the conductive layer 103 between the transfer line 136 and the second sub-fan-out line 138.

[0291] 12, an end of the transfer line 136 away from the first sub-fan-out line 133 is located around the isolation portion 140 and is electrically connected to a second sub-fan-out line 138. An end of the second sub-fan-out line 138 away from the transfer line 136 extends to the second sub-fan-out region BB22.

[0292] It is understood that the second sub-fan-out lines 138 are used to electrically connect the transfer lines 136 to the driving ICs, i.e., the ends of the second sub-fan-out lines 138 away from the display area AA can be electrically connected to the driving ICs.

[0293] By positioning the isolation section 140 between the transfer line 136 and the second sub-fan-out line 138, the isolation section 140 isolates the transfer line 136 from the second sub-fan-out line 138, thereby reducing the parasitic capacitance that occurs between the transfer line 136 and the second sub-fan-out line 138, and improving the reliability of signal transmission.

[0294] In other words, the isolation section 140 not only serves to isolate the transfer line 136 from the multiple second fan-out lines 132, but also serves to isolate the transfer line 136 from the second sub-fan-out line 138, thereby improving the reliability of signal transmission.

[0295] It is understood that at least one of the second sub-fan-out lines 138 and the second fan-out line 132 (the fourth sub-fan-out line 1322) is located in the same conductive layer 103. In some examples, the second sub-fan-out lines 138 are located in the first gate metal layer Gate1 and / or the second gate metal layer Gate2. Also, among the second sub-fan-out lines 132 and the second sub-fan-out lines 138, any two adjacent (adjacent in orthogonal projection on the base 102) fan-out lines 130 (including the fourth sub-fan-out line 1322 of the second fan-out line 132 and the second sub-fan-out line 138 of the first fan-out line 131) are located in different gate metal layers Gate (including the first gate metal layer Gate1 and the second gate metal layer Gate2).

[0296] By arranging them in this manner, the space occupied along the second direction Y when the multiple fan-out lines 130 (including the fourth sub-fan-out line 1322 of the second fan-out line 132 and the second sub-fan-out line 138 of the first fan-out line 131) are electrically connected to the driving IC can be further reduced. Furthermore, crosstalk occurring between two adjacent fan-out lines 130 can be reduced, improving the reliability of signal transmission.

[0297] 12, an end of the transfer line 136 away from the first sub-fan-out line 133 is located around the isolation portion 140 and is electrically connected to the second sub-fan-out line 138. An end of the second sub-fan-out line 138 away from the transfer line 136 extends to the second sub-fan-out region BB22.

[0298] By providing the isolation section 140 in this manner, when the transfer line 136 is electrically connected to the second sub-fan-out line 138, it is possible to avoid any influence on the isolation section 140 located between the transfer line 136 and the second sub-fan-out line 138. It is also possible to improve the isolation effect of the isolation section 140 between the transfer line 136 and the second sub-fan-out line 138, thereby improving the reliability of signal transmission.

[0299] FIG. 40 is a partial enlarged view of region 3F of FIG.

[0300] 40 , a position of the transfer line 136 where the transfer line 136 is connected to the second sub-fan-out line 138 is defined as a first connection point M. An orthogonal projection of a portion of the transfer line 136 that is close to the first connection point M and beyond the isolation portion 140 on the base 102 substantially overlaps with an orthogonal projection of a portion of the second sub-fan-out line 138 that is close to the first connection point M and beyond the isolation portion 140 on the base 102.

[0301] It is understood that the signal transmitted on the transmission line 136 is the same as the signal transmitted on the second sub-fanout line 138 that is electrically connected to the transmission line 136. The transmission line 136 and the second sub-fanout line 138 cannot be isolated through the isolation section 140 because the transmission line 136 and the second sub-fanout line 138 extend beyond the end of the isolation section 140.

[0302] Therefore, by arranging the orthogonal projection of the portion of the transfer line 136 near the first connection point M and beyond the isolation section 140 on the base 102 so that it approximately overlaps with the orthogonal projection of the portion of the second sub-fan-out line 138 near the first connection point M and beyond the isolation section 140 on the base 102, the orthogonal projections of the two conductive wirings (the transfer line 136 and the second sub-fan-out line 138 electrically connected to the transfer line 136) that transmit the same signal approximately overlap.

[0303] By arranging them in this manner, the orthogonal projection of the transfer line 136 or the second sub-fan-out line 138 on the base 102 is prevented from overlapping with the orthogonal projection of other conductive wirings on the base 102, reducing the parasitic capacitance generated between the transfer line 136 and other conductive wirings and the parasitic capacitance generated between the second sub-fan-out line 138 electrically connected to the transfer line 136 and other conductive wirings, thereby improving the signal transmission reliability. In addition, the space occupied by the multiple second sub-fan-out lines 138 along the second direction Y can be reduced, thereby reducing the width of the first sub-fan-out region BB21.

[0304] In some examples, the transfer line 136 and the second sub-fan-out line 138 are electrically connected via a transfer hole T, as shown in FIG.

[0305] In some embodiments, as shown in FIG. 34, the portions of the multiple transfer lines 136 that are close to the first connection point M and extend beyond the isolation portion 140 are located on at least one side of the isolation portion 140 along the first direction X. Exemplarily, the portions of the multiple transfer lines 136 that are close to the first connection point M and extend beyond the isolation portion 140 on the same side of the isolation portion 140 along the first direction X are defined as the first extension portion 136a. The multiple first extension portions are sequentially arranged along the second direction Y, and in the second direction Y, the lengths of the multiple first extension portions 136a gradually increase and then gradually decrease. Alternatively, the lengths of the multiple first extension portions 136a gradually decrease and then gradually increase (as shown in FIG. 34).

[0306] It will be appreciated that the plurality of first extension portions 136a extend along a first direction X and are spaced apart along a second direction Y.

[0307] In some examples, the connection line 120, the transfer line 136, and the second signal transmission line 137 are located in a source-drain metal layer SD (including a first source-drain metal layer SD1 and a second source-drain metal layer SD2). The plurality of second fan-out lines 132 are located in a gate metal layer Gate (including a first gate metal layer Gate1 and a second gate metal layer Gate2). It is understood that the resistance of the source-drain metal layer SD is smaller than the resistance of the gate metal layer Gate.

[0308] As can be seen from the above, the first transmission path a includes the first fan-out line 131 (including the transfer line 136 and the second signal transmission line 137), the connection line 120 and the first data line 111, and the second transmission path b includes the second fan-out line 132 and the second data line 112. Since the resistance of the source-drain metal layer SD is smaller than the resistance of the gate metal layer Gate, in some cases, the loading of the first transmission path a will be smaller than the loading of the second transmission path b, which will affect the luminance consistency of the display panel 210.

[0309] 34, in some examples, the extension length of the transfer line 136 is increased by arranging the multiple first extension portions 136a in sequence along the second direction Y and gradually increasing and then gradually decreasing, or gradually decreasing and then gradually increasing, in the second direction Y. Also, since the second sub-fan-out line 138 is electrically connected to an end of the transfer line 136 that exceeds the isolation portion 140, the length of the second sub-fan-out line 138 can also be increased in this manner.

[0310] In other words, by adopting the above installation method, the length of the first transmission path a can be increased, thereby increasing the loading of the signal on the first transmission path a, improving the consistency of the loading between the first transmission path a and the second transmission path b, and improving the consistency of the pixel brightness, thereby improving the display performance of the display panel 210.

[0311] Furthermore, the lengths of the multiple first extension portions 136a change slowly along the second direction Y, thereby avoiding abrupt changes in the loading on different first transmission paths a, and further improving the consistency of pixel brightness, thereby improving the display performance of the display panel 210.

[0312] In addition, by adopting the above installation method, the space occupied by the multiple transfer lines 136 along the second direction Y can be reduced, thereby improving the area utilization rate of the first sub-fan-out region BB21 and reducing the width of the first sub-fan-out region BB21.

[0313] In some other examples, the lengths of the multiple first extension portions 136a in the second direction Y gradually decrease or gradually increase.

[0314] In some other examples, the lengths of the multiple first extending portions 136a change multiple times in the second direction Y. That is, in the second direction Y, the lengths of the multiple first extending portions 136a gradually decrease and then gradually increase, or gradually increase and then gradually decrease, multiple times.

[0315] In some other examples, the lengths of the multiple first extension portions 136a in the second direction Y are the same or approximately the same, thereby further reducing the impact of the jumper on the loading of different transmission paths and improving the consistency of pixel brightness.

[0316] FIG. 41 is a partial structural view of a display substrate according to some other embodiments.

[0317] In some examples, as shown in FIG. 41, the lengths of the first transmission path a and the second transmission path b are the same or approximately the same, thereby improving the consistency of the resistances of the first transmission path a and the second transmission path b, improving the consistency of the parasitic capacitance formed between the first transmission path a and other conductive layers 103 and the consistency of the parasitic capacitance formed between the second transmission path b and other conductive layers 103, thereby improving the consistency of the loading between the first transmission path a and the second transmission path b, further reducing the impact of the jumper on the loading of different transmission paths, and improving the consistency of the pixel brightness.

[0318] Fig. 42 is a partial enlarged view of region 4B of Fig. 23. Fig. 43 is a partial enlarged view of region 5B of Fig. 23. Fig. 44 is a structural diagram of a transfer line according to some embodiments.

[0319] 42 and 43 , in some embodiments, the orthogonal projection of the transfer line 136 at the base 102 is U-shaped or approximately U-shaped with an opening toward the bend region CC. One end of the transfer line 136 is electrically connected to the first sub-fan-out line 133, and the other end of the transfer line 136 is electrically connected to the second sub-fan-out line 138.

[0320] It will be understood that by having the U-shaped transfer line span at least one second fan-out line 132, the transfer line 136 can adjust the arrangement order of the ends of the first fan-out lines 131 away from the display area AA along the first direction, so that the ends of the first fan-out line 130 to the nth fan-out line 130 away from the display area AA can be spaced apart in sequence along the direction from the first edge to the center line Q, i.e., the arrangement order of the ends of the multiple fan-out lines 130 away from the display area AA along the first direction X will be the same as the arrangement order of the multiple first data lines 111 along the first direction X.

[0321] In some embodiments, as shown in FIG. 44, the U-shaped transfer line is located in the first sub-fan-out region BB21. When one second type first data line 111b is electrically connected to one column of the light emitting elements 300 emitting green light, and any first type first data line 111a is electrically connected to one column of the first sub-pixels, and the first sub-pixels include the sub-pixels 101 emitting red light and the sub-pixels 101 emitting blue light, a U-shaped transfer line may be provided to transfer the first sub-fan-out line 133 electrically connected to the first type first data line 111a. That is, the U-shaped transfer line can electrically connect the first sub-fan-out line 133 to the second sub-fan-out line 138, so that the arrangement order of the ends of the multiple fan-out lines 130 away from the display area AA in the first direction X can be the same as the arrangement order of the multiple data lines 110 in the first direction X.

[0322] In some embodiments, at least one compensation line 151 is provided within the opening of the U-shaped transfer line, as shown in Figure 43. It is understood that the compensation line 151 is used to improve the convenience of etching the U-shaped transfer line and to facilitate patterning of the U-shaped transfer line.

[0323] In some examples, the plurality of conductive layers 103 includes at least one gate metal layer Gate, a first source-drain metal layer SD1, and a second source-drain metal layer SD2. The first source-drain metal layer SD1 and the second source-drain metal layer SD2 are both located on a side of the at least one gate metal layer Gate away from the base 102, and the first source-drain metal layer SD1 is closer to the base 102 than the second source-drain metal layer SD2. The first sub-fan-out line 133, the second sub-fan-out line 138, and the plurality of second fan-out lines 132 are located in the at least one gate metal layer Gate. The isolation portion 140 is located in the first source-drain metal layer SD1, and the transfer line 136 is located in the second source-drain metal layer SD2.

[0324] In some examples, when the multiple conductive layers 103 include multiple gate metal layers Gate (two or more layers), any two adjacent fan-out lines 130 (adjacent in orthogonal projection on the base 102) among the first sub-fan-out line 133, the second sub-fan-out line 138 and the multiple second fan-out lines 132 are located on different gate metal layers Gate, thereby reducing crosstalk between the two adjacent fan-out lines 130 and improving signal transmission reliability, while reducing the distance between the two fan-out lines 130 whose orthogonal projection on the base 102 is adjacent, thereby reducing the space occupied by the multiple fan-out lines 130 along the second direction Y.

[0325] The first source-drain metal layer SD1 and the second source-drain metal layer SD2 are both located on the side of at least one gate metal layer Gate that is away from the base 102, and the first source-drain metal layer SD1 is closer to the base 102 than the second source-drain metal layer SD2. Therefore, by positioning the isolation portion 140 in the first source-drain metal layer SD1 and the transfer line 136 in the second source-drain metal layer SD2, the isolation portion 140 is located between the transfer line 136 and the second sub-fan-out line 138 and between the transfer line 136 and the multiple second fan-out lines 132, and the parasitic capacitance generated by the transfer line 136 and the second sub-fan-out line 138 and the parasitic capacitance generated by the transfer line 136 and the multiple second fan-out lines 132 can be reduced, thereby improving the signal transmission reliability.

[0326] In some examples, the isolation unit 140 includes at least one power signal line, which is used to transmit a stable voltage signal, and may be, for example, at least one of a Vdd signal line that provides a voltage to the anode of the light-emitting element 300, a Vss signal line that provides a voltage to the cathode of the light-emitting element 300, etc., but is not limited to this.

[0327] It is understood that the isolation between the transfer line 136 and the second fan-out line 132, and the isolation between the transfer line 136 and the second sub-fan-out line 138 are achieved through the power supply signal line, thus eliminating the need to install additional components, simplifying the manufacturing process, and reducing the cost of the display substrate 100.

[0328] As can be seen from the above, in some examples, the transfer line 136 is located in the first sub-fan-out region BB21. In some other embodiments, the second fan-out region BB2 includes the first sub-fan-out region BB21 and the second sub-fan-out region BB22, and the first sub-fan-out region BB21 is closer to the bending region CC than the second sub-fan-out region BB22. The transfer line 136 is located in the second sub-fan-out region BB22. In this case, the transfer line 136 and the second adapter 1342 can still be electrically connected via the second signal transmission line 137. That is, the second signal transmission line 137 extends from the first sub-fan-out region BB21 to the second sub-fan-out region BB22.

[0329] By configuring in this way, the transfer line 136 can transfer the first sub-fan-out line 133 to different sub-fan-out regions (including the first sub-fan-out region BB21 and the second sub-fan-out region BB22) to meet different usage needs.

[0330] In the following, an example will be described in which the transfer line 136 is located in the second sub-fan-out region BB22.

[0331] FIG. 45 is a partial structural view of a display substrate according to some other embodiments.

[0332] 45, the display substrate 100 includes a first fan-out region BB1, a bending region CC, a first sub-fan-out region BB21, a CT region, a second sub-fan-out region BB22, a COP region, an ILB region, and an FOP region, which are arranged in order from the display region AA. Here, a driving chip (e.g., a driving IC) may be attached in the COP region, a binding connection block (e.g., a gold finger) may be provided in the FOP region, and a signal line connecting a pin of the driving chip and a conductive binding connection block may be arranged in the ILB region. A test circuit may be provided in the CT region, and the test circuit is used to test the performance (e.g., display effect) of the display panel 210.

[0333] Fig. 46 is a partial structural view of a display substrate according to some other embodiments, Fig. 47 is a partial enlarged view of a region 1H in Fig. 46, Fig. 48 is a partial enlarged view of a region 2H in Fig. 46.

[0334] 46, the transfer line 136 includes a first sub-transfer line 31 and a second sub-transfer line 32. The first sub-transfer line 31 is electrically connected to a first sub-fan-out line 133 (not shown in FIG. 46).

[0335] It is understood that the electrical connection here does not refer to a direct structural connection, and that, for example, a signal transmission line (e.g., the first signal transmission line 135 and the second signal transmission line 137) passing through the bending region CC and the first sub-fan-out region BB21 may be connected between the first sub-transmission line 31 and the first sub-fan-out line 133.

[0336] 47, the second signal transmission line 137 extends to the second sub-fan-out region BB22, and the first sub-transmission line 31 is electrically connected to an end of the second signal transmission line 137 away from the bending region CC via a transfer hole T. As shown in FIG. 47, the first sub-transmission line 31 spans at least one second fan-out line 132, i.e., the orthogonal projection of the first sub-transmission line 31 at the base 102 intersects with the orthogonal projection of the at least one second fan-out line 132 at the base 102.

[0337] The second sub-transport line 32 is electrically connected to an end of the first sub-transport line 31 away from the first sub-fan-out line 133. As shown in FIG. 48 , the orthogonal projection of at least one second sub-transport line 32 on the base 102 is located between the orthogonal projections of two adjacent second fan-out lines 132 on the base 102.

[0338] The first sub-transmission line 31 is electrically connected to the first sub-fan-out line 133 and spans at least one second fan-out line 132, so that the first sub-transmission line 31 can play a role of jumper transmission, so that the arrangement order of the ends of the multiple fan-out lines 130 away from the display area AA along the first direction X can be the same as the arrangement order of the multiple data lines 110 along the first direction X.

[0339] Furthermore, as shown in FIG. 48, the orthogonal projection of at least one second sub-transfer line 32 at the base 102 is located between the orthogonal projections of two adjacent second fan-out lines 132 at the base 102, thereby avoiding overlap between the orthogonal projection of the second sub-transfer line 32 at the base 102 and the orthogonal projections of the multiple second fan-out lines 132 at the base 102, thereby reducing the parasitic capacitance between the second sub-transfer line 32 and the multiple second fan-out lines 132 and improving the reliability of signal transmission.

[0340] In some examples, the first sub-transport line 31 and the second sub-transport line 32 of the same transfer line 136 are located on the same conductive layer 103, thereby improving the convenience of the electrical connection between the first sub-transport line 31 and the second sub-transport line 32.

[0341] In some examples, multiple transfer lines 136 are located on one or more other conductive layers 103. When transfer lines 136 are located on multiple conductive layers 103, two adjacent transfer lines 136 may be located on different conductive layers 103.

[0342] 49 is a partial structural view of a display substrate according to some other embodiments, and FIG 50 is a partial enlarged view of region 3H in FIG 49.

[0343] In some examples, as shown in FIGS. 49 and 50, the multiple transfer lines 136 are located in the first source-drain metal layer SD1 and / or the second source-drain metal layer SD2.

[0344] For example, when the multiple transfer lines 136 are located in the first source-drain metal layer SD1 and the second source-drain metal layer SD2, two adjacent transfer lines 136 (adjacent in their orthogonal projections on the base 102) are located in different source-drain metal layers (the first source-drain metal layer SD1 and the second source-drain metal layer SD2). That is, the multiple transfer lines 136 are alternately located in the first source-drain metal layer SD1 and the second source metal layer SD2.

[0345] By installing in this manner, crosstalk between two adjacent transfer lines 136 can be reduced and signal transmission reliability can be improved, while the orthogonal projection on the base 102 can reduce the distance between two adjacent transfer lines 136, thereby reducing the space occupied by the transfer lines 136 along the second direction Y and reducing the width of the second sub-fan-out region BB22.

[0346] Fig. 51 is a partial structural view of a display substrate according to still other embodiments, Fig. 52 is a partial structural view of a display substrate according to still other embodiments, Fig. 53 is a partial structural view of a display substrate according to still other embodiments.

[0347] 51, the second sub-fan-out region BB22 includes two first regions K01, and the two first regions K01 are located on both sides of the center line Q. It is understood that the two first regions K01 may have the same or approximately the same shape and area.

[0348] In some examples, as shown in Figures 52 and 53, at least one first region K01 includes multiple sub-regions. The multiple sub-regions include a first sub-region K1, a second sub-region K2, and a third sub-region K3. The first sub-region K1, the second sub-region K2, and the third sub-region K3 are arranged in order along a direction from an edge away from the centerline to the centerline Q. That is, the first sub-region K1 is farther away from the centerline than the second sub-region K2, and the second sub-region K2 is farther away from the centerline than the third sub-region K3.

[0349] As shown in FIGS. 52 and 53, for ease of explanation, the direction from the edge portion away from the center line of the first region K01 to the center line Q may be referred to as a third direction X1.

[0350] 51 to 53, an end P of the first sub-transfer line 31 electrically connected to the first sub-fan-out line 133 (i.e., the position of the transfer hole T in FIGS. 47 and 50, shown as the position P in FIGS. 51 to 53) is located in at least one of the first sub-region K1, the second sub-region K2, and the third sub-region K3. The second sub-transfer line 32 is located in the first sub-region K1.

[0351] In some examples, as shown in Fig. 49, the ends P electrically connected to the first sub-fan-out lines 133 of the multiple first sub-transfer lines 31 are all located in the first sub-region K1. In some other examples, as shown in Fig. 46, the ends P electrically connected to the first sub-fan-out lines 133 of the multiple first sub-transfer lines 31 are all located in the second sub-region K2. In some other examples, as shown in Fig. 52, the ends P electrically connected to the first sub-fan-out lines 133 of the multiple first sub-transfer lines 31 are all located in the third sub-region K3.

[0352] It is understood that the closer an end P of the multiple first sub-transfer lines 31 that is electrically connected to the first sub-fan-out line 133 is to the center line Q, the larger the overlap area between the orthogonal projection of the first sub-transfer line 31 on the base 102 and the orthogonal projection of the multiple second fan-out lines 132 on the base 102 becomes, the larger the parasitic capacitance generated between them becomes, and the higher the signal transmission loading becomes. Conversely, the farther an end P of the multiple first sub-transfer lines 31 that is electrically connected to the first sub-fan-out line 133 is from the center line Q, the smaller the overlap area between the orthogonal projection of the first sub-transfer line 31 on the base 102 and the orthogonal projection of the multiple second fan-out lines 132 on the base 102 becomes, the smaller the parasitic capacitance generated between them becomes, and the lower the signal transmission loading becomes.

[0353] The magnitude of the parasitic capacitance affects loading when a signal is transmitted through different transmission paths. In this way, the ends P electrically connected to the first sub fan-out lines 133 of the plurality of first sub transmission lines 31 can be arranged to be located in different sub-regions (at least one of the first sub-region K1, the second sub-region K2, and the third sub-region K3) according to different needs, thereby improving the flexibility of the display substrate 100.

[0354] It is understood that by locating the second sub-transport line 32 in the first sub-region K1, the parasitic capacitance between the second sub-transport line 32 and the multiple second fan-out lines 132 is reduced, thereby improving the signal transmission reliability.

[0355] In some examples, as shown in FIG. 53, ends P of the multiple first sub-transfer lines 31 that are electrically connected to the first sub-fan-out lines 133 are located in different sub-regions of the first region K01.

[0356] This arrangement can further improve the flexibility of the display substrate 100 and meet different usage needs.

[0357] In some examples, as shown in FIG. 53, the ends P of the multiple first sub-transfer lines 31 that are electrically connected to the first sub-fan-out lines 133 are evenly distributed in the first sub-region K1, the second sub-region K2, and the third sub-region K3.

[0358] By arranging them in this manner, the regularity of the structure of the plurality of first sub-transfer lines 31 is improved, and manufacturing and processing are facilitated.

[0359] In some examples, the two first regions K01 each include a first sub-region K1, a second sub-region K2, and a third sub-region K3. The installation positions of the ends Q1 electrically connected to the first sub-fan-out lines 133 of the transfer lines 136 in the two first regions K01 may be the same or different.

[0360] As can be seen from the above, the electrical connection between the transmission line 136 and the data line 110 can be divided into forward FIAA and reverse FIAA. In some examples, when wiring is performed using the reverse FIAA method, it can be understood that the first data line 110, the second data line 110, and the third data line 110 approach the center line Q in sequence, and the second end of the first connecting line 120 electrically connected to the first data line 110, the second end of the second connecting line 120 electrically connected to the second data line 110, and the second end of the third connecting line 120 electrically connected to the third data line 110 move away from the center line Q in sequence.

[0361] Thus, as shown in FIG. 46, the first second signal transmission line 137a, the second second signal transmission line 137b, and the third second signal transmission line 137c move away from the center line Q in order, and as a result, the multiple first sub-transmission lines 31 electrically connected to the first second signal transmission line 137a, the second second signal transmission line 137b, and the third second signal transmission line 137c move away from the center line Q in order.

[0362] FIG. 54 is a partial structural view of a display substrate according to some other embodiments.

[0363] In some other examples, when wiring is performed using the forward FIAA method, it can be understood that, as shown in FIG. 54, the first data line 110, the second data line 110, and the third data line 110 approach the center line Q in that order, and the second end of the first connecting line 120 electrically connected to the first data line 110, the second end of the second connecting line 120 electrically connected to the second data line 110, and the second end of the third connecting line 120 electrically connected to the third data line 110 approach the center line Q in that order.

[0364] Thus, as shown in FIG. 54, the first second signal transmission line 137a, the second second signal transmission line 137b, and the third second signal transmission line 137c move closer to the center line Q in order, and as a result, the multiple first sub-transmission lines 31 electrically connected to the first second signal transmission line 137a, the second second signal transmission line 137b, and the third second signal transmission line 137c move closer to the center line Q in order.

[0365] Fig. 55 is a partial structural view of a display substrate according to still other embodiments. Fig. 56 is a partial structural view of a display substrate according to still other embodiments. Fig. 57 is a partial structural view of a display substrate according to still other embodiments. Fig. 58 is a partial structural view of a display substrate according to still other embodiments.

[0366] In some embodiments, the contour shape of the region in which the orthogonal projections of all the first sub-transfer lines 31 in the first region K01 on the base 102 are located is a trapezoid, as shown in Fig. 46, Fig. 52, Fig. 54, and Fig. 55 to Fig. 58. Alternatively, the contour shape of the region in which the orthogonal projections of all the first sub-transfer lines 31 in the first region K01 on the base 102 are located is a triangle, as shown in Fig. 49, Fig. 51, and Fig. 53.

[0367] In some examples, the upper base of the trapezoid is closer to the display area AA than the lower base (forward order FIAA), as shown in Figures 54-58. In some other examples, the upper base of the trapezoid is farther from the display area AA than the lower base (reverse order FIAA), as shown in Figures 46 and 52. Here, the upper base refers to the relatively short base side, and the lower base refers to the relatively long base side. The upper base is parallel to the lower base.

[0368] In some examples, as shown in Figures 55 and 56, the second sub-fan-out region BB22 includes a second region K02 and a third region K03. The second region K02 is closer to the first sub-fan-out region BB21 than the third region K03. The length of the edge of the second region K02 on the side closer to the first sub-fan-out region BB21 is longer than the length of the edge of the second region K02 on the side away from the first sub-fan-out region BB21.

[0369] In some examples, the second region K02 may be trapezoidal. The edge of the second region K02 closer to the first sub-fan-out region BB21 is the lower base of the trapezoid, and the edge of the second region K02 away from the first sub-fan-out region BB21 is the upper base of the trapezoid. It is understood that the upper and lower bases of the trapezoid are parallel, and the length of the upper base is shorter than the length of the lower base. In some other examples, the second region K02 may be other irregular shapes.

[0370] 56 and 57, the first sub-transfer line 31 extends along a first direction X, and the second sub-transfer line 32 extends along a second direction Y. At least one first sub-transfer line 31 is located in the second region K02, and at least one second sub-transfer line 32 extends from the second region K02 to the third region K03.

[0371] As can be seen from above, the first direction X is perpendicular or nearly perpendicular to the second direction Y, the first sub-transfer line 31 extends along the first direction, and the second sub-transfer line 32 extends along the second direction Y, such that the first sub-transfer line 31 and the second sub-transfer line 32 may be perpendicular or nearly perpendicular.

[0372] It is understood that since the length of the edge of the second region K02 closer to the first sub-fan-out region BB21 is longer than the length of the edge of the second region K02 away from the first sub-fan-out region BB21, there is an angle between at least one conductive wiring in the second region K02 (e.g., wiring on the first gate metal layer Gate1, the second gate metal layer Gate2, the first source-drain metal layer SD1, and the second source-drain metal layer SD2) and the second direction Y, i.e., at least one wiring in the second region K02 extends obliquely with respect to the second direction Y.

[0373] Exemplarily, the third region K03 may be rectangular or square. At least one conductive wiring (e.g., wiring on the first gate metal layer Gate1, the second gate metal layer Gate2, the first source-drain metal layer SD1, and the second source-drain metal layer SD2) in the third region K03 extends along the second direction Y.

[0374] Since at least one conductive wiring in the second region K02 extends obliquely with respect to the second direction Y, and at least one conductive wiring in the third region K03 extends along the second direction Y, when the first sub-transfer line 31 is located in the second region K02 (as shown in Figures 56 and 57), the overlapping area between the orthogonal projection on the base 102 of the first sub-transfer line 31 and the orthogonal projection on the base 102 of the wiring extending along the inclined direction (inclined with respect to the second direction Y) in the second region K02 is larger than the overlapping area between the orthogonal projection on the base 102 of the first sub-transfer line 31 and the orthogonal projection on the base 102 of the wiring extending along the second direction Y in the third region K03 when the first sub-transfer line 31 is located in the third region K03 (as shown in Figures 54 and 55). It will be understood that the smaller the overlapping area between the orthogonal projection on the base 102 of the first sub-transfer line 31 and the orthogonal projection on the base 102 of other wirings, the smaller the parasitic capacitance will be, and the higher the signal transmission reliability will be.

[0375] However, the second region K02 is closer to the first sub-fan-out region BB21 than the third region K03, i.e., by arranging at least a portion of the first sub-transfer lines 31 within the second region K02, it is possible to improve the area utilization rate of the second sub-fan-out region BB22 and reduce the space occupied by the multiple second sub-transfer lines 32 along the second direction Y, thereby reducing the width of the second sub-fan-out region BB22.

[0376] For example, the width h1 of the second sub-fan-out region BB22 in Figures 56 and 57 is smaller than the width h2 of the second sub-fan-out region BB22 in Figures 55 and 58. Also, for example, the width h1 of the second sub-fan-out region BB22 in Figures 52 and 53 is smaller than the width h2 of the second sub-fan-out region BB22 in Figure 51.

[0377] That is, when the first sub-transfer lines 31 are all located in the second region K02, the area utilization rate of the second sub-fan-out region BB22 is improved and the space occupied by the second sub-transfer lines 32 along the second direction Y can be reduced, and the width of the second sub-fan-out region BB22 can be reduced. However, this arrangement increases the overlap area between the first sub-transfer lines 31 and other wiring, and increases the parasitic capacitance. On the other hand, when the first sub-transfer lines 31 are all located in the third region K03, the overlap area between the first sub-adapter line 31 and other wiring can be reduced, and the parasitic capacitance can be reduced. However, this arrangement decreases the area utilization rate of the second sub-fan-out region BB22 and increases the space occupied by the second sub-transfer lines 32 along the second direction Y, and therefore increases the width of the second sub-fan-out region BB22.

[0378] Therefore, in some embodiments of the present disclosure, at least one first sub-transmission line 31 is located in the second region K02, and at least one second sub-transmission line 32 is arranged to extend from the second region K02 to the third region K03. In this way, the positions of the second sub-transmission lines 32 can be set in combination with consideration of the area utilization rate and parasitic capacitance of the second sub-fan-out region BB22 according to different needs, and the flexibility of wiring of the display substrate 100 can be improved.

[0379] As can be seen from the above, in some examples, the first sub-transmission line 31 extends along the first direction X. That is, the multiple first sub-transmission lines 31 are parallel or substantially parallel. Exemplarily, the portion of the second signal transmission line 137 located in the second sub-fan-out region BB22 is in a different layer from the first sub-transmission line 31. For example, the portion of the second signal transmission line 137 located in the second sub-fan-out region BB22 may be located in the first gate metal layer Gate1 or the second gate metal layer Gate2.

[0380] Fig. 59 is a partial structural view of a display substrate according to some other embodiments, and Fig. 60 is a partial enlarged view of region 4H in Fig. 59.

[0381] In some other examples, as shown in FIGS. 59 and 60, the distance between at least two adjacent first sub-transfer lines 31 gradually decreases along the direction from the first sub-fan-out region BB21 to the second sub-fan-out region BB22.

[0382] By arranging them in this manner, the multiple first sub-transfer lines 31 (transfer lines 136) are gathered close to each other and can be electrically connected to the second sub-transfer lines 32, which improves the wiring convenience of the multiple first sub-transfer lines 31 and enables the size of the second sub-fan-out region BB22 along the second direction Y to be reduced.

[0383] As can be seen from above, in some examples, the first fan-out line 131 further includes a second sub-fan-out line 138. The second sub-fan-out line 138 and the transfer line 136 are located in different conductive layers 103. The second sub-fan-out line 138 is located in the second sub-fan-out region BB22 and is electrically connected to an end of the transfer line 136 remote from the first sub-fan-out line 133.

[0384] It is understood that the second sub-fan-out lines 138 are used to electrically connect the transfer lines 136 (second sub-transfer lines 32) to the driving ICs. In some examples, the second sub-fan-out lines 138 are located in the first gate metal layer Gate1 and the second gate metal layer Gate2.

[0385] In some examples, at least one of the second sub-fan-out lines 138 and the second fan-out lines 132 are located in different conductive layers 103. Illustratively, among the plurality of second sub-fan-out lines 138 and the plurality of second fan-out lines 132, any two adjacent (adjacent in orthogonal projection on the base 102) fan-out lines 130 (including the second sub-fan-out line 138 and the second fan-out line 132) are located in different gate metal layers Gate (including the first gate metal layer Gate1 and the second gate metal layer Gate2).

[0386] By arranging them in this manner, the space occupied along the second direction Y when the multiple fan-out lines 130 (including the second fan-out line 132 and the second sub-fan-out line 138) are electrically connected to the driving IC can be further reduced, and the electrical connection between the driving IC and the multiple fan-out lines 130 can be easily made. In addition, crosstalk occurring between two adjacent fan-out lines 130 can be reduced, and the signal transmission reliability can be improved.

[0387] As can be seen from the above, in some examples, the plurality of conductive layers 103 includes at least one gate metal layer Gate, a first source-drain metal layer SD1, and a second source-drain metal layer SD2. The first source-drain metal layer SD1 and the second source-drain metal layer SD2 are both located on the side of the at least one gate metal layer Gate that is away from the base 102, and the first source-drain metal layer SD1 is closer to the base 102 than the second source-drain metal layer SD2. The first sub-fan-out line 133, the second sub-fan-out line 138, and the plurality of second fan-out lines 132 are located in the at least one gate metal layer Gate, and the transfer line 136 is alternately located in the first source-drain metal layer SD1 and the second source-drain metal layer SD2.

[0388] By installing in this manner, the distance between two adjacent transfer lines 136 whose orthogonal projections on the base 102 are formed can be further reduced, thereby reducing the space occupied by the multiple transfer lines 136 along the second direction Y and improving the area utilization rate of the second fan-out region BB2 (including the first sub-fan-out region BB21 and the second sub-fan-out region BB22).

[0389] In some examples, the at least one gate metal layer Gate includes a first gate metal layer Gate1 and a second gate metal layer Gate2, as shown in Figure 48. The first gate metal layer Gate1 is closer to the base 102 than the second gate metal layer Gate2.

[0390] The first sub-fan-out lines 133, the second sub-fan-out lines 138, and the second fan-out lines 132 are located in a first gate metal layer Gate1 and a second gate metal layer Gate2. Exemplarily, among the first sub-fan-out lines 133 and the second fan-out lines 132 (third sub-fan-out lines 1321) located in the first fan-out region BB1, any two adjacent fan-out lines 130 are located in different gate metal layers Gate. Among the second sub-fan-out lines 138 and the second fan-out lines 132 (fourth sub-fan-out lines 1322) located in the second fan-out region BB2, any two adjacent fan-out lines 130 are located in different gate metal layers Gate.

[0391] By installing them in this manner, crosstalk between two adjacent fan-out lines 130 (e.g., a plurality of first sub-fan-out lines 133 and a plurality of third sub-fan-out lines 1321 located in the first fan-out region BB1, or a plurality of second sub-fan-out lines 138 and a plurality of fourth sub-fan-out lines 1322 located in the second fan-out region BB2) is reduced, improving the reliability of signal transmission.

[0392] In addition, the distance between two adjacent fan-out lines 130 (for example, the multiple first sub-fan-out lines 133 and the multiple third sub-fan-out lines 1321 located in the first fan-out region BB1, or the multiple second sub-fan-out lines 138 and the multiple fourth sub-fan-out lines 1322 located in the second fan-out region BB2) whose orthogonal projections on the base 102 can also be reduced, thereby reducing the space occupied by the multiple fan-out lines 130 along the second direction Y, reducing the widths of the first fan-out region BB1 and the second fan-out region BB2, and achieving a narrower frame for the display panel 210.

[0393] In some examples, the plurality of conductive layers 103 include a light-shielding metal layer (not shown, which may be located, for example, between the active layer 1031 and the base 102 to prevent reflection of light into a channel region of the active layer 1031), at least one active layer 1031, at least one source-drain metal layer SD, a plurality of gate metal layers Gate, at least one transparent conductive layer (not shown), and an anode layer AND.

[0394] The transfer line 136 is located in at least one of the light-shielding metal layer, at least one active layer 1031, at least one source-drain metal layer SD, one of the gate metal layers Gate, at least one transparent conductor layer, and the anode layer. The second fan-out lines 132 are located in at least one of the gate metal layers Gate.

[0395] By installing them in this manner, the orthogonal projection on the base 102 can further reduce the distance between two adjacent transfer lines 136, thereby reducing the space occupied by the multiple transfer lines 136 along the second direction Y and improving the area utilization rate of the second fan-out region BB2 (including the first sub-fan-out region BB21 and the second sub-fan-out region BB22). Furthermore, the orthogonal projection on the base 102 can reduce the distance between two adjacent fan-out lines 130 (for example, the multiple first sub-fan-out lines 133 and the multiple third sub-fan-out lines 1321 located in the first fan-out region BB1, or the multiple second sub-fan-out lines 138 and the multiple fourth sub-fan-out lines 1322 located in the second fan-out region BB2), thereby realizing a narrower frame of the display panel 210.

[0396] In some examples, the multiple gate metal layers Gate include a first gate metal layer Gate1, a second gate metal layer Gate2, and a third gate metal layer (not shown). The third gate metal layer may be located on a side of the second gate metal layer Gate2 that is remote from the first gate metal layer Gate1. The at least one source-drain metal layer SD includes a first source-drain metal layer SD1, a second source-drain metal layer SD2, and a third source-drain metal layer (not shown). The third source-drain metal layer may be located on a side of the second source-drain metal layer SD2 that is remote from the first source-drain metal layer SD1.

[0397] The transfer line 136 is located in at least one of the light shielding metal layer, at least one active layer 1031, the first source-drain metal layer SD1, the second source-drain metal layer SD2, the third source-drain metal layer, the third gate metal layer, at least one transparent conductor layer, and the anode layer AND. The second fan-out lines 132 are alternately located in the first gate metal layer Gate1 and the second gate metal layer Gate2.

[0398] By installing in this manner, the orthogonal projection on the base 102 can further reduce the distance between two adjacent transfer lines 136, thereby reducing the space occupied by the multiple transfer lines 136 along the second direction Y and improving the area utilization rate of the second fan-out region BB2 (including the first sub-fan-out region BB21 and the second sub-fan-out region BB22). Furthermore, the orthogonal projection on the base 102 can reduce the distance between two adjacent fan-out lines 130, thereby achieving a narrower frame of the display panel 210.

[0399] As can be seen above, in some examples, when transfer line 136 is located in first fan-out region BB1, transfer line 136 may be a U-shaped transfer line. In some other examples, when transfer line 136 is located in second fan-out region BB2, transfer line 136 may be a U-shaped transfer line.

[0400] Illustratively, the orthogonal projection of the transfer line 136 on the base 102 is U-shaped or approximately U-shaped with an opening toward the bending region CC. One end of the transfer line 136 is electrically connected to the first sub-fan-out line 133, and the other end of the transfer line 136 is electrically connected to the second sub-fan-out line 138. It is understood that when the transfer line 136 is located in the second fan-out region BB2, the transfer line 136 may be electrically connected to the first sub-fan-out line 133 via the first signal transmission line 135 and the second signal transmission line 137, etc.

[0401] As described above, the display substrate 100 provided by some embodiments of the present disclosure uses the FIAA or partial FIAA method to reduce the width of the side frame of the display panel 210, and the transfer line 136 of the first fan-out line 131 is located on a different conductive layer 103 from the multiple second fan-out lines 132, and the transfer line 136 is arranged to span at least one second fan-out line 132, so that the arrangement order of the ends of the multiple fan-out lines 130 (including the first fan-out line 131 and the second fan-out line 132) away from the display area AA in the first direction is the same as the arrangement order of the multiple data lines 110 in the first direction X. As a result, the driving IC can sequentially provide electrical signals to the multiple data lines 110, and there is no need to redevelop the driving IC, which can reduce the cost of the display substrate 100 while realizing a narrower frame of the display substrate 100.

[0402] The display device 200 provided according to some embodiments of the present disclosure includes the above-mentioned display substrate 100, and therefore has all the above-mentioned beneficial effects, which will not be repeated here.

[0403] The above are only specific embodiments of the present disclosure, and the scope of protection of the present disclosure is not limited thereto, and any modifications or replacements that can be easily thought of by a person skilled in the art within the technical scope of the present disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be governed by the scope described in the claims.

Claims

1. A display substrate, a display region and a fan-out region, the fan-out region being adjacent to one edge of the display region, the display substrate comprising: With the base, A plurality of conductive layers disposed on the same side of the base and stacked thereon; Equipped with The plurality of conductive layers include a plurality of data lines spaced apart from one another along a first direction and all extending along a second direction, the second direction intersecting the first direction, the plurality of data lines including a plurality of first data lines and a plurality of second data lines, the plurality of first data lines being located in two edge regions along the first direction of the display area, and the plurality of second data lines being located in a central region along the first direction of the display area; a plurality of connection lines, a first end of each of which is located in an edge region along the first direction of the display area and is electrically connected to one first data line, a second end of each of the connection lines extending to a position close to the fan-out region in a central region of the display area, the connection lines spanning at least one data line and being insulated from the spanning data line, and a second end of at least one of the connection lines spanning between two adjacent second data lines; a plurality of fan-out lines located in the fan-out region, the plurality of fan-out lines including a plurality of first fan-out lines and a plurality of second fan-out lines, the first fan-out lines being electrically connected to a second end of the connection line, and the second fan-out lines being electrically connected to an end of the second data line close to the fan-out region; Includes: the display substrate further includes a bending region, the fan-out region includes a first fan-out region and a second fan-out region, the first fan-out region is closer to the display region than the second fan-out region, and the bending region is located between the first fan-out region and the second fan-out region; the first fan-out lines include transfer lines, the transfer lines are located in the second fan-out region, the transfer lines are located in a conductive layer different from the second fan-out lines, and the transfer lines cross at least one of the second fan-out lines, so that an arrangement order of ends of the fan-out lines away from the display region in the first direction is the same as an arrangement order of the data lines in the first direction; A display substrate comprising:

2. the plurality of connection lines are electrically connected to the plurality of first data lines in one-to-one correspondence, and the plurality of second fan-out lines are electrically connected to the plurality of second data lines in one-to-one correspondence; 2. The display substrate according to claim 1.

3. the plurality of first data lines include a plurality of first type first data lines and a plurality of second type first data lines, the plurality of second fan-out lines include a plurality of first type second fan-out lines and a plurality of second type second fan-out lines, the first type first data lines are electrically connected to the connection lines in one-to-one correspondence; the plurality of first type second fan-out lines are electrically connected to the plurality of second data lines in one-to-one correspondence, and the plurality of second type second fan-out lines are electrically connected to the plurality of second type first data lines in one-to-one correspondence; 2. The display substrate according to claim 1.

4. the display substrate further includes a plurality of sub-pixels, the plurality of sub-pixels being arranged in a plurality of columns along the first direction and in a plurality of rows along the second direction, the sub-pixels in one column being electrically connected to one data line; Two first type first data lines are provided between two adjacent second type first data lines; one of the two first type first data lines is electrically connected to first sub-pixels in one column, the first sub-pixels including a sub-pixel that emits red light and a sub-pixel that emits blue light; and the second type first data line is electrically connected to sub-pixels in one column that emits green light.

4. The display substrate according to claim 3.

5. The first fan-out line is a first sub-fan-out line electrically connected to a second end of the connection line; a plurality of adapters including a first adapter located in a region of the first fan-out region close to the bending region and a second adapter located in a region of the second fan-out region close to the bending region, the first adapter being electrically connected to an end of a first sub-fan-out line away from the connection line, and the transfer line being electrically connected to the second adapter; a first signal transmission line passing through the bent region and connecting the first adapter and the second adapter; Further comprising:

5. The display substrate according to claim 1, wherein the first and second electrodes are arranged in a first direction.

6. a center line of the display substrate is located at a center of the display substrate along the first direction and is parallel to the base; a portion of the second fan-out line located in the first fan-out region is defined as a third sub-fan-out line, and the third sub-fan-out line and the first sub-fan-out line are arranged along the first direction; For two adjacent fan-out lines among the third sub-fan-out line and the first sub-fan-out line, at least a portion of the line segments of the fan-out lines that are away from the center line are curved toward the fan-out line closer to the center line.

6. The display substrate according to claim 5.

7. the second fan-out region includes a first sub-fan-out region and a second sub-fan-out region, the first sub-fan-out region is closer to the bending region than the second sub-fan-out region, and at least a portion of the transfer line is located in the first sub-fan-out region; The display substrate is further comprising an isolation portion located in the first sub-fan-out region and between the transfer line and the second fan-out lines; 7. The display substrate according to claim 5 or 6.

8. The first fan-out line is a second signal transmission line connected between the second adapter and the transfer line; an orthogonal projection of the second signal transmission line at the base is located between an orthogonal projection of the isolation portion at the base and an edge of the first sub-fan-out region closer to the bend region; 8. The display substrate according to claim 7.

9. the second signal transmission line gradually approaches a center line of the display substrate from one end close to the display area to the other end away from the display area; 9. The display substrate according to claim 8.

10. the number of the second signal transmission lines is plural, and at least a portion of the second signal transmission lines, which are adjacent to each other, and which are separated from a center line, are curved toward the second signal transmission line closer to the center line; 10. The display substrate according to claim 8 or 9.

11. an end of the transfer line away from the first sub-fan-out line extends to the second sub-fan-out region; 11. The display substrate according to claim 7, wherein the display substrate is a substrate having a thickness of 100 nm or less.

12. the first fan-out line further includes a second sub-fan-out line, the second sub-fan-out line being located in a different conductive layer from the transfer line, and the isolation portion being located between the transfer line and the second sub-fan-out line; an end of the transfer line away from the first sub fan-out line is located around the isolation portion and is electrically connected to the second sub fan-out line, and an end of the second sub fan-out line away from the transfer line extends to the second sub fan-out region; 11. The display substrate according to claim 7, wherein the display substrate is a substrate having a thickness of 100 nm or less.

13. a position of the transfer line connected to the second sub fan-out line is defined as a first connection point, and an orthogonal projection of a portion of the transfer line close to the first connection point and beyond the isolation portion on the base substantially overlaps with an orthogonal projection of a portion of the second sub fan-out line close to the first connection point and beyond the isolation portion on the base. The display substrate according to claim 12 .

14. a portion of the plurality of transfer lines that is close to the first connection point and that exceeds the isolation portion is located on at least one side of the isolation portion along the first direction; a portion of the plurality of transfer lines located on the same side of the isolation portion along the first direction, the portion being close to the first connection point and extending beyond the isolation portion, is defined as a first extension portion, the plurality of first extension portions are sequentially arranged along the second direction, and in the second direction, lengths of the plurality of first extension portions gradually increase and then gradually decrease, or lengths of the plurality of first extension portions gradually decrease and then gradually increase; The display substrate according to claim 13 .

15. an orthogonal projection of the transfer line at a base thereof is U-shaped or approximately U-shaped with an opening toward a bend region, one end of the transfer line being electrically connected to a first sub-fan-out line, and the other end of the transfer line being electrically connected to a second sub-fan-out line; The display substrate according to claim 12 .

16. The plurality of conductive layers include at least one gate metal layer; a first source-drain metal layer and a second source-drain metal layer, the first source-drain metal layer and the second source-drain metal layer being both located on a side of the at least one gate metal layer away from the base, and the first source-drain metal layer being closer to the base than the second source-drain metal layer; Including, the first sub-fan-out line, the second sub-fan-out line, and the second plurality of fan-out lines are located in the at least one gate metal layer, the isolation portion is located in the first source-drain metal layer, and the transfer line is located in the second source-drain metal layer.

16. The display substrate according to claim 12,

17. The isolation unit includes at least one power supply signal line.

17. The display substrate according to claim 7,

18. the second fan-out region includes a first sub-fan-out region and a second sub-fan-out region, the first sub-fan-out region is closer to the bending region than the second sub-fan-out region, and the transfer line is located in the second sub-fan-out region; 7. The display substrate according to claim 5 or 6.

19. The transfer line is a first sub-transmission line electrically connected to the first sub-fan-out line and spanning at least one of the second fan-out lines; second sub-transfer lines electrically connected to ends of the first sub-transfer lines away from the first sub-fan-out lines, wherein an orthogonal projection of at least one of the second sub-transfer lines at the base is located between orthogonal projections of two adjacent second fan-out lines at the base; Including, 20. The display substrate according to claim 18.

20. a center line of the display substrate is located at a center of the display substrate along the first direction and is parallel to the base; the second sub-fan-out region includes two first regions, the two first regions being located on either side of the center line, at least one of the first regions includes a plurality of sub-regions, the plurality of sub-regions including a first sub-region, a second sub-region, and a third sub-region, the first sub-region, the second sub-region, and the third sub-region being sequentially arranged along a direction from an edge of the first region away from the center line to the center line; an end of the first sub-transfer line electrically connected to the first sub-fan-out line is located in at least one of the first sub-region, the second sub-region, and the third sub-region, and the second sub-transfer line is located in the first sub-region; 20. The display substrate according to claim 19.

21. ends of the first sub-transfer lines electrically connected to the first sub-fan-out line are located in different sub-regions of the first region; The display substrate according to claim 20 .

22. the ends of the first sub-transfer lines electrically connected to the first sub-fan-out lines are evenly distributed in the first sub-region, the second sub-region, and the third sub-region; 22. The display substrate according to claim 20 or 21.

23. an outer shape of a region in which orthogonal projections of all the first sub-transfer lines in the first region are located on the base is a trapezoid or a triangle; 23. The display substrate according to claim 20, wherein the display substrate is a substrate having a thickness of 100 nm or less.

24. the second sub-fan-out region includes a second region and a third region, the second region is closer to the first sub-fan-out region than the third region, and a length of an edge of the second region closer to the first sub-fan-out region is greater than a length of an edge of the second region away from the first sub-fan-out region; the first sub-transfer lines extend along the first direction, the second sub-transfer lines extend along the second direction, at least one of the first sub-transfer lines is located in the second region, and at least one of the second sub-transfer lines extends from the second region to the third region; The display substrate according to any one of claims 19 to 23.

25. a distance between at least two adjacent first sub-transmission lines gradually decreases along a direction from the first sub-fan-out region to the second sub-fan-out region; 20. The display substrate according to claim 19.

26. the first fan-out line further includes a second sub-fan-out line, the second sub-fan-out line being located in a different conductive layer than the transfer line, the second sub-fan-out line being located in the second sub-fan-out region and electrically connected to an end of the transfer line remote from the first sub-fan-out line; The display substrate according to any one of claims 19 to 25.

27. an orthogonal projection of the transfer line at a base thereof is U-shaped or approximately U-shaped with an opening toward a bend region, one end of the transfer line being electrically connected to a first sub-fan-out line, and the other end of the transfer line being electrically connected to a second sub-fan-out line; 27. The display substrate according to claim 26.

28. The plurality of conductive layers include at least one gate metal layer; a first source-drain metal layer and a second source-drain metal layer, the first source-drain metal layer and the second source-drain metal layer being both located on a side of the at least one gate metal layer away from the base, and the first source-drain metal layer being closer to the base than the second source-drain metal layer; Including, the first sub-fan-out line, the second sub-fan-out line, and the second plurality of fan-out lines are located in the at least one gate metal layer, and the transfer lines are alternately located in the first source-drain metal layer and the second source-drain metal layer.

28. The display substrate according to claim 26 or 27.

29. the at least one gate metal layer includes a first gate metal layer and a second gate metal layer, the first gate metal layer being closer to the base than the second gate metal layer; the first sub-fan-out lines, the second sub-fan-out lines, and the second fan-out lines are located in the first gate metal layer and the second gate metal layer; any two adjacent fan-out lines among the first sub-fan-out lines and the second sub-fan-out lines are located in different gate metal layers, and any two adjacent fan-out lines among the second sub-fan-out lines and the second sub-fan-out lines are located in different gate metal layers.

29. The display substrate according to claim 16 or 28.

30. the conductive layers include a light-shielding metal layer, at least one active layer, at least one source-drain metal layer, a plurality of gate metal layers, at least one transparent conductive layer, and an anode layer; the transfer line is located in at least one of the light shielding metal layer, the at least one active layer, the at least one source-drain metal layer, one gate metal layer of the plurality of gate metal layers, the at least one transparent conductor layer, and the anode layer, and the plurality of second fan-out lines are located in at least one of the plurality of gate metal layers. The display substrate according to any one of claims 12 to 15, 26 and 27.

31. A display device, comprising: A display substrate according to any one of claims 1 to 30, A display device comprising:

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