Multi-Level Pulsing System

Abstract

The synchronization module is configured to generate a synchronization signal for transmission to at least one of the generator and / or the at least one matching network, the synchronization signal being formed with pulses having varying durations, the durations of the pulses in the synchronization signal conveying information about events in the power waveform. One aspect of the disclosure is a generator comprising a power generation component configured to generate a power waveform for transmission to a secondary component and a synchronization component configured to generate a synchronization signal for transmission to the secondary component.

Description

[Technical field]

[0001] (Claim of priority under 35 U.S.C. § 119) This application for patent claims priority to non-provisional application No. 18 / 302,294, entitled "MULTI-LEVEL PULSING SYSTEM," filed April 18, 2023, which claims the benefit of priority to U.S. Provisional Application No. 63 / 332,139, entitled "Multi-level Pulsing System," filed April 18, 2022, which is incorporated herein by reference.

[0002] The present disclosure relates generally to electrical power supply systems and, in particular, but not by way of limitation, to the interoperation of electrical power system components. [Background technology]

[0003] Power delivery systems, including power supplies and matching networks, are used in a variety of contexts, including semiconductor processing. Semiconductor processing and other advanced material processing rely on increasingly sophisticated plasma processes. Such plasma processes, in turn, require increasingly sophisticated power and control systems to make the inherently unstable and nonlinear plasma more precise and consistent. Such plasmas are used for processes such as plasma etch processes, plasma-enhanced chemical vapor deposition (CEPVD) processes, plasma-enhanced atomic layer deposition (PEALD) processes, plasma-assisted atomic layer deposition (PA-ALD), RF sputtering deposition, and other plasma processing applications.

[0004] In some plasma processing recipes, it is desirable to apply a pulsed and / or multi-level power waveform having multiple states and / or levels, such as the exemplary pulsed waveform 50 of FIG. 1. The different states may exhibit, for example, but not limited to, different power levels and / or different frequencies. A waveform may include one or more cycles. In FIG. 1, the waveform 50 has a first cycle 60, a transition cycle 61, and a second cycle 62. Within each cycle, there may be one or more sequences of power states. In the power waveform 50 of FIG. 1, for example, the first pulse cycle 60 has six repeating sequences with three power states per sequence (states 1-3), and the second pulse cycle 62 has four repeating sequences with four power states per sequence (states 1-4).

[0005] Note that in power waveforms such as that shown in FIG. 1, a "sequence" having multiple power states is sometimes alternatively referred to as a multi-level "pulse", which is why waveforms such as that depicted in FIG. 1 are sometimes referred to as multi-level pulsed waveforms. Although not shown in FIG. 1, a power level of zero is also a state. However, as will become apparent below, the present disclosure also involves synchronization signals that are configured with pulses. To avoid confusion between the terminology, the following description uses the term "sequence" when referring to power waveforms and the term "pulse" when referring to synchronization signals.

[0006] The generator must support a power waveform, such as waveform 50, that has multiple states, with each state having independent control parameters such as power set point and frequency. The generator is generally used in conjunction with a matching network to optimize the delivery of the power waveform to the plasma processing chamber. The matching network is typically coupled between the generator and the plasma processing chamber and adjusts its impedance as necessary to reduce reflected power. It is important that the matching network be synchronized to any changes in the power signal, such as state changes that occur in a pulsed waveform that has multiple cycles of multiple sequences with multiple states.

[0007] Process results can be degraded if system components (such as the generator and matching network) are not coordinated and synchronized. The regulation point can be characterized as the frequency at which the input impedance of the matching network matches the output impedance of the generator. If not coordinated and synchronized, the matching network can oscillate between optimal regulation points for different states. The current matching functionality only supports single-wire signals to support two pulse states. Process results can be degraded in multi-level pulsed systems if the impedance is regulated to only one state. Also, the matching network in a typical system is not capable of reporting information on a state-by-state basis because the matching network typically does not know when each state begins and stops. Summary of the Invention [Means for solving the problem]

[0008] One aspect of the disclosure is a generator including a power generation component configured to generate a power waveform for transmission to a secondary component, and a synchronization component configured to generate a synchronization signal for transmission to the secondary component, the synchronization signal being formed with pulses having varying durations, the durations of the pulses in the synchronization signal conveying information about events in the power waveform to the secondary component.

[0009] In one implementation, the secondary component is a matching network interposed between the generator and the plasma processing chamber.

[0010] In another implementation, the duration of a pulse in the synchronization signal conveys information about a change in state of the power waveform.

[0011] In a further implementation, a first pulse of a first duration in the synchronization signal indicates that a state is ending and that the next state in the same sequence of the same cycle of the power waveform is beginning.

[0012] In a further implementation, a second pulse of a second duration in the synchronization signal indicates that the last state of a particular repeating sequence is ending and that a first state in the same particular repeating sequence of the same cycle of the power waveform is beginning.

[0013] In a further implementation, a third pulse of a third duration indicates that the state is ending and that the next state in the first sequence of the next cycle of the power waveform is beginning.

[0014] In a further implementation, a threshold time of inactivity after the pulse is initiated signals that the power is off.

[0015] Another aspect of the disclosure is a matching network having an input configured to receive a power waveform from a primary component and a synchronization component configured to receive a synchronization signal from the primary component, the synchronization signal being formed with pulses having varying durations, the durations of the pulses in the synchronization signal conveying information about events in the power waveform to the matching network.

[0016] A further aspect of the present disclosure is a plasma processing system comprising at least one matching network and at least one generator. The generator is configured to generate and transmit a power waveform to the matching network. The system also comprises a synchronization component configured to generate a synchronization signal for transmission to the generator and / or the matching network. The synchronization signal is formed with pulses having varying durations, and the durations of the pulses in the synchronization signal convey information about events in the power waveform to the matching network.

[0017] Further aspects of the present disclosure will be described in, and will be apparent from, the accompanying drawings and description. [Brief description of the drawings]

[0018] [Figure 1] FIG. 1 is a conceptual diagram of an exemplary multi-level pulsed power waveform in accordance with the present disclosure.

[0019] [Figure 2A] FIG. 2A is a block diagram of an exemplary plasma processing system according to the present disclosure.

[0020] [Figure 2B] FIG. 2B is a block diagram of another exemplary plasma processing system according to the present disclosure.

[0021] [Diagram 3] FIG. 3 is a timing diagram illustrating synchronization signals for various states of a multi-level power waveform in accordance with the present disclosure.

[0022] [Figure 4] FIG. 4 is a first segment of a timing diagram showing three synchronization signals for various states of three multi-level pulsed power waveforms in accordance with the present disclosure.

[0023] [Diagram 5]FIG. 5 is a second segment of a timing diagram showing three synchronization signals for various states of three multi-level pulsed power waveforms in accordance with the present disclosure.

[0024] [Figure 6] FIG. 6 is a third segment of a timing diagram showing three synchronization signals for various states of three multi-level pulsed power waveforms in accordance with the present disclosure.

[0025] [Figure 7] FIG. 7 is a conceptual block diagram depicting a computing system that may be utilized in connection with embodiments disclosed herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] Detailed Description

[0027] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not to be construed as preferred or advantageous over other embodiments.

[0028] Preliminary Note: The flowcharts and block diagrams in the following drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, some blocks in the flowcharts and block diagrams may represent modules, segments, or portions of code comprising one or more executable instructions for implementing a specified logical function. In some implementations, the functions described in the blocks may be performed out of the order described in the drawings. For example, depending on the functionality involved, two blocks shown in succession may in fact be executed substantially in parallel or in the reverse order. It should also be understood that each block and combination of blocks in the flowcharts and block diagrams may be implemented by a special-purpose hardware-based system that performs the specified functions or acts, or a combination of special-purpose hardware and computer instructions.

[0029] While the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or sections, it should be understood that these elements, components, regions, layers, and / or sections are not limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another region, layer, or section. Thus, a first element, component, region, layer, or section discussed below could be referred to as a second element, component, region, layer, or section without departing from the teachings of the present disclosure.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used herein, the terms "comprises" and / or "comprising" specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes all combinations of one or more of the associated listed items and may be abbreviated as " / ".

[0031] 2A is a block diagram of an example plasma processing system 100 with components including a generator 102 for providing various types of power waveforms to a nonlinear and / or chaotic plasma load 104 based on an input 106, which may arrive from a human, another controller, or from another control construct within the system 100A. The type of power waveform generated by the generator 102 may include a multi-level waveform, such as waveform 50 of FIG. 1, with the power level of each state being defined by the input 106. It should be appreciated that the states depicted in FIG. 1 may be power levels, and that in each state the generator 102 may apply many cycles of an RF voltage (e.g., a sinusoidal voltage) at frequencies, for example, but not limited to, 13.56 MHz and 60 MHz. For clarity, a high frequency voltage waveform is not depicted. Also, it should be appreciated that while power is used as an example attribute throughout this disclosure, each state may be defined by other attributes as well.

[0032] Other components depicted in Figure 2A include matching network 116, RF source 118, bias supply 120, and power supply 122 coupled to bias supply 120. The high level components of Figure 2A may include lower level components (subcomponents of higher level components), such as, for example, but not limited to, DC rail supplies, RF amplifiers, variable capacitors, and direct current (DC) power supplies within bias supply 120. In general, Figure 2A depicts a multi-component and multi-control knob nonlinear system, and aspects of the disclosure detailed further herein relate to control of multi-actuator and multi-control knob systems.

[0033] As shown, the unified controller 101 comprises an interface for receiving and processing the input signal 106, and a control section 112 for providing one or more control signals based on the input signal 106. As shown, the control section 112 includes a primary synchronization module ("sync") 124 that is coupled to a synchronization line 302, which may be coupled to components within the system 100A and provide synchronization signals, as described further herein. In some embodiments, at the physical layer, the synchronization line 302 may be a single wired connection, although this is not required.

[0034] According to one aspect of the present disclosure, the synchronization signals disclosed herein convey information that allows components of the system 100A to rapidly respond to changing events within the system 100A. For example, the synchronization signals disclosed herein may convey information about events occurring within the power waveform applied by the generator 102. More specifically, the synchronization signals applied to the synchronization lines may be formed with pulses having varying durations, the duration of the pulses conveying information about events such as, but not limited to, a change of state within a sequence, the completion of a sequence and the start of a new state in the next sequence, or the completion of a cycle and the start of a new state in the next cycle.

[0035] The primary synchronization module 124 may be implemented within the centralized controller 101 as shown in Figure 2A, but it may also be implemented in one or more other components. For example, Figure 2B depicts system 100B, which is a variation of system 100A in which the generator 102 includes the primary synchronization module 124. As shown, Figure 2B includes additional details of subcomponents that may be implemented within the generator 102. For example, the generator 102 includes a user interface 108, an optional master control unit (MCU) 110, a control section 112 (e.g., an FPGA, a CPU, or a combination of FPGA and CPU), and power generation components and sensors 114.

[0036] As shown, the control section 112 of the generator 102 includes a primary synchronization module ("sync") 124 coupled to a secondary synchronization module ("sync") 126 of the matching network 116 via a synchronization line 302, which propagates and provides a synchronization signal to the matching network 116. Coordination between the matching network 116 and the generator 102 is thereby enabled to prevent or mitigate oscillations of the matching network 116 between optimal tuning points for the power conditions applied to the plasma load 104. Also, in some implementations, the synchronization signal may enable the impedance of the matching network 116 to be changed in a state-by-state manner, thereby enabling the impedance of the matching network 116 to be separately tuned during multiple states, allowing increasingly faster embodiments of the matching network 116 to be realized. In this regard, some embodiments of the matching network 116 may be realized with solid-state switching components that may be switched very quickly to enable the impedance of the matching network 116 to be changed very quickly in a pulse-by-pulse manner utilizing the synchronization signal 302. However, the matching network 116 may be implemented using a variable vacuum capacitor in some embodiments.

[0037] According to one aspect of the disclosure, the synchronization signal conveys information about the power waveform generated by the generator 102 to the matching network 116. In particular, the synchronization signal conveys information about events occurring within the power waveform. More specifically, the synchronization signal may be formed with pulses having varying widths or durations, where the widths or durations of the pulses convey information about events such as a change of state within a sequence, the completion of a sequence and the start of a new state in the next sequence, or the completion of a cycle and the start of a new state in the next cycle.

[0038] It should be appreciated that FIGS. 2A and 2B are examples only, and that primary synchronization module 124 may be instantiated within the enclosure of any of the components depicted in FIGS. 2A and 2B.

[0039] 3 is a timing diagram 300 showing an example synchronization signal "psync" configured to synchronize a matching network 116 to various states 304 (designated as "psyncState" in FIG. 3) of a multi-level pulsed power waveform in accordance with the present disclosure. The timing diagram 300 illustrates a single synchronization signal 302 that runs from time 0 μs (the beginning of the top segment 300a) to time 760 μs (the end of the bottom segment 300d). Due to drawing and font size limitations, the timing diagram 300 is divided into four segments 300a-300d. The right side of the top segment 300a is continuous with the left side of the second segment 300b (at around 160 μs), the right side of the second segment 300b is continuous with the left side of the third segment 300c (at around 380 μs), and the right side of the third segment 300c is continuous with the left side of the bottom segment 300d (at around 640 μs).

[0040] The power waveform represented by state 304 ("psyncState") of FIG. 3 has a first cycle w0 and a second cycle w1. The first cycle w0 has three sequences, each with four states, namely w0_0, w0_1, w0_2, and w0_3. The second cycle w1 has two sequences, each with two states, namely w1_0 and w1_1. Following the first cycle w0, there is a transition state t0. The durations of the four states of the sequences of the first cycle w0 are 35 μs (w0_0), 40 μs (w0_1), 30 μs (w0_2), and 25 μs (w0_3). The durations of the two states of the sequences of the second cycle w1 are 25 μs (w1_0) and 45 μs (w1_1). Transition state t0 is essentially a transition cycle having a single state t0_0 with a duration of 50 μs. In the power waveform represented by states 304 in Figure 3, the number of cycles, the number of sequences per cycle, the number of states per sequence, and the duration of the states are arbitrary and represent only one non-limiting example of many possible waveform configurations.

[0041] The synchronization signal 302 ("psync") generally has two levels: a first level that indicates that the power waveform is active or on, and a second level that conveys information about an event occurring within the power waveform. The first level is generally shown for non-limiting purposes in FIG. 3 as a "high" level, and the second level is generally shown for non-limiting purposes in FIG. 3 as a "low" level. The second level of the synchronization signal 302 is configured into short pulses of varying width or duration that communicate information about an event (state change) within the power waveform based on the width or duration of the pulse.

[0042] The synchronization signal 302 of FIG. 3 includes two types of pulses for communicating state change information. The first pulse S1 has a first duration and communicates that a state is ending and that a new state in a repeating sequence of the same cycle is about to begin. The second pulse S2 has a second duration and communicates that a state is ending and that a new state in a new cycle is about to begin. In FIG. 3, for non-limiting purposes of illustration only, the first duration of the first pulse S1 is 5 μs and the second duration of the second pulse S2 is 10 μs. These pulse durations are arbitrary and can have many other values ​​as long as they are different from each other. Thus, the first pulse S1 of the synchronization signal 302 indicates to the receiver (here, the matching network 116) that it should advance to the next state in the repeating sequence of the same cycle, while the second pulse S2 indicates to the receiver that it should advance to the next state in the next new cycle. In some implementations, each event is defined with a duration that has a tolerance. For example, but not limited to, the tolerance may be + / - 1 microsecond.

[0043] As explained above, the first cycle w0 of the waveform has three sequences, each sequence having four states, namely w0_0, w0_1, w0_2, and w0_3. Thus, the synchronization signal 302 uses pulse S1 to communicate each upcoming state change in the first cycle w0, except for the last state change (the third occurrence of w0_3), thereby communicating to the matching network 116 that a change to a new state in the same cycle of the repeating sequence is approaching. Near the end of the last state in the first cycle w0 (the third occurrence of w0_3), the synchronization signal 302 uses pulse S2 to communicate an upcoming state change to transition state t0_0, thereby communicating to the matching network 116 that a change to a new state in a new cycle is approaching.

[0044] Transition state t0_0 is a cycle having a single state, so near the end of transition state t0_0, synchronization signal 302 uses pulse S2 to communicate another upcoming state change for second cycle w1, thereby communicating that a change to a new state in the new cycle is approaching. Second cycle w1 has two sequences, each sequence having two states, i.e., w1_0 and w1_1. Thus, synchronization signal 302 uses pulse S1 to communicate each upcoming state change in second cycle w1, except for the last state change (the second occurrence of w1_1), thereby communicating that a change to a new state in the same cycle of the repeating sequence is approaching. Near the end of the last state in the second cycle w1 (the second occurrence of w1_1), the synchronization signal 302 communicates the impending state change back to the first cycle w0 (in this example, the no-transition state) using pulse S2, thereby communicating to the matching network 116 that a change to a new state in a new cycle is approaching. The first cycle w0 again then begins with the state change in the first cycle w0 indicated by pulse S1.

[0045] FIG. 3 depicts a synchronization signal utilizing two pulses S1 and S2 with different widths or durations to communicate two types of events within a multi-level power waveform, where pulse S1 of one duration communicates a change to a new state within the same cycle of a repeating sequence, and pulse S2 of another duration communicates a change to a new state within a new cycle. Additional types of pulses with different durations may be used to communicate additional events other than these two types. A third pulse with a third duration may be used to indicate that the last state of a particular repeating sequence within a cycle is completing and that a first state of the same particular repeating sequence within the same cycle is approaching. A fourth pulse with a fourth duration may be used to communicate that a state is ending and that the receiver should go back one step. This may be used to support a "pulse within a pulse" functionality, where there is some repetition of a state before the cycle transitions to a new state. For example, in the state sequence w0_0, w0_1, w0_0, w0_1, w0_0, w0_1, w0_2, w0_3, there are four states, but the first two states are repeated three times before continuing to the third and fourth states. Also, when the synchronization signal is at a second or low level above a predefined threshold for a period of time, off is detected, i.e., no power waveform is being generated. This is shown in FIG. 3 between 0 μs and 50 μs for the synchronization signal 302. This mode of operation is useful to keep the system in a safe state when there is a problem with the synchronization signal.

[0046] 2 and 3 illustrate an embodiment in which the primary synchronization module 124 of the generator 102 produces a single synchronization signal 302 that is provided to the secondary synchronization module 126 of the matching network 116. However, in other embodiments, it may be desirable for the primary synchronization module to produce multiple synchronization signals that can be used to synchronize multiple secondary components. Such an embodiment is depicted in the timing diagrams of FIGS. 4-6. Due to drawing and font size limitations, the timing diagrams of FIGS. 4-6 are divided into three segments: a first segment 400a (FIG. 4) from 0 μs to about 600 μs, a second segment 400b (FIG. 5) from about 600 μs to about 1,200 μs, and a third segment 400c (FIG. 6) from about 1,200 μs to 1,800 μs. Thus, the right side of the first segment 400a is contiguous with the left side of the second segment 400b, and the right side of the second segment 400b is contiguous with the left side of the third segment 400c.

[0047] The first synchronization signal 402 is configured to synchronize a first component (e.g., a matching network or another generator) to a first power waveform, represented by state 404 ("PSync_1"). The second synchronization signal 412 is configured to synchronize a second component (e.g., a matching network or another generator) to a second power waveform, represented by state 414 ("PSync_2"). The third synchronization signal 422 is configured to synchronize a third component (e.g., a matching network or another generator) to a third power waveform, represented by state 424 ("PSync_3"). Although the frequencies of the first, second, and third waveforms may vary in some use cases, the frequencies of these waveforms are radio frequency (RF) frequencies (e.g., but not limited to, 13.56 MHz).

[0048] The power waveforms represented by states 404, 414, 424 in Figures 4-6 each have two cycles. The first cycle starts at 0 μs and ends at 1,200 μs (Figures 4 and 5), and the second cycle starts at 1,200 μs and ends at 1,800 μs (Figure 6). The first cycle has two repeating sequences, a first repeating sequence that starts at 0 μs and ends at 600 μs (Figure 4) and a second repeating sequence that starts at 600 μs and ends at 1,200 μs (Figure 5). The second cycle has one sequence that starts at 1,200 μs and ends at 1,800 μs (Figure 6).

[0049] A first power waveform represented by state 404 ("PSync_1") has one state P1 (FIGS. 4 and 5) in its first cycle repeat sequence and six states P1-P6 (FIG. 6) in its second cycle sequence. A second power waveform represented by state 414 ("PSync_2") has six states P1-P6 (FIGS. 4 and 5) in its first cycle repeat sequence and one state P1 (FIG. 6) in its second cycle sequence. A third power waveform represented by state 424 ("PSync_3") has three states P1-P3 (FIGS. 4 and 5) in its first cycle repeat sequence and three states P1-P3 (FIG. 6) in its second cycle sequence.

[0050] In a manner similar to that described with reference to Figure 3, the synchronization signals 402, 412, 422 of Figures 4-6 generally have two levels: a first level indicating that a power waveform is present, and a second level conveying information about an event occurring within the power waveform. The first level is generally indicated as a "high" level, and the second level is generally indicated as a "low" level. The second level comprises a short pulse of varying width or duration that communicates information about an event (state change) within the power waveform based on the width or duration of the pulse.

[0051] The synchronization signals 402, 412, 422 in Fig. 4-6 include four exemplary types of short pulses for communicating state change information. The first pulse S11 has a first duration and communicates that a state is ending and a new state in the same sequence is about to begin. The second pulse S12 has a second duration and communicates that a state is ending and a new state in a new cycle sequence is about to begin. In Fig. 5, the transition communicated by the second pulse S12 is also referred to as "next sequence". The third pulse S13 indicates that a state is ending and a new state in the next repeating sequence of the same cycle is about to begin. In Fig. 4, the transition communicated by the third pulse S13 is also referred to as "rollover". The fourth pulse S14 indicates that the power waveform is turned off. 4-6, for illustrative and non-limiting purposes only, the first duration of the first pulse S11 is 4 μs, the second duration of the second pulse S12 is 6 μs, the third duration of the third pulse S13 is 8 μs, and the fourth duration of the fourth pulse S14 is 10 μs. These pulse durations are arbitrary and may have many other values ​​as long as they are different from one another.

[0052] As noted above, each of the three waveforms depicted by states 404, 414, and 424, respectively, has a first cycle including two repeating sequences, with a first repeating sequence shown in FIG. 4 and a second repeating sequence shown in FIG. 5, and a second cycle having one sequence as shown in FIG. 6.

[0053] 4, the first waveform represented by state 404 has only one state P1 in the repeating sequence of the first cycle. Thus, the first synchronization signal 402 uses a pulse S13 at the end of state P1 to communicate that the state is ending and that a new state in the next repeating sequence of the same cycle is about to begin. The second waveform represented by state 414 has six states P1-P6 in the repeating sequence of the first cycle. Thus, the second synchronization signal 412 uses a pulse S11 at the end of states P1-P5 to communicate that the state is ending and that a new state in the same sequence is approaching, and a pulse S13 at the end of state P6 to communicate that the state is ending and that a new state in the next repeating sequence of the same cycle is about to begin. The third waveform represented by state 424 has three states P1-P3 in the repeating sequence of the first cycle. Thus, the second synchronization signal 412 uses pulses S11 at the end of states P1 and P2 to communicate that a state is ending and that a new state in the same sequence is approaching, and pulses S13 at the end of state P3 to communicate that a state is ending and that a new state in the next repeating sequence of the same cycle is beginning.

[0054] Referring to Figure 5, the three waveforms repeat the same sequence as in Figure 4, but at the end of the repeated sequence a new cycle begins, which is communicated by the use of pulse S12 in the synchronization signal. Thus, the first synchronization signal 402 uses pulse S12 at the end of state P1 to communicate that the state is ending and that a new state in the first sequence of the next cycle is about to begin. The second synchronization signal 412 uses pulse S11 at the end of states P1-P5 to communicate that the state is ending and that a new state in the same sequence is approaching, and pulse S12 at the end of state P6 to communicate that the state is ending and that a new state in the first sequence of the next cycle is about to begin. The third synchronization signal 422 uses a pulse S11 at the end of states P1 and P2 to communicate that the state is ending and that a new state in the same sequence is approaching, and a pulse S12 at the end of state P3 to communicate that the state is ending and that a new state in the first sequence of the next cycle is about to begin.

[0055] Referring to FIG. 6, the three waveforms begin a second (new) cycle. In the second cycle, each waveform has one sequence. The first waveform, represented by state 404, has six states P1-P6 in its sequence, the second waveform, represented by state 414, has one state P1 in its sequence, and the third waveform, represented by state 424, has three states P1-P3 in its sequence. At the end of the second cycle shown in FIG. 6, the power waveform is terminated or turned off, which is indicated in the synchronization signal by pulse S14. Thus, the synchronization signal 402 includes a pulse S11 at the end of states P1-P5 and a pulse S14 at the end of state P6, the synchronization pulse 412 includes a pulse S14 at the end of its only state P1, and the synchronization pulse 422 includes a pulse S11 at the end of states P1 and P2 and a pulse S14 at the end of state P3.

[0056] If some state changes occur on a secondary component (e.g., matching network 116) that receives a synchronization signal for a sequence that is active, that number of states may be latched and then applied later when the sequence is completed (this helps avoid issues with sequences such as when a primary component (e.g., synchronization module 124 of generator 102) is commanded to toggle a waveform, but there is a delay for the actual toggling for the in-process waveform to be completed).

[0057] The secondary synchronization component (e.g., matching network 116) can detect loss of synchronization, and if the primary synchronization component (e.g., generator 102) is constrained not to change duration during startup, the secondary component can detect if the same state is received with a different duration. In addition, the secondary component can detect if a terminating pulse was not received during the last state of the sequence (e.g., pulses S2, S12). For states that are indefinite, there is a predetermined delay (in one embodiment, 10 μs) from the exit stimulus until the state changes. Also, if a waveform switch request is received within a predetermined time (in one embodiment, 10 μs) of the end of the last state, the request will be delayed until the next iteration of the sequence is completed.

[0058] The methods described in connection with the embodiments disclosed herein may be embodied directly in hardware, in processor executable code encoded in a non-transitory tangible processor-readable storage medium, or in a combination of the two. With reference to Figure 7, for example, shown is a block diagram 4200 depicting physical components that may be utilized to realize the primary synchronization module 124 and / or the secondary synchronization module 126 of the matching network 116. More specifically, the collection of components depicted in Figure 7 may be instantiated in the generator 102 and / or the matching network 116.

[0059] As shown, non-volatile memory 4220 is coupled to bus 4222, which is also coupled to random access memory ("RAM") 4224, processing portion 4226, including N processing components, field programmable gate array (FPGA) 4227, and transceiver component 4228, including N transceivers. None of these components are required, and any combination of these may be included in the systems disclosed herein. For example, if FPGA 4227 is implemented, processing portion 4226 may not be used, and vice versa. Although the components depicted in FIG. 7 represent physical components, FIG. 7 is not intended to be a detailed hardware diagram, and thus many of the components depicted in FIG. 7 may be realized by a common construct or distributed among additional physical components. It is also envisioned that other existing and yet to be developed physical components and architectures may be utilized to implement the functional components described with reference to FIG. 7.

[0060] In general, the non-volatile memory 4220 is a non-transient memory that functions to store (e.g., persistently store) data and processor executable code (including executable code associated with effecting the methods described herein). In some embodiments, the non-volatile memory 4220 includes boot loader code, operating system code, file system code, and non-transient processor executable code to facilitate execution of methods for coordinating the operation of the generator 102 and the matching network 116 as described herein.

[0061] In many implementations, the non-volatile memory 4220 is realized by a flash memory (e.g., NAND or ONENAND memory), although it is envisioned that other memory types may be utilized as well. While it may be possible to execute code from the non-volatile memory 4220, executable code in the non-volatile memory is typically loaded into RAM 4224 and executed by one or more of the N processing components in the processing portion 4226.

[0062] The N processing components associated with the RAM 4224 generally operate to execute instructions stored in the non-volatile memory 4220 and enable methods for coordinating the operation of the generator 102 and the matching network 116. For example, non-transient processor executable code for effecting the methods described herein may be persistently stored in the non-volatile memory 4220 and executed by the N processing components associated with the RAM 4224. As one skilled in the art would appreciate, the processing portion 4226 may include a video processor, a digital signal processor (DSP), a microcontroller, a graphics processing unit (GPU), or other hardware processing component, or a combination of hardware and software processing components (e.g., an FPGA or an FPGA including a digital logic processing portion).

[0063] Generally, the input component 4230 operates to receive signals, such as the synchronization signal 302, that correspond to the multi-level pulsed power waveform applied by the generator 102. The signals received at the input component 4230 may include the signals depicted in Figures 3-6, which may be, for example, digital or analog signals. The output component generally operates to provide one or more analog or digital signals that correspond to the signals depicted in Figures 3-6.

[0064] The transceiver component 4228 includes N transceiver chains that can be used to communicate with external devices over wireless or wired networks. Each of the N transceiver chains can represent a transceiver associated with a particular communication scheme (e.g., WiFi, Ethernet, Profibus, etc.).

[0065] Some portions are presented in terms of algorithms or symbolic representations of operations on data bits or binary digital signals stored within a computing system memory, such as a computer memory. These algorithmic descriptions or representations are examples of techniques used by those skilled in the data processing arts to convey the substance of their work to others skilled in the art. An algorithm is a self-consistent sequence of operations or similar processes leading to a desired result. In this context, operations or processes involve physical manipulations of physical quantities. Typically, though not necessarily, such quantities may take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, or otherwise manipulated. It has proven convenient at times, primarily for reasons of common usage, to refer to such signals as bits, data, values, elements, symbols, characters, terms, numbers, numeric values, or the like. It should be understood, however, that all of these similar terms are to be associated with the appropriate physical quantities and are merely convenient labels. Unless specifically stated otherwise, throughout this specification, discussions utilizing terms such as "processing," "computing," "calculating," "determining," and "identifying," or the like, will be understood to refer to the actions or processes of a computing device, such as one or more computers or similar electronic computing devices or devices, that manipulate or transform data represented as physical electronic or magnetic quantities in the memory, registers, or other information storage, transmission, or display devices of a computing platform.

[0066] As will be appreciated by one of ordinary skill in the art, aspects of the present invention may be embodied as a system, method, or computer program product. Thus, aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects, all of which may be generally referred to herein as a "circuit," "module," or "system." Furthermore, aspects of the present invention may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon.

[0067] As used herein, the recitation of "at least one of A, B, and C" or "at least one of A, B, or C" is intended to mean "any of A, B, C, or any combination of A, B, and C." This description is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the scope of the disclosure is not limited to the embodiments shown herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0068] The present disclosure is provided to enable any person skilled in the art to make or use the embodiments described herein. Various modifications will be readily apparent to those skilled in the art, and the principles disclosed herein may be applied to other embodiments without departing from the spirit or scope of the present disclosure. Although certain embodiments are described herein, these embodiments are presented by way of example only and are not intended to limit the scope of the present disclosure.

Claims

1. A generator comprising: a power generation component configured to generate a power waveform for transmission to a secondary component; a synchronization component configured to generate a synchronization signal for transmission to the secondary component, the synchronization signal being formed with pulses having varying durations, the durations of the pulses in the synchronization signal conveying information about events in the power waveform to the secondary component; A generator comprising:

2. The generator of claim 1 , wherein the secondary component is a matching network.

3. The generator of claim 1 , wherein the duration of the pulses in the synchronization signal conveys information about a change in state of the power waveform.

4. 4. The generator of claim 3, wherein a first pulse of a first duration in the synchronization signal indicates that the state is ending and that a next state in the same sequence of the same cycle of the power waveform is beginning.

5. 5. The generator of claim 4, wherein a second pulse of a second duration in the synchronization signal indicates that a last state of a particular repeating sequence is ending and a first state of the same particular repeating sequence of the same cycle of the power waveform is beginning.

6. 6. The generator of claim 5, wherein a third pulse of a third duration indicates that the state is ending and that the next state in a first sequence of a next cycle of the power waveform is beginning.

7. The generator of claim 1 , wherein a threshold time of inactivity after a pulse is initiated signals that the power is off.

8. A matching network comprising: an input configured to receive a power waveform from the primary component via a first signal path for transmission to the plasma processing device; a synchronization component configured to receive a synchronization signal from the primary component via a second signal path, the synchronization signal being formed with pulses having varying durations, the durations of the pulses in the synchronization signal conveying information about events in the power waveform to the matching network; A matching network comprising:

9. The matching network of claim 8 , wherein the primary component is a generator.

10. The matching network of claim 8 , wherein the duration of the pulses in the synchronization signal conveys information about a change in state of the power waveform.

11. 11. The matching network of claim 10, wherein a first pulse of a first duration in the synchronization signal indicates that the state is ending and that a next state in the same sequence of the same cycle of the power waveform is beginning.

12. 12. The matching network of claim 11, wherein a second pulse of a second duration in the synchronization signal indicates that a last state of a particular repeating sequence is ending and a first state of the same particular repeating sequence of the same cycle of the power waveform is beginning.

13. 13. The matching network of claim 12, wherein a third pulse of a third duration indicates that the state is ending and that the next state in a first sequence of a next cycle of the power waveform is beginning.

14. 9. The matching network of claim 8, wherein a threshold time of inactivity after a pulse is initiated signals that the power is off.

15. 1. An electric power system comprising: at least one generator; at least one matching network, the generator configured to provide a power waveform to the matching network; a primary synchronization module configured to generate a synchronization signal for transmission to at least one of the generator and / or the at least one matching network, the synchronization signal being formed with pulses having varying durations, the durations of the pulses in the synchronization signal conveying information about events in the power waveform; A power system comprising:

16. The power system of claim 15 , wherein the duration of the pulses in the synchronization signal conveys information about a change in state of the power waveform.

17. 17. The power system of claim 16, wherein a first pulse of a first duration in the synchronization signal indicates that the state is ending and that a next state in the same sequence of the same cycle of the power waveform is beginning.

18. The power system of claim 15 , wherein the at least one generator includes the primary synchronization module.

19. The power system of claim 15 , wherein the at least one matching network includes the primary synchronizing module.

20. The power system of claim 15 , wherein a unified controller includes the primary synchronizing module.

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