Improved global flag for synchronizing coprocessors within a processing system

Abstract

A system and method for an improved global flag for synchronizing coprocessors. An exemplary processor system includes a plurality of coprocessors configured to compute processing tasks, each coprocessor connected to each remaining coprocessor via a plurality of connections, each connection from a coprocessor to a different coprocessor configured to be asserted or deasserted to indicate a status associated with a global flag of the plurality of global flags, the global flag being set based on the plurality of coprocessors asserting the global flag.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Patent Application No. 63 / 336,718, filed April 29, 2022, entitled “ENHANCED GLOBAL FLAGS FOR SYNCHRONIZING COPROCESSORS IN PROCESSING SYSTEM,” the disclosure of which is incorporated by reference in its entirety herein.

[0002] The present disclosure relates to synchronizing processors, and more particularly, to using a global flag to synchronize processors. [Background technology]

[0003] Machine learning models such as neural networks are increasingly being relied upon as the basis for modern software and hardware innovations. Indeed, neural networks may be used for image analysis and classification techniques for recommendation engines that are utilized to improve end-user content consumption. Certain innovations may rely on the vast computational power provided by remote cloud systems. For example, machine learning processing may be offloaded to remote cloud systems so that end-user devices do not need complex neural network processors. These remote cloud systems may include dedicated neural processors that are capable of quickly running forward passes through complex deep learning models.

[0004] However, other innovations can benefit from being executed on the end user device. For example, an autonomous vehicle may include a dedicated graphics processor or neural processor that can process complex deep learning models using locally acquired sensor data (e.g., images). As another example, a user's smartphone may include a graphics processor or neural processor for locally executing image classification techniques. In this example, the smartphone may associate people detected in images captured by the smartphone with specific people.

[0005] As reliance on special-purpose processors increases, there is a need to improve the operation and design of these processors to increase the speed at which machine learning models can be computed. [Brief description of the drawings]

[0006] [Figure 1A] 1 is a block diagram illustrating an exemplary processor system including multiple coprocessors and using global flags.

[0007] [Figure 1B] FIG. 2 is a block diagram illustrating a coprocessor in communication with an operating system.

[0008] [Figure 2A] FIG. 11 is a block diagram illustrating a shared mask that can be used to select a subset of coprocessors using a global flag.

[0009] [Figure 2B] FIG. 13 is a block diagram illustrating an example of a shared mask for selecting a subset of coprocessors using a global flag.

[0010] [Diagram 3] 5 is a flowchart of an example process for using a global flag by an example processor system.

[0011] [Figure 4] 1 is a block diagram illustrating an example vehicle including a processor system.

[0012] The embodiments of the present disclosure and their advantages are best understood by referring to the following detailed description: Like reference numerals have been used to identify like elements shown in one or more of the figures, and it should be understood that the indications therein are for the purpose of illustrating the embodiments of the present disclosure and are not intended to limit the disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] This application describes techniques for synchronizing processors, such as coprocessors included in a processing system. The coprocessor may be, by way of example, a neural processing unit capable of rapidly performing operations associated with processing a neural network (e.g., calculating a forward pass). As described below, one or more inter-coprocessor flags (e.g., global flags) may be used to synchronize, at least in part, the tasks being performed by the coprocessors. These flags may advantageously be asynchronous to reduce the degree to which complexity, such as hardware or software complexity, is required to enable such synchronization of the coprocessors.

[0014] The embodiments of the processing system described herein include multiple coprocessors for performing specialized processing, such as processing related to machine learning models (e.g., neural networks). Thus, one or more central processing units can at least partially offload processing related to neural networks to these coprocessors. In some embodiments, there may be three coprocessors. In some embodiments, there may be two, five, eight, etc. coprocessors.

[0015] As can be appreciated, neural network processing can require fairly large amounts of data and computer models. For example, with respect to an autonomous vehicle example, the coprocessor may receive sensor data from a number of cameras or sensors located around the vehicle. In this example, the sensor data may be received at a particular frequency (e.g., 30 Hz, 60 Hz, etc.) and may be combined or otherwise aggregated for processing. With respect to a convolutional neural network, a volume of filters may be convolved with this received sensor data.

[0016] Due to the size of the data involved and / or the complexity associated with processing the data at a particular frequency, the coprocessors may be assigned a portion of the processing task (e.g., a computational problem). For example, a first coprocessor may receive a portion of the data. Thus, in this example, the first coprocessor may determine a processing result associated with that portion. Similarly, the other coprocessor may determine a processing result associated with the remaining portion. These portions may then be aggregated or otherwise combined to determine a final processing result associated with the processing task. As another example, the first coprocessor may determine a processing result, and the second and third coprocessors may utilize the processing result in their own processing. Thus, the second and third coprocessors may require a technique to receive information indicating completion of the processing result.

[0017] A first exemplary approach for synchronizing coprocessors, such as synchronizing processing tasks as described above, may rely on software synchronization techniques. For example, software synchronization may be used with interrupts to a controlling central processing unit (CPU). However, this first exemplary approach is cumbersome, especially if the controlling CPU is running a full operating system rather than a microkernel. For example, interrupt latency may slow down communication of dependencies between coprocessors.

[0018] The present application describes the use of a global flag while limiting the extent to which additional hardware and / or software complexity is required to ensure proper synchronization of the coprocessors. Each coprocessor may be connected to the remaining coprocessors, for example, via asynchronous connections or wires. In some embodiments, this may be referred to as an all-to-all connection between the coprocessors. As described below, there may be multiple connections (e.g., "N" connections) between each processor and each of the remaining processors. For the example of N connections, there may be N flags that can be set by the coprocessors.

[0019] As an example, with respect to the first flag, each coprocessor may assert the first flag. The coprocessors may be working on a problem that is too large for a single coprocessor to address. Thus, due to interdependencies between data or operations, these coprocessors may have to complete their respective portions of the computation related to the problem. In some embodiments, asserting the first flag may indicate that the coprocessors have completed their respective portions of the computation. For example, asserting the first flag may indicate completion of an intermediate result by the coprocessor. The first flag may then be cleared (e.g., deasserted) to indicate that another actor (e.g., another coprocessor, a central processing unit) has successfully received (e.g., copied out) the intermediate result.

[0020] In some embodiments, asserting the first flag may indicate that the coprocessor has begun work on a respective portion of the computation. Upon completion, the coprocessor may then deassert the first flag.

[0021] With respect to asserting the first flag described above, each coprocessor may asynchronously assert the first flag. As described above, the coprocessors may be connected to each other such that each coprocessor receives asserted first flags from all remaining coprocessors. An assertion by a coprocessor may represent, for example, the setting of a value (e.g., a logical value of 1) on an asynchronous wire connected to another coprocessor.

[0022] The flags may thus represent an improved, architecturally simplified extension of the dependency flags that may be used for local data dependencies, as an example. The flags may thus be extended to the coprocessor hardware using the wires that connect the coprocessors. In this way, complex problems may be isolated and manipulated by the coprocessor while still respecting data dependencies.

[0023] In some embodiments, a central processing unit (CPU) may form part of the flag assertion techniques described herein. The CPU may receive from and transmit to the coprocessor, as an example. For example, the CPU may assert the first flag described above. In this example, the CPU may write the assertion to a first register (e.g., a control register) that is routed to the coprocessor. Additionally, the CPU may read from a second register (e.g., an interrupt register) to identify the status of the first flag when asserted or deasserted by the coprocessor. The status in this application may indicate whether the first flag is asserted or deasserted. In this manner, the CPU may identify a status associated with a processing task that is separated between the coprocessors. Additionally, the CPU may assert one or more flags based on the processing task that the CPU is performing. For example, the CPU may be used to fetch data from memory. In this example, the CPU may assert one or more flags upon completion of the memory fetch. Block Diagram

[0024] FIG. 1A is a block diagram illustrating an example processor system 100 that includes multiple coprocessors 102A-102C and uses global flags 104A-104C. In the illustrated embodiment, the coprocessors 102A-102C may represent neural processing units. However, in some embodiments, the coprocessors 102A-102C may be used to perform any operations related to a computational problem or the division of a problem in smaller chunks or pieces. Although three coprocessors 102A-102C are shown in FIG. 1A, in some embodiments there may be five, six, eight, etc. coprocessors.

[0025] The processor system 100 may represent a system included in a vehicle in some embodiments. For example, the processor system 100 may be used to perform, at least in part, autonomous or semi-autonomous operation of the vehicle. In this example, the processor system 100 may obtain sensor data from sensors (e.g., image sensors) positioned around the vehicle. The sensor data may then be analyzed, for example, using one or more machine learning models. At least a portion of the processing of the machine learning models may be accomplished via the coprocessors 102A-102C.

[0026] As shown, co-processor A 102A is connected to co-processor B 102B and co-processor C 102C via a number of connections. As an example, a portion of the connections between co-processor A 102A and co-processor B 102B represent connections for a number of flags (e.g., A flag 104A) that can be asserted or deasserted by co-processor A 102. Similarly, a portion of the connections between co-processor A 102A and co-processor C 102C represent connections for A flag 104A.

[0027] Thus, each coprocessor may assert or deassert a number of flags. For example, coprocessor A 102A may control the status for A flag 104A. As another example, coprocessor B 102B may control the status for B flag 104B. As another example, coprocessor C 102C may control the status for C flag 104C. These flags 104A-104C collectively form a number of flags that may be collectively asserted or deasserted by coprocessors 102-102C. For example, there may be three flags, five flags, nine flags, fifteen flags, etc. In this example, with respect to the three flags, A flag 104A may represent the status of each of the flags asserted or deasserted by coprocessor A 102A. B flag 104B may represent the status of each of the flags asserted or deasserted by coprocessor B 102B. C flags 104C may represent the status of each of the flags asserted or deasserted by coprocessor C 102C.

[0028] In this manner, the coprocessors may collectively utilize multiple flags to represent different data dependencies, processing dependencies, the time at which the coprocessors collectively completed their respective computations related to a computational task or problem, etc. In some embodiments, a flag is set (e.g., enabled) if all coprocessors 102A-102C assert the flag. With respect to a first flag, the first flag may be set if coprocessor A 102A asserts the first flag to be included in A flag 104A, coprocessor B 102B asserts the first flag to be included in B flag 104B, and coprocessor C 102C asserts the first flag to be included in C flag 104C. These coprocessors 102A-102C are connected to each other via, for example, asynchronous wires, so that each coprocessor may receive information from the remaining coprocessors indicating the assertion of the first flag.

[0029] As can be appreciated, the first flag described above may be set according to an instruction being executed by the coprocessors 102A-102C. For example, a software instruction may be associated with a computational task. In this example, the computational task may be separated into portions of operations or subtasks. As an example, a compiler may perform the separation, or the separation may be performed substantially in real-time during operation of the processor system 100. For a particular computational task, there may be data dependencies that are introduced when the tasks are separated.

[0030] As an example, there may be data that is processed by the coprocessors 102A-102C and subsequently used to determine the processing result. Thus, the processing result depends on the processing being performed by each coprocessor. With respect to the first flag mentioned above, the coprocessors 102A-102C may assert the first flag when the respective processing is completed. Thus, this first flag may be associated with determining the processing result. Similarly, other flags may be associated with other data dependencies. Thus, the coprocessor may ensure that data dependencies, data movements, etc. are constrained according to the flags.

[0031] In some embodiments, a flag may be deasserted when all coprocessors 102A-102C deassert the flag. For example, with respect to the first flag described above, the coprocessors 102A-102C may deassert the first flag following removal of a dependency associated with the first flag. Exemplary dependencies may relate to data dependencies, processing dependencies, etc., as described above.

[0032] As another example, there may be a computation task (e.g., workload) that initially has a large working set, but then tapers off towards the end to a smaller working set. The computation task may be started on coprocessors 102A-102C, each of which gets about 1 / 3 of the input data. Then, for example, about halfway through the computation task, each coprocessor may assert a global flag as the working set size has decreased. In some embodiments, the coprocessors may not be operating in lockstep, so each coprocessor may assert the global flag at a different time. For example, a particular coprocessor may have a different program that waits for the global flag to become true. In this example, once the global flag is set (e.g., asserted by all coprocessors), all coprocessors will arrive at the same point.

[0033] The particular coprocessor can then obtain the respective intermediate results from the remaining coprocessors (e.g., direct memory access) to its own local memory. The particular coprocessor can then deassert its global flag or set a different global flag to indicate to the remaining coprocessors that it has successfully copied the data, and the remaining coprocessors can terminate their workloads based on the change in the flag and optionally receive new workloads (e.g., from a task scheduler). The particular coprocessor can proceed with the remainder of the workload on its own until completion.

[0034] 1B is a block diagram illustrating coprocessors 102A-102C in communication with operating system 110. As described in FIG. 1A, coprocessors 102A-102C may control the status of a number of flags. For example, each coprocessor may assert or deassert a flag to cause the flag to be collectively set (e.g., enabled) or unset (e.g., disabled). In some embodiments, operating system 110 executed by processor system 100 may allow central processing unit 120 to participate in setting or unsetting the flag.

[0035] In the illustrated example, operating system 110A routes the status of the flags to coprocessors 102A-102C. For example, central processing unit 120 may assert or deassert the flags based on writing to one or more control registers. In this example, central processing unit 120 may interface with control registers that are mapped to global physical addresses at the system level. Thus, operating system 110 may provide information from these control registers to coprocessors 102A-102C.

[0036] Similarly, the operating system 110 may route the status of flags set or unset by the coprocessors 102A-102C via one or more interrupts. For example, the central processing unit 120 may receive the status via one or more interrupt registers. In this example, the coprocessors 102A-102C may provide information via these interrupt registers that are read by the central processing unit 120. Optionally, the central processing unit 120 may request the status of the flags from the coprocessors 102A-102C. For example, in contrast to the coprocessors 102A-102C providing an interrupt based on asserting or deasserting a flag, the central processing unit 120 may request the status. In response, the operating system 110 may provide information regarding the status to the central processing unit 120. In some embodiments, the coprocessors 102A-102C may provide an interrupt upon any change of the flag. For example, if the coprocessors 102A-102C collectively assert a flag, the assertion may trigger an interrupt to the central processing unit 120.

[0037] In this manner, the central processing unit 120 may be involved with the coprocessors 102A-102C in asserting the flag. Thus, the central processing unit 120 may be involved in ensuring that dependencies are enforced. For example, one or all of the coprocessors 102A-102C may require data that will be used in processing a computational task. In this example, the central processing unit 120 may fetch the data and indicate completion of the fetch by asserting one of the flags. As can be understood, without being constrained by the example, there may be multiple computational tasks in which the central processing unit 120 will be involved. For example, the central processing unit 120 may acquire sensor data from multiple sensors at a threshold frequency for use by the coprocessor. In this example, the coprocessor may acquire the data after the central processing unit 120 completes the acquisition process. For example, the central processing unit 120 may assert a flag that is read by the coprocessor (e.g., via a control register). The coprocessors may further assert flags when they complete their tasks (e.g., processing retrieved data). Thus, central processing unit 120 may set and unset flags in accordance with the techniques described herein.

[0038] 2A is a block diagram illustrating a shared mask 204 that can be used to select a subset of coprocessors 102A-102C that use global flags 202. In the illustrated example, a representation of global flags 202 is included. Each of global flags 0-N is represented as a column, with each row of the column corresponding to one of the coprocessors 206 or the operating system 208. Thus, each coprocessor can assert or deassert each of 0-N flags 202. As discussed above, in some embodiments, a flag may be indicated as set if all coprocessors, and optionally the operating system (e.g., a central processing unit), assert the flag. Similarly, in some embodiments, a flag may be indicated as unset if all coprocessors, and optionally the operating system, deassert the flag.

[0039] FIG. 2A further illustrates a flag mask 204 that may be shared with the coprocessors 102A-102C and the operating system 208. The flag mask 204 may be utilized to indicate which of the coprocessors 102A-102C, and optionally the operating system 208, should be concerned with the flags. For example, a particular computational task or set of tasks may utilize global flags 0-N 202. In this example, there may be numerous dependencies that require different flags to be enforced by the coprocessors 102A-102C and optionally the operating system 208. These dependencies may be relevant to only a subset of the coprocessors 102A-102C and the operating system 208 such that the flag mask 208 may remove one or more actors (e.g., coprocessors, operating systems) from enforcing the global flags.

[0040] The flags mask 204 may be provided via a central processing unit in some embodiments. For example, a process scheduler may be running on the central processing unit. In this example, the central processing unit may set the flags mask 204 via one or more control registers that write to the coprocessor (e.g., as described above).

[0041] 2A as being associated with global flags 202, it can be appreciated that there may be more than one flag mask. For example, each global flag, or a subset of global flags, may have a flag mask that identifies which of the coprocessors and optionally the operating system 208 is associated with the global flag or subset of global flags.

[0042] 2B is a block diagram illustrating an example of a sharing mask 208 that selects a subset of coprocessors that use a global flag. In FIG. 2B, coprocessors 102A-102B are to be utilized for a particular computational task or set of tasks, while coprocessor 102C is unused. For example, coprocessor 102C may be performing other computational tasks or may be performing no tasks.

[0043] Thus, the flags mask 208 may include a logical value of 1 for the coprocessors 102A-102B and the operating system 208. The flags mask may include a logical value of 0 for the coprocessor C 102C. In this manner, the coprocessors 102A-102B and the operating system 208 may have information identifying that the coprocessor C 102C is not associated with the global flags 202. Exemplary Flowchart

[0044] 3 is a flow chart of an example process 300 for using a global flag by an example processor system. For convenience, the process 300 is described as being executed by a processor system (e.g., processor system 100).

[0045] At block 302, the processor system receives a computational task. As described, the computational task may relate to the processing or training of one or more machine learning models (e.g., neural networks). For example, the machine learning models may be used to determine information usable to accomplish autonomous or semi-autonomous operation of a vehicle. The computational task may include one or more operations that are to be separated into subtasks or operations for execution by multiple coprocessors (e.g., neural processing units).

[0046] In block 304, the processor system associates the dependency with one or more global flags. A computational task may have one or more dependencies, such as data dependencies or processing dependencies, that need to be enforced for the computational task to complete. For example, each coprocessor may need to compute certain information that will then be aggregated or combined to form a processing result. Thus, in this example, the coprocessor may need a technique that can indicate when a particular dependency has completed.

[0047] Thus, each flag may be associated with a dependency. When a coprocessor completes certain tasks, it may assert one or more global flags to indicate the completion of those tasks. As described in Figures 1A-1B, the coprocessors may have all-to-all connections with each other (e.g., via asynchronous wires). In this way, each coprocessor can identify the flags that are asserted by the remaining coprocessors.

[0048] In some embodiments, when a flag is asserted, which may indicate completion or removal of a particular dependency, the coprocessor may perform subsequent processing. For example, operations to compute a computational task may require that a particular dependency be completed before additional operations can be performed. Thus, in this example, the coprocessor may assert a particular flag to indicate that the additional operations should be performed.

[0049] In block 306, the processor system causes execution of operations associated with the computational task. As described above, the coprocessor may execute operations to work toward the completion of the computational task. These operations may have data dependencies or processing dependencies, such that the coprocessor asserts or deasserts a flag to indicate when such dependencies are completed.

[0050] While FIG. 3 described above the use of a coprocessor to assert or deassert a global flag, additional processors (e.g., a central processing unit) may assert or deassert a global flag, as described in FIG. 1B. For example, the central processing unit may fetch data from storage for use by one or more of the coprocessors. In this example, the central processing unit may assert a particular flag upon fetching the data. Additionally, as described in FIGS. 2A-2B, a shared mask may be used to indicate which coprocessors should be involved in asserting or deasserting the global flag.

[0051] With respect to the central processing unit, as an example of the use of a flag, the central processing unit can synchronize with another processor that may not have a global flag. For example, the other processor may be a graphics processing unit (GPU). As an example, when processing a long neural network, there may be operations in the neural network that require the GPU to process information. In this example, the coprocessor (e.g., neural processor) may not have characteristics related to the operation. Thus, a global flag may be utilized to inform the central processing unit when the coprocessor is complete with intermediate results. The central processing unit can then start a GPU task and can safely assume that its input data (e.g., intermediate results) is ready in a known location. Then, when the GPU is finished, the central processing unit can set a global flag indicating that the coprocessor can resume processing the neural network, and the central processing unit can safely assume that the results of this function are available in a known location. Vehicle block diagram

[0052] 4 illustrates a block diagram of a vehicle 400 (e.g., vehicle 102). The vehicle 400 may include one or more electric motors 402 that cause movement of the vehicle 400. The electric motors 402 may include, for example, induction motors, permanent magnet motors, etc. As known to those skilled in the art, batteries 404 (e.g., one or more battery packs each comprising multiple batteries) may be used to power the electric motors 402.

[0053] The vehicle 400 further includes a propulsion system 406 that can be used to set the gear (e.g., propulsion direction) of the vehicle. For an electric vehicle, the propulsion system 406 can regulate the operation of the electric motor 402 to change the propulsion direction.

[0054] Additionally, the vehicle includes a matrix processor system 100 configured to perform matrix multiplication using a convolution engine (e.g., matrix processor 110). The matrix processor system 100 can process data such as images received from image sensors (e.g., cameras) positioned around the vehicle 400. The matrix processor system 100 can additionally output information to a display 408 included in the vehicle 400 and receive information (e.g., user input) therefrom. Other embodiments

[0055] All of the processes described herein may be embodied and fully automated via software code modules executed by a computing system including one or more computers or processors. The code modules may be stored in any type of non-transitory computer-readable medium or other computer storage device. Some or all of the methods may be embodied in dedicated computer hardware.

[0056] Many variations beyond those described herein will be apparent from this disclosure. For example, depending on the embodiment, certain operations, events, or functions of any of the algorithms described herein may be performed in a different order, or may be added, merged, or omitted entirely (e.g., not all acts or events described may be necessary to the implementation of an algorithm). Furthermore, in certain embodiments, operations or events may be performed simultaneously rather than sequentially, for example, via multi-threading, interrupt processing, or multiple processors or processor cores, or on other parallel architectures. In addition, different tasks or processes may be performed by different machines and / or computing systems that can function together.

[0057] The various example logic blocks, modules, and engines described in connection with the embodiments disclosed herein may be implemented or executed by a machine such as a processing unit or processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in alternative examples, the processor may be a controller, a microcontroller, or a state machine, combinations thereof, and the like. The processor may include electrical circuitry configured to process computer-executable instructions. In another embodiment, the processor includes an FPGA or other programmable device that performs logical operations without processing computer-executable instructions. The processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in combination with a DSP core, or any other such configuration. Although described herein primarily with respect to digital technology, the processor may also include primarily analog components. For example, some or all of the signal processing algorithms described herein may be implemented in analog circuitry or mixed analog and digital circuitry. The computing environment may include any type of computer system, including, but not limited to, a computer system based on a computational engine within a microprocessor, mainframe computer, digital signal processor, portable computing device, device controller, or appliance, to name a few.

[0058] Conditional language, particularly "can," "could," "might," or "may," is understood in its commonly used context to convey that certain embodiments include certain features, elements, and / or steps, while other embodiments do not, unless otherwise indicated. Thus, such conditional language is not intended to generally imply that the features, elements, and / or steps are in any way required by one or more embodiments, or that one or more embodiments necessarily include logic for determining whether or not those features, elements, and / or steps should be included in or performed in any particular embodiment, with or without user input or prompting.

[0059] Disjunctive language, such as the phrase "at least one of X, Y, or Z," is understood in the context of common usage to indicate that an item, term, etc. can be either X, Y, or Z, or any combination thereof (e.g., X, Y, and / or Z), unless otherwise indicated. Thus, such disjunctive language is generally not intended to, and should not, imply that a particular embodiment requires at least one of X, at least one of Y, or at least one of Z to each be present.

[0060] Any process descriptions, elements or blocks in the flow diagrams described herein and / or shown in the accompanying figures should be understood as potentially representing modules, segments or portions of code that contain one or more executable instructions for implementing a particular logical function or element in the process. As will be appreciated by those skilled in the art, alternative implementations in which elements or functions may be omitted, performed or described in a different order than that shown, including substantially simultaneously or in reverse order, depending on the functionality involved, are included within the scope of the embodiments described herein.

[0061] Unless otherwise noted, articles such as "a" or "an" should generally be construed to include one or more of the listed items. Thus, a phrase such as "a device configured to" is intended to include one or more of the enumerated devices. Such one or more enumerated devices may also be collectively configured to perform the stated enumeration. For example, "a processor configured to perform enumerations A, B, and C" may include a first processor configured to perform enumeration A working in conjunction with a second processor configured to perform enumerations B and C.

[0062] It should be emphasized that many variations and modifications can be made to the above-described embodiments, and that the elements are to be understood as being among the other acceptable examples, and all such modifications and variations are intended to be included herein within the scope of the present disclosure.

Claims

1. A plurality of coprocessors configured to compute one or more processing tasks, wherein each coprocessor is connected to each of the remaining coprocessors of the plurality of coprocessors via a plurality of connections, Individual connections from one coprocessor to another are configured to be asserted or deasserted by the coprocessor to indicate the status associated with one of several global flags. A processor system in which the global flag is set based on at least one subset of the plurality of coprocessors that assert the global flag.

2. The processor system according to claim 1, wherein the coprocessor is a neural processing unit.

3. Each global flag is associated with a dependency. Asserting a specific global flag indicates the removal of a specific dependency. The processor system according to claim 1, wherein a specific operation associated with a processing task is initiated based on the removal of the specific dependency.

4. The processor system according to claim 1, wherein the plurality of connections are asynchronous wires.

5. The processor system according to claim 1, wherein the coprocessor utilizes a shared mask, and the shared mask indicates which of the coprocessors should be included in the assertion or deassertion of the global flag.

6. The processor system communicates with the central processing unit via the operating system, and the central processing unit is configured to assert or deassert the flag. The processor system according to claim 1, wherein the global flag is set based on at least one subset of the plurality of coprocessors that assert the global flag and the central processing unit.

7. The processor system according to claim 6, wherein the central processing unit is configured to write the status of the global flag to a control register, and the operating system routes the status to the coprocessor.

8. The processor system according to claim 1, wherein the processing task is associated with a plurality of operations, and the operations are associated with a plurality of dependencies associated with the global flag.

9. A method implemented by a processor system, A step of receiving one or more computation tasks, wherein the computation task is configured to be completed through a plurality of coprocessors included in the processor system, each coprocessor is connected to the remaining coprocessors of the plurality of coprocessors via a plurality of connections, and the computation task is associated with a plurality of dependencies. A step of associating individual dependencies with individual global flags of a plurality of global flags, wherein individual connections from one coprocessor to a different coprocessor are configured to be asserted or deasserted by the coprocessor to indicate the status associated with the individual global flag, and the individual global flags are set based on at least one subset of the plurality of coprocessors that assert the individual global flags; The coprocessor triggers the execution of an operation associated with the computation task, Methods that include...

10. The method according to claim 9, wherein the coprocessor is a neural processing unit.

11. The method according to claim 9, wherein the plurality of connections are asynchronous wires.

12. The method according to claim 9, wherein the coprocessor utilizes a shared mask, and the shared mask indicates which of the coprocessors should be included in the assertion or deassertion of the global flag.

13. The processor system communicates with the central processing unit via the operating system, and the central processing unit is configured to assert or deassert the flag. The method according to claim 9, wherein the global flag is set based on at least one subset of the plurality of coprocessors that assert the global flag and the central processing unit.

14. The method according to claim 13, wherein the central processing unit is configured to write the status of the global flag to a control register, and the operating system routes the status to the coprocessor.

15. Asserting a specific global flag indicates the removal of a specific dependency. The method according to claim 9, wherein a specific action associated with a processing task is initiated based on the removal of the specific dependency.

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