Processing unit, computing device and instruction processing method

Abstract

Embodiments of the present application provide a processing unit, a computing device and an instruction processing method. The present solution is applicable to various chips including CISC instruction set, RISC reduced instruction set (especially RISC-V instruction set) or VLIM instruction set architecture, such as Internet of Things chips, audio / video chips and the like. The processing unit comprises: an instruction fetching unit configured to perform instruction fusion on sequentially adjacent vector configuration instructions and vector operation instructions to obtain fused instructions; an instruction decoding unit configured to decode the fused instructions to obtain first execution information and second execution information; a vector configuration unit configured to execute the vector configuration instructions according to the first execution information, modify a vector control register, and bypass the value of the modified vector control register to a vector operation unit; and the vector operation unit configured to execute the vector operation instructions according to the second execution information and the value of the modified vector control register. The present solution can improve the efficiency of vector operation of the processing unit.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a processing unit, computing device, and instruction processing method. Background Technology

[0002] In high-performance processing units, vector operation instructions are frequently processed. Execution of these instructions requires multiple pieces of execution information, including instruction type, element width, number of elements, register grouping, and rounding type. Due to instruction length constraints and considerations for enhancing program versatility, not all execution information is encoded in the instruction code of the vector operation instruction. For example, the instruction type is included in the instruction code, while element width, number of elements, register grouping, and rounding type are configured through vector control registers. During vector operations, the vector control registers may need to be frequently modified to change the operand width, etc.

[0003] Currently, vector operation instructions need to wait for the vector configuration instruction to configure the vector control register first. After the configuration of the vector control register takes effect, the vector operation instructions are executed based on the updated execution information.

[0004] However, since vector operation instructions need to wait for the configuration result of the vector configuration instruction on the vector control register, the vector operation instructions need to be executed after the vector configuration instruction is completed. This results in a large execution delay between the vector configuration instruction and the vector operation instruction, which in turn leads to low efficiency of the processing unit in performing vector operations. Summary of the Invention

[0005] In view of this, embodiments of this application provide a processing unit, a computing device, and an instruction processing method to at least solve or alleviate the above-mentioned problems.

[0006] According to a first aspect of the embodiments of this application, a processing unit is provided, comprising: an instruction fetching unit, configured to, upon detecting sequentially adjacent vector configuration instructions and vector operation instructions, fuse the vector configuration instructions and the vector operation instructions to obtain a fused instruction; an instruction decoding unit, configured to decode the fused instruction to obtain first execution information corresponding to the vector configuration instructions and second execution information corresponding to the vector operation instructions; a vector configuration unit, configured to execute the vector configuration instructions according to the first execution information to modify a vector control register, and bypass the modified value of the vector control register to a vector operation unit; and a vector operation unit, configured to execute the vector operation instructions according to the second execution information and the modified value of the vector control register.

[0007] According to a second aspect of the embodiments of this application, a computing device is provided, comprising: a processing unit as described in the first aspect above; and a memory coupled to the processing unit for storing the vector configuration instructions and the vector operation instructions.

[0008] According to a third aspect of the embodiments of this application, an instruction processing method is provided, comprising: upon detecting sequentially adjacent vector configuration instructions and vector operation instructions, fusing the vector configuration instructions and the vector operation instructions to obtain a fused instruction; decoding the fused instruction to obtain first execution information corresponding to the vector configuration instructions and second execution information corresponding to the vector operation instructions; executing the vector configuration instructions according to the first execution information through a vector configuration unit to modify a vector control register, and bypassing the modified value of the vector control register to a vector operation unit; and executing the vector operation instructions according to the second execution information and the modified value of the vector control register through the vector operation unit.

[0009] According to the instruction fusion scheme provided in this application embodiment, the instruction fetching unit fuses sequentially adjacent vector configuration instructions and vector operation instructions into a single fused instruction. After the fused instruction is decoded by the instruction decoding unit, the vector configuration instruction and the vector operation instruction can be executed simultaneously. The vector configuration unit executes the vector configuration instruction to modify the vector control register, and then bypasses the modified value of the vector control register to the vector operation unit. The vector operation unit executes the vector operation instruction based on the bypassed modified value of the vector control register. By fusing the vector configuration instruction and the vector operation instruction, the modification result of the vector configuration instruction on the vector control register is bypassed to the vector operation unit. The vector operation unit does not need to wait for the vector configuration instruction to finish executing before executing the vector operation instruction, allowing the vector configuration instruction and the vector operation instruction to be executed simultaneously. This shortens the execution delay between the vector configuration instruction and the vector operation instruction, thereby improving the efficiency of the processing unit in performing vector operations. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0011] Figure 1 This is a schematic diagram of a computing device used in one embodiment of this application;

[0012] Figure 2 This is a schematic diagram of a processing unit according to an embodiment of this application;

[0013] Figure 3 This is a schematic diagram of a processing unit according to another embodiment of this application;

[0014] Figure 4 This is a schematic diagram of a processing unit according to yet another embodiment of this application;

[0015] Figure 5 This is a flowchart of an instruction processing method according to an embodiment of this application. Detailed Implementation

[0016] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the essence of the present application, well-known methods, processes, and flows are not described in detail. Furthermore, the accompanying drawings are not necessarily drawn to scale.

[0017] First, some nouns or terms that appear in the description of the embodiments of this application shall be interpreted as follows.

[0018] Instruction fusion: Combining two or more adjacent instructions in an instruction sequence into one instruction to save resources used for subsequent instruction processing.

[0019] Vector operations: Vector operations are a type of operation that can produce the results of multiple elements in parallel. That is, for similar operations, such as calculating the profit for each type of goods, the unit price, sales quantity, and profit margin of multiple goods can be retrieved at once and calculated in parallel, depending on the requirements such as register capacity.

[0020] Element: In parallel computing of vector operations, the operands of a computation are elements. In the example above where the unit price, sales quantity, and profit margin of multiple goods are retrieved and calculated in parallel, these unit prices, sales quantities, and profit margins are the elements of the vector, and the number of elements contained in the vector is the number of elements that can be processed in parallel at a single operation.

[0021] Vector operation instructions: Instructions used to perform the vector operations mentioned above. For example, `vadd.vvv8,v8,v4` is a vector addition instruction, where `v8,v8,v4` are the operands used by this instruction.

[0022] Vector parameters: Vector parameters are resource configuration parameters used when executing vector operation instructions, such as the size of elements in the vector and the number of elements in a single operation. They are not operands in vector operation instructions. Operands are the objects of vector operations. Vector parameters are not objects of operation, but rather reflect the resources allocated during the operation (such as the number of bits occupied in registers).

[0023] The size of an element in a vector refers to how many bits (in bits) an element occupies in the vector register. Assuming the total width of the vector register is 128 bits, the number of bits an element occupies determines the maximum number of elements the vector register can hold, i.e., the maximum number of elements that can be processed simultaneously in parallel. For example, if an element in the vector occupies 16 bits, the vector register can hold a maximum of 8 elements simultaneously, allowing for a maximum of 8 elements to be processed in parallel.

[0024] Vector configuration instructions: These are separate from vector operation instructions and are used to configure the vector parameters used by vector operation instructions. Since directly encoding vector parameters into vector operation instructions is not conducive to the reuse of software code segments, dedicated vector configuration instructions are used to uniformly configure vector parameters. The configured vector parameters can be reused by multiple subsequent vector operation instructions.

[0025] computing devices

[0026] Figure 1 A schematic block diagram of a computing device 10 is shown. The computing device 10 can be built based on various types of processing units and driven by any operating system such as Windows, UNIX, or Linux. Furthermore, the computing device 10 can be implemented in hardware and / or software such as PCs, desktops, laptops, servers, and mobile communication devices.

[0027] like Figure 1 As shown, the computing device 10 may include one or more processing units 12 and a memory 14. The memory 14 in the computing device 10 may serve as main memory (or simply main memory or RAM) for storing instruction information and / or data information represented by data signals. For example, the memory 14 may store data provided by the processing unit 12 (e.g., budget results) and may also be used to realize data exchange between the processing unit 12 and the external storage device 16 (or auxiliary memory or external memory).

[0028] In some cases, the processing unit 12 needs to access the memory 14 via the bus 11 to retrieve or modify data in the memory 14. Because the access speed of the memory 14 is relatively slow, to alleviate the speed difference between the processing unit 12 and the memory 14, the computing device 10 also includes a cache memory 18 communicatively connected to the bus 11. The cache memory 18 is used to cache program data or message data in the memory 14 that may be repeatedly accessed. The cache memory 18 can be implemented using a storage device such as Static Random Access Memory (SRAM). The cache memory 18 can be a multi-level structure, such as a three-level cache structure with a Level 1 cache (L1 cache), a Level 2 cache (L2 cache), and a Level 3 cache (L3 cache). The cache memory 18 can also be a cache structure with more than three levels or other types of cache structures. In some embodiments, a portion of the cache memory 18 (e.g., the Level 1 cache, or both the Level 1 cache and the Level 2 cache) can be integrated inside the processing unit 12 or integrated with the processing unit 12 on the same on-chip system.

[0029] Based on this, the processing unit 12 may include an instruction execution unit 121 and a memory management unit 122, among other components. When executing instructions that require memory modification, the instruction execution unit 121 initiates a write access request, specifying the data to be written into memory and its corresponding physical address. The memory management unit 122 translates the virtual addresses specified by these instructions into the physical addresses mapped to those virtual addresses. The physical address specified in the write access request may be consistent with the physical address specified in the corresponding instruction.

[0030] Information exchange between memory 14 and cache memory 18 can be organized according to data blocks. In some embodiments, cache memory 18 and memory 14 can be divided into data blocks with the same spatial size. A data block can serve as the smallest unit of data exchange between cache memory 18 and memory 14 (including one or more data of a preset length). For the sake of brevity and clarity, each data block in cache memory 18 will be referred to as a cache block (or cache line), and different cache blocks will have different cache block addresses. Each data block in memory 14 will be referred to as a memory block, and different memory blocks will have different memory block addresses. Cache block addresses and / or memory block addresses may include physical address tags used to locate data blocks.

[0031] Due to space and resource limitations, cache memory 18 cannot cache all the contents of memory 14; that is, the storage capacity of cache memory 18 is usually smaller than that of memory 14, and the addresses of individual cache blocks provided by cache memory 18 cannot correspond to all the memory block addresses provided by memory 14. When processing unit 12 needs to access memory, it first accesses cache memory 18 via bus 11 to determine whether the content to be accessed is already stored in cache memory 18. If the content to be accessed is already stored in cache memory 18, cache memory 18 is hit, and processing unit 12 directly retrieves the content to be accessed from cache memory 18. If the content to be accessed is not stored in cache memory 18, cache memory 18 and processing unit 12 need to access memory 14 via bus 11 to find the corresponding information in memory 14. Because the access speed of cache memory 18 is very fast, the efficiency of processing unit 12 can be significantly improved when cache memory 18 is hit, thereby improving the performance and efficiency of the entire computing device 10.

[0032] In addition, the computing device 10 may also include a storage device 16, a display device, an audio device, a mouse / keyboard, and other input / output devices. The storage device 16 may be a hard disk, optical disk, or flash memory, etc., coupled to the bus 11 via a corresponding interface, for storing and retrieving information. The display device may be coupled to the bus 11 via a corresponding graphics card, and is used to display information according to the display signals provided by the bus 11.

[0033] The computing device 10 may also include a communication device 17, enabling the computing device 10 to communicate with networks or other devices in various ways. The communication device 17 may include one or more communication modules, including wireless communication modules adapted to specific wireless communication protocols. For example, the communication device 17 may include a WLAN module for implementing WiFi communication conforming to the IEEE 802.11 standard. The communication device 17 may include a WWAN module for implementing wireless wide area communication conforming to cellular or other wireless wide area protocols. The communication device 17 may also include communication modules employing other protocols, such as a Bluetooth module, or other custom-type communication modules. The communication device 17 may also be a port for serial data transmission.

[0034] It should be noted that the structure of the computing device 10 may vary depending on the motherboard, operating system, and instruction set architecture. For example, many current computing devices are equipped with an input / output control center connected between the bus 11 and various input / output devices, and this input / output control center may be integrated into the processing unit 12 or independent of the processing unit 12.

[0035] Processing unit

[0036] Figure 2 This is a schematic block diagram of a processing unit 12 according to one embodiment of this application. Figure 2 As shown, each processing unit 12 may include one or more processor cores 120 for processing instructions. The processing and execution of instructions can be controlled by a user (e.g., through an application program) and / or the system platform. Each processor core 120 can be used to process a specific instruction set, which can support Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or Very Long Instruction Word (VLIW) based computation. Specifically, processor core 120 is suitable for processing the RISC-V instruction set. Different processor cores 120 can each process different or the same instruction sets. Processor core 120 may also include other processing modules, such as a Digital Signal Processor (DSP). As an example, Figure 2 The diagram shows processor cores 1 through m, where m is a positive integer.

[0037] Figure 1 The cache memory 18 shown can be wholly or partially integrated into the processing unit 12. Depending on the architecture, the cache memory 18 can be a single or multi-level internal cache memory located within and / or outside each processor core 120 (e.g., ...). Figure 2 The three-level cache memory L1 to L3 are shown. Figure 2 The cache memory (referred to as 18 in the original text) may include instruction-oriented cache and instruction cache, as well as data cache. The components in processing unit 12 may share at least a portion of the cache memory; for example, processor cores 1 to m may share the third-level cache L3. Processing unit 12 may also include an external cache (not shown), and other cache structures may also serve as external caches for processing unit 12.

[0038] like Figure 2As shown, the processing unit 12 may include a register file 126, which may include multiple registers for storing different types of data and / or instructions. These registers may be of different types, such as integer registers, floating-point registers, status registers, instruction registers, and pointer registers. The registers in the register file 126 may be implemented using general-purpose registers, or a specific design may be adopted according to the actual needs of the processing unit 12.

[0039] Processing unit 12 may include a memory management unit (MMU) 122 for translating virtual addresses to physical addresses. The memory management unit 122 caches a portion of the entries in the page table and can also retrieve uncached entries from memory. Each processor core 120 may have one or more memory management units 122. The memory management units 122 in different processor cores 120 can be synchronized with those in other processing units or processor cores, allowing each processing unit or processor core to share a unified virtual memory system.

[0040] The processing unit 12 is used to execute the instruction sequence (i.e., the program). The process of the processing unit 12 executing each instruction includes: fetching the instruction from the memory where the instructions are stored, decoding the fetched instruction, executing the decoded instruction, and keeping the instruction execution result, etc., and so on, until all the instructions in the instruction sequence are executed or a halt instruction is encountered.

[0041] To implement the above process, the processing unit 12 may include an instruction fetch unit 124, an instruction decoding unit 125, an instruction dispatch unit (not shown), an instruction execution unit 121, and a retirement unit 123, etc.

[0042] The instruction fetch unit 124 serves as the startup engine for the processing unit 12, used to move instructions from memory 14 to the instruction register (which may be...). Figure 2 The instruction is stored in one of the registers in the register file 126 shown, and the next fetch address is received or calculated according to the fetch algorithm, which can be an incrementing or decrementing address based on the instruction length.

[0043] After the instruction is fetched, the processing unit 12 enters the instruction decoding stage. The instruction decoding unit 125 decodes the fetched instruction according to a predetermined instruction format to obtain the operand acquisition information required by the fetched instruction, thereby preparing for the operation of the instruction execution unit 121. The operand acquisition information may include pointers to immediate values, registers, or other software / hardware that can provide source operands.

[0044] The instruction dispatch unit, typically located within the high-performance processing unit 12, lies between the instruction decoding unit 125 and the instruction execution unit 121. It is used for instruction scheduling and control, efficiently allocating instructions to different instruction execution units 121, thus enabling parallel operation of multiple instructions. After an instruction is fetched, decoded, and scheduled to the corresponding instruction execution unit 121, the unit begins executing the instruction, performing the operation specified by the instruction, and thus fulfilling the corresponding function.

[0045] The retirement unit 123 (or instruction retirement unit or instruction write-back unit) is mainly used to write the execution results generated by the instruction execution unit 121 back to the corresponding storage location (e.g., a register inside the processing unit 12) so that subsequent instructions can quickly obtain the corresponding execution results from that storage location.

[0046] For different types of instructions, different instruction execution units 121 can be set up in the processing unit 12 accordingly. The instruction execution unit 121 can be an arithmetic unit (e.g., including an arithmetic logic unit, an integer processing unit, a vector arithmetic unit, a vector configuration unit, etc., used to perform operations based on operands and output the operation results), a memory execution unit (e.g., used to access memory according to instructions to read data in memory or write specified data to memory, etc.), and a coprocessor, etc. In the processing unit 12, each instruction execution unit 121 can run in parallel and output the corresponding execution results.

[0047] When executing a certain type of instruction (such as a memory access instruction), the instruction execution unit 121 needs to access memory 14 to obtain information stored in memory 14 or to provide data that needs to be written to memory 14. It should be noted that the instruction execution unit 121 used to execute memory access instructions can also be simply referred to as a memory execution unit, which can be a load store unit (LSU) and / or other units used for memory access.

[0048] After the memory access instruction is fetched by the instruction fetch unit 124, the instruction decoding unit 125 can decode the memory access instruction, allowing the source operand of the memory access instruction to be fetched. The decoded memory access instruction is then provided to the corresponding instruction execution unit 121, which can perform corresponding operations on the source operand of the memory access instruction (e.g., the arithmetic logic unit performs operations on the source operand stored in the register) to obtain the address information corresponding to the memory access instruction, and initiate corresponding requests based on the address information, such as address translation requests, write access requests, etc.

[0049] The source operand of a memory access instruction typically includes an address operand. The instruction execution unit 121 performs operations on this address operand to obtain the virtual or physical address corresponding to the memory access instruction. When the memory management unit 122 is disabled, the instruction execution unit 121 can directly obtain the physical address of the memory access instruction through logical operations. When the memory management unit 122 is enabled, the corresponding instruction execution unit 121 initiates an address translation request based on the virtual address corresponding to the memory access instruction. This address translation request includes the virtual address corresponding to the address operand of the memory access instruction. The memory management unit 122 responds to the address translation request and converts the virtual address in the address translation request into a physical address based on the entry matching the virtual address, so that the instruction execution unit 121 can access the cache memory 18 and / or memory 14 according to the translated physical address.

[0050] Depending on their function, memory access instructions can include load instructions and store instructions. The execution of a load instruction typically does not require modification of information in memory 14 or cache memory 18; the instruction execution unit 121 only needs to read data stored in memory 14, cache memory 18, or external storage devices based on the address operand of the load instruction. Unlike load instructions, the source operand of a store instruction includes not only address operands but also data information. The execution of a store instruction typically requires modification of information in memory 14 and / or cache memory 18. The data information in a store instruction can point to data to be written. The source of this written data can be the execution result of an arithmetic instruction, load instruction, or other instructions; data provided by registers or other storage units in the processing unit 12; or immediate values.

[0051] Currently, when the instruction sequence includes consecutive vector configuration instructions and vector operation instructions, the vector configuration unit must first execute the vector configuration instruction to modify the vector control register so that the vector parameters defined in the vector control register meet the operation requirements of the vector operation instruction. Then, the vector operation unit obtains the vector parameters by reading the value of the vector control register and executes the vector operation instruction based on the obtained vector parameters. Since the vector operation instruction needs to wait for the vector configuration instruction to complete before it begins execution, there is a significant execution delay between the vector configuration instruction and the vector operation instruction, which leads to low efficiency in vector operations performed by the processing unit 12.

[0052] This embodiment of the application is designed to address the problem of low efficiency in vector operations performed by the processing unit 12. It is primarily implemented through the instruction fetch unit 124, instruction decoding unit 125, and instruction execution unit 121 included in the processing unit 12. The process of the processing unit 12 executing vector configuration instructions and vector operation instructions will be discussed in detail below.

[0053] Figure 3 This is a schematic diagram of the internal structure of a processing unit 12 according to an embodiment of this application. Figure 3 As shown, the processing unit 12 includes an instruction fetch unit 124, an instruction decoding unit 125, a vector configuration unit 127, and a vector operation unit 128. When the instruction fetch unit 124 detects sequentially adjacent vector configuration instructions and vector operation instructions, it can fuse the vector configuration instructions and vector operation instructions to obtain a fused instruction. The instruction decoding unit 125 can decode the fused instruction to obtain first execution information corresponding to the vector configuration instruction and second execution information corresponding to the vector operation instruction. The vector configuration unit 127 can execute the vector configuration instruction according to the first execution information to modify the vector control register and bypass the modified value of the vector control register to the vector operation unit 128.

[0054] The instruction fetch unit 124 can detect the instruction sequence to determine whether there are sequentially adjacent vector configuration instructions and vector operation instructions in the instruction sequence. When sequentially adjacent vector configuration instructions and vector operation instructions are detected, the instruction fetch unit 124 can fuse the sequentially adjacent vector configuration instructions and vector operation instructions to obtain a fused instruction.

[0055] It should be understood that sequentially adjacent vector configuration instructions and vector operation instructions refer to instructions that are adjacent in the instruction sequence, with the vector configuration instruction preceding the vector operation instruction. For example, if the instruction sequence includes instructions 1 to 64, where instruction 6 is a vector configuration instruction and instruction 7 is a vector operation instruction, then instructions 6 and 7 are sequentially adjacent vector configuration and vector operation instructions, and instructions 6 and 7 can be fused together.

[0056] After decoding the fused instruction, the instruction decoding unit 125 can obtain first execution information and second execution information. The first execution information includes the register index and immediate value carried by the vector configuration instruction, and the second execution information includes the register index and immediate value carried by the vector operation instruction.

[0057] The vector configuration unit 127 executes a vector configuration instruction according to the first execution information, modifies the vector control register, and generates a vector control register modification bypass request. The result of the modified vector control register is bypassed to the vector operation unit 128. That is, the vector configuration unit 127 bypasses the value of the modified vector control register to the vector operation unit 128.

[0058] In this embodiment, the instruction fetch unit 124 merges sequentially adjacent vector configuration instructions and vector operation instructions into a single fused instruction. This fused instruction is then decoded by the instruction decoding unit 125, allowing the vector configuration and vector operation instructions to be executed simultaneously. The vector configuration unit 127 executes the vector configuration instruction to modify the vector control register and then bypasses the modified value of the vector control register to the vector operation unit 128. The vector operation unit 128 executes the vector operation instruction based on the bypassed modified value of the vector control register. By fusing the vector configuration and vector operation instructions, the modification result of the vector configuration instruction on the vector control register is bypassed to the vector operation unit 128. The vector operation unit 128 does not need to wait for the vector configuration instruction to finish executing before executing the vector operation instruction, allowing the vector configuration and vector operation instructions to be executed simultaneously. This shortens the execution delay between the vector configuration and vector operation instructions, thereby improving the efficiency of vector operations performed by the processing unit 12.

[0059] In one possible implementation, the instruction fetch unit 124 can decode the vector configuration instruction, store the decoding result in an additional decoding field, and store the instruction type information used to indicate that the fused instruction is formed by fusing the vector configuration instruction and the vector operation instruction in the additional decoding field. Then, the instruction code of the vector operation instruction is used as the main decoding information and fused with the additional decoding field to obtain the fused instruction.

[0060] Instruction fusion allows for the fusion of various instruction types to obtain different types of fused instructions. To enable the instruction decoding unit 125 to recognize fused instructions formed by the fusion of vector configuration instructions and vector operation instructions, instruction type information can be stored in the additional decoding field. After decoding the fused instruction, the instruction decoding unit 125 can determine that the instruction is formed by the fusion of vector configuration instructions and vector operation instructions based on the instruction type information in the additional decoding field. Then, it can decode the main decoding information and the additional decoding field separately to obtain first execution information and second execution information. The instruction type information can be an instruction type code; different types correspond to different instruction type codes, and fused instructions and non-fused instructions also correspond to different instruction type codes.

[0061] In this embodiment, the instruction fetch unit 124 can pre-decode the vector configuration instruction to obtain the information required to execute the vector configuration instruction. After integrating the decoded information into the additional decoding field, the instruction code of the vector operation instruction is used as the main decoding information and fused with the additional decoding field to obtain the fused instruction. Then, when the instruction decoding unit 125 decodes the fused instruction, it can obtain the second execution information required to execute the vector operation instruction and the first execution information required to execute the vector configuration device. Thus, the first execution information and the second execution information can be sent to the vector configuration unit 127 and the vector operation unit 128 respectively in the same clock cycle, ensuring that the vector configuration instruction and the vector operation instruction can be executed simultaneously, thereby reducing the execution delay between the vector configuration instruction and the vector operation instruction, improving the efficiency of the processing unit 12 in performing vector operations, and ensuring the performance of the processing unit 12.

[0062] In one possible implementation, after receiving the fusion instruction, the instruction decoding unit 125 can decode the main decoding information and the additional decoding field included in the fusion instruction respectively, and obtain the first execution information and the second execution information based on the instruction type information stored in the additional decoding field after determining that the decoding object is a fusion instruction formed by the fusion of vector configuration instructions and vector operation instructions.

[0063] Upon receiving an instruction pair information marked as a fused instruction, the instruction decoding unit 125 simultaneously decodes the main decoding information and additional decoding fields of the fused instruction and determines the type of the fused instruction. After determining, based on the instruction type information, that the fused instruction is a fusion of a vector configuration instruction and a vector operation instruction, the instruction decoding unit 125 prepares the necessary information for the synchronous and accurate execution of the vector operation instruction and the vector configuration instruction according to the additional decoding fields. That is, it prepares the first execution information required for the execution of the vector configuration instruction and the second execution information required for the execution of the vector operation instruction.

[0064] In this embodiment, the main decoding information of the fusion instruction includes the instruction code of the vector operation instruction, and the additional decoding field includes the pre-decoding information of the vector configuration instruction. The instruction decoding unit 125 decodes the main decoding information and the additional decoding field of the fusion instruction simultaneously, and can synchronously obtain the first execution information required to execute the vector configuration instruction and the second execution information required to execute the vector operation instruction. As a result, the subsequent vector configuration unit and vector operation unit can synchronously execute the vector configuration instruction and the vector operation instruction, thereby reducing the execution delay between the vector configuration instruction and the vector operation instruction and improving the efficiency of the processing unit 12 in performing vector operations.

[0065] In one possible implementation, the first execution information includes at least one of a general-purpose register value, a general-purpose register number, a destination general-purpose register number, and instruction decoding information, and the second execution information includes at least one of a source vector register value, a destination vector register number, and instruction decoding information.

[0066] In this embodiment, the first execution information is the information required for the execution of the vector configuration instruction, and the second instruction information is the information required for the execution of the vector operation instruction. The first execution information includes general-purpose register values, general-purpose register numbers, destination general-purpose register numbers, and instruction decoding information of the vector configuration instruction. The second execution information includes source vector register values, destination vector register numbers, and instruction decoding information of the vector operation instruction. This ensures that the vector configuration unit 127 can correctly modify the vector control register based on the first execution information, and similarly ensures that the vector operation unit 128 performs correct vector operations based on the second execution information and the modified value of the vector controller, thus ensuring the correctness of the vector operation result.

[0067] Figure 4 This is a schematic diagram of the internal structure of a processing unit according to another embodiment of this application. Figure 4 As shown, the processing unit 12 may further include an instruction issuing unit 129. When the instruction issuing unit 129 sends the fusion instruction to the vector configuration unit 127 and the vector operation unit 128 for execution, it can assign an instruction identifier to the fusion instruction. The instruction identifier is used to determine the relationship between different instructions, and the instruction identifiers of the vector configuration instruction and the vector operation instruction are the same as the instruction identifier of the fusion instruction. The instruction issuing unit 129 also sends first execution information to the vector configuration unit 127 and second execution information to the vector operation unit 128, so that the vector configuration unit 127 executes the vector configuration instruction based on the first execution information, and the vector operation unit 128 executes the vector operation instruction based on the second execution information.

[0068] The instruction issuing unit 129 assigns a unique instruction identifier to the fused instruction allocation pipeline. Based on this identifier, the age relationship between two instructions in the pipeline can be determined. The age relationship refers to the order in which these two instructions are placed in the pipeline; the older instruction precedes the newer instruction. The instruction identifier can be an instruction ID, and different instructions in the pipeline have different instruction IDs. The instruction identifier can increment or decrement according to the instruction sequence. When the instruction identifier increments according to the instruction sequence, the instruction with the larger identifier is newer than the instruction with the smaller identifier; when the instruction identifier decrements according to the instruction sequence, the instruction with the larger identifier is older than the instruction with the smaller identifier.

[0069] In this embodiment, when the instruction issuing unit 129 issues the fusion instruction, it assigns an instruction identifier to the fusion instruction. Moreover, the vector configuration instruction and the vector operation instruction have the same instruction identifier as the fusion instruction. The relationship between the old and new instructions can be determined through the instruction identifier. Then, the vector operation unit 128 can execute the instruction using the value of the vector control register before modification or the value of the vector control register after modification according to the instruction identifier, which ensures that the vector operation can be performed normally and thus ensures the accuracy of the vector operation result.

[0070] In one possible implementation, after receiving the value of the modified vector control register bypassed by the vector configuration unit 127, the vector operation unit 128 determines whether the instruction identifier of the currently executed instruction is the same as that of the vector configuration instruction. If the instruction identifier of the currently executed instruction is the same as that of the vector configuration instruction, the value of the modified vector control register is used to execute the currently executed instruction.

[0071] In this embodiment, when the vector operation unit 128 obtains the value of the modified vector control register bypassed by the vector configuration unit 127, it also simultaneously obtains the instruction identifier of the vector configuration instruction that modifies the vector control register. Since the vector configuration instruction and the vector operation instruction have the same instruction identifier as the fusion instruction, the vector operation unit 128 can determine whether the instruction currently being executed is the same as the instruction identifier of the vector configuration instruction. If the instruction identifier of the instruction currently being executed is the same as the instruction identifier of the vector configuration instruction, it means that the instruction currently being executed is the vector operation instruction that is fused with the vector configuration instruction to obtain the fusion instruction. Then, the vector operation unit 128 uses the value of the modified vector control register to execute the instruction currently being executed, ensuring the accuracy of the execution result of the vector operation instruction.

[0072] In one possible implementation, if the vector operation unit 128 determines that the instruction identifier of the currently executed instruction is different from that of the vector configuration instruction, then the relationship between the current execution instruction and the vector configuration instruction is determined based on the instruction identifier. If the currently executed instruction is newer than the vector configuration instruction, then the modified value of the vector control register is used to execute the currently executed instruction. If the currently executed instruction is older than the vector configuration instruction, then the unmodified value of the vector control register is used to execute the currently executed instruction.

[0073] Since multiple instructions may be executing within the vector operation unit 128, after the instruction issuing unit 129 issues the fusion instruction to the vector operation unit 128 and the vector configuration unit 127, the following situations may occur: When the vector configuration unit 127 executes the vector configuration instruction and bypasses the modified vector control register value to the vector operation unit 128, the vector operation unit 128 has not yet started executing the corresponding vector operation instruction. At this time, the vector operation unit 128 should use the unmodified value of the vector control register to execute the currently executed instruction. After the vector operation unit 128 corresponding to the fusion instruction has finished executing, if there are no other vector configuration instructions between this vector operation instruction and subsequent vector operation instructions, the vector operation unit 128 should use the modified value of the vector control register to execute the subsequent vector operation instruction.

[0074] For example, a program fragment includes instructions 1 through 5 arranged in sequence, as shown below:

[0075] Command 1: vsetvli a6,a5,e8,m1,tu,mu

[0076] Command 2: vwcvtu.xxv v8,v12

[0077] Command 3: vsetvli a6,a5,e16,m2,tu,mu

[0078] Command 4: vwmaccu.vx v4,t2,v10

[0079] Command 5: vslide1down.vx v2,v8,a4

[0080] Among them, instructions 1 and 3 are vector configuration instructions, and instructions 2, 4 and 5 are vector operation instructions.

[0081] Since instructions 1 and 2 are sequentially adjacent vector configuration instructions and vector operation instructions, and instructions 3 and 4 are sequentially adjacent vector configuration instructions and vector operation instructions, instructions 1 and 2 can be fused together, and instructions 3 and 4 can be fused together.

[0082] In one example, when vector configuration unit 127 executes instruction 3 and bypasses the modified vector control register value to vector operation unit 128, vector operation unit 128 is executing instruction 2. Therefore, vector operation unit 128 uses the value of the vector control register before the modification by instruction 3 to execute instruction 2, that is, it uses the value of the vector control register after the modification by instruction 1 to execute instruction 2. When vector operation unit 128 executes instruction 4, since the instruction identifier of instruction 4 is the same as that of instruction 3, vector operation unit 128 uses the modified vector control register value after instruction 3 to execute instruction 4. There is no vector configuration instruction between instruction 4 and instruction 5, and instruction 5 is newer than instruction 3, so vector operation unit 128 uses the modified vector control register value after modification by instruction 3 to execute step 5.

[0083] In this embodiment, the vector operation unit 128 determines the relationship between the currently executed instruction and the vector configuration instruction based on the instruction identifier. When the currently executed instruction is newer than the vector configuration instruction, the value of the vector control register modified by the vector configuration instruction is used to execute the currently executed instruction. When the currently executed instruction is older than the vector configuration instruction, the value of the vector control register before the vector configuration instruction is modified is used to execute the currently executed instruction. This reduces the execution delay between vector configuration instructions and vector operation instructions with the same instruction identifier, while ensuring the correct execution of other vector operation instructions by the vector operation unit 128 and the correctness of vector operations performed by the processing unit 12.

[0084] In one possible implementation, after receiving the vector configuration instruction fused by instruction fusion, the vector configuration unit 127 treats the instruction as a normal vector configuration instruction and generates a vector control register modification bypass request. The result of the modified vector control register is bypassed to the vector operation unit 128. After the vector configuration instruction is completed normally and allowed to be submitted, the vector configuration instruction completes the update of the configuration control register normally and writes the result back.

[0085] In this embodiment, the vector configuration unit 127 executes the vector configuration instruction and bypasses the result of modifying the vector control register to the vector operation unit 128. When the vector configuration instruction is executed normally and is allowed to be submitted, the vector configuration instruction normally completes the update of the vector control register and writes the result back, ensuring the correctness of the overall execution behavior.

[0086] It should be noted that, depending on the actual application scenario, vector configuration instructions and vector operation instructions can be executed by different or the same instruction execution unit. When vector configuration instructions and vector operation instructions are executed by the same instruction execution unit, vector configuration unit 127 and vector operation unit 128 are the same instruction execution unit.

[0087] Instruction processing methods

[0088] Figure 5 This is a flowchart of an instruction processing method according to an embodiment of this application, which can be executed by the processing unit 12 in the above embodiment. Figure 5 As shown, the instruction processing method includes the following steps:

[0089] Step 501: When sequentially adjacent vector configuration instructions and vector operation instructions are detected, the vector configuration instructions and vector operation instructions are fused to obtain a fused instruction;

[0090] Step 502: Decode the fusion instruction to obtain the first execution information corresponding to the vector configuration instruction and the second execution information corresponding to the vector operation instruction;

[0091] Step 503: Through the vector configuration unit, execute the vector configuration instruction according to the first execution information to modify the vector control register, and bypass the modified value of the vector control register to the vector operation unit;

[0092] Step 504: Execute vector operation instructions through the vector operation unit based on the second execution information and the modified value of the vector control register.

[0093] In this embodiment, sequentially adjacent vector configuration instructions and vector operation instructions are fused into a single fused instruction. After decoding, the fused instruction allows both the vector configuration and operation instructions to be executed simultaneously. The vector configuration unit executes the vector configuration instruction to modify the vector control register and then bypasses the modified value of the vector control register to the vector operation unit. The vector operation unit then executes the vector operation instruction based on the bypassed modified value of the vector control register. By fusing the vector configuration and operation instructions, the modification result of the vector configuration instruction on the vector control register is bypassed to the vector operation unit. The vector operation unit does not need to wait for the vector configuration instruction to complete before executing the vector operation instruction, allowing both instructions to be executed simultaneously. This shortens the execution delay between the two instructions and improves the efficiency of vector operations performed by the processing unit.

[0094] In one possible implementation, when fusing vector configuration instructions and vector operation instructions to obtain a fused instruction, the instruction code of the vector configuration instructions can be decoded, the decoding result can be stored in an additional decoding field, and the instruction type information used to indicate that the fused instruction is formed by fusing the vector configuration instructions and the vector operation instructions can be stored in the additional decoding field. The instruction code of the vector operation unit can be used as the main decoding information and fused with the additional decoding field to obtain the fused instruction.

[0095] In one possible implementation, when decoding the fusion instruction, the main decoding information and the additional decoding field included in the fusion instruction can be decoded separately, and the first execution information and the second execution information can be obtained according to the instruction type information stored in the additional decoding field.

[0096] In one possible implementation, the instruction processing method further includes: assigning an instruction identifier to the fusion instruction, sending first execution information to the vector configuration unit, and sending second execution information to the vector operation unit, wherein the instruction identifier is used to determine the relationship between different instructions, and the instruction identifiers of the vector configuration instruction and the vector operation instruction are the same as the instruction identifier of the fusion instruction.

[0097] In one possible implementation, when executing a vector operation instruction based on the second execution information and the value of the modified vector control register, the value of the modified vector control register bypassed by the vector configuration unit is received, and it is determined whether the instruction identifier of the currently executed instruction is the same as the instruction identifier of the vector configuration instruction. If the instruction identifier of the currently executed instruction is the same as the instruction identifier of the vector configuration instruction, the value of the modified vector control register is used to execute the currently executed instruction.

[0098] In one possible implementation, the instruction processing method further includes: when it is determined that the instruction identifier of the currently executed instruction is different from the instruction identifier of the vector configuration instruction, determining the relationship between the current execution instruction and the vector configuration instruction based on the instruction identifier; if the currently executed instruction is newer than the vector configuration instruction, then the modified value of the vector control register is used to execute the currently executed instruction; if the currently executed instruction is older than the vector configuration instruction, then the unmodified value of the vector control register is used to execute the currently executed instruction.

[0099] In one possible implementation, the instruction processing method further includes: after bypassing the modified value of the vector control register to the vector arithmetic unit, updating the vector control register and writing back the result after confirming that the vector configuration instruction has been executed normally and is allowed to be submitted.

[0100] In one possible implementation, the first execution information includes at least one of: a general-purpose register value, a general-purpose register number, a destination general-purpose register number, and instruction decoding information; the second execution information includes at least one of: a source vector register value, a destination vector register number, and instruction decoding information.

[0101] It should be noted that the details of the instruction processing method have been described in detail in the processing unit section of the above embodiments in conjunction with the structural diagram. For the specific process, please refer to the description in the aforementioned processing unit embodiments, and will not be repeated here.

[0102] Computer storage media

[0103] This application also provides a computer-readable storage medium storing instructions for causing a machine to perform the instruction processing method as described herein. Specifically, a system or apparatus equipped with a storage medium storing software program code that implements the functions of any of the embodiments described above, and enabling the computer (or CPU or MPU) of the system or apparatus to read and execute the program code stored in the storage medium.

[0104] In this case, the program code read from the storage medium can itself implement the function of any of the above embodiments, and therefore the program code and the storage medium storing the program code constitute part of this application.

[0105] Examples of storage media used to provide program code include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), magnetic tapes, non-volatile memory cards, and ROMs. Alternatively, program code can be downloaded from a server computer via a communication network.

[0106] Computer program products

[0107] This application also provides a computer program product, including computer instructions that instruct a computing device to perform any corresponding operation in the above-described plurality of method embodiments.

[0108] The commercial value of the embodiments in this application

[0109] In addressing the issue of significant execution delay between sequentially adjacent vector configuration instructions and vector operation instructions, this application embodiment fuses the vector configuration instructions and vector operation instructions. The modification result of the vector control register by the vector configuration instruction is bypassed to the vector operation unit. The vector operation unit does not need to wait for the vector configuration instruction to finish executing before executing the vector operation instruction, allowing the vector configuration instructions and vector operation instructions to be executed simultaneously. This shortens the execution delay between the vector configuration instructions and vector operation instructions, thereby improving the efficiency of the processing unit in performing vector operations.

[0110] It should be understood that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the methods described in the apparatus and system embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions of other embodiments.

[0111] It should be understood that the foregoing describes specific embodiments of this specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0112] It should be understood that the use of a singular form to describe an element or to show only one element in the accompanying drawings does not imply that the number of such element is limited to one. Furthermore, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be broken down into multiple modules or elements.

[0113] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.

Claims

1. A processing unit, comprising: The instruction fetching unit is used to decode the instruction code of the vector configuration instruction when sequentially adjacent vector configuration instructions and vector operation instructions are detected, store the decoding result in an additional decoding field, and fuse the instruction code of the vector operation instruction as the main decoding information with the additional decoding field to obtain a fused instruction. The instruction decoding unit is used to decode the fusion instruction to obtain first execution information corresponding to the vector configuration instruction and second execution information corresponding to the vector operation instruction; The vector configuration unit is configured to execute the vector configuration instruction according to the first execution information to modify the vector control register and bypass the modified value of the vector control register to the vector operation unit; The vector operation unit is configured to execute the vector operation instruction according to the second execution information and the modified value of the vector control register; and to receive the modified value of the vector control register bypassed by the vector configuration unit, determine whether the instruction identifier of the currently executed instruction is the same as the instruction identifier of the vector configuration instruction, and if the instruction identifier of the currently executed instruction is the same as the instruction identifier of the vector configuration instruction, then the modified value of the vector control register is used to execute the currently executed instruction, wherein the instruction identifier is pre-assigned by the instruction issuing unit for the fusion instruction.

2. The processing unit according to claim 1, wherein, The instruction fetching unit is further configured to: store instruction type information indicating that the fused instruction is formed by the fusion of vector configuration instructions and vector operation instructions into the additional decoding field.

3. The processing unit according to claim 2, wherein, The instruction decoding unit is configured to, upon receiving the fusion instruction, decode the main decoding information and the additional decoding field included in the fusion instruction respectively, and obtain the first execution information and the second execution information according to the instruction type information stored in the additional decoding field.

4. The processing unit according to claim 1, wherein, The processing unit further includes: The instruction issuing unit is used to assign an instruction identifier to the fusion instruction, send the first execution information to the vector configuration unit, and send the second execution information to the vector operation unit. The instruction identifier is used to determine the relationship between different instructions. The instruction identifiers of the vector configuration instruction and the vector operation instruction are the same as the instruction identifier of the fusion instruction.

5. The processing unit according to claim 4, wherein, The vector operation unit is configured to determine the relationship between the currently executed instruction and the vector configuration instruction based on the instruction identifier when the instruction identifier of the currently executed instruction is different from the instruction identifier of the vector configuration instruction. If the currently executed instruction is newer than the vector configuration instruction, the modified value of the vector control register is used to execute the currently executed instruction. If the currently executed instruction is older than the vector configuration instruction, the unmodified value of the vector control register is used to execute the currently executed instruction.

6. The processing unit according to any one of claims 1-5, wherein, The vector configuration unit is used to bypass the modified value of the vector control register to the vector operation unit, and after determining that the vector configuration instruction has been executed normally and is allowed to be submitted, to update the vector control register and write back the result.

7. The processing unit according to any one of claims 1-5, wherein, The first execution information includes at least one of: a general-purpose register value, a general-purpose register number, a destination general-purpose register number, and instruction decoding information; The second execution information includes at least one of the following: source vector register value, destination vector register number, and instruction decoding information.

8. A computing device, comprising: The processing unit according to any one of claims 1-7; The memory, coupled to the processing unit, stores the vector configuration instructions and the vector operation instructions.

9. An instruction processing method, comprising: When sequentially adjacent vector configuration instructions and vector operation instructions are detected, the instruction code of the vector configuration instructions is decoded, the decoding result is stored in an additional decoding field, and the instruction code of the vector operation unit is used as the main decoding information and fused with the additional decoding field to obtain a fused instruction. The fusion instruction is decoded to obtain first execution information corresponding to the vector configuration instruction and second execution information corresponding to the vector operation instruction; The vector configuration unit executes the vector configuration instruction according to the first execution information to modify the vector control register, and then bypasses the modified value of the vector control register to the vector operation unit. The vector operation unit executes the vector operation instruction based on the second execution information and the modified value of the vector control register; and receives the modified value of the vector control register bypassed by the vector configuration unit, determines whether the instruction identifier of the currently executed instruction is the same as the instruction identifier of the vector configuration instruction, and if the instruction identifier of the currently executed instruction is the same as the instruction identifier of the vector configuration instruction, then the modified value of the vector control register is used to execute the currently executed instruction, wherein the instruction identifier is pre-assigned by the instruction issuing unit for the fusion instruction.

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