Through-substrate via with metal plane layer and method of manufacture - Patents.com

Abstract

Embodiments disclosed herein include post-TSV top-out processing methods and devices formed using such processing methods. In some embodiments, the methods include forming an electrically and thermally conductive layer on a device that can be used as a power / ground connection path or forming a heat spreading plane that includes multiple interconnected stacked devices in a device assembly.

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE This disclosure relates generally to the manufacture and assembly of semiconductor devices, and more particularly to electronic device assemblies formed with through-substrate vias (TSVs) and methods of forming electronic device assemblies. [Background technology]

[0002] A through-substrate via (TSV) is a conductive feature, or "through-silicon via," that is provided completely through a substrate, e.g., from the device or "active" surface of a silicon wafer to the non-device or "backside" surface, and can be used to provide electrical connections between individual devices. TSVs can substantially increase the wiring density and substantially decrease the wiring length of device-to-device interconnections compared to traditional interconnections, e.g., wirebond or flip-chip interconnections. Thus, TSVs, e.g., those used for power delivery or inter-device communication in three-dimensional integrated circuit (3D-IC) device assembly schemes, are increasingly being relied upon in multi-device integration schemes to meet the seemingly endless drive for reduced power consumption and smaller electronic device packages.

[0003] TSVs are conventionally formed within the boundaries of a die using via-first, via-middle, or via-last fabrication approaches. Generally, in via-first and via-middle fabrication approaches, the conductive features that will become TSVs are first formed within the device-side surface of the substrate so that they extend through the thickness direction but do not extend all the way through (i.e., as "blind vias"). In the via-first approach, the blind vias are formed before the front-end-of-line (FEOL) of the individual device elements, such as transistors, resistors, and capacitors. In the via-middle approach, the blind vias are formed after FEOL processing but before the back-end-of-line (BEOL) of the metal interconnects. Generally, in either approach, the base (bottom) surface of the blind via is exposed once the device fabrication is substantially complete, such as during post-fabrication device assembly and test operations. To expose the base surface of the blind vias, material is removed from the non-device surface of the substrate using a series of substrate thinning operations (collectively known as the "TSV reveal").

[0004] Unfortunately, process irregularities during blind via formation and the relatively narrow process window during TSV topping often combine to cause substantial interconnect defects during device assembly and test operations. Such irregularities may include variations in blind vias formed within a device (intra-die irregularities), across a substrate (intra-substrate irregularities), and / or between devices formed on different substrates (substrate-to-substrate irregularities). Problems associated with blind via irregularities are further complicated in outsourced assembly and test (OSAT) facilities that receive and assemble devices from different device manufacturers. The combined effects of process irregularities and associated interconnect defects often result in breakage of packaged electronic devices, thus reducing yields and increasing overall manufacturing costs. As a result, new integration technologies utilizing TSV interconnects, such as three-dimensional integrated circuits (3D-ICs), have yet to achieve widespread commercial viability. Therefore, there is a need for improved and more robust TSV cu-up and post-cu-up methods that use a wide processing window that accounts for the introduction of variability into blind vias formed by via-first or via-middle TSV fabrication techniques. Summary of the Invention

[0005] Embodiments disclosed herein include post-TSV top-out processing methods and devices formed using such methods. In some embodiments, the methods include forming an electrically and thermally conductive layer on a device that can be used as a power / ground connection path or forming a heat spreading plane that includes multiple interconnected stacked devices in a device assembly.

[0006] In one embodiment, a method is provided for forming a conductive plane around a via pillar that protrudes from a surface of a substrate. The method includes forming a support layer stack having a metal plane layer and a first dielectric layer disposed on the metal plane layer, where the metal plane layer surrounds at least a base portion of the via pillar and the first dielectric layer covers an upwardly facing surface of the via pillar. The method further includes removing a portion of the first dielectric layer and a portion of the via pillar using a polishing process to expose a surface of the metal via. In this case, the surface of the metal via is surrounded by a second portion of the first dielectric layer remaining after the polishing process. In some embodiments, one or more second dielectric layers may be disposed between the metal plane layer and an inactive surface of the substrate and between the metal plane layer and a base portion of the via pillar. In some embodiments, the substrate has a semiconductor portion, the metal via extends through the semiconductor portion, and a dielectric liner is disposed between the metal via and the semiconductor portion and between the metal via and the one or more second dielectric layers.

[0007] In some embodiments, forming the metal support layer includes depositing a metal support layer and recessing a surface of the metal support layer below the upwardly facing surface of the via pillar. Recessing a surface of the metal support layer may include removing a portion of the metal support layer by use of a polishing process, an etching process, or a combination thereof. In some embodiments, the metal plane layer forms a ground plane or a power plane of a power supply or distribution network to two or more interconnect devices.

[0008] In another embodiment, a method for forming uniform through-substrate vias in a microelectronic device is provided. The method includes depositing a support layer to surround a plurality of via pillars protruding from a surface of a substrate, and removing the support layer and the plurality of via pillars to expose an upwardly facing surface of each of the through-substrate vias. In some embodiments, the support layer is deposited to a thickness greater than the height of the plurality of via pillars. In some embodiments, the support layer is removed using a polishing process. In some embodiments, the support layer is made of a metal or metal alloy. In some embodiments, the metal may include copper, tungsten, nickel, mixtures thereof, and / or alloys thereof. In some embodiments, the exposed via surface may be formed of one or more of the same metals used to form the support layer.

[0009] In another embodiment, a microelectronic structure is provided. The microelectronic structure may include a semiconductor substrate having a first surface and a second surface opposite the first surface, a first dielectric layer disposed on the first surface, and a via structure disposed through the first dielectric layer. In this case, the via structure may extend at least partially through the semiconductor substrate, at least a portion of the via structure protruding above the first dielectric layer to define a via pillar. The microelectronic structure may further include a metal plane layer disposed on the first dielectric layer and a second dielectric layer disposed on the metal plane layer. In some embodiments, the via structure is formed of a conductive material. In some embodiments, the via structure is formed of a conductive material electrically insulated from the metal plane layer by a portion of a dielectric liner disposed between the via structure and the metal plane layer. In some embodiments, the metal plane layer is formed of a material selected from the group consisting of copper, tungsten, nickel, mixtures thereof, and / or alloys thereof.

[0010] In some embodiments, the metal plane layer is coupled to an external power source. In some embodiments, the metal plane layer is coupled to a ground connection path. In some embodiments, the metal plane layer forms a bias plane for the packaged electronic device.

[0011] The above and other objects and advantages of the present disclosure will become apparent from a consideration of the following detailed description taken in conjunction with the accompanying drawings. [Brief description of the drawings]

[0012] [Figure 1A] 1A to 1C are cross-sectional views showing how to form a blind via by a via-first or via-middle process. [Figure 1B] 1A to 1C are cross-sectional views showing how to form a blind via by a via-first or via-middle process. [Figure 1C] 1A to 1C are cross-sectional views showing how to form a blind via by a via-first or via-middle process. [Figure 1D] 1A to 1C are cross-sectional views showing how to form a blind via by a via-first or via-middle process. [Figure 1E] 1A to 1C are cross-sectional views showing how to form a blind via by a via-first or via-middle process. [Figure 1F] 1A to 1C are cross-sectional views showing how to form a blind via by a via-first or via-middle process. [Diagram 2] 1A-1B are schematic diagrams of methods that can be used to form one or more of the devices shown in FIGS. 1A-1B in accordance with some embodiments. [Figure 3A] 3A-3C are schematic cross-sectional views of a substrate at different stages of the method depicted in FIG. 2 according to some embodiments. [Figure 3B] 3A-3C are schematic cross-sectional views of a substrate at different stages of the method depicted in FIG. 2 according to some embodiments. [Figure 3C]3A-3C are schematic cross-sectional views of a substrate at different stages of the method depicted in FIG. 2 according to some embodiments. [Figure 3D] 3A-3C are schematic cross-sectional views of a substrate at different stages of the method depicted in FIG. 2 according to some embodiments. [Figure 3E] 3A-3C are schematic cross-sectional views of a substrate at different stages of the method depicted in FIG. 2 according to some embodiments. [Figure 4] 1D is a block diagram of a method that can be used to form one or more of the devices shown in FIG. 1C in some embodiments. [Figure 5A] 5A-5C are schematic cross-sectional views of a substrate at different stages of the method depicted in FIG. 4 according to some embodiments. [Figure 5B] 5A-5C are schematic cross-sectional views of a substrate at different stages of the method depicted in FIG. 4 according to some embodiments. [Figure 6] 1 is a schematic cross-sectional view of a device assembly formed in accordance with some embodiments. [Figure 7] 1 is a schematic cross-sectional view of a device assembly formed in accordance with some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] The figures in this application depict various embodiments of the present invention for purposes of illustration only, and it will be recognized that additional or alternative structures, systems and methods may be implemented within the scope of the principles illustrated by this disclosure.

[0014] Embodiments provided herein relate to methods for substantially reducing and / or eliminating processing defects in a through-substrate via (TSV) top-off process and devices formed using such methods. In some embodiments, the methods can be advantageously used to substantially reduce TSV breaks caused by in-coming variations in blind vias formed using via-first or via-middle TSV fabrication techniques during one or more post-top-off chemical mechanical polishing (CMP) processes. In some embodiments, the methods include forming an electrically and thermally conductive layer on a device that can be used as a power / ground connection path or a heat spreading plane that includes multiple interconnect stacked devices in a device assembly.

[0015] The term "substrate" as used herein includes any workpiece that serves as a support material on which the various elements of a semiconductor device are fabricated or attached, as well as any layers of material, features, and / or electronic devices formed on, in, or through a semiconductor device. Thus, the term substrate includes both the semiconductor substrate on which device elements are fabricated, and reduced thickness semiconductor substrates, layers of material, devices, and features formed on, in, or through the semiconductor substrate when fabrication and / or assembly is complete. It should also be understood that the term substrate as used herein further includes any layers of material, devices, and features formed on, in, or through the semiconductor substrate at any point during the device fabrication and assembly process, regardless of whether the layers of material, devices, or features are present in the completed device or feature in the completed device or assembly.

[0016] As described below, a substrate as used herein generally has a "device side", e.g., a side on which semiconductor device elements, e.g., transistors, resistors, and capacitors are fabricated, and a "back side" opposite the device side. The term "active side" should be understood to include the device side surface of a substrate, which may include the device side surface of a semiconductor substrate and / or any material layer, device element, or feature formed on or extending outwardly from the semiconductor substrate, and / or any opening formed in the semiconductor substrate. Thus, it should be understood that the materials forming the active side may vary depending on the stage of device fabrication and assembly. Similarly, the term "non-active side" (opposite the active side) includes the non-active side of a substrate at any stage of device fabrication, which may include the surface of any material layer, device element, or feature formed on or extending outwardly from the substrate, and / or any opening formed in the substrate. Thus, the terms "active surface" and "non-active surface" can include the respective surfaces of a semiconductor substrate at the start of device fabrication and any surfaces formed during material removal, for example after a substrate thinning operation. Depending on the device fabrication or assembly stage, the terms "active surface" and "non-active surface" are also used to describe surfaces of material layers or features formed on, in, or through a semiconductor substrate, regardless of whether the material layers or features are ultimately present in a fabricated or assembled device.

[0017] Spatial terms are used herein to describe relationships between elements, such as between a semiconductor substrate and individual layers of material, devices, and features, as described below. Unless otherwise specified, terms such as "above," "over," "upper," "upwardly," "outwardly," "on," "below," "under," "beneath," "lower," and the like, are generally used with respect to active or inactive surfaces of a semiconductor substrate and / or layers of material disposed thereon. Thus, it should be understood that spatial terms used herein include different orientations of the substrate and are not limited by the direction of gravity, unless otherwise noted. Terms describing relationships between elements, such as "on," "embedded in," "coupled to," and "connected by," alone or in combination with spatial terms, include both relationships that include intervening elements and direct relationships without intervening elements.

[0018] 1A-1F are schematic diagrams illustrating the formation of blind vias in an active surface 102 of a substrate 100 and the emergence of via pillars 126 (FIG. 1E) from a non-active surface 104 using a via-first or via-middle processing approach. It is contemplated that the processes illustrated in FIGS. 1A-1F may be used in combination with any of the methods described herein to form through-substrate vias (TSVs). In this case, the substrate 100 comprises a semiconductor substrate 101 made of a Group IV semiconductor, such as silicon, silicon germanium or germanium, a III-V compound semiconductor, or a II-VI semiconductor, and any device elements formed or partially formed on the semiconductor substrate. In some embodiments, the semiconductor substrate 101 may be made of a Group IV semiconductor, such as silicon, silicon germanium or germanium, a III-V compound semiconductor, or a II-VI semiconductor. In some embodiments, for example in a via-middle processing scheme, the substrate 100 may include device elements, such as one or a combination of transistors, capacitors, or resistors, formed on or in the active surface 102. To avoid overcomplicating the drawings, such devices are not shown here.

[0019] 1A, a via-first or via-middle TSV is typically formed by forming a high aspect ratio opening 106 in the active surface 102 of the substrate 100, where the opening 106 is formed to a depth D in the thickness direction (Z direction) of the substrate 100, but does not extend all the way through to the non-active surface 104. In some embodiments, the depth D of the opening 100 may be from about 50 μm to about 200 μm, and the thickness T1 of the substrate 100 may be from about 600 μm to about 1000 μm.

[0020] 1B, one or more barrier layers 108 are deposited to line the walls and base surface of opening 106, and a conductive material 116 is deposited over barrier layer 108 to fill the remainder of opening 106 to form conductive via feature 118 (FIG. 3C). In some embodiments, conductive material 116 includes copper, copper alloy tungsten, tungsten alloy, and / or mixtures, alloys, and combinations thereof, where copper alloy and tungsten alloy include mixtures of copper and / or tungsten with other metals that will form alloys upon annealing.

[0021] The barrier layer 108 can be used to prevent unwanted diffusion of the conductive material 116 into the surrounding material of the semiconductor substrate 101, to provide an adhesive interface layer between the conductive metal and the walls and base surface of the opening 106, and / or to facilitate subsequent deposition of the conductive material 116. For example, the barrier layer 108 can include a dielectric layer 110, one or more metal or metal nitride layers 112 deposited on the dielectric layer 110, and a seed material layer 114 each deposited on the one or more metal or metal nitride layers 112 as shown in FIG. 1B. Examples of materials that can be used for the dielectric layer 110 include silicon oxide (SiO 2 ), silicon oxynitride (SiO 2 ), and / or a silicon nitride layer 114. x O y ), silicon nitride (SiN x ), silicon oxynitride (Si x O y N z ), silicon carbide (SiC), aluminum oxide (Al x O y Examples of materials that can be used for the metal or metal nitride layer 112 include Ti, Ta, W, TiN, TaN, WN, and combinations thereof.

[0022] In some embodiments, the seed material layer 114 is made of the same metal as the conductive material 116 used to fill the openings 106, for example to facilitate electrodeposition of the conductive material 116. For example, in some embodiments, the seed material layer 114 may include copper, a mixture of metals including copper, and / or a copper alloy. In other embodiments, the seed material layer 114 may include a different material, for example, Co, Ru, Mn, Ti, Ta, W, or a combination thereof. To reduce visual clutter, the remaining figures only show the dielectric layer 110 of one or more of the barrier layers 108.

[0023] In FIG. 1C, the overburden of conductive material 116 is removed from the field of active surface 102, for example, using a CMP process, and then substrate 100 is sent for further device fabrication processing. Typically, the base surface 122 of each blind via 120 is exposed when semiconductor substrate 101 is thinned in preparation for device assembly, for example, in a TSV topping process shown in FIGS. 1D-1F, which may be used in combination with any of the methods described below. Once thinned, substrate 100 may be difficult to handle due to warping or bending caused by the substrate thinning process and caused by inherent stresses in the material layer stack that forms active surface 102. Thus, to facilitate substrate handling, active surface 102 of substrate 100 may be temporarily bonded to a second "carrier substrate" (not shown) that provides structural support during TSV topping and post-topping processing methods described herein. Substrate 100 may be bonded to a carrier substrate before or after substrate thinning, and if so, removed before or after singulation of the individual devices formed on substrate 100.

[0024] 1D-1F show schematic diagrams of a via topping process that is performed after device fabrication is substantially complete, e.g., after an interconnect layer 130 is formed in the active surface 102 of the substrate 100 during BEOL fabrication. In this case, the topping process includes a bulk material removal process to thin the substrate 100 to a thickness T2 (FIG. 1D), followed by a selective material removal process to thin the substrate 100 to a thickness T3 (FIG. 1E). The bulk material process typically includes a backgrinding process and an optional CMP process to uniformly remove semiconductor material from the non-active surface 104 to a thickness T2. The thickness T2 may be selected based on the depth D of the opening 106 formed in the active surface 102 so as not to expose the base surface 122 of the blind via 120.

[0025] The base surface 122 is topped off during a selective material removal process, such as a wet etching process, a plasma-based (dry) etching process, a CMP process, or a combination thereof. Typically, semiconductor material is selectively removed from the backside of the semiconductor substrate 101 relative to the dielectric layer 110, so that the conductive material 116 underneath the semiconductor substrate is not exposed during the topping off process. The selective material removal process protects the non-active surface 104 of the semiconductor substrate 101 from contamination that would occur if the semiconductor substrate 101 were exposed to the conductive material 116 during the topping off process. Thus, as shown in FIG. 1E, the non-active surface 104 (recessed surface 124) of the semiconductor substrate 101 is recessed under a portion of the (former) blind via 120, which protrudes above the recessed surface 124 to form a via pillar 126 having a height H1. The via pillar 126 includes a protruding portion of the barrier layer 118 including the via feature 118 and the dielectric layer 110 disposed thereover. In some embodiments, the average height H1 of the via pillars 126 across the entire non-contact surface is between about 1 μm and about 10 μm, for example between about 1 μm and about 5 μm, and the difference in height H1 between different via pillars 126 may be in the range of about 1 μm to about 5 μm.

[0026] Typically, one or more dielectric layers 128, such as one or more layers of silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof, are deposited on the recessed surface 124 and the via pillars 126 projecting upwardly from the recessed surface. The one or more dielectric layers 128 form a passivation and / or isolation layer on the recessed surface 124 that protects the recessed surface 124 of the semiconductor substrate 101 from damage or contamination caused by exposure to atmospheric conditions and / or subsequent substrate processing operations. In some embodiments, the one or more dielectric layers 128 are used to facilitate direct bond device assembly methods, such as those described in the methods below. Typically, the dielectric layers 110, 128 covering the conductive material 116 of the pillars 126 are removed prior to device assembly to form suitable TSV contact and / or bonding surfaces, such as by use of a planarizing CMP process. In these embodiments, the dielectric layer 128 protects the recessed surface from contamination caused by the conductive material, such as copper, that is exposed during the planarizing CMP process. In some embodiments, the dielectric layer 128 comprises a silicon oxide layer deposited on a silicon nitride layer (or vice versa). As shown in FIG. 1F, the dielectric layer 128 is deposited to a total thickness T4, measured from the recessed surface 124, that is less than the height H1 of the pillars 126, e.g., about 0.5 μm to about 3 μm.

[0027] In general, in a planarizing CMP process, the non-active surface 104 of the substrate 100 is pressed against a polishing pad surface (not shown) in the presence of a polishing slurry. The non-active surface 104 may be pressed against the polishing surface by applying a force, e.g., in the Z direction, to the substrate 100 toward the polishing surface while the substrate 100 and the polishing surface are moved relative to each other in the X-Y plane (orthogonal to the Z direction). The mechanical forces resulting from the relative motion of the non-active surface 104, the polishing pad, and the slurry abrasive at the polishing interface, combined with the chemical reaction of the polishing slurry with the non-active surface 104, planarize the surface, i.e., remove the protruding portions of the via pillars 126 from the surface. Unfortunately, the lateral force F (shown in FIG. 1F) exerted on the TSV pillars 126 due to the combination of the lateral motion in the Z direction and the applied force may contribute to undesired pillar breakage or undesired "pillar knockdown" of some portions of the TSVs and / or the dielectric layer 126. Pillar breaks and / or other defects, such as cracking or cracking of the dielectric layer 128, often occur at or under the original stress point 129 near the recessed surface 124. Such defects may result in loss of electrical connection between devices, thus resulting in device failure during assembly. Generally, such defects increase with increasing pillar height, possibly due to an increase in moment about the original stress point 129. As a result, the process window for material removal during the selective material removal process during TSV topping is significantly narrowed, as the wider window to allow for increased pillar height variation typically results in an increase in pillar break and cracking defects. Accordingly, the method provided herein includes removing at least a portion of the pillar 126 from the non-active surface 104 while simultaneously protecting the pillar 126 from the lateral abrasive forces exerted during the removal process.

[0028] In some embodiments, the via pillars 126 are protected from lateral polishing forces by one or more pillar support layers that surround the pillars 126, for example in the X-Y plane (orthogonal to the thickness direction Z) shown in FIG. 3C. In these embodiments, the lateral polishing forces that would otherwise cause undesirable fracture of individual via pillars 126 are redistributed across the surface of the support layers at the polishing interface. Thus, the one or more pillar support layers beneficially provide controlled and uniform planarization of both the pillar support layers and the outwardly facing surfaces of the TSVs 126 disposed therein.

[0029] 2 is a block diagram of a method 200 that can be used to redistribute lateral polishing forces across a surface of a support layer while simultaneously forming electrical contacts or heat spreading planes that can be used in a stacked device assembly. Figures 3A-3E are cross-sectional views of a substrate 100 that generally illustrate various aspects of the method 200 according to some embodiments.

[0030] The method 200 generally includes forming a support layer stack 322 (FIG. 3C) on the non-active surface 104 of the substrate 100 (after TSV exposing) and planarizing the surface of the support layer stack 322 to expose a plurality of via contact surfaces 312 (FIG. 3D). As described above in connection with FIG. 1F, the non-active surface 104 may include a plurality of via pillars 126 and one or more dielectric layers 128 disposed on the plurality of via pillars 126 and on portions of the recessed surface 124 disposed between the plurality of via pillars. The support layer stack 322 is formed by forming a metal planar layer 306 (FIG. 3B) and depositing a dielectric support layer 308 (FIG. 3C) on the metal planar layer 306, respectively.

[0031] In block 202, the method 200 includes depositing a metal support layer 304 (FIG. 3A) on the inactive surface 104 of the substrate 100. In some embodiments, the metal support layer 304 is made of an electrically and / or thermally conductive material, such as a metal or a metal alloy. In some embodiments, the metal support layer 304 is made of a conductive material suitable for use as a power plane 619 or a ground plane 617 in a power delivery network of a stacked device assembly, such as the device assembly shown in FIG.

[0032] Examples of materials that can be used to form the metal support layer 304 include the exemplary materials described above with respect to the conductive material 116. In some embodiments, the metal support layer 304 is made of the same or approximately the same metal composition as the conductive material 116. In some embodiments, the metal support layer 304 may be formed directly on the dielectric layer 128, i.e., without a barrier or adhesive film layer between them. In some embodiments, the metal support layer 304 may be formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or a combination thereof. For some of these embodiments, the metal support layer 304 may be formed by depositing a conductive seed layer (not shown), such as a metal or metal alloy, on the dielectric layer 128, such as a CVD or PVD deposited seed layer, and depositing the bulk material of the metal support layer 304 on the seed layer using an electrodeposition process. The seed layer may be made of a material of a different or substantially approximately the same composition as the bulk material. In other embodiments, the method 200 may include depositing one or more barrier or adhesion layers (not shown) over the dielectric layer followed by depositing the metal support layer 304. Examples of suitable materials that may be used as the barrier or adhesion layer include silicon nitride, titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride, titanium silicon nitride, tantalum silicon nitride, tungsten silicon nitride, and combinations thereof.

[0033] In block 204, the method 200 includes selectively removing a portion of the metal support layer 304 to form a metal planar layer 306 (FIG. 3B). Removing the portion of the metal support layer 304 recesses a surface 318 below a top surface of an end portion 316 of the via pillar 126 (FIG. 3B). The remaining portion of the metal support layer 304 forms the metal planar layer 306, which surrounds and rests on the recessed surface 124 between at least a base portion 314 of the via pillar 126. In this case, the base portion 314 of the via pillar 126 is located adjacent to the recessed surface 124 and the end portion 316 is spaced from the recess 124 by the base portion 314.

[0034] The metal plane 306 may be formed in block 204 using a selective material removal process suitable for planarizing the metal support layer 304 without removing the portions of the dielectric layer 128 disposed over the via pillars 126. In some embodiments, the surface 318 may be recessed using an etching process that etches a portion of the metal support layer 304 but removes a relatively small portion of the dielectric layer 128. In these embodiments, at least a portion of the dielectric layer 128 remains over the surface of the via pillars 126. In some embodiments, the etching process is a planarizing etching process using a liquid etchant, such as a spin-etch process. In some embodiments, the surface 318 may be recessed using a highly selective CMP process, such as by using a selective metal polishing slurry typically used in metal damascene processes. In some embodiments, the CMP process may use a relatively low polishing force and / or a relatively soft polishing pad (as compared to CMP processes typically used for dielectric planarization) to avoid pillar fracture due to lateral forces exerted during more aggressive CMP processes, if not configured as described above.

[0035] 3B, the metal plane layer 306 forms a continuous electrically and / or thermally conductive layer of material across the non-active surface 104 of the substrate 100. A plurality of discontinuous openings are provided in the metal plane layer 306, with a corresponding via pillar 126 extending upwardly through each of the plurality of openings. Thus, in some embodiments, the metal plane layer 306 is formed to surround the base portions 314 of the individual via pillars 126 in the X-Y plane. In some embodiments, at least a portion of the dielectric layer 128 provided on the sidewalls of the via pillars 126 remains after the CMP process, such that the conductive via feature 118 is electrically insulated from the metal plane layer 306 by the portions of the dielectric layers 110, 128 provided therebetween.

[0036] In some embodiments, the metal planar layer 306 has a thickness of about 0.1 μm to about 5 μm, such as 0.1 μm to about 3 μm. In some embodiments, the via pillars 126 extend (in the Z direction) above the surface 318 of the metal planar layer 306 a height H2 ranging from about 0.25 μm or more, such as about 0.5 μm or more, such as from about 0.25 μm to about 5 μm.

[0037] At block 206, the method 200 includes depositing a dielectric support layer 308 over the metal planar layer 306 and the via pillars 126 extending therethrough. Examples of materials that can be used to form the dielectric support layer 308 are found above in the exemplary materials for the dielectric layers 110, 128. The dielectric support layer 318 and the underlying metal planar layer 306 each surround a sidewall portion of an individual via pillar 126 in the XY direction. As shown, the dielectric support layer 308 is deposited to a thickness that lies around the length of the end portion 316 in the XY direction. In some embodiments, the dielectric support layer 308 is deposited to a thickness of about 0.1 μm or more, such as between about 1 μm and about 5 μm, or about 1 μm or more, such as between about 1 μm and about 5 μm.

[0038] In block 208, the method 200 includes using a CMP process to remove a portion of the dielectric support layer 308 and the upwardly facing portions of the via pillars 126 disposed therein to form a dielectric planar layer 310. In this case, the dielectric planar layer 310 is the portion of the dielectric support layer 308 that remains after the CMP process. As shown, the backside surface 320 further includes a plurality of via contact surfaces 312 disposed through and flush or slightly recessed from the dielectric planar layer 310. The CMP process in block 208 may include any process suitable for planarizing a dielectric layer and may be substantially similar to the CMP process used to planarize an interlayer dielectric, such as tetra-ethyl-ortho-silicate (TEOS) deposited oxide, in a BEOL CMP process.

[0039] In block 210, the method 200 optionally includes forming a plurality of metal plane connection pads 324 (FIG. 3E) on the backside that can be used as inter-device connections between the ground plane 617 and adjacent devices in a stacked device assembly, e.g., as described below with reference to FIG. 6. The connection pads 324 can be formed of any suitable conductive material, e.g., any of the exemplary metals and metal alloys described above with respect to the conductive material 116 and the metal support layer 304. In some embodiments, the connection pads 324 are formed of substantially the same material as the metal plane layer 306. In some embodiments, the connection pads 324 are formed by a damascene process, e.g., by patterning the dielectric plane layer 310, depositing a metal layer (not shown) on the patterned surface, and removing raised portions of the metal layer from the fields of the dielectric layer. In other embodiments, the connection pads 324 can be formed by patterning the dielectric support layer 308 and depositing a connection metal before performing the CMP process in block 208. In these embodiments, the CMP process used in block 208 may include multiple polishing steps, such as a first step to remove the interconnect metallization buildup and a second step to form the backside surface 320 .

[0040] In some embodiments, the metal plane layer 306 can be used to optimize the cumulative stress of the material layers deposited on the active and non-active surfaces 104 to control bowing and warping of the substrate. Typically, the metal layers, e.g., the metal plane layer 306, have an inherent tensile stress and the dielectric layers have an inherent compressive stress. In some embodiments, the thickness of the metal plane layer 306 can be selected to offset the compressive stress in the material layers already deposited or to be deposited. In some embodiments, the metal plane layer 306 can be deposited to a thickness that provides a substantially stress-neutral structure after the contact surface 312 is formed, thus reducing undesirable stress-related warping and bending of the substrate 101 and / or individual devices formed therefrom. In some embodiments, the thickness of the metal plane layer 306 can be tailored to bowing and warping within processing limits appropriate for the direct bonding surfaces of different devices, e.g., as described below in connection with Figures 6 and 7.

[0041] 4 is a block diagram of another embodiment of a method 400 that can be used to substantially mitigate CMP-related pillar breakage and / or cracking when forming a metal planar layer is undesirable. Figures 5A and 5B are cross-sectional views of a substrate 100 that generally illustrate various aspects of the method 400 in accordance with some embodiments. The method generally includes depositing a metal support layer 304 on the non-active surface 104 following TSV topping while simultaneously removing the metal support layer 304 and the plurality of via pillars 126 using a planarizing CMP process.

[0042] In block 402, the method includes depositing a metal support layer 304 on the non-active surface 104 of the substrate following the TSV topping process. As described above with respect to method 200 and in conjunction with FIG. 1F, the non-active surface 104 following the TSV topping generally has a plurality of via pillars 126 extending upward from a recessed surface 124, and one or more dielectric layers 128 deposited on the plurality of via pillars 126 and the recessed surface 124. The one or more dielectric layers 128 provide an isolation layer and / or diffusion barrier that protects the recessed surface 124 of the semiconductor substrate 101 from undesired contamination and / or material diffusion from the metal support layer 304. In some embodiments, the metal support layer 304 is formed directly on the dielectric layer without the use of a barrier and / or adhesion material layer. In other embodiments, the method 400 includes depositing one or more barrier and / or adhesion layers (not shown) on the dielectric layer prior to deposition of the metal support layer 304. Examples of suitable materials that can be used as the barrier and / or adhesion layer are described above in connection with method 200. In some embodiments, metal support layer 304 is deposited to a thickness greater than the height H1 of via pillars 126, e.g., as shown in FIG. 5A, such that metal support layer 304 surrounds each of via pillars 126 along its length, i.e., in the Z direction.

[0043] At block 404, the method 400 includes simultaneously removing the metal support layer 304 and the via pillars 126 disposed therein using a planarizing CMP process. In some embodiments, the metal support layer 304 and the plurality of via pillars 126 are simultaneously removed using a low-selectivity CMP process that simultaneously planarizes a surface of the metal support layer 304 and an upwardly facing surface of the via pillars 126 disposed therein. For example, in some embodiments, the CMP process has a material removal rate selectivity of between 3:1 and 1:3, e.g., between about 2:1 and 1:2, between about 3:2 and 2:3, between about 4:3 and about 3:4, between about 5:4 and about 4:5, or about 1:1 with respect to one or more or each of the materials forming the metal of the metal support layer 304 and the dielectric layer 128. In embodiments in which the dielectric layer 128 comprises a silicon oxide layer, the CMP process may have a material removal rate selectivity of about 2:1 to about 1:2, such as about 3:2 to 2:3, about 4:3 to about 3:4, about 5:4 to about 4:5, or about 1:1.

[0044] In some embodiments, the metal support layer 304 and the via pillars 126 are simultaneously removed using two or more different selective polishing processes in an alternating sequence that includes removal of portions of the metal support layer 304 and portions of the via pillars 126. For example, the sequence may include an alternating sequence of a metal-selective CPM process and a dielectric-selective CMP process. The metal-selective process may exhibit a higher material removal rate for the metal support layer 304 than for the dielectric layer 128, and the dielectric-selective process may exhibit a higher material removal rate for the dielectric layer 128. In such embodiments, the alternating sequence may be repeated until the metal support layer 304 is removed from the field side of the dielectric layer 128 and the via contact surface 312 of the via feature disposed therein is substantially flush with or slightly recessed below the field side.

[0045] The embodiments described above with reference to Figures 2 and 4 can be advantageously used to significantly reduce CMP-related breakage and / or cracking of the via pillars 126 during post-topping processing. The support layer used in each of these methods provides mechanical support for the via pillars 126 in the X-Y direction while redistributing the lateral polishing forces from the individual via pillars 126 to the larger surface area of ​​the support layer surrounding the via pillars 126. During the CMP process described above in the block diagram, the polishing forces are distributed across the entire surface of the support layer at the polishing interface, thus reducing the shear stresses that would be exerted on the exposed via pillar sidewalls if the support layer were not present. The lateral support is provided by the support layer surrounding the via pillars 126 in the X-Y plane to provide a mechanical reaction, e.g., a brace, to the lateral polishing forces exerted on the via pillars 126, thus reducing the moment generated at the stress point (Figure 1F).

[0046] By simultaneously redistributing the polishing forces and providing lateral support to the TSV pillars 126, the incidence of pillar breaks and / or cracks can be substantially reduced regardless of pillar height. Thus, the above-described method can be advantageously used to increase the amount of material removed from a semiconductor substrate during selective material removal processes without increasing the incidence of defects associated therewith, as shown in FIG. 1E. This increase in processing window can be used to accommodate unknown variations in the depth of blind vias formed in via-first or via-middle processes.

[0047] 6 and 7 are schematic cross-sectional views of example device assemblies, e.g., three-dimensional integrated circuits (3D-ICs), that can be formed using the methods described above. As shown, each of the device assemblies includes multiple devices stacked together in a face-back bonding integration manner. In other embodiments, the device assemblies may be formed using a face-face bonding manner or a combination of face-back and face-face bonding integration manners. In some embodiments, the active and non-active dielectric and / or metal surfaces of the individual devices are directly bonded together in an adhesive-free wafer-wafer, chip-wafer, or chip-chip assembly process. Examples of suitable direct bond technologies that may be used to form the device assemblies include DBI® (Direct Bond Interconnect) or ZiBond® (Direct Interconnect Technology) commercially available from Xperi Holding Corp. of San Jose, Calif. Other embodiments of the device assemblies shown in FIGS. 6 and 7 may be formed using any suitable direct, hybrid, or conventional method of forming electrical connections between the TSV features, connection pads, and / or metal planar contacts of individual devices.

[0048] In FIG. 6, the device assembly 600 includes a plurality of devices 600a-600c arranged in a stacked configuration and directly bonded to one another using a front-to-back bonding integration scheme. As shown, each of the devices 600a-600c includes a substrate 101 having an active side 602 and an opposing non-active side 604. In FIG. 6, the active sides 602 are shown facing face-down, with each active side having device elements 605, such as transistors, capacitors, resistors, and / or other active components, formed in or on the active side. Each of the devices 600a-600c includes a plurality of metal interconnect layers 130 disposed on the active sides 602, the metal interconnect layers 130 including local and global interconnects used to connect the device elements 605 to one another and to circuitry external to the devices 600a-600c, such as to other devices within the device assembly 600. The base device 600a and the intermediate device 600b in the device assembly 600 each have a number of TSV features 118 formed through the semiconductor substrate 101 in a via-first or via-middle fabrication process.

[0049] In this case, the TSV features 118 include signal TSVs 607 and power TSVs 609. The signal TSVs 607 communicatively connect the individual device elements 605 to each other and / or to external circuitry, facilitating the exchange of information therebetween. The power TSVs 609 connect each of the individual devices to a power plane 619 or ground plane 617 of a power delivery network (PDN) 615. In this case, the vertical arrangement of the devices 600a-600c and the short connection paths provided by the signal TSVs 607 extending through the devices substantially reduces data transfer times between the active components of each of the devices. The short data transfer paths thus provide faster processing speeds and reduced power consumption when compared to other data transmission methods, such as wirebond interconnects.

[0050] The power TSVs 609 are generally larger in diameter than the signal TSVs 607, e.g., to allow for larger current flow through the power TSVs by reducing the resistance of the power delivery path. The relatively large size of the power TSVs 609 means that they occupy valuable surface area within the individual devices 600a-600c (the area of ​​the lower device 600a dedicated to the power TSVs 609 is larger than that of the upper device 600b, i.e., its purpose is to accommodate a direct power delivery path from the power plane 619 to each device located above it). Despite the relative difference in size between the power TSVs 609 and the signal TSVs 607, the power TSVs 609 typically have a smaller cross-sectional area than the cross-sectional area of ​​other power delivery connections, e.g., traces or wire bonds. Thus, the resistance per unit length of a string of power TSVs 609 used to connect power to upper devices in a multi-device stack can result in significant power dissipation, undesirable generation of heat, and undesirable voltage variations between devices.

[0051] The device assembly 600 shown in FIG. 6 provides current paths, e.g., ground connection paths, through one or more metal plane layers 306 formed correspondingly on the non-active sides 604 of the individual devices 600a, 600b in accordance with the methods described above. Each of the upper devices 600b, 600c is connected to a metal plane layer 306 formed on the non-active side 604 of the device below, e.g., through, a number of connection pads 324, which are connected to a ground plane 617 using external connection paths 621, e.g., side traces or a number of wire bond connections (not shown). The metal plane 306 can be advantageously used to reduce the number of power TSVs 609 and / or increase the current capacity of the power delivery network 615 while simultaneously reducing power consumption. In another embodiment, the device assembly includes a number of ground TSVs 611 connected to the ground plane 617, as shown in FIG. 7, and the metal plane layer 306 is connected to the power plane 619 through the external connection paths 621.

[0052] In some embodiments, the metal plane layers 306 may be used as bias planes configured to provide one or more independently controllable bias voltages to devices positioned above the metal plane layers. In one example, one or more of the metal plane layers are electrically connected to an independently controllable bias voltage generator configured to provide a bias voltage to the metal plane layers. In some embodiments, such as that shown in FIG. 7, one or more of the metal plane layers 306 may be used as a heat spreader to redistribute heat generated and / or concentrated within a localized region of the active surface 602 disposed above or below the metal plane layers 306.

[0053] 7 is a schematic cross-sectional view of a device assembly 700 with multiple devices 700a-700c arranged in a front-to-back stacked configuration. Power is delivered to each of the devices 700b, 700c through a power TSV 609 and a ground TSV 611 formed through each of the lower devices 700a, 700b, where the power TSV 609 is connected to a power plane 619 and one or more ground TSVs are connected to a ground plane 617. In this case, each of the metal plane layers 306 of the devices 700a, 700b is configured to be usable as a heat spreader to redistribute heat generated from the active surface 602 of an adjacent device (the corresponding device and / or the adjacent device arranged above the corresponding device). As shown, each of the metal plane layers 306 is in thermal communication with a thermal TSV (TTSV) 703, e.g., a via-last TSV made of a thermally conductive material that couples to a cooling system of the metal plane layer 306, e.g., a heat sink 705. Inter-device heat spreaders may be advantageously used to transfer heat away from between devices in stacked device assemblies, thus potentially increasing the number of devices that can be incorporated into such a structure.

[0054] The above-mentioned methods, devices, and device assemblies are illustrative and not limiting. As will be appreciated by those skilled in the art, individual aspects of the methods described herein may be omitted, modified, combined, and / or arranged without departing from the scope of the present invention. For example, in some embodiments, the device assembly may include one or more metal plane layers 306, each configured to be used as an inter-device ground or power plane, e.g., as shown in FIG. 6, and one or more metal plane layers 306, each configured to be used as a heat spreader, e.g., as shown in FIG. 7. Generally speaking, the above disclosure is illustrative and not limiting. Only the following claims set boundaries regarding the scope of protection of the present invention.

Claims

1. A method for forming a conductive plane around via pillars protruding from the surface of a substrate, The steps include forming a support layer stack having a metal planar layer surrounding at least the base portion of the via pillar and a first dielectric layer provided on the metal planar layer and covering the surface facing upward of the via pillar, A method comprising the step of removing a portion of the first dielectric layer and a portion of the via pillar by using a polishing process to expose one surface of a metal via surrounded by the rest of the first dielectric layer.

2. The method according to claim 1, wherein one or more second dielectric layers are provided between the metal planar layer and the inactive surface of the substrate and between the metal planar layer and the base portion of the via pillar.

3. The method according to claim 2, wherein the substrate has a semiconductor portion, the metal via penetrates the semiconductor portion, and a dielectric liner is provided between the metal via and the semiconductor portion and between the metal via and one or more second dielectric layers.

4. The method according to claim 1, wherein the metal planar layer is made of copper, tungsten, nickel, or a combination thereof.

5. The method according to claim 1, wherein the step of forming the metal planar layer comprises the step of depositing a metal support layer and the step of recessing one surface of the metal support layer below the upward-facing surface of the via pillar.

6. The method according to claim 5, wherein the step of recessing one surface of the metal support layer comprises removing a portion of the metal support layer by using a polishing process, an etching process, or a combination thereof.

7. The method according to claim 1, wherein the metal planar layer forms a ground plane or power plane of a power supply network to two or more interconnecting devices.

8. A method for forming uniform through-substrate vias in a microelectronic device, The process includes the step of depositing a support layer so as to surround a plurality of via pillars protruding from one surface of a substrate, wherein the support layer is deposited to a thickness greater than the height of the plurality of via pillars. A method comprising the step of removing the support layer and the plurality of via pillars to expose the upward-facing surface of each of the substrate through vias.

9. The method according to claim 8, wherein the support layer is made of metal.

10. The method according to claim 9, wherein the metal is copper, tungsten, nickel, or a combination thereof.

11. The method according to claim 10, wherein the exposed surface is made of the metal.

12. The method according to claim 9, wherein the support layer is removed by a polishing process.

13. The method according to claim 12, wherein the polishing process exhibits a removal rate selectivity of about 2:1 to 1:2 for each of the materials forming the support layer and the via pillar.

14. A microelectronic structure, A semiconductor substrate having a first surface and a second surface opposite to the first surface, Having a first dielectric layer provided on the first surface, The invention has a via structure that penetrates the first dielectric layer and also penetrates at least partially the semiconductor substrate, wherein at least a portion of the via structure protrudes above the first dielectric layer to form a via pillar. The first dielectric layer has a metal planar layer provided on it, A microelectronic structure having a second dielectric layer provided on the aforementioned metal planar layer.

15. The via structure is made of a conductive material, according to claim 14.

16. The microelectronic structure according to claim 15, wherein the conductive material of the via structure is electrically insulated from the metal planar layer by a portion of a dielectric liner provided between the via structure and the metal planar layer.

17. The microelectronic structure according to claim 15, wherein the metal planar layer is made of copper, tungsten, nickel, or a combination thereof.

18. The microelectronic structure according to claim 14, wherein the metal planar layer is coupled to an external power supply.

19. The microelectronic structure according to claim 14, wherein the metal planar layer is coupled to an earth connection path.

20. The microelectronic structure according to claim 14, wherein the metal planar layer forms a bias plane of a packaged electronic device.

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