Pacemaker and method of operation of such pacemaker

Abstract

The present invention generally relates to a cardiac pacemaker (10), e.g., an ILP, for a patient's heart (20) that achieves a small integrated circuit footprint and simple design, covering many operating modes despite the need for complex and dynamically adaptive algorithms for robust behavior. The cardiac pacemaker (10) includes a processing unit (120), a detector (126), and a pacing signal generator (124), the processing unit, the detector, and the pacing signal generator being electrically interconnected, the detector configured to detect cardiac electrical signals, e.g., intracardiac electrogram (IEGM) electrical signals, and transmit these signals to the processing unit (120), the processing unit configured to sense intrinsic ventricular and intrinsic atrial signals from the signals received from the detector, enable or disable sensing of the intrinsic atrial signal, and generate a ventricular pacing control signal (Vp).

Description

[Technical field]

[0001] The present invention generally relates to cardiac pacemakers, methods of operation of such pacemakers, and respective computer program products and computer readable data carriers.

[0002] A cardiac pacemaker (or artificial pacemaker) is a medical device that generates electrical pulses delivered by electrodes connected to or affixed to the pacemaker to contract the myocardial chambers (i.e., atria and / or ventricles) and thereby pump blood. In doing so, the device replaces and / or regulates the function of the heart's electrical conduction system. One purpose of a pacemaker is to maintain an adequate heart rate, either because the heart's natural pacemaker is not fast enough or because a block exists in the heart's electrical conduction system. Additionally or alternatively, the pacemaker can stimulate different locations within the ventricles to improve synchronization between the pacemaker and the ventricles or provide a defibrillation function to treat life-threatening arrhythmias. Modern pacemakers are externally programmable, allowing the healthcare provider (HCP) to select the optimal pacing mode for an individual patient.

[0003] A conventional pacemaker includes a control and generator device that includes a processing unit and power source provided outside the patient's heart and electrodes implanted in the heart muscle. The electrodes are connected to the device via leads and a header placed on the device. In most cases, the device is implanted percutaneously in the front of the chest in the area of ​​the left or right shoulder. An implantable intracardiac pacemaker (also known as an implantable leadless pacemaker (ILP)) is a miniaturized pacemaker that is implanted entirely in the ventricle (V) or atrium (A) of the patient's heart. ILPs are considered to be very important for the future of cardiac pacing. Alternative or additional functions of conventional or intracardiac pacemakers include providing other electrical or electromagnetic signals to the heart or its surrounding tissues and sensing other physiological parameters of the heart and / or its surrounding tissues, such as electrical or electromagnetic signals (e.g., signals from an electrical depolarization field), physical motion signals, or intrinsic (i.e., the heart's natural) atrial contractions or intrinsic (i.e., the heart's natural) ventricular contractions. Due to the very limited size of the device, the ILP has a small battery capacity.

[0004] The pacing function of a conventional pacemaker or ILP aims to maintain as much synchronization as possible with the heart's natural activity.

[0005] The ILP may be operated in a VDD pacing mode (i.e., a pacing mode in which the ventricles are stimulated according to the intrinsic atrial signal and monitoring of AV conduction). In the VDD mode, the pacemaker synchronizes ventricular pacing with the intrinsic atrial timing by sensing when an atrial depolarization or atrial contraction (i.e., the intrinsic atrial signal) occurs. An ILP implanted in the right ventricle can detect atrial contraction information as a far-field signal, but the reliability or accuracy of such far-field signals may be lower than that of a conventional dual chamber pacemaker that has leads in the right atrium as well as in the right ventricle.

[0006] Additionally, pacemakers are known to use a specific rate to determine the rate at which to pace the heart. The specific rate may be achieved by counting clock signals for intervals corresponding to this specific rate. The simplest pacemakers use a fixed rate, typically programmable, that meets the patient's needs under most circumstances. It is common to use a sensor-derived rate based on demand-correlated measurements such as acceleration. To replace a dysfunctional AV conduction signal, an AV-synchronous pacemaker attempts to pace the ventricles at a rate corresponding to a detected atrial signal (e.g., an atrial contraction signal or an atrial depolarization signal). It is also possible to estimate physiologically missing electrical heart rate signals from other systems in the body (e.g., the brain and baroreceptors) from other sensors.

[0007] The intrinsic rate used by all modern pacemakers is the intrinsic rate of the heart. When the intrinsic rate is near the pacing rate, the refractory period of the cardiac conduction pathways tends to block conduction of intrinsic electrical signals, but when the intrinsic signals are at a rate significantly faster than the pacing rate, these signals can be conducted and trigger heart chamber contractions. These heart chamber contractions are sensed by the pacemaker, and detection of such sensing is used to inhibit pacing.

[0008] Sudden, large changes in heart rate can induce potentially dangerous, undesirable arrhythmias and can be noticeable and uncomfortable for some patients, so such large changes in heart rate should be avoided.

[0009] Therefore, there is a need for a cardiac pacemaker that addresses the intrinsic rate changes and the inability to detect intrinsic atrial signals, and avoids large changes in pacing rate. Additionally, in the case of ILP, the pacemaker must meet challenging power consumption needs.

[0010] The above problem is solved by a cardiac pacemaker having the features of claim 1, by a method for operating a cardiac pacemaker having the features of claim 8, by a computer program product having the features of claim 14 and by a computer-readable data carrier having the features of claim 15.

[0011] In particular, the above problem is solved by a cardiac pacemaker, e.g., an ILP, for a patient's heart, the cardiac pacemaker including a processing unit, a detector, and a pacing signal generator, the processing unit, the detector, and the pacing signal generator being electrically interconnected, the detector being configured to detect cardiac electrical signals, e.g., electrical signals of an intracardiac electrogram (IEGM), and transmit these signals to the processing unit, the processing unit being configured to sense an intrinsic ventricular signal and an intrinsic atrial signal from signals received from the detector, enable or disable the sensing of the intrinsic atrial signal, generate a ventricular pacing control signal including ventricular pacing time information, and transmit the ventricular pacing control signal to the pacing signal generator for providing a pacing signal for the patient's heart, the processing unit being configured to generate the ventricular pacing control signal using a VDD mode or using at least one assist mode, and the processing unit being configured to, depending on a condition, using a VDD mode in the current cardiac cycle if intrinsic atrial signal sensing is enabled, and where pacing in the VDD mode is based on a current AV delay if an intrinsic atrial signal is sensed by the processing unit in the current cardiac cycle, or based on a current VV delay determined from a previous intrinsic ventricular and / or atrial signal if an intrinsic atrial signal is not sensed by the processing unit in the current cardiac cycle; Alternatively, using at least one assist mode in the current cardiac cycle based on a current VV delay determined from a previous VV delay or determined from another different allocation rule taking into account at least one additional parameter. This problem is solved by a pacemaker, which is designed to

[0012] The pacemaker may be a conventional cardiac pacemaker or an ILP having the general structure as described above and below. Moreover, in general, the units and components may operate at a time rate or may use a corresponding time interval. Thus, any description below of a time interval should be understood to refer to a rate as well, and vice versa.

[0013] In the context of the present invention, a processing unit is generally considered to be a functional unit of the pacemaker that interprets and executes instructions, including an instruction control unit and an arithmetic and logic unit. The processing unit may include or be a microprocessor, a controller, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a discrete logic circuit, or any combination thereof. Alternatively or additionally, the processing unit may be realized using integrated dedicated hardware logic circuits due to the small size and extreme power limitations, especially in the case of ILP.

[0014] The processing unit processes the signal data received from the detector, for example the electrical signals of the patient's heart detected over time. In particular, the detector may be configured to detect time-dependent depolarization and repolarization field electrical signals, such as an electrocardiogram (ECG) or an intracardiac electrogram (IEGM). These signals may include signals caused by depolarization of the atria (hereinafter intrinsic atrial signals) and electrical signals caused by depolarization of the ventricles (hereinafter intrinsic ventricular signals). In the case of an ILP, the intrinsic atrial signals may be far-field electrical signals. The detector may pre-process these data, for example digitizing the signals, filtering the signals, and / or amplifying the signals.

[0015] A processing unit to which the detector's electrical signals are transmitted perceives intrinsic ventricular and intrinsic atrial signals from the electrical signals, e.g., intrinsic atrial signals from the P waves and intrinsic ventricular signals from the QRS waves. Since the amplitude of the electrically measured P waves in the far field is very small compared to the near field ventricular signals, a large amplification can be used within the time period of the signal where the P waves are expected, compared to the time intervals of the QRS and T waves.

[0016] In VDD pacing mode (i.e., a pacing mode in which the ventricles are stimulated according to monitoring of atrial activity and AV conduction), the ILP or conventional pacemaker is operated normally. In VDD mode, the pacemaker synchronizes ventricular pacing with the intrinsic atrial signal based on the current AV delay. In an ILP implanted in the right ventricle, atrial contraction information can be detected as a far-field signal as described above.

[0017] The processing unit may further include a counter and a clock. In one embodiment, the clock may run at 128 Hz. The counter may be used to count the clock signals of the clock. The counter may start at the sensing of every atrial or ventricular depolarization and count the number of clock signals until the next atrial or ventricular depolarization occurs or until ventricular pacing is provided by the pacing signal generator. In the VDD mode, the processing unit may determine the VV delay of the actual cardiac cycle corresponding to the actual heart rate from the intrinsic atrial signal and the intrinsic ventricular signal or from the ventricular pacing signal. For example, the "current (average) VV delay" may be determined as the average of the previous VV delay of the previous cardiac cycle and the VV delay of the actual cardiac cycle. In one embodiment, the VV delay of the actual cardiac cycle and the VV delay of the previous cardiac cycle are used to determine the current VV delay only if at least one intrinsic signal (the intrinsic atrial signal or the intrinsic ventricular signal) was used to determine the VV delay of the respective cardiac cycle. The current VV delay may be used to provide a ventricular pacing control signal including a ventricular pacing time, which may then be transmitted to a pacing signal generator.

[0018] The pacing signal generator generates an electrical pacing signal based on the pacing control signal and delivers the electrical pacing signal to the electrode, which applies the signal to the cardiac tissue adjacent to the electrode. The pacing signal is a pulse that starts at a desired time and has a desired intensity and duration. Furthermore, the waveform of the pulse can be varied. Information about the pacing signal, e.g., a ventricular pacing signal, required to generate the correct pacing signal is provided by a pacing control signal, e.g., a ventricular pacing control signal, of the processing unit or by the pacing signal generator itself. In particular, the ventricular pacing control signal provides time information of the pacing signal, i.e., information about when the pacing signal should be immediately delivered to the patient's heart, e.g., that pacing should be delivered without further delay. In one embodiment, if an intrinsic ventricular signal is detected within a predetermined time period (e.g., AV delay) after an intrinsic atrial signal is detected in VDD mode, the pacing signal is not determined (i.e., inhibited) or is not delivered to the electrode.

[0019] The pacemaker may include a data memory, which may include any volatile, non-volatile, magnetic, or electrical medium, such as a random access memory (RAM), a read-only memory (ROM), a non-volatile RAM (NVRAM), an electrically erasable programmable ROM (EEPROM), a flash memory, or any other memory device. The data memory stores the thresholds and conditions described above and below, which are required by the processing unit during the processing of the steps described above and below.

[0020] The detector may further include an accelerometer, a vibration sensor, an acoustic sensor (including ultrasound), and / or any other mechanical, electrical, and / or magnetic sensor capable of detecting the patient's activity as a function of time (i.e., a motion sensor), e.g., including motion, whether the patient is moving or not, e.g., sleeping, sitting, moving quickly, or moving slowly. The detector collects and converts the patient's activity signal into an electrical signal. Furthermore, the detector may digitize, filter, and / or smooth the analog signal to reduce signal noise. Some pre-processing steps may also be provided by the detector. The time-dependent motion signal generated by the detector is preferably transmitted directly to the processing unit.

[0021] The pacemaker may include further modules, such as a communication unit for communicating with a remote computer, and a power source, such as a battery. The communication unit may exchange messages, for example, unidirectionally or bidirectionally, with an external (at least partially outside the body) remote computer. The communication may be provided through the patient's body, preferably by acoustic conduction and / or magnetic coupling, and / or through the air, using electromagnetic waves, for example, using Bluetooth, WLAN, ZigBee, NFC, Wibree, or WiMAX in the radio frequency domain, or using IrDA or free space optical communication (FSO) in the infrared or optical frequency domain, or by wires (electrical and / or optical communication). The remote computer is a functional unit capable of performing substantial calculations involving numerous arithmetic and logical operations without human intervention, such as, for example, a personal mobile device (PMD), a desktop computer, a server computer, a cluster / warehouse scale computer, or an embedded system. The pacemaker units and components may be housed in a hermetically sealed housing.

[0022] In one embodiment, the pacemaker includes electrodes for applying the electrical pacing signals provided by the pacing signal generator. The electrodes are electrically connected to the pacing signal generator via the header of the pacemaker. In one embodiment (i.e., when the pacemaker is a conventional pacemaker), the electrodes can include leads that can be removably connected to the respective connectors of the header. With respect to the ILP, one electrode can be located at the distal end of the ILP in the vicinity of a fixation member by which the ILP is fixed to the tissue of the patient's heart, for example against the tissue of the ventricle or inside the tissue of the ventricle. The second electrode can be located at the proximal end of the ILP or, for example, in a part of the ILP housing that can function as a counter electrode. Furthermore, the electrodes can be adapted to detect the intrinsic ventricular or intrinsic atrial signals over time, in each case, by tapping the electrical potential. Thus, the electrodes can be part of the detector of the pacemaker.

[0023] The processing unit may be adapted to control pacing of the right ventricle normally in VDD mode based on the sensed intrinsic atrial signal of the current cardiac cycle if sensing of the intrinsic atrial signal (i.e., atrial tracking) is enabled.

[0024] Typically, the pacing mode supported by the pacemaker is VDD. This mode assumes that the patient has either a form of complete or intermittent AV block. The sinus node is assumed to be generally normal, and VDD mode attempts to track sinus rhythm to provide AV synchrony. If an inherent atrial signal is identified by the processing unit, a time interval "current AV delay" is initiated, for example by counting down a respective counter that counts clock signals. If an inherent ventricular signal is perceived by the processing unit within the current AV delay, pacing is inhibited. If the AV delay expires without detecting an inherent ventricular signal, a ventricular pacing control signal is generated and transmitted to the pacing signal generator, which causes a respective pacing of the patient's heart (except in the case of hysteresis). The current AV delay may be determined based on the current VV delay (see above) and may be set to the normal time difference between an inherent atrial contraction or depolarization and an inherent ventricular contraction or depolarization. The current AV delay may be determined from the current VV delay by known calculations or using a look-up table contained in a data memory. The current AV delay varies with the current (average) VV delay. As noted above, the VV delay represents the time between two successive ventricular contractions, where the contractions are either intrinsic or pacing-generated contractions.

[0025] However, in VDD mode, if no intrinsic atrial signal is identified within the current cardiac cycle, the current VV delay is used to generate a ventricular pacing control signal. The countdown of the current VV delay is initiated by the most recently sensed intrinsic ventricular signal or pacing signal. If an intrinsic atrial signal is seen, the counting of the AV delay initiated by this atrial signal takes precedence. If no intrinsic atrial signal is detected, the counting of the current VV delay is "stepped in." If no intrinsic ventricular signal is seen, a pacing control signal is generated as soon as the current VV delay expires, causing a corresponding pacing of the patient's heart. If an intrinsic ventricular signal is seen and the AV delay has not expired, pacing is inhibited. The same applies to the current VV delay (if no intrinsic atrial signal is sensed and therefore no AV delay is counted), i.e., if the current VV delay has not expired and an intrinsic ventricular signal is seen, pacing is inhibited.

[0026] The qualification for using the VV interval to determine the current VV delay is that the measured VV interval should only be used from intrinsic sensing, i.e., VV intervals involving either an atrial signal or a ventricular signal, or both. If there is no intrinsic timing information in a cycle, the VV interval is not used to determine the current VV delay and therefore the pacing rate. If the cycle had an intrinsic atrial signal or ended with an intrinsic ventricular signal, then the cycle was an intrinsic cycle. A cycle with an intrinsic atrial signal provides phase information but not necessarily rate information. Two consecutive intrinsic cycles also provide rate information, which qualifies the use of the VV interval to determine the current VV delay.

[0027] If certain predefined conditions apply, the processing unit will exit the VDD mode and use at least one assist mode for pacing. For example, the VDD mode may be exited or not used if synchronization with the intrinsic atrial and / or ventricular signals is lost after a predefined time or number of cardiac cycles (i.e., if the atrial and / or ventricular signals are not sensed by the processing unit), if the actual cardiac rate (the determined VV delay of the actual or immediately preceding cardiac cycle) is greater than a predefined threshold, or if a transition back to the VDD mode is attempted. In the at least one assist mode, the current VV delay is determined from a previous VV delay taking into account at least one additional parameter, or is determined from another different allocation rule. The other different allocation rule may be based on signals of other sensors than the intrinsic atrial or ventricular signals, e.g., motion signals, or may be based on setting the current VV delay to a predefined value, or may be based on ramping the current VV delay to a predefined target value.

[0028] In one embodiment, the first assist mode is a VVI mode and the second assist mode is a sensor mode, in which in the VVI mode the processing unit is configured to determine the current VV delay from the base rate, and in which in the sensor mode the processing unit is configured to determine the current VV delay based on a signal of a sensor of a detector that detects a signal different from the intrinsic ventricular signal and the intrinsic atrial signal, e.g., a motion signal, when the sensing of the corresponding sensor signal is enabled. Thus, the sensor mode is similar to the VVI(R) mode, in which the current VV delay is determined, e.g., by adapting the current VV delay based on the dynamics of the patient's motion. Whether the first assist mode or the second assist mode is used depends on whether the second assist mode is enabled by respective programming or predefined settings. The base rate is the minimum rate that the patient should have during pacing. The current VV delay from the base rate is determined as an interval corresponding to the base rate. The current VV delay in the second assist mode is determined depending on the strength of the patient's motion as perceived from the sensor's motion signal. If no motion is detected, the current VV delay is determined using the resting rate. If the patient's motion has a certain strength, the corresponding current VV delay can be determined using a certain calculation or using a stored value in a look-up table. As described below, the current VV delay may be determined by ramping up or down the VV delay, in which case the VV delay value corresponding to the strength of the patient's actual motion becomes the target value if the difference to the VV delay of the actual cardiac cycle is too large. The same applies to other sensor signals different from the motion signal as well. In one embodiment, in the sensor mode, the perception of the intrinsic atrial signal is disabled, i.e. atrial tracking is disabled, since atrial tracking has a certain energy demand. Furthermore, in the sensor mode, the sensor is configured to detect a corresponding signal.

[0029] In this embodiment, in a pacemaker, for example in an ILP, the VDD mode and one of the first and second assist modes are generally mutually exclusive because the power budget to do both would be prohibitive for devices with such small batteries. Therefore, both modes, i.e., the VDD mode and the assist mode, are treated as complementary timing mechanisms. The second assist mode works more reliably at higher rates, where the VDD mode is problematic because of the temporal intermixing of atrial signals with larger amplitude ventricular signals. The VDD mode provides AV synchronization and is therefore more hemodynamically efficient.

[0030] In one embodiment, in the VDD mode or the second assist mode, if no intrinsic ventricular signal is sensed within the time interval of the current VV delay, the current VV delay may be extended by a first hysteresis delay, and this extension is provided for a predetermined number of consecutive cardiac cycles during which no intrinsic ventricular signal is sensed. The hysteresis delay may be, for example, between 50 ms and 100 ms. The predetermined number of consecutive cycles during which no intrinsic ventricular signal is sensed may be between 3 and 10. Both values ​​may be hard coded or programmable by the HCP using a programmer. By extending the VV delay, the pacing rate is automatically reduced because a pacing control signal is generated by the processing unit when this VV delay extended (stretched) by the hysteresis delay expires and during which no intrinsic ventricular signal has been sensed (i.e., within this cardiac cycle). It is assumed that a sudden drop in the intrinsic heart rate or loss of AV conduction has occurred.

[0031] In one embodiment, the processing unit includes a hysteresis component, which provides a first hysteresis delay for the VDD mode and the second assist mode. Alternatively or additionally, a second hysteresis delay for the VDD mode to extend the AV delay can be provided by the hysteresis component. The second hysteresis delay can be equal to or different from the first hysteresis delay. The second hysteresis delay can be, for example, between 50 ms and 100 ms. The second hysteresis delay extends the AV delay, such that a ventricular pace (and pacing control signal) is provided only if the AV delay extended by the second hysteresis delay expires and no intrinsic ventricular signal has been sensed within the cardiac cycle. This encourages ventricular sensing in the VDD mode. The hysteresis delay value may be shorter than typical AV hysteresis values ​​used in DDD pacemakers to avoid unnecessary ventricular pacing. In atrial tracking in VDD mode, the interval source is the current average ventricular interval (VV delay). The atrial signal in an AV-synchronized ventricular ILP is a far-field signal, which may be qualified by where it occurs in the cardiac cycle to avoid being overwhelmed by ventricular artifacts. Such sense detection is essentially unavailable for some cardiac cycles. When in atrial tracking in VDD, the most recently measured and averaged VV interval (current VV delay) may be used as the pacing rate to "fill in" or "compensate" for missed atrial senses (see above). In the presence of intermittent intrinsic AV conduction, the extended hysteresis with a second hysteresis delay may help to avoid competitive pacing for cardiac cycles with AV conduction.The hysteresis component can include a hysteresis logic component that is used to track whether the pacemaker should use hysteresis extensions, such as the first hysteresis delay and the second hysteresis delay, for any given cycle. Thus, the hysteresis logic component includes a counter for counting consecutive cardiac cycles in which no intrinsic ventricular signal is present. Additionally, the hysteresis component can include a hysteresis timer component for providing the correct time for the first hysteresis delay and the second hysteresis delay at the end of the AV delay or the current VV delay, respectively, if no intrinsic ventricular signal has occurred so far within the respective cardiac cycle.

[0032] In one embodiment, the processing unit is configured to use a first subsequent mode, i.e., a rate fading mode, starting from the next cardiac cycle following a predetermined number of consecutive cardiac cycles in which the first hysteresis delay provides an extension of the current VV delay and in which no intrinsic ventricular signal is sensed in the VDD mode or the second assist mode (i.e., the next cardiac cycle follows immediately after the predetermined number of consecutive cardiac cycles), in which the VV delay is ramped up (i.e., the rate corresponding to the VV delay is ramped down) from the current VV delay until it reaches the VV delay corresponding to the basic rate or the current sensor rate. This means that the basic rate and the current sensor rate respectively form a target rate for the rate fading process. This embodiment is based on the consideration that after a predetermined number of consecutive cycles in which no intrinsic ventricular signal is sensed (this number may be, for example, between 3 and 10, counted by the counter mentioned above), the current VV delay is no longer applicable to the patient's current situation and must be considered out of date. Thus, the processing unit ramps up the VV delay (or ramps down the pacing rate) since the inherent heart rate drop still appears to be present. For example, by using a rate limiter component as follows, the rate (corresponding to the VV delay) can be ramped down by approximately 0.5 bpm (the decrement rate change value) in each step (e.g., each cardiac cycle). This can be accomplished using three different slopes (based on a resolution of 7.8125 ms or 128 Hz), each in a different rate region. If the current VV rate is less than or equal to 40, the decrement value is the current VV delay divided by 8 minus 16, and if the rate is greater than 40 but less than 80, the decrement value is the current VV delay divided by 16 minus 4. If the rate is greater than or equal to 80, the decrement value is the current VV delay divided by 32 minus 1.

[0033] Alternatively or additionally, the rate interval can be incremented in 7.8125 ms units by adding 1 / 64 of the current interval to the current interval (if the rate is less than 120 bpm, one additional unit is added).

[0034] As mentioned above, the basic rate is the minimum pacing rate that should be used for the patient. The resting rate is the rate that the patient should have if the patient is at rest. The resting rate is usually higher than the basic rate. In one embodiment, the basic rate is used as the target rate for the VDD mode, and the current sensor rate is the target rate for the second assist mode (sensor mode). The minimum sensor rate is the resting rate. If the current motion signal received by the processing unit indicates that the patient is not at rest and is moving, the sensor rate is correspondingly larger. The basic rate and / or the resting rate may be predefined or may be programmable by the HCP for a particular patient, for example, by using a programmer.

[0035] Rate fading is a subsequent mode that recognizes when a sudden drop in the intrinsic rate occurs. In VDD mode with VV delay, this sudden drop can be the result of either a malfunction of the sinus node or the AV conduction pathway. If atrial tracking is supported, the malfunction of AV conduction is addressed by the atrial tracking algorithm as described above, but a malfunction of sinus rhythm can still result in a sudden drop in the intrinsic rate. According to one embodiment, the sinus rhythm degradation while in atrial tracking state can be addressed by recognizing the absence of intrinsic sensing and switching to a non-atrial tracking mode (VDD mode with VV delay tracking, first assist mode, or second assist mode). This means that during rate fading mode, the perception of the intrinsic atrial signal is disabled. In terms of power and space efficiency, this feature is realized as described above by using the rate management known from the sensor mode with some small additions (see above).

[0036] In one embodiment, the processing unit switches to a second subsequent mode, i.e., FindSync mode, in which the processing unit seeks to sense an intrinsic atrial signal and an atrial tracking opportunity when the current VV delay corresponds to a basic rate or a resting rate over a predefined time interval in rate fading or sensor mode. The FindSync (short for "find synchronization") state defines a behavior that provides basic support while attempting to encourage detection of intrinsic activity. The FindSync state is a hybrid state between atrial tracking (VDD) state and non-atrial tracking (VVI) state. In the absence of intrinsic sensing, the FindSync state provides an asynchronous (i.e., intrinsic atrial signal and intrinsic ventricular signal are not synchronized) mode, in which the pacing rate is the resting rate regardless of what the undetected intrinsic heart rate may be. If intrinsic atrial signals are detected, they initiate an AV delay (determined from the resting rate), which serves for a phase shift to align the pacemaker activity with the heart activity. Detecting only one intrinsic atrial signal does not provide enough information to allow rate matching between the pacemaker and the heart. If two consecutive cardiac cycles both contain either intrinsic atrial or ventricular signals, the VV interval between these cycles can be measured and used as the VV delay (corresponding to the pacing rate), which ensures that both the phase and rate of the heart and the pacemaker are aligned, and thus the ventricular pace can be delivered synchronously with the intrinsic heart signal. A condition indicating that pacing is locked to the intrinsic rate returns the pacemaker to VDD mode.

[0037] In one embodiment, the processing unit includes a rate limiter component that determines a current rate for ramping the current VV delay in rate fading mode or for adapting the current VV delay to the detected sensor signal in sensor mode, and provides a fixed attack rate change value and a fixed decrement rate change value as described above, which define step sizes in the attack and decay directions, respectively. An example for the decrement rate change value is provided above, and the attack rate change value may be, for example, 2 bpm. Both rate change values ​​may be predefined in the pacemaker or may be user selectable by the HCP using the programmer. The attack rate change value may be approximated by dividing the current VV delay by 64.

[0038] Above, it was shown that a rate change limit can be provided to ramp the current VV delay (corresponding to the pacing rate) in the rate fading mode. Additionally, a rate change mechanism (or, equivalently, an interval change mechanism) can be used to adapt the VV delay to the current motion signal received by the processing unit. As in the VVI(R) mode, the time interval of the current VV delay is changed 1) to a longer interval if the current motion signal indicates that the patient's motion is decreasing, 2) to a time interval corresponding to the resting rate if the motion signal indicates that the patient is resting, and 3) to a shorter interval if the current motion signal indicates that the patient's motion is increasing.

[0039] The rate limiter component is responsible for providing rate transitions, where the rate change is limited to a predefined attack rate change value or a predefined decrement rate change value. The target rate for the transition is referred to as the target rate. Each step towards the target is at the next rate, and a step occurs every cardiac cycle. The rate limiter component can operate on intervals rather than rates. The attack change interval and the decrement change interval can be rate dependent. The maximum delta (up or down) for the next cardiac cycle interval is calculated by the rate limiter component based on the current VV delay. In one embodiment, the current VV delay that can be applied for the rate transition can be limited to an upper tracking interval. The current VV delay is compared to the target interval by the rate limiter component to know if the rate needs to be accelerated or decelerated to move towards the target interval at the maximum allowed rate of change. The next interval output is determined from the current rate and the maximum step allowed in one cardiac cycle. The significance or importance of this attack / decay limiting component is to prevent oscillations when tracking / approaching the target rate. The allowed step size is typically larger than the resolution of the target interval. To prevent such oscillations that may unnecessarily use extra power from the battery, the logic of the rate limiter component can track when the target value transitions from attack to decay or vice versa. When this transition occurs, the next step can be set accurately to the target interval. To be used correctly, the rate limiter component can first be initialized, which sets the current VV delay to the current pacing interval, i.e., the last interval used in the previous mode or in the state of the previous mode (e.g., if the patient's motion activity is changing). This provides an automatic, gradual transition from the previous source interval to the new source interval. The rate limiter component may be used in sensor mode or rate fading mode.

[0040] To adapt the rate limiter component to different modes of the processing unit, an interval source (rate source) can be selected for the target interval (target rate). This selection may be provided by a rate limiter target selection component of the processing unit. Possible sources for this selection may include a sensor-derived interval (e.g., from a motion sensor in sensor mode, corresponding to the patient's actual motion intensity) or an interval corresponding to a lower rate, such as a resting rate or a base rate in rate fading mode. The selection of the target interval is provided based on the current mode of the pacemaker.

[0041] In one embodiment, the processing unit includes a rate multiplexer component that selects an appropriate pacing rate corresponding to a current VV delay depending on the current mode of the processing unit. In sensor mode, VVI mode, rate fading mode, or FindSync mode, a lower rate such as a resting rate or a basic rate can be selected if certain conditions apply. In VDD mode, the current (average) VV delay is selected. Furthermore, in sensor mode or rate fading mode, a VV delay (interval) corresponding to a rate determined by a rate limiter component can be selected.

[0042] In one embodiment, the processing unit is configured to allow the HCP to select the sensor mode and / or the VVI mode as the normal mode using the programmer. Thus, atrial tracking is not permitted. The processing unit is adapted to generate ventricular pacing control signals based on the sensor mode or the VVI mode, respectively. The processing unit does not use the VDD mode selected by the clinician in this state, and thus the FindSync mode is not enabled for atrial tracking.

[0043] The above problem is a method of operating a cardiac pacemaker, e.g., an ILP, for a patient's heart, the cardiac pacemaker including a processing unit, a detector, and a pacing signal generator, the processing unit, the detector, and the pacing signal generator being electrically connected to each other, the detector detects cardiac electrical signals, e.g., electrical signals of an intracardiac electrogram (IEGM), and transmits them to the processing unit, the processing unit senses an intrinsic ventricular signal and an intrinsic atrial signal from the signal received from the detector, the processing unit can enable or disable the sensing of the intrinsic atrial signal, the processing unit generates a ventricular pacing control signal including ventricular pacing time information, and transmits it to the pacing signal generator for generating a pacing signal for the patient's heart, the ventricular pacing control signal is generated using a VDD mode or using at least one assist mode depending on a condition, if intrinsic atrial signal sensing is enabled, then VDD mode is used in the current cardiac cycle, and pacing in VDD mode is based on a current AV delay if an intrinsic atrial signal is sensed by the processing unit in the current cardiac cycle, or based on a current VV delay determined from a previous intrinsic ventricular and / or atrial signal if an intrinsic atrial signal is not sensed by the processing unit in the current cardiac cycle; Alternatively, at least one assist mode is used in the current cardiac cycle based on a current VV delay determined from a previous VV delay or determined from another different allocation rule taking into account at least one additional parameter. The problem is further solved by the method.

[0044] In one embodiment of the method, the first assist mode is a VVI mode and the second assist mode is a sensor mode, where in the VVI mode the current VV delay is determined from the base rate and in the sensor mode the current VV delay is determined based on a signal, e.g., a motion signal, of a detector sensor that detects a signal different from the intrinsic ventricular signal and the intrinsic atrial signal when sensing of the corresponding sensor signal is enabled.

[0045] In one embodiment of the method, in the VDD mode or the second assist mode, if no intrinsic ventricular signal is perceived within the time interval of the current VV delay, the current VV delay is extended by a first hysteresis delay, which extension is provided for a predetermined number of consecutive cardiac cycles during which no intrinsic ventricular signal is perceived; additionally or alternatively, in the VDD mode, a second hysteresis delay is used to extend the AV delay, and the first hysteresis delay and / or the second hysteresis delay may be provided, for example, by a hysteresis component of the processing unit.

[0046] In one embodiment of the method, a first subsequent mode, i.e., a rate fading mode, is used, starting from the next cardiac cycle following a predetermined number of consecutive cardiac cycles in which an extension of the VV delay is provided by the first hysteresis delay and no intrinsic ventricular signal is perceived in the VDD mode or the second assist mode, and in the rate fading mode, the VV delay is ramped up from the current VV delay to a VV delay corresponding to the base rate or the current sensor rate.

[0047] In one embodiment, the method switches to a second subsequent mode, i.e., FindSync mode, in which the processing unit seeks to perceive an intrinsic atrial signal and an atrial tracking opportunity when the current VV delay corresponds to the basic rate or resting rate over a predetermined time interval in rate fading mode or sensor mode.

[0048] In one embodiment, the rate limiter component determines a current rate for ramping the VV delay in rate fading mode or a current rate for adapting the current VV delay to the detected sensor signal in sensor mode, and provides an attack rate change value and a decrement rate change value.

[0049] The above embodiment of the operating method has the same advantages as the above pacemaker, which may be implemented in the operating method as well, see the above description of the pacemaker in this regard.

[0050] The above method is, for example, realized as a computer program comprising instructions which, when executed, cause a processing unit (processor) to perform the steps of the above method (to be executed by the cardiac pacemaker, in particular in its processing unit); this computer program is a combination of computer instructions and data definitions as specified above and below, enabling computer hardware to perform a computational or control function, or this computer program is a syntactic unit conforming to the rules of a particular programming language, consisting of declarations and statements or instructions required to solve a function, task or problem as specified above and below.

[0051] Further disclosed is a computer program product comprising instructions which, when executed by a processing unit, cause the processing unit to perform the steps of the above method. Accordingly, disclosed is a computer readable data carrier having such a computer program product stored thereon.

[0052] The above pacemakers, methods, computer programs, and computer program products provide a common rate management design implementing different programmed pacing modes and managing dynamic assist and follow-on modes. Additionally, the solution according to the invention provides dynamic selection of rate (interval) source based on programmed mode conditions, rate source driven control of rate change limit or instantaneous rate change, integration of rate source selection and rate smoothing functions, sharing of common mechanisms for rate limit and rate slope change for different modes, and use of hysteresis delay to trigger rate fading behavior.

[0053] In the following the invention will be explained in more detail with reference to the accompanying schematic drawings. [Brief description of the drawings]

[0054] [Figure 1] FIG. 1 illustrates a first embodiment of a pacemaker in cross-section of a patient's heart. [Diagram 2] FIG. 2 is a functional block diagram of the pacemaker shown in FIG. 1. [Diagram 3] FIG. 2 is an enlarged side view of the pacemaker of FIG. 1. [Figure 4] 2 is a block diagram showing components of a processing unit visualizing pacemaker timing and rate management in different modes of the pacemaker of FIG. 1. [Diagram 5] FIG. 2 shows rate behavior over time in VDD mode (without atrial tracking) around a sudden drop in heart rate provided by the processing unit of the pacemaker of FIG. 1. [Figure 6] FIG. 2 shows rate behavior over time in sensor mode around a sudden drop in heart rate provided by the processing unit of the pacemaker of FIG. 1.

[0055] In the following, the invention will be described with reference to an ILP, although the invention may be implemented in conventional pacemakers as well.

[0056] FIGURE 1 illustrates an exemplary leadless ventricular pacemaker (ILP) 10 implanted in a heart 20 of a patient 30. The exemplary ILP 10 is depicted in an expanded view in FIGURE 3. The ILP 10 may have a distal end 10a and a proximal end 10b and may be configured for implantation in a right ventricle 21 of the heart 20 and configured to pace the ventricle, sense intrinsic ventricular depolarizations and intrinsic atrial depolarizations (e.g., in the right atrium 22), and inhibit ventricular pacing in response to a detected intrinsic ventricular signal in a VDD mode. A programmer (not shown) can be used to program and acquire data from the ILP 10. The ILP 10 is one example of a cardiac pacemaker 10. Other embodiments of the cardiac pacemaker 10 are possible.

[0057] FIG. 2 shows a functional block diagram of the circuit 101 of the ILP 10 configured to be implanted in the ventricle 21 (FIG. 1). The circuit 101 of the ILP 10 includes a processing unit 120 with a clock providing a clock signal, preferably between 100 and 200 Hz, particularly preferably 128 Hz, a counter for the clock signal, and a register, a data memory 122, which may include a register, a pacing signal generator 124, a detector 126, a communication unit 128, and a power source 132. The power source 132 may be electrically connected to one or more of the other components 120, 122, 124, 126, 128 (not shown in FIG. 2) and may include a battery, for example a rechargeable or non-rechargeable battery. The power source supplies electrical energy to all units and components of the ILP 10, in particular to all the above-mentioned units, and is therefore electrically connected to these units and components. The above-mentioned units included in the ILP 10 represent their respective functions. Similar or identical units and functions may also be included in the ILP 10. The units of the pacemaker of the present disclosure may include any discrete and / or integrated electronic circuit components implementing analog and / or digital circuits capable of generating the functions attributed to the units herein. For example, the units may include analog circuits, such as amplification circuits, filtering circuits, and / or other signal conditioning circuits. The units may also include digital circuits, such as combinational or sequential logic circuits, memory devices, etc. The units may further be realized using integrated dedicated hardware logic circuits. The data memory 122 may include any volatile, non-volatile, magnetic, or electrical media described above. Furthermore, the processing unit 120 may include instructions that, when executed by one or more processing circuits, cause the units to perform the various functions attributed to the units herein. The functions attributed to the units or components herein may be embodied as one or more processors, hardware, firmware, software, or any combination thereof.The depiction of different features as units or components is intended to highlight different functional aspects and does not necessarily imply that such units must be realized by separate hardware or software components. Rather, functionality associated with one or more units or components may be performed by separate hardware or software components or may be integrated within a common or separate hardware or software component. The data memory 122 may store computer-readable instructions that, when executed by the processing unit 120, cause the processing unit 120 to perform different functions attributed to the processing unit 120 herein. Additionally, the data memory 122 may store parameters related to these functions, such as pacing signal parameters, conditions, and thresholds described above and below. The pacing instructions and pacing signal parameters, conditions, and thresholds may be updated by a programmer using the communication unit 128. The communication unit 128 may include an antenna or a transceiver.

[0058] The processing unit 120 can be in communication with the pacing signal generator 124 and the detector 126, thereby transmitting signals. The pacing signal generator 124 and the detector 126 are electrically coupled to the electrodes 111, 112 of the ILP 10. The detector 126 is configured to monitor signals from the electrodes 111, 112 to detect electrical activity of the heart 20. Additionally, the detector 126 can include a motion sensor, such as an accelerometer or any other motion sensor described above. The motion sensor collects a time-dependent motion signal as described above and transmits the signal to the processing unit 120. The pacing signal generator 124 is configured to deliver an electrical stimulation signal to the ventricle 21 via the electrodes 111, 112. The processing unit 120 can control the pacing signal generator 124 to generate and transmit electrical stimuli to the ventricle 21 via the electrodes 111, 112. The electrical stimuli can include pacing pulses.

[0059] The electrode 112 is located where the mechanical connector resides, which means that in a preferred or practical construction embodiment, it is not easy to place the electrode 112 at the most proximal end (as shown in Figure 3). A better approach would be to provide a ring-shaped electrode near the proximal end, rather than at the absolute extreme end of the device.

[0060] The processing unit 120 can control the pacing signal generator 124 to deliver electrical stimulation therapy according to one or more therapy programs that include pacing parameters, which may be stored in the data memory 122 or may be hard-coded within the processing unit 120.

[0061] The detector 126 may further include circuitry for acquiring time-dependent electrical signals from the heart including the intrinsic cardiac electrical activity (e.g., electrical depolarization and repolarization signals). The detector 126 may filter, amplify, and digitize or otherwise preprocess the acquired electrical signals of the heart chamber contractions. The processing unit 120 may receive the intrinsic electrical signals generated by the detector 126 and perceive the intrinsic atrial and intrinsic ventricular signals of the patient's heart.

[0062] The processing unit 120 can evaluate the intrinsic atrial and intrinsic ventricular signals received from the detector 126 and is configured to determine the intrinsic interval between two successive ventricular signals (at least one of which is an intrinsic ventricular signal) or the intrinsic AV interval (the interval between an intrinsic atrial signal and a subsequent ventricular signal).

[0063] The ILP 10 can include a housing 105, fixed tines 107, and electrodes 111, 112. The housing 105 can have a pill-shaped, cylindrical form factor in some examples. The fixed tines 107 are configured to connect (e.g., anchor) the ILP 10 to the heart 20. The fixed tines 107 can be fabricated from a shape memory material, such as Nitinol. In some examples, the fixed tines 107 can connect the ILP 10 to the heart 20 within one of the chambers of the heart 20. For example, as shown and described herein with respect to FIG. 1, the fixed tines can be configured to anchor the ILP 10 to the heart 20 within the right ventricle 21. Although the ILP 10 includes a plurality of fixed tines 107 configured to anchor the ILP 10 to cardiac tissue within the right ventricle, it is contemplated that a pacemaker according to the present disclosure may be anchored to cardiac tissue in other chambers of the patient's heart 20 using other types of anchoring mechanisms.

[0064] The ILP 10 may include two electrodes 111, 112, although in other examples, the pacemaker may include more than two electrodes. The electrodes 111, 112 may be spaced apart from each other by a sufficient distance to be able to detect different electrical signals generated by the heart 20, such as P waves generated by the atria and QRS waves generated by the ventricles. For example, the first electrode 111 is disposed at the distal end 10a of the ILP 10 and the second electrode 112 is disposed at the proximal end 10b of the ILP 10. The housing 105 houses the electronic components (circuit 101) of the ILP 10. The electronic components may include any discrete and / or integrated electronic circuit components implementing analog and / or digital circuits capable of generating the functions belonging to the ILP 10 described above and below.

[0065] A communication unit 128 of the circuitry 101 can enable the ILP 10 to communicate with other electronic devices, such as a programmer or other external patient monitor. In some examples, the housing 105 can house an antenna or transceiver for wireless communication. The housing can also include a power source 132.

[0066] The processing unit 120 may be adapted to control the pacing of the right ventricle 21 in the VDD mode based on an intrinsic atrial signal including atrial contractions and an intrinsic ventricular signal indicative of ventricular contractions. Alternatively, the assist mode can be used by the processing unit 120 if the VDD mode is found not to be appropriate for an individual patient in the current situation, e.g. with respect to the detected electrical signals or the patient's motion state.

[0067] Processing unit 120 provides synchronization and timing for ventricular pacing and inhibition based on clinical programming and sensed intrinsic timing from the heart (e.g., sensed electrical signals from the heart) provided by detector 126. Additionally, detector 126 can provide detected time-dependent motion signals and transmit these to processing unit 120.

[0068] In one embodiment, the first assist pacing is a (non-atrial tracking mode) similar to the VVI mode, and the second assist mode is a sensor mode similar to the VVI(R) mode. Other assist pacing modes (e.g., VOO) may be supported as test modes or for other different situations. Sensor mode can only be used if motion-based rate response is enabled (e.g., by the HCP using the programmer).

[0069] The VDD mode allows an atrial tracking mode, i.e., tracking of the intrinsic heart timing, when an atrial or ventricular sense or both are detected. When an atrial sense is detected, it resynchronizes the cycle by initiating an AV delay, where the AV delay is determined using the current VV delay and a look-up table contained in the data memory 122. The next cycle is initiated when a ventricular sense is detected or when a ventricular pace is delivered at the end of the AV delay. By prioritizing AV conduction when it occurs, improved hemodynamics can often be achieved, even at the expense of a longer than normal AV interval. The second hysteresis delay described above can be used to extend the AV delay to support scanning of intrinsic AV conduction and to sustain intrinsic AV conduction that may otherwise be masked by pacing using standard timing according to the AV delay.

[0070] The VDD pacing mode in the preferred normal mode may be R-synchronous in ILP10, which means that every cycle is synchronized by every used ventricular event (i.e., by an intrinsic ventricular contraction or ventricular pacing). The time interval between ventricular events (VV interval) is measured. In the VDD mode, atrial tracking is provided, which means that the timing can be shifted by every sensed atrial contraction. In other words, the VDD mode is both R-synchronous and P-synchronous. The timing of the next potential ventricular pacing signal is scheduled based on the most recent ventricular event and the pacing interval (e.g., VV delay). A sensed atrial contraction "reschedules" the next pacing signal by starting an AV interval.

[0071] The first assist mode may be used by the ILP for pacing that acts similar to VVI pacing. Alternatively, if enabled by the HCP, a sensor mode may be used, to which the processing unit 120 automatically switches if AV synchrony is not achieved for a relatively long interval (e.g., 5-10 cycles without any intrinsic atrial or ventricular signals detected). The sensor mode operates similarly to VVI(R) pacing and uses a signal provided by the detector motion sensor. If the motion sensor indicates that the patient only requires resting rate cardiac support, the algorithm of the processing unit 120 may be configured to automatically return to VDD mode, for example, after a period of time, and attempt to establish AV synchrony in a subsequent FindSync mode.

[0072] VDD mode uses the continuously measured certified VV interval to determine the pacing interval (current VV delay). Since the pacing rate is matched to the intrinsic rate, there is a race condition where the intrinsic ventricular signal and the paced ventricular signal of one cardiac cycle are expected at approximately the same time. If intrinsic AV conduction is not present (third degree block), there is no race. If intrinsic AV conduction is reliable, the heart should win. This can be addressed by providing an AV delay hysteresis (selectable by the HCP). If there is a recent intrinsic ventricular signal and the pacemaker detects an intrinsic atrial signal, the phasing of the ventricular pace to the intrinsic atrial signal is shifted by making the AV delay longer than the programmed AV delay. This is accomplished by a second hysteresis delay added to the programmed AV delay (i.e., AV hysteresis is active), which encourages the intrinsic ventricular signal.

[0073] When the intrinsic ventricular signal is not continuously observed by the processing unit for a relatively long period of time, the processing unit ramps down the pacing rate (VV delay) to the target rate, the resting rate, which is expected to be the rate at which the patient is normally not exercising as described above. In rate fading mode, the pacing rate transitions from the initial rate to the target rate by stepping down using steps of decrement rate change value.

[0074] The subsequent FindSync mode defines a behavior that provides basic support while attempting to encourage detection of intrinsic activity, as described above. As described above, FindSync mode provides an asynchronous mode in which the pacing rate (VV delay) is the resting rate. In FindSync mode, the sensing of intrinsic atrial and ventricular signals is enabled. If two consecutive cardiac cycles both contain either intrinsic atrial or ventricular signals, the VV interval between these cycles can be measured and the measurements can be used to set the VV delay and start time of the cardiac cycle, thereby aligning both the phase and rate of the heart and the pacemaker.

[0075] In the second assist mode, the motion sensor is active and the timing system ignores the intrinsic atrial signal. The processing unit 120 effectively operates in VVI(R) mode. When the motion sensor rate slows to the resting rate, the system returns to FindSync mode and begins monitoring intrinsic activity again.

[0076] In this embodiment, all timing and measurements are performed with a resolution of 7.8125 ms (1 tick at 128 Hz). At this resolution, rates up to 30 bpm can be timed by using a 1 byte counter. This resolution is also the resolution for the AV delay. The ILP 10 can have a maximum rate of 170 bpm. The calculated timer value is limited by hardware to ensure that pacing does not occur faster than 170 bpm.

[0077] The processing unit 120 includes a timer that is an up-counter with a comparator, allowing the same counter to time multiple events that are all referenced to the same starting point. Typically, the timers are all synchronized (i.e., started over) by a common reset called the main timer reset, or MTR, but when the timers are reset, only the main timer continues to count.

[0078] The block diagram of Figure 4 shows the main interactions between the components of the processing unit 120. The inputs consist of the output of the detector 126 and stored predefined or programmed parameter values ​​read from the data memory 122, which provide the main configurability of the timer system. The only output related to pacing is the ventricular pace output, i.e., the ventricular pacing control signal. Additionally, the timer system can be included in measuring time intervals for statistics.

[0079] The subsystems of the processing unit that reference timing may be controlled by registers and the operating modes can be read in a series of registers. The HCP configures the ILP 10 by setting screen parameters and transmitting a corresponding set of program parameters. All of these registers have a reset mode that is active when a system or initial power-up reset is triggered.

[0080] Control of the used mode of the processing unit is provided by the enable bits. The mode of the processing unit is selected according to the value of these bits. If the As enable bit is low, the intrinsic atrial signal is masked and the clock to the AV delay timer is never started. In that case, for example, the first assist mode (VVI(R) mode) is used. If the intrinsic ventricular signal enable bit is low, the intrinsic ventricular signal is masked and does not cause any main timer reset. If the intrinsic atrial signal enable bit is high, the intrinsic ventricular signal enable bit is high, and the pacing bit is high, the processing unit operates in normal VDD mode.

[0081] The method illustrated in the diagram of FIG. 4 includes controlling the source of the pacing interval, the behavior of the tracking interval, the motion circuit (enable / disable), the atrial tracking behavior (enable / disable atrial sensing), and the rate fading behavior under different conditions that may occur while the pacemaker is programmed in VDD mode. The ideal behavior in VDD mode is to have the ventricular event (either an intrinsic ventricular contraction or, if intrinsic AV conduction is insufficient, a ventricular pacing signal) track the intrinsic atrial contraction. If an intrinsic ventricular contraction occurs before the AV delay timeout, the pacemaker stops the AV delay and waits for the next atrial depolarization provided by the intrinsic atrial signal. When the AV delay timeout occurs, a ventricular pacing control signal is generated based on which a ventricular pacing signal is delivered.

[0082] The diagram includes a rate multiplexer component 302, which provides a rate source (actually an interval source) as an output selected by the control logic component 301 (see the rate multiplexer input in the upper left corner and the inputs "Lower", "Preferred", and "Rate Limiter"). In other words, the rate multiplexer component 302 selects one of the rates at the inputs for pacing within the actual cardiac cycle. The output of the rate multiplexer component 302 is used as an input to one of the comparators of the main timer component 310. The lower rate input register ("Lower" input) is programmed with either the base rate (for the first assist mode) or the resting rate (for VDD mode or sensor mode) at the time the pacing mode is programmed. The rate at the "Preferred" input is the current (average) VV interval provided by the interval monitor component 332 for VDD mode. The "rate limiter" rate is provided by the rate limiter component 305 for the sensor mode (second auxiliary mode) or the rate fading mode.

[0083] The control logic component provides a selection signal for the rate multiplexer component 302 based on the programmed pacing mode (e.g., VDD or VVI(R)) and information about the current mode, which can be a normal pacing mode (e.g., VDD), or one of its assisted modes, or one of the subsequent modes listed above.

[0084] As mentioned above, the rate limiter component 305 is responsible for providing rate transitions, where the rate change is limited to a predefined attack rate change value or a predefined decrement rate change value (sensor mode or rate fading mode). The target rate for the transition is called the "target rate" (see input "target"). Each step towards the target is at the "next rate" (see output "next"), with the step occurring at every period determined by the MTR. The next rate is provided to the rate multiplexer 302 at the "rate limiter" input.

[0085] In one embodiment, the rate limiter component 305 operates on intervals rather than rates. The attack and decrement interval change values ​​are rate dependent. The maximum delta (up or down) for the next cardiac cycle interval is calculated by the processing unit 120 based on the current (selected) rate (interval) received from the rate multiplexer 302 (see input "current interval"). The arithmetic required for this calculation is explained above.

[0086] The rate limiter component's 305 current interval is typically derived from the interval that occurred as the next interval during the previous period (see feedback path), but is initialized with a preloaded "preferred rate" that is the intrinsic average VV delay. The current interval value is compared to the target interval (determined from the target rate at the input) to figure out if the rate needs to speed up or slow down to move toward the target interval at the maximum allowed rate of change. The next interval output is the maximum step allowed in one period from the previous rate.

[0087] If the use of subsequent rate fading mode is enabled (see input "RF Enabled"), the current interval of the rate limiter component 305 is preloaded (i.e., tracked) with the inherent average VV delay whenever repetitive hysteresis is active, i.e., whenever a ventricular sense has recently been detected.

[0088] The rate limiter target selection component 307 selects a target rate for the rate limiter component 305 as described above, where the target rate is a target based on the actual motion signal (see input "motion signal") or one of the lower rates (base rate, resting rate). The target rate is selected based on a selection signal sent by the control logic component 301.

[0089] A main timer component 310 is used to time each cardiac cycle. Since there is one ventricular event (i.e., intrinsic ventricular signal or ventricular pacing) in every cardiac cycle, but there may be cardiac cycles where the intrinsic atrial signal is not detected due to the far-field sensing approach to monitor the intrinsic atrial signal, the main timer component 310 is always synchronized by the ventricular event. This timer component is restarted by the timer reset component 334 for every ventricular event (MTR) used and is always running. The main timer component 310 is provided with a clock rate (128 Hz), as are the AV timer component 312 and the hysteresis timer component 314, also referred to as the hysteresis component 314 or timer component 314. These two timer components 312, 314 are also restarted via the MTR signal.

[0090] The main timer component 310 may be used to determine the period within the cardiac cycle where it should be possible to separate the intrinsic atrial signal from the intrinsic ventricular signal. This window of time is known as the atrial sensing window. The atrial sensing window is always closed at every main timer reset.

[0091] There is a maximum rate at which the ventricular pace tracks the intrinsic atrial signal. This rate may be a patient-specific, user-programmable value referred to by the programmer as the upper tracking rate (UTR). The programmer converts this rate into an interval (UTI) for programming the pacemaker. When the corresponding time is reached, a signal is sent to the pace component 320 to enable pacing (see input "UTI Timeout").

[0092] In all supported pacing modes, there is a maximum time interval starting from a ventricular event, by which the pacemaker must deliver a ventricular pace if no ventricular sense has been detected. An interval corresponding to the programmed basic rate is timed by the main timer component 310 ("main timeout"). If this interval is exceeded before the timer is restarted, the main timeout is provided to the hysteresis timer component 314, and thus a ventricular pace is triggered. The main timeout is further provided to the pace component 320 ("basic rate timeout"). This main timeout is then the minimum pacing rate. The main timer component 310 never counts beyond this value, since reaching this interval will always result in the triggering of a ventricular pace, which in turn will cause the main timer to be reset.

[0093] Processing unit 120 further includes an AV timer component 312. AV timer component 312 is used to measure the AV delay and is started for every intrinsic atrial signal, where the AV timer component 312 can be restarted when a larger qualified intrinsic atrial signal is received by processing unit 120. When a main timer reset (MTR) occurs, the AV timer component 312 is stopped and the counter is reset to 0.

[0094] The processing unit 120 further includes a hysteresis logic component 330, also referred to as a hysteresis component 330, which is used only when hysteresis is enabled. As described above, hysteresis is used to encourage intrinsic atrial or ventricular signals rather than pacing. For example, a second hysteresis delay is used to lengthen the AV delay to encourage ventricular sensing. Furthermore, in an R-synchronous version of VDD where the current VV delay is used to time ventricular pacing when necessary, a first hysteresis delay is applied to the VV delay when there is no atrial pace and to encourage ventricular sensing. Additionally, to handle sudden drops in the intrinsic heart rate (see below), a first hysteresis delay is used as described above. For this purpose, the hysteresis logic component 330 includes a counter. The hysteresis counter is set to a predetermined number (e.g., a value between 10 and 3). In every cycle in which there is no intrinsic ventricular signal, the counter is decremented by one. When an intrinsic ventricular signal is received by the processing unit, the counter is reset to a predetermined number. When the counter is decremented to zero, the use of hysteresis is stopped and the processing unit switches to rate fading mode using the rate limiter target selection component 307, the rate limiter component 305, and the rate multiplexer component 302 to switch the rate input (from the "priority" input to the "rate limiter" input). Information on whether hysteresis is active is sent to the hysteresis timer component 314.

[0095] The hysteresis timer component 314 is used to provide a first hysteresis delay and alternatively a second hysteresis delay. The first hysteresis delay (which is the hysteresis interval) provides additional time before delivering a ventricular pace to encourage detection of a ventricular sense. Inputs to this timer include event triggers from the main timer component 310 reaching its time constant value and the AV timer component 312 reaching its time constant value. The second hysteresis delay is provided only if an intrinsic atrial signal is detected, and the intrinsic atrial signal information is received via the "As" input. When either the first hysteresis delay or the second hysteresis delay times out, a signal (output "Vp run") is provided to the pace component 320 to encourage a pacing signal.

[0096] The processing unit 120 further includes an interval monitor component 332 that measures the intrinsic VV interval (VV delay). The VV interval in timer units is captured in a register from the main timer value of the main timer component 310 just before it is reset by the MTR. This, together with the event information from the period, is used as the basis for the interval information provided by this component. For example, the interval monitor component can calculate an average value (e.g., arithmetic mean or median) using the last 5-10 measured VV intervals. The determined average value (the "intrinsic mean", also referred to as the current VV delay) is provided as an input to the rate limiter component 305 and the rate multiplexer component 302.

[0097] The VV interval is initiated by an MTR, eg, an intrinsic ventricular signal or a ventricular pacing signal, and is terminated by an intrinsic ventricular signal or a ventricular pacing signal.

[0098] In one embodiment, the VV interval may be averaged using a recursive filter and may be qualified before being used for the average calculation depending on whether an intrinsic signal was detected in this cycle or in the previous cycle. If this cycle had an intrinsic atrial signal or ended with an intrinsic ventricular signal, this cycle was an intrinsic cycle. A cycle with an intrinsic atrial signal provides phase information but not necessarily rate information. Two consecutive intrinsic cycles also provide rate information, thereby forming an intrinsic interval. The time period between two MTRs is referred to as a cardiac interval.

[0099] The pace component 320 of the processing unit triggers the ventricular pace, i.e., sends a ventricular pacing control signal (Vp) to the pacing signal generator 124. This control signal is based on the "Vp run" signal of the hysteresis timer component 314 or the "basic rate timeout" signal of the main timer component 310. The pace component 320 also needs to know whether the processing unit 120 is in VDD mode. If the processing unit 120 is in VDD mode and the UTI (see above) has not yet timed out, the pace is delayed until a UTI timeout signal is received (as the minimum pacing interval corresponding to the UTR). If the processing unit 120 is not in VDD mode, the motion signal can trigger a pace that exceeds the UTR up to the programmed maximum sensor rate (MSR limit). The motion sensor rate generator can limit the VV delay that is fitted to the motion signal by the MSR limit. Additionally, the pace component uses a signal from the AV timer component 312 (see input "Main AV Timeout") to guarantee a minimum interval from a detected intrinsic atrial signal. The pacing signal generator 124 uses the pacing time information contained in the ventricular pacing control signal (Vp) to generate a pacing signal based on further parameters such as pulse width, autoshort, and blanking timing. The pacing signal generator 124 then transmits the pace signal to the electrodes 111, 112.

[0100] The processing unit 120 further includes a timer reset component 334. Either the intrinsic ventricular signal or the ventricular pace used triggers a main timer reset (MTR). The MTR resets the timer components 310, 312, and 314 and stops the timers of the first hysteresis delay and the second hysteresis delay. The MTR provides a basis for counting cardiac cycles and clears the logic, which starts over every cycle. The main timer value of the main timer component 310 is captured before the timer is reset and transmitted to the interval monitor component 332, which provides a measurement of the actual VV delay and, if the actual VV delay is qualified, uses the actual VV delay to calculate the current (average) VV delay.

[0101] The following describes the behavior of the processing unit 120 when the inherent heart rate drops suddenly (ie, the VV interval becomes significantly longer) in VDD mode or sensor mode.

[0102] 5 shows the behavior of the processing unit in VDD mode (without atrial tracking). The solid line 401 represents the intrinsic heart rate determined by the processing unit. When the intrinsic heart rate drops significantly, pacing begins and the solid line 401 branches into two solid lines (see point 408), where the upper solid line 402 represents the pacing rate and the lower solid line 401 is the intrinsic heart rate. The upper dashed line 405 is the intrinsic average rate (corresponding to the average VV interval). The lower dashed line 406 is the intrinsic average rate minus the hysteresis rate (corresponding to the current average VV delay plus the first hysteresis delay).

[0103] As the intrinsic heart rate drops, pacing becomes active at a hysteresis delta below the last current VV delay (see reference numeral 408 where the solid line branches), where the last current VV delay is represented in FIG. 5 by value 410. After a predetermined number of consecutive pacing cycles (e.g., 3-10) without any intrinsic ventricular signal (counted by a counter in hysteresis logic component 330), the hysteresis delta is no longer applied (see point 412 in FIG. 5 ), because processing unit 120 now switches to rate fading mode and slowly ramps down the rate (corresponding to the last current VV delay) to the base rate (see line 415). Initially, the pacing rate jumps up a little because the initial rate value for rate fading is the rate corresponding to the last average VV delay (without hysteresis). This means that when hysteresis is no longer active, the target rate of the rate limiter component 305 is set to the basic rate, and the pacing rate is ramped down using the rate limiter component 305 at the allowed decrement rate change value (see line 402 in FIG. 5). Thus, the rate multiplexer component 302 selects the rate received from the rate limiter component 305. This means that the VV delay for pacing corresponds to the rate provided by the rate limiter component 305. As can be derived from FIG. 5, the pacing rate approaches the basic rate (represented by line 415) over time.

[0104] FIG. 6 shows the same situation as FIG. 5, but for the sensor mode. The behavior is similar to that described with respect to FIG. 5. However, in the sensor mode, there is additionally a sensor rate 420, which is a rate corresponding to the detected motion signal of the motion sensor indicating the level of patient activity. The sensor rate is depicted by line 420 in FIG. 6. In the rate fading section starting at point 412, the rate fading selects the sensor rate as the target rate because the motion sensor signal is available. Thus, the sensor rate is selected by the rate limiter target selection component 307 (instead of the base rate) and provided to the target input of the rate limiter target selection component 305. Thus, as can be seen in the rightmost section of the line 402 representing the pacing rate in FIG. 6, the pacing rate approaches the sensor rate over time.

[0105] The above-described embodiments of the cardiac pacemaker (ILP10) and their respective methods of operation provide for small integrated circuit space and simple design, covering many operating modes, yet requiring complex dynamic adaptive algorithms for robust behavior. The above-described design and operation provide an infrastructure to meet these needs.

Claims

1. A cardiac pacemaker (10) for the patient's heart (20), for example, an ILP, The cardiac pacemaker (10) includes a processing unit (120), a detector (126), and a pacing signal generator (124). The processing unit, the detector, and the pacing signal generator are electrically interconnected. The detector is configured to detect electrical signals from the heart, such as the electrical signals of an intracardiac electrophysism (IEGM), and to transmit the signals to the processing unit (120). The processing unit is configured to perceive the inherent ventricular and atrial signals from the signals received from the detector, enable or disable the perception of the inherent atrial signals, generate a ventricular pacing control signal (Vp) including ventricular pacing time information, and transmit the ventricular pacing control signal to the pacing signal generator for providing pacing signals for the patient's heart. The processing unit is configured to generate the ventricular pacing control signal using the VDD mode or at least one auxiliary mode. The processing unit, depending on the conditions, If the perception of the inherent atrial signal is enabled, the VDD mode is used in the current cardiac cycle, and the pacing in the VDD mode is based on the current AV delay if the inherent atrial signal is perceived by the processing unit in the current cardiac cycle, or on the current VV delay determined from previous inherent ventricular and / or atrial signals if the inherent atrial signal is not perceived by the processing unit in the current cardiac cycle. Alternatively, the at least one auxiliary mode in the current cardiac cycle is used based on the current VV delay, which is determined from a previous VV delay that takes into account at least one additional parameter, or from a different assignment rule. A pacemaker is configured in such a way.

2. The first auxiliary mode is VVI mode, and the second auxiliary mode is sensor mode. In the VVI mode, the processing unit (120) is configured to determine the current VV delay from the base rate. In the sensor mode, the processing unit is configured to determine the current VV delay based on the sensor signal of the detector (126), which detects a signal different from the inherent ventricular signal and the inherent atrial signal, for example, a motion signal, when the perception of the corresponding sensor signal is enabled. The pacemaker according to claim 1.

3. In the VDD mode or the second auxiliary mode, if the inherent ventricular signal is not perceived within the time interval of the current VV delay, the current VV delay is extended by the amount of the first hysteresis delay. The extension is provided over a predetermined number of consecutive cardiac cycles in which no inherent ventricular signals are perceived. The pacemaker according to claim 1 or 2.

4. The processing unit (120) is configured to use a first subsequent mode, namely rate fading mode. The rate fading mode is provided by the first hysteresis delay, which extends the current VV delay, and begins from the next cardiac cycle following a predetermined number of consecutive cardiac cycles in which the inherent ventricular signal is not perceived in the VDD mode or the second auxiliary mode. In the rate fading mode, the current VV delay is graded upward from the current VV delay to the VV delay corresponding to the base rate or the current sensor rate. The pacemaker according to claim 3.

5. The processing unit (120) is configured to switch to a second subsequent mode, namely the FindSync mode. In the FindSync mode, the processing unit attempts to perceive the inherent atrial signal and atrial tracking opportunity when the current VV delay corresponds to the base rate or resting rate over a predetermined time interval, in the first auxiliary mode, the rate fading mode, or the sensor mode. The pacemaker according to claim 1 or 2.

6. The processing unit (120) includes a rate limiter component (305), The rate limiter component (305) determines, in the rate fading mode, the current rate for gradually changing the VV delay, or, in the sensor mode, the current rate for adapting the current VV delay to the detected sensor signal. The rate limiter component provides an attack rate change value and a decrement rate change value. The pacemaker according to claim 1 or 2.

7. The processing unit (120) includes hysteresis components (330, 314), The hysteresis components (330, 314) also provide the first hysteresis delay for the VDD mode and the second auxiliary mode, and preferably a second hysteresis delay for the VDD mode to extend the AV delay. The pacemaker according to claim 1 or 2.

8. A method of operating a cardiac pacemaker (10) for a patient's heart (20), for example, an ILP, The cardiac pacemaker (10) includes a processing unit (120), a detector (126), and a pacing signal generator (124). The processing unit, the detector, and the pacing signal generator are electrically interconnected. The detector detects the electrical signals of the heart, such as the electrical signals of the intracardiac electrophysismogram (IEGM), and transmits them to the processing unit (120). The processing unit perceives the inherent ventricular signals and inherent atrial signals from the signals received from the detector. The processing unit can enable or disable the perception of the inherent atrial signals. The processing unit generates a ventricular pacing control signal (Vp) including ventricular pacing time information, which is transmitted to the pacing signal generator for generating a pacing signal for the patient's heart. The ventricular pacing control signal is generated using the VDD mode or at least one auxiliary mode, depending on the conditions. If the perception of the inherent atrial signal is enabled, the VDD mode is used in the current cardiac cycle, and the pacing in the VDD mode is based on the current AV delay if the inherent atrial signal is perceived by the processing unit in the current cardiac cycle, or on the current VV delay determined from previous inherent ventricular and / or atrial signals if the inherent atrial signal is not perceived by the processing unit in the current cardiac cycle. Alternatively, the at least one auxiliary mode may be used in the current cardiac cycle based on the current VV delay determined from a previous VV delay that takes into account at least one additional parameter, or from a different assignment rule. method.

9. The first auxiliary mode is VVI mode, and the second auxiliary mode is sensor mode. In the VVI mode, the current VV delay is determined from the base rate. In the aforementioned sensor mode, if the perception of the corresponding sensor signal is enabled, Based on the signal from the sensor of the detector (126) that detects signals different from the inherent ventricular signal and the inherent atrial signal, for example, a motion signal, the current VV delay is determined. The method according to claim 8. [In sensor mode, the perception of atrial signals is disabled, and the sensor is configured to detect the corresponding signals.]

10. In the VDD mode or the second auxiliary mode, if the inherent ventricular signal is not perceived within the time interval of the current VV delay, the current VV delay is extended by the amount of the first hysteresis delay. The extension is provided over a predetermined number of consecutive cardiac cycles in which no inherent ventricular signals are perceived. Additionally or alternatively, in the VDD mode, a second hysteresis delay is used to extend the AV delay. The first hysteresis delay and / or the second hysteresis delay may be provided, for example, by the hysteresis components (330, 314) of the processing unit. The method according to claim 8.

11. The first subsequent mode, namely rate fading mode, is used. The rate fading mode is provided by the first hysteresis delay, which extends the current VV delay, and begins from the next cardiac cycle following a predetermined number of consecutive cardiac cycles in which the inherent ventricular signal is not perceived in the VDD mode or the second auxiliary mode. In the rate fading mode, the VV delay is graded upward from the current VV delay to the VV delay corresponding to the base rate or the current sensor rate. The method according to claim 10.

12. The method described above switches to a second subsequent mode, namely the FindSync mode, In the FindSync mode, the processing unit (120) attempts to perceive the inherent atrial signal and atrial tracking opportunity when the current VV delay corresponds to the base rate or resting rate over a predetermined time interval in the rate fading mode or the sensor mode. The method according to claim 8.

13. The rate limiter component (305) determines, in the rate fading mode, the current rate for gradually changing the VV delay, or, in the sensor mode, the current rate for adapting the current VV delay to the detected sensor signal. The rate limiter component provides an attack rate change value and a decrement rate change value. The method according to claim 8.

14. A computer program product that, when executed by a processing unit, includes an instruction causing the processing unit (120) to perform a step of the method according to any one of claims 8 to 13.

15. A computer-readable data carrier storing the computer program product described in claim 14.

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