Data storage method, storage device and readable storage device

Abstract

The present application discloses a data storage method, which includes: writing data to a first buffer area and a second buffer area of ​​a page buffer; writing data to a third buffer area of ​​the page buffer, in which the data written to the third buffer area is obtained from the data of the first buffer area and the data of the second buffer area through a logical operation using the computing resources of the page buffer, and first data information is determined by the data of the first buffer area, the second buffer area and the third buffer area; and writing the first data information buffered in the page buffer to a storage unit. The present application further discloses a storage device and a computer-readable storage device. The present application can improve the data reliability of a TLC / QLC storage device without consuming the computing resources of the system.

Description

[Technical field]

[0001] The present application relates to the technical field of storage, and in particular to data storage methods, storage devices and computer readable storage devices. [Background technology]

[0002] Nowadays, as the use of storage devices becomes more and more widespread, the storage technology of storage devices continues to advance and develop. Take the currently widely used TLC / QLC memory as an example. TLC can store 3 bits of data information in one storage unit, while QLC can store 4 bits of information data in one storage unit. In order to distinguish between multiple types of data information in one storage unit, it is necessary to divide the corresponding voltage sections to distinguish them. In the case of TLC, 8 voltage sections need to be divided, while in the case of QLC, 16 voltage sections need to be divided. However, since the voltage sections inside the storage unit are limited, the more voltage sections are divided, the smaller the interval between the sections becomes. When the interval between the sections becomes smaller, if a voltage offset occurs in the voltage data due to various factors, the voltage data will exceed the critical voltage value, and if the data is read according to the critical voltage value of the original section, a data error will occur, which reduces the reliability of the stored data. Summary of the Invention [Problem to be solved by the invention]

[0003] A main object of the present application is to provide a data storage method, a storage device, and a computer-readable storage device that can solve the problem of improving data reliability of a storage device. [Means for solving the problem]

[0004] In order to solve the above problems, a first technical aspect of the present application is to provide a data storage method, the method including: writing data into a first buffer area and a second buffer area of ​​a page buffer, writing data into a third buffer area of ​​the page buffer, in which the data written into the third buffer area is obtained from the data in the first buffer area and the data in the second buffer area through a logical operation using the computing resources of the page buffer, and first data information is determined by the data in the first buffer area, the second buffer area and the third buffer area, and writing the first data information buffered in the page buffer into a storage unit.

[0005] In order to solve the above problems, a second technical aspect of the present application is to provide a storage device including a memory and a processor, the memory being for storing program data, the program data being executable by the processor to implement the method according to the first technical aspect.

[0006] In order to solve the above problems, a third technical aspect adopted by the present application is to provide a computer-readable storage device, which stores program data that can be executed by a processor to realize the method according to the first technical aspect. Effect of the Invention

[0007] The beneficial effects of the present application are as follows. Unlike the prior art, the data in the first and second buffer areas is not determined and then the data in the third buffer area is determined using the threshold voltage value, but the data in the third buffer area is obtained by performing a logical operation on the data in the first and second buffer areas. The buffer data has two types, 0 and 1, and buffer data of 1-bit data information is stored in each buffer area. In the prior art, when the first, second, and third buffer data is determined using the threshold voltage value, 8 types of data information are obtained. In contrast, in the present application, the data in the third buffer area is obtained by performing an operation on the data in the first and second buffer areas that have already been determined. In other words, by making the data status of the third buffer area correspond to the 4 types of state data of the first and second buffer areas, the data information finally obtained based on the data in the first, second, and third buffer areas is only 4 statuses, not the original 8 statuses. Since the occurrence status of the data information is reduced, a larger voltage section can be partitioned for the 4 types of data information within the same maximum voltage section, and the degree of error resistance to the data voltage offset is increased, thereby improving the reliability of the stored data. In addition, the present invention realizes the logical operation process by using the logical operation function of the page buffer, so there is no need to occupy the calculation resources of the master, and the calculation capacity of the system can be saved. [Brief description of the drawings]

[0008] In order to more clearly explain the technical aspects in the embodiments of the present invention, the following briefly introduces drawings that need to be used in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention, and those skilled in the art can also obtain other drawings from these drawings without paying creative labor. [Figure 1] FIG. 1 is a schematic diagram of writing and reading voltages in a TLC NAND FLASH memory according to the present application. [Diagram 2] FIG. 2 is a schematic diagram showing a case where a left-right offset occurs in the voltage stored in the storage unit of the TLC according to the present application. [Diagram 3] FIG. 3 is a flow diagram of a first embodiment of the data storage method according to the present application. [Figure 4] FIG. 4 is a flow diagram of a second embodiment of the data storage method according to the present application. [Diagram 5] FIG. 5 is a flow diagram of a third embodiment of the data storage method according to the present application. [Figure 6] FIG. 6 is a flow diagram of a fourth embodiment of the data storage method according to the present application. [Figure 7] FIG. 7 is a flow diagram of a fifth embodiment of the data storage method according to the present application. [Figure 8] FIG. 8 is a schematic diagram of determination of a voltage reading section after a logical operation according to the present application. [Figure 9] FIG. 9 is a flow diagram of a sixth embodiment of the data storage method according to the present application. [Figure 10] FIG. 10 is a flow diagram of a seventh embodiment of the data storage method according to the present application. [Figure 11] FIG. 11 is a schematic flow diagram of an eighth embodiment of the data storage method according to the present application. [Figure 12] FIG. 12 is a schematic flow diagram of a ninth embodiment of the data storage method according to the present application. [Figure 13] FIG. 13 is a schematic flow diagram of a tenth embodiment of the data storage method according to the present application. [Figure 14] FIG. 14 is a schematic flow diagram of an eleventh embodiment of a data storage method according to the present application. [Figure 15] FIG. 15 is a schematic flow diagram of a twelfth embodiment of the data storage method according to the present application. [Figure 16] FIG. 16 is a schematic flow diagram of a thirteenth embodiment of the data storage method according to the present application. [Figure 17] FIG. 17 is a schematic flow diagram of a fourteenth embodiment of the data storage method according to the present application. [Figure 18] FIG. 18 is a schematic diagram showing the structure of an embodiment of a storage device according to the present application. [Figure 19]FIG. 19 is a structural schematic diagram of one embodiment of a computer-readable storage device according to the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the technical aspects of the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, but it is obvious that the described embodiments are only some of the embodiments of the present application, and are not all of the embodiments. Based on the embodiments of the present application, other embodiments obtained by those skilled in the art without paying creative labor shall all be within the scope of protection of the present application.

[0010] In this application, terms such as "first", "second", etc. are used to distinguish different objects and are not intended to describe a particular order. Furthermore, the terms "comprise" and "have" and any variations thereof are intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but optionally includes additional steps or units that are not listed, or optionally includes other steps or units that are inherent to the process, method, product, or apparatus.

[0011] Reference to an "embodiment" in this specification means that a particular feature, structure, or characteristic described with respect to the embodiment may be included in at least one embodiment of the present application. The appearance of the term in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. Those skilled in the art will understand, both explicitly and implicitly, that the embodiments described herein can be combined with other embodiments.

[0012] Before introducing the technical aspects of the present application, a brief introduction to related art will be given.

[0013] Please refer to FIG. 1, which is a schematic diagram of writing and reading voltages in a TLC NAND FLASH memory.

[0014] At present, in practical applications, TLC NAND FLASH memory and QLC NAND FLASH memory are widely used. Of these two types of memory, TLC can store 3-bit information in one storage unit, while QLC can store 4-bit information in one storage unit. Meanwhile, MLC can only store 2-bit information in one storage unit, so the production costs of both are lower than MLC. However, the maximum voltage intervals of the storage units are all the same, and under the same maximum voltage interval, storing more information means dividing the voltage interval into more small intervals, and identifying the stored voltage according to the interval threshold to read the data. In the case of TLC, as shown in the figure, one storage unit can store 3-bit information, so 8 types of voltage states are required, and 8 intervals are required, and they are distinguished using different read levels.

[0015] The information stored in the TLC has 3 bits. When storing, each bit of data is first stored in a different page buffer, and after all bits of data are stored in the buffer, the data is written collectively into the memory die. In the figure, the write mode of the memory unit is 2-3-2 mode. First, writing is performed using read level 1 and read level 5, the written data is stored in the lower page buffer, the state of the data written thereto from left to right is 101, and the data written thereto is the least significant bit of data; then, writing is performed using read level 2, read level 4, and read level 6, the written data is stored in the middle page buffer, the state of the data written thereto from left to right is 1010, and the data written thereto is the middle bit of data; finally, writing is performed using read level 3 and read level 7, the written data is stored in the upper page buffer, and the data written thereto is the most significant bit of data; according to this order, the resulting data are 111, 110, 100, 000, 010, 011, 001, 101, in that order; and finally, all the data are stored together in the memory die.

[0016] When writing data, various interference factors cause left and right offsets and spreads in the distribution of voltages in each state, so that the read level cannot properly distinguish between the eight voltage states when reading. As shown in Figure 2, Figure 2 is a schematic diagram of left and right offsets occurring in the voltages stored in the TLC storage unit. If a certain number of error bits is exceeded, data reading will fail and data will be lost. The larger the small voltage section of data storage, the easier it is to distinguish when reading by the read level after the left and right offsets occur due to interference, and the less likely data errors will occur, resulting in higher reliability of data storage.

[0017] In some application scenarios, the requirements for data reliability are very high, while the requirements for its storage capacity are not so strict, and the reliability of TLC / QLC does not meet the actual needs of users. Therefore, the present application provides the following examples to improve the data reliability of TLC / QLC products to meet the usage requirements.

[0018] Referring to Fig. 3, Fig. 3 is a flow diagram of a first embodiment of a data storage method according to the present application, which includes the following steps S11 to S13.

[0019] S11: Data is written to the first buffer area and the second buffer area of ​​the page buffer.

[0020] According to the original memory write flow, the first two bits of data are written into the buffer area according to the read level of the write. Taking the above TLC write 2-3-2 mode as an example, writing is performed using read level 1 and read level 5, and the written data is stored in the lower page buffer, and then writing is performed using read level 2, read level 4, and read level 6, and the written data is stored in the middle page buffer. Here, the first buffer area is the lower page buffer, and the second buffer area is the middle page buffer, but this is merely an illustrative description, and in the actual application process, the first buffer area and the second buffer area may be any two of all the set buffer areas. The subsequent third buffer area is a buffer area different from the first buffer area and the second buffer area.

[0021] S12: Write data to the third buffer area of ​​the page buffer.

[0022] After the data writing to the first buffer area and the second buffer area is completed, the data is not written to the third buffer area according to the read level as per the original flow, but the data to be written to the third buffer area is obtained from the data of the first buffer area and the data of the second buffer area through a logical operation using the calculation resource of the page buffer. In the storage device, the logical operation process can be realized by using a logical operation function in the buffer, such as a logical sum (OR) operation, a logical product (AND) operation, a negative logical sum (NOR) operation, a negative logical product (NAND) operation, a negative exclusive logical sum (XNOR) operation, an exclusive logical sum (XOR) operation, etc. Furthermore, the first data information is determined by the data in the first buffer area, the second buffer area, and the third buffer area. The first data information is determined by the data written to the corresponding first buffer area, the second buffer area, and the third buffer area under the same voltage section.

[0023] S13: Write the first data information buffered in the page buffer to the storage unit.

[0024] After the data has been written into the buffer, the final data is written into the storage unit to complete the data storage.

[0025] In this embodiment, all logical operations can be realized by the logical operation capacity of the page buffer itself, and there is no need to occupy the calculation resources of the master, so that the calculation capacity of the system can be saved.

[0026] According to the present embodiment, the data of the first and second buffer regions is not determined and then the data of the third buffer region is determined using the threshold voltage value, but the data of the first and second buffer regions is obtained by performing a logical operation on the data of the first and second buffer regions, and since the buffer data has two types, 0 and 1, and the buffer data of 1 bit of data information is stored in each buffer region, in the prior art, when the first, second, and third buffer data is determined using the threshold voltage value, 8 types of data information are obtained, whereas in the present application, the data of the third buffer region is obtained by performing an operation on the already determined data of the first and second buffer regions, that is, the data status of the third buffer region is made to correspond to the 4 types of state data of the first and second buffer regions, so that the data information finally obtained based on the data of the first, second, and third buffer regions is only 4 statuses, not 8 statuses as originally intended. Since the appearance status of the data information is reduced, a larger voltage section can be divided for the 4 types of data information within the same maximum voltage section, and the degree of error resistance to the data voltage offset is increased, thereby improving the reliability of the stored data.

[0027] 4, which is a flow diagram of a second embodiment of the data storage method according to the present application. This method is a further expansion of step S12, and includes the following steps S21 to S22.

[0028] S21: A first logical operation is performed on the data in the first buffer area and the data in the second buffer area to obtain intermediate data.

[0029] A first logical operation is first performed according to the data already written in the first buffer area and the second buffer area, and the logical operation may be an XNOR operation.

[0030] S22: Data obtained by performing a second logical operation on the intermediate data and the data in the first buffer area is written to a third buffer area, or data obtained by performing a second logical operation on the intermediate data and the data in the second buffer area is written to the third buffer area.

[0031] The intermediate data thus obtained may be subjected to a second logical operation with the data in the first buffer area to obtain data to be written to the third buffer area. The logical operation may be an OR operation. The intermediate data thus obtained may be subjected to a second logical operation with the data in the second buffer area to obtain data to be written to the third buffer area.

[0032] Taking the above TLC 2-3-2 mode as an example, if the data written in the first buffer area is 10000111 and the data written in the second buffer area is 11001100, the two data are XNORed to obtain 10110100, which is then ORed with the data in the first buffer area to obtain 10110111, which is the data in the third buffer area. The data voltages stored therein are finally in four states, which are 111, 001, 010, and 101, respectively, out of the original eight states. Since the voltage intervals of the four finally obtained voltage states are far apart, new data read voltages can be set for them. By distinguishing the four voltage states by the new read voltage, the intervals of the new four voltage intervals are increased from the previous ones, so that the tolerance for the left and right offset of the voltage is increased, the reliability of the data is enhanced, and the probability of data error occurrence is reduced.

[0033] Similarly, if an OR operation is performed on the intermediate data and the data in the second buffer area, the data in the third buffer area obtained thereby is 11111100. The data voltages stored therein will finally have four states, which are 111, 011, 001, and 100, respectively, which are among the original eight states. Among them, the voltage section of 100 is far away from the other three voltage sections, and the other three sections are still close to each other, so after setting a new data read voltage, the new voltage section corresponding to 100 will have its section interval increased, and its tolerance to the left and right offset of the voltage will be higher, thus enhancing the reliability of the data and reducing the probability of data error, while the section intervals of the other three voltage sections will probably not be significantly different, and the reliability of the data will not fluctuate significantly.

[0034] Therefore, in the process of performing logical operations, it is necessary to consider that the original voltage intervals of the four finally obtained voltage states are distributed relatively uniformly throughout the entire maximum voltage interval. In this way, among the interval intervals of the four new voltage states, all intervals can be increased to a certain extent, rather than only some of the interval intervals being obviously increased, and as a result, the reliability of all of the stored data, not just some of the data, can be improved.

[0035] 5, which is a flow diagram of a third embodiment of the data storage method according to the present application, which is a further extension of the above embodiment and includes the following steps S31 to S33.

[0036] S31: After writing data to the first buffer area, the data in the first buffer area is copied to the third buffer area.

[0037] The TLC page buffer has a three-layer page buffer structure, and each page buffer buffers one bit of data. In the process of performing the above logical operation, when the least significant bit of data is stored in the first buffer area corresponding to the lower page buffer, the data in the first buffer area is copied and written to the third buffer area.

[0038] S32: After writing the data into the second buffer area, perform a first logical operation on the data in the third buffer area and the data in the second buffer area to obtain intermediate data, and write the intermediate data into the third buffer area.

[0039] When the second bit of data is stored in the second buffer area, a logical operation is performed on the data of the first buffer area stored in the third buffer area at this time and the data of the second buffer area. The logical operation may be an XNOR operation. After the operation, intermediate data is obtained, and the data of the first buffer area written in the third buffer area is updated with the intermediate data.

[0040] S33: Data obtained by performing a second logical operation on the data in the third buffer area and the data in the first buffer area is written to the third buffer area.

[0041] After the intermediate data is written to the third buffer area, a logical operation is again performed with the buffer data in the first buffer area, which may be an OR operation, and the resulting data becomes the final data to be written to the third buffer area, and the intermediate data is updated with the resulting data and written to the third buffer area.

[0042] After all the data is written to the buffer area, it is written collectively to the storage unit.

[0043] The logical operations can all be realized by the logical operation capabilities of the page buffer itself, without occupying the computing resources of the master, thus saving the computing capabilities of the system.

[0044] 6, which is a flow diagram of a fourth embodiment of the data storage method according to the present application. This method is a further expansion of step S13, and includes the following steps S41 to S42.

[0045] S41: Determine a corresponding section voltage signal according to the first data information buffered in the page buffer.

[0046] After performing a logical operation on the data in the first buffer area and the second buffer area to obtain data in the third buffer area, four types of voltage status data can be obtained correspondingly, and these four types of voltage status data become the data information currently stored in the buffer.

[0047] In the above embodiment, an XNOR operation is performed on the data in the first buffer area and the data in the second buffer area to obtain intermediate data, and then an OR operation is performed on the intermediate data and the data in the first buffer area to obtain data in the third buffer area, and the four types of voltage state data finally obtained are 111, 100, 010, and 101. According to the illustration in Fig. 1, the voltage sections corresponding to the four types of voltage state data are the first section, the third section, the fifth section, and the eighth section counted from left to right. The corresponding voltage signals are read level 1 which defines the first section, read level 2 and read level 3 which define the third section, read level 4 and read level 5 which define the fifth section, and read level 7 which defines the eighth section.

[0048] S42: Write the first data information into the storage unit according to the corresponding section voltage signal.

[0049] After the data information of the buffer is determined, an interval voltage signal corresponding to the data information can be obtained, and data can be written into the storage unit according to the corresponding voltage interval signal. The write voltage corresponding to 111, which is stored in the storage unit, is lower than read level 1 or is not written, the write voltage corresponding to 100, which is stored in the storage unit, is between read level 2 and read level 3, the write voltage corresponding to 010, which is stored in the storage unit, is between read level 4 and read level 5, and the write voltage corresponding to 101, which is stored in the storage unit, is higher than read level 7.

[0050] 7, which is a flow diagram of a fifth embodiment of the data storage method according to the present application, which is a further extension of the above embodiment and includes the following steps S51 to S52.

[0051] S51: Eight voltage sections corresponding to 3-bit data are determined.

[0052] In the TLC storage mode, one storage unit can store 3 bits corresponding to 8 kinds of state data, each occupying one voltage range, and it is easy to distinguish them according to the critical voltage of the voltage range when reading. The 8 voltage ranges are determined by 7 critical voltage values. In the above embodiment, the 7 critical voltages are read level1 to read level7.

[0053] S52: Determine four voltage sections defined by the first buffer area, the second buffer area and the third buffer area.

[0054] Referring to FIG. 8, FIG. 8 is a schematic diagram of the determination of voltage read intervals after logical operation according to the present application. After logical operation, only four of the eight types of state data remain. For example, after the logical operation of the above embodiment, only 111, 100, 010, and 101 corresponding to the first, third, fifth, and eighth voltage intervals remain. Meanwhile, in order to increase the reliability of the data, a new read voltage needs to be determined for it, that is, a new voltage interval needs to be defined for it to distinguish the remaining four types of voltage states. The four voltage intervals are determined by three critical voltage values.

[0055] The three critical voltage values ​​are represented by one of the seven critical voltage values ​​and the corresponding offset amount. After determining the voltage intervals corresponding to the remaining four types of status data, the respective critical voltages are determined accordingly. In the above embodiment, the first, third, fifth and eighth voltage intervals correspond to six types of critical voltages, namely, read level 1, 2, 3, 4, 5 and 7. In order to effectively improve the reliability of each type of status data, the new critical voltages of 111 and 100 are determined to be intermediate between the first and third voltage intervals, that is, intermediate voltages between read level 1 and read level 2, and the voltage is obtained by adding half the difference between read level 1 and read level 2 to read level 1, or by subtracting half the difference between read level 1 and read level 2 from read level 2. Similarly, the new critical voltages of 100 and 010 are determined to be midway between the third and fifth voltage sections, i.e., the midway voltage between read level 3 and read level 4, and the voltage is obtained by adding an offset value to read level 3 or subtracting an offset value from read level 4. The new critical voltages of 010 and 101 are determined to be midway between the fifth and eighth voltage sections, i.e., the midway voltage between read level 5 and read level 7, and the voltage is obtained by adding an offset value to read level 5 or subtracting an offset value from read level 7. The determined new critical voltages are not necessarily in the middle of both base critical voltages and can be adjusted according to the actual situation. However, if the new critical voltages are determined to be in the middle of both base voltages, the reliability of each data can be improved as much as possible.

[0056] 9, which is a flow diagram of a sixth embodiment of the data storage method according to the present application, which is a further extension of the above embodiment and includes the following step S61.

[0057] S61: Compare the voltage information in the storage unit with the four voltage intervals to read the first data information stored in the storage unit.

[0058] After the data in the buffer area is stored in the memory unit, when the data is read, it is read according to the new threshold voltage value determined in the above embodiment.

[0059] 10, which is a flow diagram of a seventh embodiment of the data storage method according to the present application. This method is a further extension of the first embodiment, and includes the following steps S71 to S72.

[0060] S71: Data is written to the fourth buffer area of ​​the page buffer.

[0061] The data written to the fourth buffer area is obtained from any two of the data in the first buffer area, the data in the second buffer area, and the data in the third buffer area through a logical operation using the calculation resources of the page buffer, and the second data information is determined by the data in the first buffer area, the second buffer area, the third buffer area, and the fourth buffer area. After writing data to the first buffer area and the second buffer area based on the above embodiment, the data in the third buffer area is obtained by performing a logical operation on the data in the first buffer area and the second buffer area. Furthermore, the data in the fourth buffer area is obtained by performing a logical operation again on the data in any two of the first buffer area, the second buffer area, and the third buffer area.

[0062] In the QLC memory unit, each memory unit can store 4 bits of data information. It corresponds to 16 kinds of voltage states, has 16 voltage intervals, and is distinguished by 15 critical voltage values. The page buffer has a four-layer structure, and each page buffer corresponds to 1 bit of data. When writing, writing is performed sequentially from the least significant bit.

[0063] For the process of performing the logical operation to obtain the data of the third buffer area, the description of the above embodiment can be referred to. For example, after writing data to the first buffer area, the data of the first buffer area is copied to the third buffer area, and after writing data to the second buffer area, a logical operation is performed on the data in the third buffer area and the data in the second buffer area. The operation may be an XNOR operation. After the operation, intermediate data is obtained, and the data of the first buffer area written to the third buffer area is updated with the intermediate data. After the intermediate data is written to the third buffer area, a logical operation is performed again with the buffer data in the first buffer area. The logical operation may be an OR operation. The obtained data becomes the final data to be written to the third buffer area, and the intermediate data is updated with the obtained data and written to the third buffer area.

[0064] After the process of obtaining the fourth buffer area by logical operation, four kinds of voltage state data are left correspondingly, which correspond to four of the original 16 kinds of voltage data. In order to enhance the reliability of the four kinds of voltage state data, it is necessary to determine a new larger voltage range for the four kinds of voltage states. In order to improve the reliability of all data, not just a part of the data, among the four kinds of voltage state data to a certain extent, it is necessary to ensure that the voltage ranges originally corresponding to the finally obtained four kinds of voltage state data are distributed relatively evenly throughout the maximum voltage range, so that each new voltage range is obviously larger than the previous voltage range. The specific operation logic can refer to the idea provided in the above embodiment, and will not be repeated here.

[0065] The logical operations can all be realized by the logical operation capabilities of the page buffer itself, without occupying the computing resources of the master, thus saving the computing capabilities of the system.

[0066] In practical application, the first buffer area, the second buffer area, the third buffer area, and the fourth buffer area may be any one of all the configured buffer areas, and the first, second, third, and fourth do not limit the positions of the buffer areas, but only indicate that the positions of the buffer areas are different.

[0067] S72: The second data information buffered in the page buffer is written to the storage unit.

[0068] After the data is written into the buffer, a second data information of the buffer is written into the storage unit, and the second data information is determined by the data written into the corresponding first buffer area, second buffer area, third buffer area and fourth buffer area under the same voltage section. After the data is written into the storage unit, the storage of the data is completed.

[0069] 11, which is a flow diagram of an eighth embodiment of the data storage method according to the present application. This method is a further expansion of step S72, and includes the following steps S81 to S82.

[0070] S81: Determine a corresponding section voltage signal according to second data information buffered in a page buffer.

[0071] A logical operation is performed on the data in the first buffer area and the second buffer area to obtain data in the third buffer area, and then a logical operation is performed again to obtain data in the fourth buffer area, and four types of voltage status data can be obtained correspondingly, and these four types of voltage status data become the data information currently stored in the buffer.

[0072] After the four kinds of voltage state data are determined, the original voltage range and the critical voltage value of the voltage range can be further determined. The determination procedure can be referred to the above embodiment, and will not be repeated here.

[0073] S82: Writing second data information into the storage unit according to the corresponding section voltage signal.

[0074] According to the determined buffer data, determine its voltage interval and threshold voltage value. Write data to the storage unit according to the interval voltage. The corresponding data information is that the voltage written to the storage unit is within the corresponding voltage interval. For details, please refer to the description of step S42 in the above embodiment, and will not be repeated here.

[0075] 12, which is a flow diagram of a ninth embodiment of the data storage method according to the present application, which is a further extension of the above-mentioned embodiment, and includes the following steps S91 to S92.

[0076] S91: 16 voltage sections corresponding to 4-bit data are determined.

[0077] In the QLC memory mode, one memory unit can store 4 bits corresponding to 16 kinds of state data, each occupying one voltage range, which can be easily distinguished according to the critical voltage of the voltage range when reading. The 16 voltage ranges are determined by 15 critical voltage values. The 15 critical voltage values ​​are read level 1 to read level 15.

[0078] S92: Determine four voltage sections defined by a first buffer area, a second buffer area, a third buffer area and a fourth buffer area.

[0079] After the logical operation, only four of the 16 types of state data remain. For example, assume that the voltage intervals corresponding to the four remaining types of voltage state data after the logical operation are the first interval, the fifth interval, the tenth interval, and the sixteenth interval. Meanwhile, in order to increase the reliability of the data, a new read voltage needs to be determined for it, that is, a new voltage interval needs to be defined for it to distinguish the remaining four types of voltage states. The four voltage intervals are determined by three critical voltage values.

[0080] The three critical voltage values ​​are represented by one of the 15 critical voltage values ​​and the corresponding offset amount. After determining the voltage intervals corresponding to the remaining four types of status data, the respective critical voltages are determined accordingly. Assume that the remaining voltage intervals are the first, fifth, tenth, and sixteenth voltage intervals, and the first, fifth, tenth, and sixteenth voltage intervals correspond to six types of critical voltages, i.e., read level 1, 4, 5, 9, 10, and 15. In order to effectively improve the reliability of each status data, the first new critical voltage is determined to be the intermediate voltage between the first and fifth voltage intervals, that is, the intermediate voltage between read level 1 and read level 4, and the voltage is obtained by adding half the difference between read level 1 and read level 4 to read level 1, or by subtracting half the difference between read level 1 and read level 4 from read level 4. Similarly, the second new critical voltage is determined to be a voltage between the fifth and tenth voltage sections, i.e., a voltage between read level 5 and read level 9, and the voltage is obtained by adding an offset value to read level 5 or subtracting an offset value from read level 9. The third new critical voltage is determined to be a voltage between the tenth and sixteenth voltage sections, i.e., a voltage between read level 10 and read level 15, and the voltage is obtained by adding an offset value to read level 10 or subtracting an offset value from read level 15. The determined new critical voltage is not necessarily in the middle of both basic critical voltages and can be adjusted according to the actual situation. However, if the new critical voltage is determined to be in the middle of both basic voltages, the reliability of each data can be improved as much as possible.

[0081] 13, which is a flow diagram of a tenth embodiment of the data storage method according to the present application, which is a further extension of the above embodiment and includes the following step S101.

[0082] S101: To read second data information stored in the storage unit, voltage information in the storage unit is compared with four voltage intervals.

[0083] After the data in the buffer area is stored in the memory unit, when reading, the data is read according to the determined new threshold voltage value.

[0084] Based on the above embodiment, it can be conceived that in the QLC storage unit, data is written into the first buffer area, the second buffer area, and the third buffer area according to the original threshold voltage value, and then eight kinds of voltage state data are obtained by logical operation, so that the data of the eight kinds of voltage states are evenly distributed throughout the entire voltage range. Furthermore, according to the original voltage ranges and threshold voltage values ​​corresponding to the eight kinds of voltage state data, new eight voltage ranges and corresponding seven threshold voltage values ​​are determined. The new seven threshold voltage values ​​may be obtained based on the threshold voltage values ​​corresponding to the eight kinds of voltage state data. After the data information stored in the buffer is stored in the storage unit, the storage unit is read by the new seven threshold voltage values. The method of such an embodiment is also within the scope of protection of the present application.

[0085] As shown in Fig. 14, which is a flow diagram of an eleventh embodiment of the data storage method according to the present application, the method includes the following steps S111 to S113.

[0086] S111: Data is written to the first buffer area, the second buffer area, and the third buffer area of ​​the page buffer.

[0087] In the QLC memory unit, data is written to the first buffer area, the second buffer area, and the third buffer area according to the original read level voltage value, in accordance with the original memory write flow.

[0088] S112: Write data into the fourth buffer area.

[0089] The data written to the fourth buffer area is obtained by performing a logical operation using the computing resources of the page buffer from any two of the data in the first buffer area, the data in the second buffer area, and the data in the third buffer area. The third data information is determined by the data in the first buffer area, the second buffer area, the third buffer area, and the fourth buffer area.

[0090] S113: The third data information stored in the page buffer is written to the storage unit.

[0091] After the data has been written into the buffer, the final data is written into the storage unit to complete the data storage.

[0092] In practical application, the first buffer area, the second buffer area, the third buffer area, and the fourth buffer area may be any one of all the configured buffer areas, and the first, second, third, and fourth do not limit the positions of the buffer areas, but only indicate that the positions of the buffer areas are different.

[0093] As shown in Fig. 15, Fig. 15 is a schematic flow diagram of a twelfth embodiment of the data storage method according to the present application. This method is a further expansion of step S113, and includes the following steps S121 to S122.

[0094] S121: Determine a corresponding section voltage signal according to third data information buffered in the page buffer.

[0095] After writing data to the first buffer area, the second buffer area, and the third buffer area, data in the fourth buffer area is obtained through logical operations using the computational resources of the page buffer, and eight types of voltage status data can finally be obtained. These eight types of status data become the data information currently stored in the buffer.

[0096] After the eight kinds of voltage state data are determined, the original voltage range and the critical voltage value of the voltage range can be further determined. The determination procedure can be referred to the above embodiment, and will not be repeated here.

[0097] S122: Write third data information into the storage unit according to the corresponding section voltage signal.

[0098] According to the determined buffer data, determine its voltage interval and threshold voltage value. Write data to the storage unit according to the interval voltage. The corresponding data information is that the voltage written to the storage unit is within the corresponding voltage interval. Please refer to the above embodiment, and it will not be repeated here.

[0099] 16, which is a flow diagram of a thirteenth embodiment of the data storage method according to the present application. This method is a further extension of the above-mentioned embodiments, and includes the following steps S131 to S132.

[0100] S131: 16 voltage intervals corresponding to 4-bit data are determined.

[0101] In the QLC memory mode, one memory unit can store 4 bits corresponding to 16 kinds of state data, each occupying one voltage range, which can be easily distinguished according to the critical voltage of the voltage range when reading. The 16 voltage ranges are determined by 15 critical voltage values. The 15 critical voltage values ​​are read level 1 to read level 15.

[0102] S132: Determine eight voltage sections defined by the first buffer area, the second buffer area, the third buffer area and the fourth buffer area.

[0103] After the logical operation, only 8 of the 16 types of state data remain. For example, assume that the voltage intervals corresponding to the remaining 8 types of voltage state data after the logical operation are the first interval, the third interval, the fifth interval, the seventh interval, the ninth interval, the eleventh interval, the thirteenth interval, and the sixteenth interval. Meanwhile, in order to increase the reliability of the data, it is necessary to determine a new read voltage for it, that is, it is necessary to define a new voltage interval for it to distinguish the remaining 8 types of voltage states. The 8 voltage intervals are determined by 7 critical voltage values.

[0104] The seven critical voltage values ​​are represented by one of the fifteen critical voltage values ​​and the corresponding offset amount. After determining the voltage intervals corresponding to the remaining eight types of state data, the critical voltages are determined accordingly. Assuming that the remaining intervals are the first interval, the third interval, and the fifth interval, and the critical voltage corresponding to the third interval is read level 2, 3, the first interval corresponds to read level 1, and the fifth interval corresponds to read level 4, 5, the first new critical voltage is in the middle between the first interval and the third interval, and may be the middle voltage between read level 1 and read level 2, which can be obtained by adding half the difference between read level 1 and read level 2 to read level 1, or by subtracting half the difference between read level 1 and read level 2 from read level 4. The other new critical voltages are determined by referring to the above description. The determined new critical voltage is not necessarily in the middle between the two basic critical voltages, and can be adjusted according to the actual situation. However, if the new critical voltage is determined to be midway between the two base voltages, the reliability of each data can be improved to the maximum extent possible.

[0105] 17, which is a flow diagram of a fourteenth embodiment of the data storage method according to the present application, which is a further extension of the above-mentioned embodiment, and includes the following step S141.

[0106] S141: To read the third data information stored in the storage unit, voltage comparison is performed between the voltage information in the storage unit and the eight voltage intervals.

[0107] After the data in the buffer area is stored in the memory unit, when reading, the data is read according to the eight new threshold voltage values ​​determined above.

[0108] Based on the above embodiment, further, for a storage device capable of storing multiple bits of information in one storage unit, the bit information stored in one storage unit is reduced by logical operations in the above-mentioned page buffer, but the technical aspects of increasing data reliability are all within the scope of protection of the present application.

[0109] As shown in FIG. 18, FIG. 18 is a structural schematic diagram of an embodiment of a storage device according to the present application.

[0110] The storage device includes a processor 110 and a memory 120 .

[0111] The processor 110 controls the operation of the storage device, and may further be referred to as a CPU (Central Processing Unit). The processor 110 may be an integrated circuit chip capable of processing signal sequences. The processor 110 may also be a general-purpose processor, a digital signal sequence processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, etc. The general-purpose processor may be a microprocessor, any conventional processor, etc.

[0112] The memory 120 stores instructions and program data necessary for the operation of the processor 110 .

[0113] The processor 110 is for executing instructions such that the method according to any one of the embodiments and possible combinations of the data storage methods described herein above is implemented.

[0114] The storage device may be a TLC / QLC NAND FLASH memory.

[0115] As shown in FIG. 19, FIG. 19 is a structural schematic diagram of an embodiment of a computer-readable storage device according to the present application.

[0116] An embodiment of the readable storage device of the present application includes a memory 210, which stores program data, and when the program data is executed, realizes a method according to any one of the embodiments of the data storage method of the present application and possible combinations thereof.

[0117] The memory 210 may be a medium capable of storing program instructions, such as a USB flash drive, a portable hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or the like, or a server that stores the program instructions, and the server may transmit the stored program instructions to other devices for operation, or may operate the stored program instructions itself.

[0118] In summary, the present application does not determine the data of the first and second buffer areas and then determine the data of the third buffer area using the threshold voltage value, but performs a logical operation on the data of the first and second buffer areas to obtain the data of the third buffer area, and since there are two types of buffer data, 0 or 1, and each buffer area stores buffer data of 1 bit of data information, in the prior art, when the first, second, and third buffer data is determined using the threshold voltage value, 8 types of data information are obtained, whereas in the present application, the data of the third buffer area is obtained by performing an operation on the already determined data of the first and second buffer areas, that is, the data status of the third buffer area corresponds to the 4 types of state data of the first and second buffer areas, so that the data information finally obtained based on the data of the first, second, and third buffer areas is only 4 statuses, not 8 statuses as originally intended. Since the occurrence status of the data information is reduced, a larger voltage section can be divided for the 4 types of data information within the same maximum voltage section, and the degree of error resistance to the data voltage offset is increased, thereby improving the reliability of the stored data. Furthermore, the logical operation process is realized by the logical operation function in the buffer, and there is no need to borrow the computing resources of the upper layer, so the computing power of the system is saved.

[0119] It should be understood that in some embodiments of the present application, the disclosed methods and devices may be realized in other forms. For example, the above-described device embodiments are merely illustrative. For example, the division of the modules or units is merely a division in terms of logical functions, and other division methods are possible in actual implementation. For example, multiple units or components may be incorporated or integrated into another system, or some features may be ignored or not implemented.

[0120] The units described as separate components may or may not be physically separated, and the components listed as units may or may not be physical units, i.e., they may be co-located or distributed across multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the aspects of the present embodiment.

[0121] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may be provided physically separately. Furthermore, two or more units may be integrated into one unit. The integrated unit may be realized in the form of hardware, or may be realized by adding a software functional unit to hardware.

[0122] The integrated units in the above other embodiments may be realized in the form of a software functional unit and stored in a computer-readable storage medium when sold or used as an independent product. Based on this understanding, the essential part of the technical aspects of the present application, or the part that contributes to the prior art, or all or part of the technical aspects can be embodied in the form of a software product. The computer software product is stored in one storage medium and includes several instructions to cause one computer device (which may be a personal computer, a server, or a network device) or a processor to execute all or part of the steps of the method according to each embodiment of the present application. The above-mentioned storage medium includes various media that can store program code, such as a USB flash drive, a portable hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0123] The above are merely examples of the present application and do not limit the scope of the claims of the present application. Any equivalent structure or equivalent flow transformation made by utilizing the contents of the specification and drawings of the present application, or direct or indirect application to other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. 1. A method of storing data, comprising: writing data into a first buffer area and a second buffer area of ​​a page buffer; writing data into a third buffer area of ​​the page buffer, the data to be written into the third buffer area being obtained from the data of the first buffer area and the data of the second buffer area through a logical operation using a computing resource of the page buffer, and first data information being determined by the data of the first buffer area, the second buffer area, and the third buffer area; writing the first data information buffered in the page buffer to a storage unit; Including, A data storage method comprising:

2. The writing of data to the third buffer area of ​​the page buffer includes: performing a first logical operation on the data in the first buffer area and the data in the second buffer area to obtain intermediate data; performing a second logical operation on the intermediate data and the data in the first buffer area to obtain data, the data being written to the third buffer area; or writing data obtained by performing a second logical operation on the intermediate data and the data in the second buffer area into the third buffer area; Including, 2. The method of claim 1, wherein the data is stored in a memory.

3. The above-mentioned first logical operation is performed on the data in the first buffer area and the data in the second buffer area to obtain intermediate data, After writing data to the first buffer area, copying the data of the first buffer area to the third buffer area; after writing the data into the second buffer area, performing a first logical operation on the data in the third buffer area and the data in the second buffer area to obtain intermediate data, and writing the intermediate data into the third buffer area; Including, writing data obtained by performing a second logical operation on the intermediate data and the data in the first buffer area into the third buffer area; writing data obtained by performing a second logical operation on the data in the third buffer area and the data in the first buffer area into the third buffer area; Including, 3. The method of claim 2, wherein the data is stored in a memory.

4. 4. The method of claim 2, wherein the first logical operation is an XNOR logical operation, and the second logical operation is an OR logical operation.

5. The writing of the first data information buffered in the page buffer to the storage unit includes: determining a corresponding section voltage signal according to the first data information buffered in the page buffer; writing the first data information into a storage unit according to the corresponding section voltage signal; 2. The method of claim 1, further comprising:

6. determining eight voltage intervals corresponding to three-bit data, the eight voltage intervals being determined by seven threshold voltage values; determining four voltage intervals defined by the first buffer region, the second buffer region, and the third buffer region, the four voltage intervals being defined by three threshold voltage values; Among them, the three critical voltage values ​​are represented by one of the seven critical voltage values ​​and a corresponding offset amount.

6. The method of claim 5, wherein the data is stored in a memory.

7. 7. The method of claim 6, further comprising: comparing voltage information in the memory unit with the four voltage intervals to read the first data information stored in the memory unit.

8. writing data into a fourth buffer area of ​​the page buffer, the data to be written into the fourth buffer area being obtained from any two of the data of the first buffer area, the data of the second buffer area, and the data of the third buffer area through a logical operation using a calculation resource of the page buffer, and second data information being determined by the data of the first buffer area, the second buffer area, the third buffer area, and the fourth buffer area; writing the second data information buffered in the page buffer to a storage unit; Further comprising:

2. The method of claim 1, wherein the data is stored in a memory.

9. The writing of the second data information buffered in the page buffer to the storage unit includes: determining a corresponding section voltage signal according to the second data information buffered in the page buffer; writing the second data information into a storage unit according to the corresponding section voltage signal; Including, 9. The method of claim 8, wherein the data is stored in a memory.

10. determining 16 voltage intervals corresponding to 4-bit data, the 16 voltage intervals being determined by 15 threshold voltage values; determining four voltage intervals defined by the first buffer region, the second buffer region, the third buffer region, and the fourth buffer region, the four voltage intervals being defined by three threshold voltage values; Further comprising: Among them, the three critical voltage values ​​are represented by one of the fifteen critical voltage values ​​and a corresponding offset amount.

10. The method of claim 9, wherein the data is stored in a memory.

11. voltage comparing the voltage information in the memory unit with the four voltage intervals to read the second data information stored in the memory unit; Further comprising:

11. The method of claim 10.

12. After writing data into the first buffer area and the second buffer area of ​​the page buffer, writing data to the third buffer area of ​​the page buffer; writing data into a fourth buffer area, the data to be written into the fourth buffer area being obtained from any two of the data of the first buffer area, the data of the second buffer area, and the data of the third buffer area through a logical operation using a calculation resource of the page buffer, and third data information being determined by the data of the first buffer area, the second buffer area, the third buffer area, and the fourth buffer area; writing the third data information stored in the page buffer to a storage unit; Including, 2. The method of claim 1, wherein the data is stored in a memory.

13. The writing of the third data information stored in the page buffer to the storage unit includes: determining a corresponding section voltage signal according to the third data information buffered in the page buffer; writing the third data information into a storage unit according to the corresponding section voltage signal; Including, 13. The method of claim 12.

14. determining 16 voltage intervals corresponding to 4-bit data, the 16 voltage intervals being determined by 15 threshold voltage values; determining eight voltage intervals defined by the first buffer region, the second buffer region, the third buffer region, and the fourth buffer region, the eight voltage intervals being defined by seven threshold voltage values; Further comprising: Among them, each of the eight critical voltage values ​​is represented by one of the fifteen critical voltage values ​​and a corresponding offset amount.

14. The method of claim 13.

15. Further comprising: comparing voltage information in the memory unit with the eight voltage intervals to read the third data information stored in the memory unit; 15. The method of claim 14.

16. A storage device comprising a memory and a processor, the memory being for storing program data, the program data being executable by the processor to implement the data storage method according to any one of claims 1 to 15.

16. A storage device comprising:

17. The storage device is a TLC / QLC NAND FLASH memory.

17. The storage device according to claim 16 .

18. A computer readable storage device storing program data that can be executed by a processor to implement the data storage method according to any one of claims 1 to 15.

16. A computer readable storage device comprising:

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