Write-combining by HMB for optimizing write performance

Abstract

The present disclosure generally relates to improved processing of write commands. A host memory buffer (HMB) or other storage space can be utilized to delay the execution of host write commands, which improves write performance in different use cases and enables having more concurrent streams than open blocks without affecting write or read performance. Generally, when a write command is received, the write command is modified as a new write command that is logically equivalent to the original write command. The modified write command is moved to the HMB along with the data. By doing so, the write commands are coalesced and the processing of the write commands is improved.

Description

Technical Field

[0001] Cross - Reference to Related Applications This application claims the benefit of U.S. Non - Provisional Patent Application No. 17 / 885,265, entitled "Write Coalescing Via HMB To Optimize Write Performance", filed on August 10, 2022, and incorporates the entire contents thereof by reference herein for all purposes.

Background Art

[0002] Embodiments of the present disclosure generally relate to improved write command processing.

[0003] Field of the Invention Write performance is important for both client and server storage applications and is one of the most important metrics for clients. Write performance can be hampered in different use cases limited by system resources. For example, a data storage device typically holds open blocks for each stream ID currently in use by the host, and data written from a stream ID is written to the corresponding open block.

[0004] If the number of open blocks in the data storage device is less than the number of different streams, it may cause excessive writes and reads, resulting in the problem of reducing write performance. When the host writes data to the data storage device, it may be useful to temporarily store the data in an intermediate space to perform some operation before actually writing the data to the storage medium. This intermediate storage space may be a dedicated buffer within the storage space of the data storage device, but instead, to save space, it may be a host memory buffer (HMB) located within the host. The HMB is a host storage space dedicated to the needs of the storage controller. Usually, the HMB stores a management table or other management data according to the configuration of the controller.

[0005] In an existing architecture, when a corresponding write command is interpreted, the written data is directly passed from the host's data buffer to the controller of the data storage device by a Hardware (HW) module. Information regarding command interpretation is passed to a completion queue. The write data itself does not necessarily have to be immediately written to the memory device and may be stored in a cache. The cache may be within the data storage device or on the host side within the HMB.

[0006] If the number of concurrent streams is greater than the number of open blocks, the data coming from the streams may be written to the same open block, which may later degrade the read throughput. The data from these extra streams can also be rearranged when later inducing write amplification. Alternatively, the host may be restricted to the number of streams determined by the number of open blocks.

[0007] Therefore, there is a need in the art to improve the processing of write commands. SUMMARY OF THE INVENTION

[0008] The present disclosure generally relates to improved processing of write commands. A host memory buffer (HMB) or other storage space can be utilized to delay the execution of host write commands, which improves write performance in different use cases and enables having more concurrent streams than open blocks without affecting write or read performance. Generally, when a write command is received, the write command is modified as a new write command that is logically equivalent to the original write command. The modified write command is moved to the HMB along with the data. By doing so, the write commands are combined and the processing of the write commands is improved.

[0009] In one embodiment, the data storage device includes a first memory device and a controller coupled to the memory device. The controller is configured to receive a write command, determine that the write command can be coalesced, allocate one or more buffers in a second memory device separate from the first memory device, generate a modified write command from the write command, and move data associated with the write command to at least one of the allocated one or more buffers.

[0010] In another embodiment, the data storage device includes a first memory device and a controller coupled to the memory device. The controller is configured to receive a write command, modify the write command to create a modified write command, store the modified write command in a second memory device different from the first memory device, determine that a predetermined period has elapsed or a trigger mechanism has occurred, and execute the modified write command.

[0011] In another embodiment, the data storage device includes a memory means and a controller coupled to the memory means. The controller is configured to convert a write command from a Physical Region Page (PRP) entry to a Scatter-Gather List (SGL) entry, store the data associated with the PRP entry and the converted write command in a host device, notify the host device that the write command has been completed, and after the notification, execute the converted write command, which includes writing the stored data to the memory means.

Brief Description of the Drawings

[0012] To enable a more detailed understanding of the above features of the present disclosure, a more specific description of the present disclosure, briefly summarized above, may be made by reference to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only typical embodiments of the present disclosure and should not be considered as limiting its scope, as the present disclosure may admit other equally effective embodiments.

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[0013] For ease of understanding, the same reference numbers are used as much as possible to denote the same elements common to the drawings. It is contemplated that elements disclosed in one embodiment may be beneficially utilized in other embodiments without particular recitation. DETAILED DESCRIPTION OF THE INVENTION

[0014] The following refers to embodiments of the present disclosure. However, it should be understood that the present disclosure is not limited to the specifically described embodiments. Instead, any combination of the following features and elements is intended to implement and practice the present disclosure, regardless of whether they are related to different embodiments. Furthermore, embodiments of the present disclosure may achieve advantages over other possible solutions and / or over the prior art, but whether a particular advantage is achieved by a given embodiment does not limit the present disclosure. Thus, the following aspects, features, embodiments, and advantages are merely illustrative and are not considered elements or limitations of the appended claims, except as explicitly recited in the claims (s). Similarly, references to "the present disclosure" should not be construed as a generalization of the subject matter of any invention disclosed herein and should not be considered an element or limitation of the appended claims, except as explicitly recited in the claims.

[0015] The present disclosure generally relates to improved processing of write commands. A host memory buffer (HMB) or other storage space can be utilized to delay the execution of host write commands, which improves write performance in different use cases and enables having more simultaneous streams than open blocks without affecting write or read performance. Generally, when a write command is received, the write command is modified as a new write command that is logically equivalent to the original write command. The modified write command is moved to the HMB along with the data. By doing so, write commands are consolidated and the processing of write commands is improved.

[0016] FIG. 1 is a schematic block diagram showing a memory system 100 in which a host device 104 communicates with a data storage device 106 according to a particular embodiment. For example, the host device 104 may utilize a non-volatile memory (NVM) 110 included in the data storage device 106 to store and retrieve data. The host device 104 includes a host DRAM 138 and optionally a host memory buffer 150. In some embodiments, the memory system 100 may include multiple storage devices such as the data storage device 106 that can operate as a memory array. For example, the memory system 100 may include multiple data storage devices 106 configured as a redundant array of inexpensive / independent disks (RAID) that collectively function as a mass storage device for the host device 104.

[0017] The host device 104 may store and / or retrieve data to and / or from one or more storage devices such as the data storage device 106. As illustrated in FIG. 1, the host device 104 may communicate with the data storage device 106 via an interface 114. The host device 104 may comprise any of a wide range of devices including, for example, a computer server, a network-attached storage (NAS) unit, a desktop computer, a notebook (i.e., laptop) computer, a tablet computer, a set-top box, a telephone such as a so-called "smart" phone, a so-called "smart" pad, a television, a camera, a display device, a digital media player, a video game console, a video streaming device, or any other device capable of transmitting or receiving data from a data storage device.

[0018] The data storage device 106 includes a controller 108, an NVM 110, a power supply 111, a volatile memory 112, an interface 114, and a write buffer 116. In some embodiments, the data storage device 106 may include additional components not shown in FIG. 1 for clarity. The controller 108 may include a volatile memory such as a DRAM 152 and a controller memory buffer (CMB) dedicated to the use of the host device 104. For example, the data storage device 106 may include a printed circuit board (PCB) to which components such as the data storage device 106 are mechanically attached and which includes conductive traces for electrically interconnecting the components of the data storage device 106. In some embodiments, the physical dimensions and connector configuration of the data storage device 106 may conform to one or more standard form factors. Some exemplary standard form factors include, but are not limited to, 3.5” data storage devices (e.g., HDDs or SSDs), 2.5” data storage devices, 1.8” data storage devices, Peripheral Component Interconnect (PCI), PCI Extended (PCI-X), PCI Express (PCIe) (e.g., PCIe×1, ×4, ×8, ×16, PCIe mini cards, mini PCI, etc.). In some embodiments, the data storage device 106 may be directly coupled (e.g., directly soldered or plugged into a connector) to the motherboard of the host device 104.

[0019] Interface 114 may include one or both of a data bus for exchanging data with host device 104 and a control bus for exchanging commands with host device 104. Interface 114 may operate according to any suitable protocol. For example, Interface 114 may operate according to one or more of the following protocols: Advanced Technology Attachment (ATA) (e.g., Serial ATA (SATA) and Parallel ATA (PATA)), Fibre Channel Protocol (FCP), Serial Attached SCSI (SAS), PCI, and PCIe, Small Computer System Interface (SCSI), Non-Volatile Memory Express (NVMe), OpenCAPI, GenZ, Cache Coherent Interface Accelerator (CCIX), Open Channel SSD (OCSSD), etc. Interface 114 (e.g., the data bus, the control bus, or both) is electrically connected to controller 108, provides an electrical connection between host device 104 and controller 108, and enables the exchange of data between host device 104 and controller 108. In some embodiments, the electrical connection of Interface 114 may also enable data storage device 106 to receive power from host device 104. For example, as illustrated in FIG. 1, power supply 111 may receive power from host device 104 via Interface 114.

[0020] The NVM 110 may include a plurality of memory devices or memory units. The NVM 110 may be configured to store and / or retrieve data. For example, the memory units of the NVM 110 may receive data and a message from the controller 108 that instructs the memory unit to store the data. Similarly, the memory unit may receive a message from the controller 108 that instructs the memory unit to retrieve the data. In some embodiments, each of the memory units may be referred to as a die. In some embodiments, the NVM 110 may include a plurality of dies (i.e., a plurality of memory units). In some embodiments, each memory unit may be configured to store a relatively large amount of data (e.g., 128 MB, 256 MB, 512 MB, 1 GB, 2 GB, 4 GB, 8 GB, 16 GB, 32 GB, 64 GB, 128 GB, 256 GB, 512 GB, 1 TB, etc.).

[0021] In some embodiments, each memory unit may include any type of non-volatile memory device, such as a flash memory device, a phase change memory (PCM) device, a resistive random access memory (ReRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (F-RAM), a holographic memory device, and any other type of non-volatile memory device.

[0022] The NVM 110 may include a plurality of flash memory devices or memory units. The NVM flash memory device may include a NAND or NOR-based flash memory device and may store data based on the charge contained in the floating gate of the transistor of each flash memory cell. In the NVM flash memory device, the flash memory device may be divided into a plurality of dies, each die of the plurality of dies includes a plurality of physical blocks or logical blocks, and the plurality of physical blocks or logical blocks may be further divided into a plurality of pages. Each block of the plurality of blocks within a particular memory device may include a plurality of NVM cells. The rows of the NVM cells may be electrically connected using word lines to define each page of the plurality of pages. Each cell in each of the plurality of pages may be electrically connected to a respective bit line. Further, the NVM flash memory device may be a 2D or 3D device and may be a single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), or quad-level cell (QLC). The controller 108 may write data to the NVM flash memory device and read data from the NVM flash memory device at the page level, and may erase data from the NVM flash memory device at the block level.

[0023] Power supply 111 can supply power to one or more components of data storage device 106. When operating in standard mode, power supply 111 can supply power to one or more components using power provided by an external device such as host device 104. For example, power supply 111 can supply power to one or more components using power received from host device 104 via interface 114. In some embodiments, power supply 111 can include one or more power storage components configured to supply power to one or more components when operating in a shutdown mode, such as when power reception from an external device is stopped. Thus, power supply 111 can function as an on-board power supply. Some examples of one or more power storage components include, but are not limited to, capacitors, supercapacitors, batteries, etc. In some embodiments, the amount of power that can be stored by one or more power storage components can be a function of the cost and / or size (e.g., area / volume) of the one or more power storage components. In other words, as the amount of power stored by one or more power storage components increases, the cost and / or size of the one or more power storage components also increases.

[0024] Volatile memory 112 can be used by controller 108 to store information. Volatile memory 112 can include one or more volatile memory devices. In some embodiments, controller 108 can use volatile memory 112 as a cache. For example, controller 108 can store information cached in volatile memory 112 until the cached information is written to NVM 110. As illustrated in FIG. 1, volatile memory 112 can consume power received from power supply 111. Examples of volatile memory 112 include, but are not limited to, random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, etc.)).

[0025] The controller 108 may manage one or more operations of the data storage device 106. For example, the controller 108 may manage the reading of data from the NVM 110 and / or the writing of data to the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 may initiate a data storage command to store the data in the NVM 110 and monitor the progress of the data storage command. The controller 108 may determine at least one operating characteristic of the storage system 100 and store the at least one operating characteristic in the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 temporarily stores this data in the internal memory of the controller 108 (i.e., the second volatile memory) before transmitting the data associated with the write command to the NVM 110. This memory may be SRAM memory.

[0026] FIG. 2 is a block diagram showing a method 200 for operating a storage device to execute a read or write command according to an embodiment. The method 200 may be used with the storage system 100 of FIG. 1 having a host device 104 and a data storage device 106, and the data storage device includes a controller 108.

[0027] The method 200 begins at operation 250, where the host device writes a command as an entry to a submission queue (SQ). The host device may write one or more commands to the SQ in operation 250. The command may be a read command or a write command. The host device may include one or more SQs.

[0028] In operation 252, the host device writes one or more updated SQ tail pointers and rings a doorbell or sends an interrupt signal to notify or signal the storage device of new commands that are ready to be executed. The host may write the updated SQ tail pointers and send a doorbell or interrupt signal for each of the SQs if there are two or more SQs. In operation 254, in response to receiving the doorbell or interrupt signal, the controller of the storage device fetches commands from one or more SQs and the controller receives the commands.

[0029] In operation 256, the controller processes the commands and writes or transfers the data associated with the commands to the host device memory. The controller may process two or more commands at a time. The controller may process one or more commands in the order of transmission or sequential order. Processing a write command may include identifying the zone to write the data associated with the command, writing the data to one or more logical block addresses (LBAs) of the zone, and advancing the write pointer of the zone to identify the next available LBA within the zone.

[0030] In operation 258, when the command is fully processed, the controller writes a completion entry corresponding to the executed command to the completion queue (CQ) of the host device and moves or updates the CQ head pointer to point to the newly written completion entry.

[0031] In operation 260, the controller generates an interrupt signal or a doorbell and sends it to the host device. The interrupt signal indicates that the command has been executed and the data associated with the command is available in the memory device. The interrupt signal further notifies the host device that the CQ is ready to be read or processed.

[0032] In operation 262, the host device processes the completion entry. In operation 264, the host device writes the updated CQ head pointer to the storage device and rings the doorbell or sends an interrupt signal to the storage device to free the completion entry.

[0033] FIG. 3 is a flowchart 300 showing the execution of a write command. First, a write command is received. Next, at 302, the write command is processed. At 304, data corresponding to the write command is fetched from the host device. The data is typically in the host device data buffer. Next, the data is processed and stored in the cache. The cache may be the HMB, CMB, controller DRAM, or NVM of the data storage device. When the data enters the cache, the completion queue is updated at 306.

[0034] As described herein, the write sequence is modified so that data can be stored in the HMB (or any similar host-based memory space) or CMB in order to delay the execution of host write commands and improve the overall write performance of the system. Thus, more simultaneous streams than open blocks are possible without degrading write performance.

[0035] The method is based on analyzing the write workflow and determining that temporarily delaying the actual writes to the memory device will benefit the overall write performance. The determination may be based on host-specified or device-specified write alignment / granularity considerations. For example, writes that do not meet the stream write granularity or namespace write granularity guidance may be coalesced. In another example, writes may be temporarily coalesced if urgent foreground maintenance is required to free open blocks, allowing the host to free the write buffer while the device is unable to simultaneously write new data to the memory device (i.e., NAND).

[0036] The write coalescing function includes a hardware (HW) modification such that the host device pointer is modified and written to point to the HMB space. The HW automatically direct memory accesses (DMA) the original payload to the new HMB location before automatically completing the command. Following the DMA, the firmware (FW) or HW can release the write, and then the write is resent as if the write were a new write command without additional completion.

[0037] Figure 4 is a schematic diagram of an architecture incorporating a write command coalescing, showing the concept using an example. The original NVMe write command 406 in the host memory 402 is queued in the transmit queue 404 by the host. The command 406 holds a pointer to a data buffer. PRP1 holds a pointer to a first buffer. PRP2 holds a pointer to the PRP list 408, each being a pointer to a data buffer 410. The device controller first fetches the original write command, classifies the original write command, and determines whether to execute the write command now or defer it. This decision is based on the classification result (e.g., stream ID) and the current state of the open blocks within the device. If the write command is deferred, the content of the write command is copied to the HMB 412 with some adaptation. In Figure 4, the modified command 416 uses the scatter-gather list (SGL) method and does not use the physical region page (PRP). The modified command 416 including the SGL segment is stored in the internal transmit queue 404 implemented in the HMB 412. The device prepares an SGL list 418 in the HMB 412, each entry pointing to a data buffer 420 within the HMB. The data from the original data buffer 410 is copied to the data buffer 420 allocated within the HMB 412. A completion entry is notified to the host device. Later, the modified command 416 is executed by the data storage device while fetching all relevant information from the HMB 412. The completion entry is not notified to the host device as it has already been notified when copying the original data from the data buffer 410 to the data buffer 420.

[0038] After command interpretation, the new "write coalescing module" can analyze the current write considering the state of the last command, HMB content, and memory-related characteristics. The module can then determine whether to delay the command using the HMB, write the data directly to the storage device (normal write), or execute a previously delayed command from the HMB and write the delayed command data to the data storage device together with the current write data.

[0039] When the host device issues a flash command instructing the data storage device to write all data that has not yet been written to the memory device, the data storage device executes all previously delayed commands and writes the data to the memory device. In one embodiment, the data storage device typically has a limited number of reserved open blocks. An open block is a block that has not been fully written, and different protection mechanisms are applied due to reduced tolerance to different factors. When a block is fully written, that block is closed and another block is opened instead. In a host device that supports streams, the open blocks may be associated with a stream so that continuously written data is written to the same physical block (meta-block). However, the number of streams supported by the host device may be more than the number of available open blocks in the memory device. As described herein, it is proposed to use write coalescing to stack data related to a particular stream (not supported by the open blocks in the storage controller) within the HMB. HMB-based data may be written to the memory device when complete blocks are coalesced or at another time determined by the controller, which allows for effective support of any number of simultaneous streams without the need to dedicate space in the controller.

[0040] Figure 5 is a flowchart 500 showing a write command combination according to an embodiment showing a write process. First, a write command is received, and classification of the write command (such as stream ID) and the current state of the system (such as open block count) is performed at 502 in the write combination module, and a determination is made at 504 as to whether a combination should be performed on the command. In the case of a positive result, an HMB space is allocated at 506. At 508, a modified write command is generated in the HMB together with a pointer list to the HMB. At 510, the write command data content is copied to the allocated location, and at 512, a completion entry is notified to the host device. At 504, if a write combination for the write command should not be applied, at 514, the corresponding data is fetched from the data buffer, processed, stored in the cache, and then the completion queue is updated at 512.

[0041] Figure 6 is a flowchart 600 showing a delayed command flow execution according to an embodiment, explaining the decision to write the content of a delayed write command from the HMB to a data storage device. The decision to execute a delayed command may be caused by either a "flush" command sent by the host device or the number of open blocks changed (some blocks closed) by the data storage device. When a decision is made to write a delayed write command from the HMB, the data is written to the storage device and no additional overhead related to notifying the host device of a completion entry is required.

[0042] In one embodiment, the device controller implements a reserved SQ that is not visible to the host device. The data storage device queues the modified write commands to the reserved SQ. If there is a trigger to execute some of the modified commands, the data storage device simply rings the doorbell of the associated reserved SQ. Then, the modified write commands within the reserved SQ are executed as normal, except that there is no notification to the CQ. In other words, while the reserved SQ exists, the corresponding reserved CQ does not exist, and thus there is no place to notify completion. Since completion should have been notified previously, it is not necessary to notify completion to the normal CQ. The number of reserved SQs may be a function of the supported streams and open blocks.

[0043] When the cached operation is invalidated by the host device either globally or command-specific, the same flow functions, and the only difference is that completion is sent only after the execution of the modified command is complete and only after the data is stored in the memory device (e.g., NAND).

[0044] In flowchart 600, when a trigger event occurs or a predetermined time elapses, at 602, a determination is made as to whether it is time to execute the deferred command. The trigger event can be, for example, a flash command. If it is not time to execute the deferred write command, the process continues to wait. If it is time to execute the deferred write command, at 604, the HW is activated to execute the deferred write command, and at 606, the deferred write command is executed. The deferred write command is executed using the HMB as the data buffer instead of the host data buffer as in the original write command. When the deferred write command is complete, the completion queue is not updated at 608. This is because the completion queue was previously updated when the deferred write command was created and the data was stored in the HMB buffer.

[0045] In another embodiment, a CMB-based write delay for combining small write commands may be used. The CMB is a memory buffer located within a data storage device controller that may be used for different host device applications. In this context, the CMB may be used as a memory space (typically a much smaller memory space) for delaying shorter write commands.

[0046] FIG. 7 is a schematic diagram of a system 700 incorporating write command coalescing, showing a high-level block diagram of the system for write command coalescing. System 700 includes a host device 702 having a DRAM 704 and an HMB 706. System 700 also includes a memory device 710 and a data storage device controller 708.

[0047] The controller 708 includes one or more processors 724, a Flash Interface Module (FIM) 726 for interfacing with the memory device 710, a Host Interface Module (HIM) 712 for interfacing with the host device 702, a command scheduler 722 coupled between the FIM 726 and the HIM 712, an encryption / decryption module 718 disposed between the FIM 726 and the HIM 712, and a data path and ECC and RAID disposed between the encryption / decryption module 718 and the FIM 726. The HIM 712 includes an HMB write command coalescing module 714, which determines when to execute the write command while activating a DMA copy engine 716 for copying commands with some modifications and all data structures from the host device 702 memory to the HMB 706.

[0048] In one embodiment, the modified command held in the HMB can be a write-dispersed command that includes not just one but several LBA ranges. In an embodiment of the write-dispersed command, several host device write commands can be compressed into a single modified write-dispersed command stored in the HMB. In another embodiment, the grouping of the delayed write commands may be based on a context attribute identifier or on regions / zones within the DPM / ZNS device.

[0049] FIG. 8 is a flowchart 800 showing the coalescence and execution of write commands according to one embodiment. The process starts when a write command is received at 802, and more specifically, the write command is placed in a transmit queue within the host, and a doorbell rings to notify the data storage device that there is a command to fetch in the transmit queue. At 804, a determination is made as to whether the write commands can be coalesced. If the write commands cannot be coalesced at 804, the write commands are executed as normal and the completion queue is updated to indicate that the write commands have been executed.

[0050] If the write commands can be coalesced at 804, the write commands are modified at 808 and stored in a new location along with the data. In one embodiment, the new location is the HMB. In another embodiment, the new location is the CMB. In yet another embodiment, the new location is within the host controller volatile memory. In any of the embodiments, the new location is not the NVM where the data of the original write command is ultimately written. After modifying the write commands and storing the associated data in the new location, at 810, completion is notified to the completion queue and a doorbell rings to notify the host that the write commands have completed even though the write commands have not actually completed, thereby updating the completion queue. At this point, the write commands have been modified and the data has been moved to the new location. The modified write commands are executed at a later point in time when the original write commands technically finally complete.

[0051] The corrected write command can be executed after a predetermined period has elapsed or after a trigger event has occurred. If it exceeds the time threshold at 812, at 814, the corrected command is executed and no completion is notified to the completion queue at 816. If it does not exceed the time threshold at 812, a determination is made at 818 as to whether a trigger event has occurred. If a trigger event has occurred at 818, at 814, the corrected command is executed and no completion is notified to the host at 816. If no trigger event has occurred at 818, the corrected write command is still not executed and simply waits to be executed. Note that the check for whether the trigger event and the time threshold have been exceeded may be performed in any order or simultaneously. An example of a trigger event is the receipt of a flash command from the host. In any case, the host is not notified regardless of when the corrected write command is executed. This is because the host recognizes that the write command has already been completed and is unaware of the existence of the corrected write command.

[0052] In any case, the host is notified that the original write command has been completed before the corrected write command is completed. In other words, the host device recognizes that the original write command has been completed even if the original write command has not actually been completed and the data to be written to the NVM has not yet been written to the NVM. Completing the corrected write command technically means completing the original write command by writing the data to the NVM, but this is done after the host recognizes it, and thus the write command is processed more effectively and efficiently. The location for storing the corrected write command and related data waiting to be executed is in a memory location such as HMB, CMB, or another storage location other than the final storage location indicated by the original write command (i.e., NVM or NAND).

[0053] By using a write command aggregation in the HMB (or CMB or other memory areas), improved write performance is achieved for different scenarios, such as having more concurrent streams than open blocks, and thus the write commands are processed more effectively and efficiently.

[0054] In one embodiment, the data storage device includes a first memory device and a controller coupled to the memory device. The controller is configured to receive a write command, determine that the write command can be write-aggregated, allocate one or more buffers in a second memory device separate from the first memory device, generate a modified write command from the write command, and move data associated with the write command to at least one of the allocated one or more buffers. The controller is further configured to generate a pointer list to the at least one buffer. The controller is configured to update a completion queue for the write command. The update is performed before completing the write command. The update is performed after execution of the modified write command. The second memory device is a host memory buffer (HMB). The second memory device is a controller memory buffer (CMB). The write command is a non-volatile memory express (NVMe) write command using one or more physical region page (PRP) entries. The modified write command uses scatter-gather list (SGL) elements. The controller is further configured to execute the modified write command in response to either a trigger mechanism or a predetermined period of time having elapsed.

[0055] In another embodiment, the data storage device comprises a first memory device and a controller coupled to the memory device, the controller receiving a write command, modifying the write command to create a modified write command, storing the modified write command in a second memory device different from the first memory device, determining that a predetermined period has elapsed or that a trigger mechanism has occurred, and executing the modified write command. The controller is further configured to activate hardware (HW) to execute the modified write command. Executing the modified write command includes retrieving data associated with the modified write command from the second memory device. Storing the modified write command in the second memory device includes storing the modified write command and data associated with the write command in the second memory device. Executing the modified write command includes retrieving data associated with the write command from the second memory device and writing the data to the first memory device. The completion queue in the host device is updated before the modified write command is executed. The completion queue is not updated after the modified write command is executed.

[0056] In another embodiment, the data storage device comprises memory means and a controller coupled to the memory means, the controller converting a write command from a physical region page (PRP) entry to a scatter-gather list (SGL) entry, storing the data associated with the PRP entry and the converted write command in the host device, notifying the host device that the write command has been completed, and after the notification, executing the converted write command, the execution including writing the stored data to the memory means. The controller is configured not to notify the host device that the converted write command has been executed. The controller is configured to execute the converted write command after receiving a flush command from the host device.

[0057] The foregoing is intended to be illustrative of embodiments of the present disclosure, but other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof, which is determined by the claims that follow.

Claims

1. A first memory device, A controller coupled to the memory device, Comprising, the controller being configured to: Receive a write command, Determine that the write command can be write-combined, Allocate one or more buffers in a second memory device separate from the first memory device, Generate a modified write command from the write command, Move data associated with the write command to at least one of the allocated one or more buffers, A data storage device configured as such.

2. The data storage device according to claim 1, wherein the controller is further configured to generate a pointer list to the at least one buffer.

3. The data storage device according to claim 1, wherein the controller is configured to update a completion queue for the write command.

4. The data storage device according to claim 3, wherein the update is performed before completing the write command.

5. The data storage device according to claim 4, wherein the update is performed after execution of the modified write command.

6. The data storage device according to claim 1, wherein the second memory device is a host memory buffer (HMB).

7. The data storage device according to claim 1, wherein the second memory device is a controller memory buffer (CMB).

8. The data storage device according to claim 1, wherein the write command is a non-volatile memory express (NVMe) write command using one or more physical region page (PRP) entries.

9. The data storage device according to claim 8, wherein the modified write command uses scatter-gather list (SGL) elements.

10. The data storage device according to claim 1, wherein the controller is further configured to execute the modified write command in response to either a trigger mechanism or a predetermined period of time having elapsed.

11. A first memory device, A controller coupled to the memory device, Comprising, the controller being configured to: Receive a write command, Modify the write command to create a modified write command, Store the modified write command in a second memory device different from the first memory device, Determine whether a predetermined period has elapsed or a trigger mechanism has occurred, Execute the modified write command, A data storage device configured as described above.

12. The data storage device according to claim 11, wherein the controller is further configured to activate hardware (HW) to execute the modified write command.

13. The data storage device according to claim 12, wherein executing the modified write command includes retrieving data associated with the modified write command from the second memory device.

14. The data storage device according to claim 13, wherein storing the modified write command in the second memory device includes storing the modified write command and data associated with the write command in the second memory device.

15. The data storage device according to claim 11, wherein executing the modified write command includes retrieving data associated with the write command from the second memory device and writing the data to the first memory device.

16. The data storage device according to claim 15, wherein a completion queue in the host device is updated before executing the modified write command.

17. The data storage device according to claim 16, wherein the completion queue is not updated after executing the modified write command.

18. Memory means, A controller coupled to the memory means, Comprising, the controller, Convert a write command from a physical region page (PRP) entry to a scatter-gather list (SGL) entry, Store the data associated with the PRP entry and the converted write command in the host device, Notify the host device that the write command has been completed, After the notification, execute the converted write command, which is configured to include writing the stored data to the memory means, a data storage device.

19. The data storage device according to claim 18, wherein the controller is configured not to notify the host device that the converted write command is to be executed.

20. The data storage device according to claim 18, wherein the controller is configured to execute the converted write command after receiving a flash command from the host device.

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