High-speed TX topology with a supply-controlled serialization stage embedded in the PMOS output stage

Abstract

A high-speed transmitter system is disclosed that uses a supply-controlled serialization stage embedded in a PMOS output stage. In some embodiments, the transmitter includes a serialization circuit configured to convert parallel data to serial data by one or more serialization stages, a logic circuit configured to connect each input of the last stage of the one or more serialization stages of the serialization circuit to a respective dedicated output stage of an output circuit via respective logic functions, and an output circuit configured to implement an output stage to generate a signal using PMOS transistors based on the received input. Also, the logic circuit is connected to a low-voltage power supply, whereby its output can be adjusted to be close to the switching point of a PMOS-based gm stage so as to accelerate the operation of the transmitter.

Description

Technical Field

[0001] The present disclosure relates to a transmitter system that uses a supply controlled serialization stage and a p-channel metal oxide semiconductor (PMOS)-based output stage to enable high-speed operation, low power consumption, and high reliability.

Background Art

[0002] A transmitter (Tx) is an important component of a physical layer communication system. It is an electronic component that converts a digital signal from an encoder into an analog signal that can be transmitted through a transmission medium (e.g., wiring, wireless channel) and received by a receiver (Rx). The data transmitted by the Tx is often generated by a logic unit. Usually, the logic unit generates data at a much slower speed than the data rate that the Tx can handle. Therefore, in order to achieve the required data rate, parallel-in, serial-out (PISO) conversion is widely used in the Tx. Serialization is generally implemented by a chain of multiplexers (muxes) to output a single signal with a high frequency. However, this topology (especially the last mux) has a large speed limitation and can hardly or not at all meet the speed requirements of state-of-the-art Tx systems.

Summary of the Invention

[0003] To address the above drawbacks, a high-speed transmitter system is disclosed that uses a supply-controlled serialization stage embedded in a PMOS output stage. In some embodiments, the transmitter includes a serialization circuit configured to convert parallel data to serial data by one or more serialization stages, a logic circuit configured to connect each input of the last stage of the one or more serialization stages of the serialization circuit to each dedicated output stage of the output circuit via respective logic functions, and an output circuit configured to implement an output stage to generate a signal using PMOS transistors based on the received input. Also, the logic circuit is connected to a low-voltage power supply, whereby its output can be adjusted to be close to the switching point of the PMOS-based gm stage so as to accelerate the operation of the transmitter.

[0004] The above and other preferred features, including various novel implementation details and combinations of elements, will be described more specifically hereinafter with reference to the accompanying drawings and pointed out in the claims. It will be understood that the specific methods and apparatuses are shown by way of example only and not as limitations. As will be understood by those skilled in the art, the principles and features described herein may be used in a variety of embodiments.

[0005] The disclosed embodiments have advantages and features that will become more readily apparent from the detailed description, the appended claims, and the accompanying drawings (or figures). A brief introduction to the figures is as follows.

Brief Description of the Drawings

[0006]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

[0007] The drawings and the following description are related to preferred embodiments for illustrative purposes only. From the following description, alternative embodiments of the structures and methods disclosed herein will be readily recognized as viable alternatives that can be used without departing from the principles of what is claimed.

[0008] Some embodiments will now be referred to in detail, examples of which are illustrated in the accompanying drawings. Wherever practicable, similar or the same reference numbers may be used in the figures and may indicate similar or the same functions. The figures represent embodiments of the disclosed system (or method) for illustrative purposes only. Those skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods represented herein can be used without departing from the principles described herein.

[0009] FIG. 1 shows an exemplary topology 100 of a DAC-based Tx. Note that while a DAC-based Tx is provided, the systems and approaches described herein are not limited to only DAC-based Tx topologies and are applicable to all Tx topologies using analog output drivers. The example of the DAC-based Tx in FIG. 1 includes three parts (a), (b), and (c). In FIG. 1(a), a logic unit or data acquisition circuit generates the data to be transmitted by the Tx. In this example, the data is generated in m parallel branches or links.

[0010] The data generated by the m parallel branches has a data rate that is much slower (e.g., 160 times slower in FIG. 1) than the data rate of Tx. As described above, due to this low-speed data generation from the logic section, Tx often uses PISO to increase the data rate. PISO enables the data to be converted from a parallel format to a serial format. The data is loaded into Tx in parallel format. That is, data bits are generated and provided simultaneously on multiple low-speed branches (e.g., individual wirings). Then, the data is output after serialization. That is, data bits are output sequentially in time on a single wiring or branch. In other words, the PISO conversion can enable the data received in parallel to be stored, shifted based on a clock, and delayed by the product of the clock period and the number of stages until a single data stream is obtained. FIG. 1(b) shows PISO or serialization, where data with a lower rate is serialized to reach the required higher data rate for Tx.

[0011] As shown in FIG. 1(b), the serialization process can be implemented by a chain of multiplexers, e.g., mux102, 104, and 106. Each mux is controlled by a clock phase such that the correct data can be routed to the output at the appropriate time. The result of the serialization process is a single signal with a high frequency. Unfortunately, this topology (mainly the last mux) is speed-limited and often cannot meet the speed requirements of Tx. The system of the present application described herein addresses the speed-limitation problem and dramatically improves system performance.

[0012] In some embodiments, as shown in FIG. 1(c), when the data is serialized, the output stage 112 is driven to convert the input serialized data 108 into an analog signal 110.

[0013] In non-return-to-zero (NRZ) Tx, each analog symbol is represented by a single logic bit. However, in DAC-based Tx, when equalization is used, each analog symbol may contain multiple digital bits, and a combination of digital bits generates the analog symbol. As can be seen from FIG. 1, the analog symbol 110 can be generated by m analog segments. Here, m is a positive integer. In this example, the m analog segments are mutual conductance (gm) segments. The analog or gm segment 112 is supplied with digital data 108. The output of the analog / gm segment is short-circuited to a common resistive load, thereby generating the analog symbol 110 as shown in FIG. 1(c). In contrast, NRZ Tx comprises only a single gm segment since such an analog symbol is represented by a single bit.

[0014] An approach to implementing serialization is shown in FIG. 1, for example, as shown in FIG. 1(b). Serialization is performed in a plurality of cascaded stages. When the amount of parallel data branches decreases in subsequent stages (for example, mux104 operates after mux102), the data rate increases. The amount of parallel data branches continues to decrease until serialization proceeds to the last serialization stage, and the remaining parallel data branches are serialized into one single data branch with a high data rate (for example, 108). This last serialization stage is the most difficult since it operates at the highest speed.

[0015] In some embodiments, the load of the last PISO or serialization stage is the other "off" branches and the subsequent analog buffers. FIG. 2 represents the last serialization stage 200 of FIG. 1. This stage includes an "n-to-1" or n:1 mux, for example, a 4:1 mux 106 as shown in FIG. 1(b). The n:1 mux has n - 1 "off" pass gates (e.g., n - 1 off branches) and one gm stage. This load is typically too heavy to support the high data rates present in state-of-the-art Tx. For example, a FinFET-based Tx can handle data at speeds exceeding 10 gigahertz (GHz). Note that this speed issue exists similarly in both NRZ-based and DAC-based topologies. Therefore, the solution to the speed problem is described herein in the context of DAC-based topologies, but it is applicable to NRZ-based and other topologies as well.

[0016] One conventional method for reducing the load and reaching the required bandwidth is to reduce the transistor size. However, this attenuates the signal. The attenuated signal needs to be compensated by a large amount of power consumption, which in turn causes significant reliability issues.

[0017] Figure 3 represents an exemplary n:1 (e.g., 4:1) circuit structure 300. This structure is an improved configuration of the last PISO stage in Figure 1. As shown in Figure 3, in some embodiments, the speed - limiting problem of the last PISO stage can be addressed by connecting each input 302 of the last PISO stage to a dedicated analog stage 304 (e.g., gm stage) via a logic function or cell 306. The inputs 302 are connected to the analog stage 304 at the relevant clock phase (not shown) so that they can be activated at the appropriate time. The logic function can be, for example, an "AND" function between the input 302 and the associated clock phase. As shown above in (b) of Figure 1 and Figure 2, the last PISO stage is a 4:1 mux 106. Using this 4:1 mux as an example, in Figure 3, the 4 - bit inputs of the 4:1 mux 106 can be connected to four logic functions and four gm stages. This appears m times according to the exemplary DAC topology of Figure 1. The structure of Figure 3 can reduce the data load and increase the processing speed. Also, by connecting each bit to a dedicated analog stage, calibration of the gain mismatch of each bit becomes possible.

[0018] As shown in Figure 3, transistors can be used to amplify or switch electrical signals and power. A transistor typically includes at least three terminals (e.g., 308, 310, and 312) for connection to an electronic circuit. When a voltage is applied, the current passing through a pair of terminals is controlled. For example, when a voltage is applied to the gate 308 of the transistor, an electric field is generated that controls the flow of charge carriers (e.g., electrons) between the source 310 (e.g., the terminal through which current enters the transistor) and the drain 312 (e.g., the terminal through which current exits the transistor). Since the output power can be higher than the control power or input power, the transistor can amplify the signal to obtain an output signal 314.

[0019] When using a gm stage in the analog stage, the voltage of the source of the input pair is the drain voltage of the current source, i.e., the Vds of the current source. This indicates that in order to operate the gm stage, the gate voltage must be higher than the sum of the current source voltage Vds and the Vt of the transistor. Since the logic function / cell 306 switches between ground (Vss) and the supply voltage (Vdd), it may take some time to charge the gate 308 from Vss to the voltage of Vds+Vt to turn on the analog stage. This gate charging time cannot be ignored in the state-of-the-art Tx system, thus affecting the performance of Tx regarding speed, gain, efficiency, etc.

[0020] The transmitter topology of the present disclosure is further improved to address this drawback, as described with reference to FIG. 4. The system 400 of the present application enables the analog stage or the analog output stage 402 to be implemented with PMOS devices / transistors. The PMOS transistor PMOS refers to a p-channel metal-oxide-semiconductor field-effect transistor (MOSFET). Also, the system 400 of the present application is configured to connect the logic circuit 404 (including n logic functions) to a lower supply region (e.g., the low voltage source 406). In this way, the high state output of the logic circuit 404 can be adjusted to be close to the switching point of the analog output stage 402. The switching point is the point at which the circuit of the analog output stage 402 is turned on (e.g., a specific voltage value).

[0021] As shown in FIG. 4, the PMOS transistor may include three terminals such as a gate 408, a source 410, and a drain 412. When the gate voltage is lower than the source voltage by only the threshold voltage (in absolute value), or when Vg<Vs+Vt (when Vt is negative), the PMOS transistor is turned on (e.g., open). When the gate voltage drops to this Vs+Vt level, current begins to flow through the transistor from the source 410 to the drain 412. Otherwise, when a higher voltage is applied to the gate 408, the PMOS is off and does not conduct current.

[0022] In the system of the present application, the voltage of the source 410 (i.e., the source voltage) is the drain voltage of the current source. That is, in order to turn on the gm stage, the gate voltage of the gate 408 needs to be lowered from the supply voltage of the logic circuit 404 to a voltage obtained by adding Vt to the drain voltage of the current source (for example, Vs + Vt when Vt < 0). In the illustrated embodiment, the logic circuit 404 is connected to a lower power supply (e.g., the low voltage source 406). This connection allows the gate voltage of the gate 408 to be discharged from a voltage value lower than Vdd to the value of Vs + Vt in order to turn on the gm stage. In other words, the gm stage is turned off at a voltage close to the switching point of the gm stage. As a result, the analog stage 402 can operate (e.g., turn on) much faster, and the operating efficiency is significantly improved.

[0023] In some embodiments, the supply voltage of the logic circuit 404 can be further adjusted so that the current source can operate in the saturation mode. Therefore, regardless of the source voltage, the output current is stabilized. Also, the gain, speed, and common-mode rejection ratio (CMRR) can be improved.

[0024] [System flowchart] The system of the present application discloses a transmitter topology with a supply-controlled serialization stage embedded in a PMOS output stage, which not only improves the operating speed but also improves the gain, power consumption, stability, etc. of the transmitter. To achieve these technical advantages, the system of the present application includes at least three different features. First, the transmitter system of the present application uses a unique gm stage for each bit in the last serialization stage so that the speed limit associated with the last serialization stage can be relaxed. This unique connection feature alone can solve the speed problems existing in various types of transmitters (e.g., DAC transmitters, NRZ transmitters). Second, the data is transferred to a PMOS-based gm stage to generate an output signal, e.g., an analog signal. That is, the transmitter system of the present application uses a logic circuit to send the digital data obtained from the last serialization stage to the PMOS-based gm stage to generate an analog signal. Third, the logic circuit is connected to a low-voltage power supply. With the low-voltage power supply, the gate voltage of the PMOS can be easily adjusted to be close to the switching point of the PMOS gm stage. Therefore, by combining these two functions, not only is the improvement of speed promoted, but other advantages can also be obtained (e.g., power consumption).

[0025] FIG. 5 represents an exemplary process 500 for constructing and implementing a transmitter that uses a supply-controlled serialization stage embedded in a PMOS output stage. In some embodiments, the transmitter may include a data acquisition circuit, a serialization circuit, a logic circuit, and an output circuit. These are electrically and communicatively connected so as to operate in a fast and reliable manner.

[0026] In some embodiments, the transmitter can be a DAC transmitter, an NRZ transmitter, etc. In relation to the DAC transmitter, the data acquisition circuit can generate or collect digital data associated with a plurality of data branches. The serialization circuit and the logic circuit can receive data in parallel from these data branches and convert the received data into a single data stream for the output circuit to generate a signal, such as an analog signal.

[0027] In step 505, data from a plurality of data branches is received by the serialization circuit. The serialization circuit can include one or more serialization stages, as represented in FIG. 1(b). The last stage of the serialization stage, implemented by an n:1 mux such as the 4:1 mux in FIG. 1(b) for example, may lack the ability to handle a large data load at the required high data rate, thus causing a performance degradation.

[0028] In step 510, the logic circuit connects each input of the last stage to each dedicated output stage of the output circuit via respective logic functions. For example, when the last stage is a 4:1 mux, 4-bit data is connected to 4 logic functions and 4 gm stages. In this way, the data load is reduced and the processing speed is improved. In some embodiments, the logic circuit is connected to a low-power region.

[0029] In step 515, the output circuit implements an output stage to generate a signal using PMOS based on the received input. In some embodiments, the output stage is a PMOS-based gm stage. As described above, by using a PMOS-based gm stage and a low-voltage source, the output of the logic circuit (e.g., a high-state output) is adjusted to a voltage value close to the switching point of the gm stage to accelerate the operation of the gm stage, thereby further accelerating the transmitter operation. In some embodiments, each output stage is supplied with digital data and output to a common resistive load to generate an analog symbol.

[0030] [Additional factor] In some embodiments, at least a portion of the approaches described above can be implemented, when executed, by instructions that cause one or more processing devices to perform the processes and functions described above. Such instructions can include, for example, interpreted instructions such as script instructions, or executable code, or other instructions stored on a non-transitory computer-readable medium. The storage devices can be distributed over a network and implemented, for example, as a server farm or a collection of widely distributed servers, or alternatively, can be implemented on a single computing device.

[0031] Although an example processing system is described, embodiments of the subject matter, functional operations, and processes described in this specification can be implemented in other types of digital electronic circuitry, in computer software or firmware tangibly embodied, or in computer hardware including the structures disclosed in this specification and their structural equivalents, or in one or more combinations thereof. Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, i.e., as one or more modules of computer program instructions encoded on a tangible non-volatile program carrier for execution by, or to control the operation of, a data processing apparatus. Alternatively, or in addition, the program instructions can be encoded in an artificially generated propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, that is generated to encode information for transmission to a suitable receiver device for execution by a data processing apparatus. A computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them.

[0032] The term "system" may well encompass all kinds of devices, apparatuses, and machines for processing data, by way of example, programmable processors, computers, or multiple processors or computers. A processing system may include special-purpose logic circuitry, such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). In addition to hardware, the processing system may include code for creating an execution environment for the computer program in question, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, or one or more combinations thereof.

[0033] A computer program (which may also be called or described as a program, software, a software application, a module, a software module, a script, or code) can be written in any form of programming language, including a compiled or interpreted language, or a declarative or procedural language, and can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program may or may not correspond to a file in a file system. The program may be stored in a part of a file that holds other programs or data (such as one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple cooperating files (such as files storing one or more modules, subprograms, or portions of code). A computer program may be deployed on one computer or located in one place, or may be distributed across multiple locations and deployed on multiple computers interconnected by a communication network.

[0034] The processes and logical flows described herein can be performed by one or more programmable computers that execute one or more computer programs to perform functions by operating on input data to generate output. The processes and logical flows can also be performed by special-purpose logic circuitry, such as an FPGA (field programmable gate array) or ASIC (application specific integrated circuit), and the apparatus can also be implemented as such special-purpose logic circuitry.

[0035] Computers suitable for the execution of a computer program can include, by way of example, general purpose computers, or special purpose microprocessors, or both, or any other kind of central processing unit. In general, a central processing unit receives instructions and data from a read only memory or a random access memory or both. A computer generally includes a central processing unit for executing instructions and one or more memory devices for storing instructions and data. In general, a computer also includes, or can be operatively coupled to receive data from, or transfer data to, or both, one or more mass storage devices for storing data, such as magnetic disks, magneto-optical disks, or optical disks. However, a computer need not have such devices. Further, a computer can be embedded in other devices, some examples of which include, for example, a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver, or a portable storage device (e.g., a universal serial bus (USB) flash drive).

[0036] Computer-readable media suitable for storing computer program instructions and data include, by way of example, semiconductor memory devices such as EPROM, EEPROM, and flash memory devices, magnetic disks such as internal hard disks or removable disks, magneto-optical disks, and all forms of non-volatile memory, media, and memory devices including CD-ROM disks and DVD-ROM disks. The processor and the memory may be supplemented by, or incorporated in, special purpose logic circuitry.

[0037] To provide for interaction with a user, embodiments of the subject matter described herein may be implemented on a computer having a display device for displaying information to the user, such as a CRT (cathode ray tube) or LCD (liquid crystal display) monitor, and a keyboard and a pointing device by which the user can provide input to the computer, such as a mouse or trackball. Other kinds of devices can be used to provide for interaction with a user as well. For example, feedback provided to the user can be any form of sensory feedback, such as visual feedback, auditory feedback, or tactile feedback, and input received from the user can be in any form including acoustic, speech, or tactile input. Also, the computer can interact with the user by sending documents to and receiving documents from devices used by the user, for example, by sending a web page to a web browser on a user's user device in response to a request received from the web browser.

[0038] Embodiments of the subject matter described herein can be implemented in a computing system that includes back-end components, such as a data server, or includes middleware components, such as an application server, or includes front-end components, such as a graphical user interface or a web browser through which a user can interact with an implementation of the subject matter described herein, or any combination of one or more such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication, such as a communication network. Examples of communication networks include local area networks (“LANs”) and wide area networks (“WANs”), such as the Internet.

[0039] A computing system can include clients and servers. Clients and servers are generally remote from each other and typically interact through a communication network. The relationship between a client and a server arises by computer programs running on each computer and having a client-server relationship to each other.

[0040] This specification includes many specific implementation details, but these should not be construed as limitations on the scope of the claimed subject matter, but rather as descriptions of features that may be specific to particular embodiments. The specific features described in this specification in connection with separate embodiments can also be implemented in combination in a single embodiment. Conversely, the various features described in connection with a single embodiment can also be implemented separately or in any suitable sub - combination in multiple embodiments. Further, although features are described above as functioning in a particular combination and were initially claimed as such, one or more features from the claimed combination may in some cases be deleted from the combination, and the claimed combination may be directed to a sub - combination or variation of a sub - combination.

[0041] Similarly, operations are represented in the drawings in a particular order, but this should not be understood as requiring that such operations be performed in the particular order shown or in a sequential order to achieve the desired result, nor that all of the operations shown be performed. In certain circumstances, multitasking or parallel processing may be advantageous. Further, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated into a single software product or packaged into multiple software products.

[0042] Certain embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the acts described in the claims can be performed in a different order and still achieve the desired result. As one example, the processes depicted in the accompanying drawings do not necessarily require the particular order or sequential order shown to achieve the desired result. In certain implementations, multitasking or parallel processing may be advantageous. Other steps or stages may be provided, or steps or stages may be deleted from the described processes. Accordingly, other embodiments are within the scope of the following claims.

[0043] The expressions and terms used herein are for illustrative purposes and should not be regarded as limiting.

[0044] As used herein in the specification and claims, the term "about," the phrase "substantially equal," and other similar phrases (e.g., "X has a value of about Y" or "X is substantially equal to Y") are to be understood to mean that a value (X) is within a predetermined range of another value (Y). The predetermined range may be plus or minus 20%, 10%, 5%, 3%, 1%, 0.1%, or less than 0.1% unless otherwise specified.

[0045] As used in this specification and the claims, the indefinite articles "a" and "an" should be understood to mean "at least one" unless the contrary is clearly indicated. The phrase "and / or" as used in this specification and the claims should be understood to mean "either or both" of the elements so joined, i.e., elements that may be present conjointly in some cases and separately in other cases. Multiple elements listed with "and / or" should likewise be construed as "one or more" of the elements so joined. Elements other than those specifically recited in an "and / or" clause may optionally be present whether or not they are related to those specifically recited. Thus, by way of non-limiting example, reference to "A and / or B" when used in combination with open-ended language such as "comprising" may, in one embodiment, refer to only A (optionally including elements other than B), in another embodiment, refer to only B (optionally including elements other than A), in yet another embodiment, refer to both A and B (optionally including other elements), and so forth.

[0046] As used in this specification and the claims, the terms "or", "OR", or "alternatively" shall be understood to have the same meaning as "and / or" as defined above. For example, when separating items in a list, "or" or "and / or" is inclusive, that is, it shall be interpreted to include not only one or more elements or a list of elements, and optionally, at least one additional item not listed, but also more than one of them. Only terms that clearly indicate the contrary, such as "only one" or "exactly one", or when used in the claims, terms such as "consisting of", refer to exactly one element out of a number of elements or a list of elements. In general, the term "or" used shall be interpreted to indicate an exclusive alternative (i.e., "either one, not both") only when preceded by terms indicating exclusivity such as "either", "one", "only one", or "exactly one". "Consisting essentially of" shall have the ordinary meaning used in the field of patent law when used in the claims.

[0047] In this specification and the claims, the phrase "at least one" used with respect to a list of one or more elements should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but does not necessarily include at least one of every element specifically recited in the list of elements, nor does it exclude any combinations of elements in the list of elements. This definition also allows that elements other than those specifically identified in the list of elements referred to by the phrase "at least one" may optionally be present, whether or not they are related to the specifically identified elements. Thus, by way of non-limiting example, "at least one of A and B" (or equivalently, "at least one of A or B", or equivalently, "at least one of A and / or B") can, in one embodiment, refer to at least one A (optionally including more than one A) where B is not present (and optionally including elements other than B), in another embodiment, refer to at least one B (optionally including more than one B) where A is not present (and optionally including elements other than A), and in yet another embodiment, refer to at least one A (optionally including one or more A) and at least one B (optionally including one or more B) (optionally including other elements), and so on.

[0048] The use of "including", "comprising", "having", "containing", "involving", and variations thereof is intended to encompass the items listed previously and additional items.

[0049] The use of ordinal numbers such as "first", "second", "third", etc. in the claims to change claim elements does not, in itself, mean that one claim element is prior, antecedent, or ranked ahead of other claim elements, or that it means the chronological order in which the acts of a method are performed. Ordinal numbers are used only as labels to distinguish one claim element having a particular name from another element having the same name (except that the ordinal number is used).

[0050] Having described some aspects of at least one embodiment of the present invention above, it will be apparent to those skilled in the art that various changes, modifications, and improvements can be readily conceived. Such changes, modifications, and improvements are intended to be part of this disclosure and within the spirit and scope of the present invention. Accordingly, the foregoing description and drawings are by way of example only.

[0051] [Cross - Reference to Related Applications] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 342,980, filed on May 17, 2022, entitled "High Speed Tx Topology with a Supply Controlled Serialization Stage Embedded in a PMOS Output Stage", the entire contents of the prior U.S. application are incorporated herein by reference.

Claims

1. A serialization circuit configured to convert parallel data into serial data by one or more serialization stages; electrically coupled to the serialization circuit and an output circuit, and configured to connect each input of the last serialization stage of the one or more serialization stages of the serialization circuit to each dedicated output stage of the output circuit via respective logic functions, and a logic circuit connected to a low voltage supply region; the output circuit configured to implement an output stage to generate a signal using a p-channel metal oxide semiconductor (PMOS) field effect transistor based on a received input A transmitter having.

2. The dedicated output stage is a PMOS-based transconductance (gm) stage. The transmitter according to claim 1.

3. By using the PMOS-based gm stage and the low voltage supply region, the output of the logic circuit is adjusted to a voltage value close to the switching point of the gm stage so as to accelerate the operation of the gm stage, and the switching point is the threshold voltage value at which the PMOS transistor is turned on. The transmitter according to claim 2.

4. The serialization circuit includes a series of multiplexers in the one or more serialization stages; The last serialization stage is an n:1 multiplexer; The logic circuit is configured to connect an n-bit input from the last serialization stage to n gm stages via n logic functions. The transmitter according to claim 1.

5. The input of the last serialization stage is connected to each dedicated output stage with a related clock phase. The transmitter according to claim 4.

6. The serialization circuit and the output circuit are connected by the logic circuit so as to reduce the data load of the last serialization stage and increase the operating speed of the transmitter. The transmitter according to claim 5.

7. Each output stage is supplied with digital data and output to a common resistive load to generate an analog symbol. The transmitter according to claim 1.

8. Further comprising a data acquisition circuit configured to generate the parallel data with a plurality of data branches. The serialization circuit and the output circuit are configured to convert the parallel data received from the plurality of data branches into a single data stream. The transmitter according to claim 1.

9. The transmitter is one of a digital-to-analog converter (DAC)-based transmitter, a non-return-to-zero (NRZ) transmitter, or another type of transmitter. The transmitter according to claim 1.

10. The logic circuit is connected to a control power supply and is adjusted to enable the current source to operate in a saturation state. The transmitter according to claim 1.

11. A method of constructing and implementing a transmitter, receiving data in parallel from a plurality of data branches by a serialization circuit including one or more serialization stages; connecting each input of the last serialization stage of the one or more serialization stages to each dedicated output stage of the output circuit via each logic function of a logic circuit; connecting the logic circuit to a low voltage supply region; implementing an output stage by the output circuit to generate a signal using a p-channel metal-oxide-semiconductor (PMOS) field-effect transistor based on the received input A method having.

12. The dedicated output stage is a PMOS-based transconductance (gm) stage. The method according to claim 11.

13. further comprising adjusting an output of the logic circuit to a voltage value close to a switching point of the gm stage so as to accelerate the operation of the gm stage based on the PMOS-based gm stage and the low voltage supply region, The switching point is a threshold voltage value at which the PMOS transistor is turned on. The method according to claim 12.

14. configuring a series of multiplexers in the one or more serialization stages of the serialization circuit, wherein the last serialization stage is an n:1 multiplexer; connecting an n-bit input from the last serialization stage to n gm stages via n logic functions by the logic circuit The method according to claim 11, further comprising.

15. The input of the last serialization stage is connected to each dedicated output stage at a related clock phase. The method according to claim 14.

16. The serialization circuit and the output circuit are connected by the logic circuit so as to reduce the data load of the last serialization stage and increase the operating speed of the transmitter. The method according to claim 15.

17. Each output stage is supplied with digital data and output to a common resistive load to generate an analog symbol. The method according to claim 11.

18. generating the data with the plurality of data branches; converting the data received in parallel from the plurality of data branches into a single data stream The method according to claim 11, further comprising:

19. The transmitter is one of a digital-to-analog converter (DAC)-based transmitter, a non-return-to-zero (NRZ) transmitter, or another type of transmitter. The method according to claim 11.

20. connecting the logic circuit to a control power supply; adjusting the logic circuit so as to enable the current source to operate in a saturated state The method according to claim 11, further comprising:

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