Memory access popularity statistics method and memory

Abstract

A method for statistically analyzing memory access popularity, a controller, a chip, a memory, a motherboard, and a computer device are disclosed, which relate to the field of computers. The method includes: collecting statistics on the access frequency of a processor accessing data blocks in a memory based on the operations performed on the memory by an application program executed by the processor; and determining the access popularity of the data blocks based on the access frequency. The access frequency represents the frequency at which the application program accesses the data blocks. The fact that the number of accesses by the application program to a data block is greater indicates that the access frequency of the application program to the data block is higher and the access popularity of the data block is higher. The fact that the number of accesses by the application program to a data block is less indicates that the access frequency of the application program to the data block is lower and the access popularity of the data block is lower. In this way, hot data is transferred to near-memory, and cold data is transferred to far-memory. As a result, the processor can obtain the frequently accessed data from near-memory as quickly as possible. Thereby, the data processing speed of the system is improved, the delay in data processing is reduced, and the access performance of the system is significantly improved.

Description

Technical Field

[0001] This application claims priority to Chinese Patent Application No. 202210575022.5, titled "DATA MIGRATION METHOD", filed with the China National Intellectual Property Administration on May 24, 2022, and Chinese Patent Application No. 202211016161.0, titled "MEMORY ACCESS POPULARITY STATISTICS METHOD AND RELATED APPARATUS AND DEVICE", filed with the China National Intellectual Property Administration on August 24, 2022, the entire contents of which are incorporated herein by reference.

[0002] This application relates to the field of computers, and in particular, to a method for statistically analyzing memory access popularity, a controller, a chip, a memory, a motherboard, and a computer device.

Background Art

[0003] Currently, memory devices with high-speed access are expected to store frequently accessed data, and memory devices with low-speed access are expected to store infrequently accessed data. However, due to the low accuracy of existing methods for statistically analyzing memory access popularity, a memory device with high-speed access may store infrequently accessed data, or a memory device with low-speed access may store frequently accessed data. This affects the data processing speed and latency of the system.

Summary of the Invention

[0004] This application provides a method for statistically analyzing memory access popularity, a controller, a chip, a memory, a motherboard, and a computer device for improving the data processing speed of a system and reducing the latency of data processing.

[0005] According to a first aspect, a memory access popularity statistics method is provided, and this method is executed by a controller. The method includes: collecting statistics on the access frequency of a processor accessing a data block in a memory based on operations performed on the memory of a computer device by an application program executed by the processor in the computer device, and determining the access popularity of the data block based on the access frequency.

[0006] In this way, the access frequency intuitively represents the frequency at which the application program accesses the data block. The fact that the application program accesses the data block more times indicates that the access frequency of the application program to the data block is higher and the access popularity of the data block is higher. The fact that the application program accesses the data block fewer times indicates that the access frequency of the application program to the data block is lower and the access popularity of the data block is lower. Therefore, when data migration is triggered based on the access popularity of the data block, hot data can be migrated to near memory, and cold data can be migrated to far memory. As a result, the processor can obtain the frequently accessed data from near memory as quickly as possible. Thereby, the data processing speed of the system is improved, the delay in data processing is reduced, and the access performance of the system is significantly improved.

[0007] In a possible implementation form, the step of collecting statistics on the access frequency of accessing the data block where the first address is located includes: collecting statistics on the access frequency of accessing the data block where the unit storage space to which the first address belongs is located.

[0008] The size of a data block is a multiple of the unit memory space within the memory accessible to the processor. By using a cache line as the granularity, a computer device performs read or write operations on the memory space within the memory, and manages the memory space within the memory by using a page as the granularity. A page may contain a plurality of cache lines. The size of a data block is the size of one page within the memory accessible to the processor within the computer device. The size of the unit memory space may be the size of a cache line when the processor within the computer device accesses the memory. Operations performed on the cache lines within the memory by an application program executed by the processor within the computer device may be regarded as operations on pages. In this way, the processor performs operations on the memory by using a cache line as the granularity, and the cache line belongs to a managed page. Therefore, when an operation is performed on a cache line within the memory once, the page to which the cache line belongs is read and written once. The controller collects statistics regarding the access frequency of accessing the page to which the cache line on which the operation is performed belongs. Thereby, the accuracy of identifying the access popularity of the page is effectively improved. In addition, the controller collects statistics regarding the access frequency of accessing a page by using the page as the granularity, which is compatible with the method of memory page management executed by the computer device. The memory access popularity statistics method is easy to use.

[0009] In addition, the interleaving method means that a processor in a computer device distributes data to multiple memories for operation. An application program executed by a processor in a computer device operates on the memory of the computer device in an interleaving manner, and performs data processing based on multiple memory channels, thereby improving the memory bandwidth utilization rate and processing performance of the computer device. Alternatively, the size of the data block can be the size of the interleaved data block in the memory that can be accessed by the processor in the computer device in an interleaving manner.

[0010] In another possible implementation, the method further includes: identifying a second address based on the address of the data block where the first address is located and the address mapping relationship. The second address indicates a location in the controller where the access frequency for accessing the data block is stored. The address mapping relationship indicates the mapping relationship between the address of the data block and the address of the storage space where the access frequency is stored. Therefore, the controller obtains the access frequency for accessing the data block stored in the first storage medium based on the second address, and updates the access frequency for accessing the data block.

[0011] In another possible implementation, the memory includes a first storage medium, the first storage medium is configured to store the access frequency for accessing the data block in the memory, and the second address indicates the storage space in the first storage medium where the access frequency for accessing the data block is stored.

[0012] In another possible implementation, when the processor accesses the first storage medium, in order for the computer device to pre-allocate the capacity of the memory device in the memory, the computer device allocates a physical address space corresponding to the capacity of the first storage medium from the capacity of the memory device in the memory to the first storage medium, and the controller maps the physical address for accessing the first storage medium to the first storage medium. In this way, the corresponding capacity in the memory device cannot be used, resulting in waste of the storage space of the memory device. For example, the total capacity of the memory device in the memory is 64 GB, the page size is 4 KB, and the bit width of the access frequency for storing each data block is 4 B. As a result, 64 MB of memory storage space is wasted. This method further includes: identifying a second address based on a third address indicated by the processor and an address mapping relationship, and obtaining the access frequency for accessing the data block, where the third address is determined based on the second address. Therefore, the storage space of the memory device is saved, and the utilization rate of the storage space of the memory device is improved.

[0013] In another possible implementation, the method further includes: the controller determines the access popularity of the data block based on the access frequency, and triggers data migration based on the access popularity. For example, the controller feeds back the access popularity of the data block to the processor, and the processor controls the data blocks with different access popularities to perform data migration. For example, the processor stores cold data in the far memory and hot data in the near memory. In this way, when the controller triggers data migration based on the access popularity of the data block, the hot data can be migrated to the near memory, and the cold data can be migrated to the far memory. As a result, the processor can obtain the data from the near memory as quickly as possible. Thereby, the data processing speed of the system is improved, the delay of data processing is reduced, and the overall processing performance of the system is improved.

[0014] According to a second aspect, a memory access popularity statistics method is provided. This method is executed by a processor: receiving the access frequencies of interleaved data blocks transmitted by a plurality of memories, and obtaining the access frequency of accessing a page by combining the access frequencies of accessing the interleaved data blocks. The access frequency of accessing the interleaved data blocks indicates the access frequency at which the processor accesses the data blocks in one of the plurality of memories in an interleaved manner.

[0015] In this way, in order to improve the memory bandwidth utilization rate and processing performance of a computer device, when an application program executed by a processor in the computer device operates on the memory of the computer device in an interleaved manner and performs data processing based on a plurality of memory channels, the controller combines the access frequencies of accessing the interleaved data blocks transmitted by the plurality of memories to obtain the access frequency of accessing a page. As a result, the access popularity of the page is determined based on the access frequency of accessing the page. When data migration is triggered based on the access popularity of the page, hot data can be migrated to near memory, and cold data can be migrated to far memory. In this way, the processor can obtain the frequently accessed data from the near memory as quickly as possible. Thereby, the data processing speed of the system is improved, the delay of data processing is reduced, and the access performance of the system is greatly improved.

[0016] According to a third aspect, a memory access popularity statistics apparatus is provided. This apparatus includes a module configured to execute the memory access popularity statistics method in any one of the first aspect or possible designs of the first aspect, or a module configured to execute the memory access popularity statistics method in any one of the second aspect or possible designs of the second aspect.

[0017] According to the fourth aspect, a controller is provided. The controller includes a processing unit and a memory unit. The memory unit is configured to store a group of computer instructions. When the processing unit is used as the controller in any one of the first aspect or a possible implementation form of the first aspect to execute a group of computer instructions, the processing unit executes the operation steps of the memory access popularity statistics method in any one of the first aspect or a possible implementation form of the first aspect. The controller is a Register Clock Driver (RCD) or an extended controller in the memory of a computer device.

[0018] According to the fifth aspect, a chip including a processor and a power circuit is provided. The power circuit is configured to supply power to the processor, and the processor is configured to execute the operation steps of the memory access popularity statistics method in any one of the first aspect or a possible implementation form of the first aspect.

[0019] According to the sixth aspect, a memory is provided. The memory includes a storage device and a controller according to the fourth aspect. The storage device is configured to store a group of computer instructions. When executing a group of computer instructions, the controller executes the operation steps of the memory access popularity statistics method in any one of the first aspect or a possible implementation form of the first aspect.

[0020] According to the seventh aspect, a main board is provided. The main board includes a controller according to the fourth aspect, and the controller executes the operation steps of the memory access popularity statistics method in any one of the first aspect or a possible implementation form of the first aspect.

[0021] According to the eighth aspect, a computer device is provided. The computer device includes a main board according to the seventh aspect.

[0022] According to a ninth aspect, there is provided a computer-readable storage medium comprising computer software instructions. When the computer software instructions are executed on a computing device, the computing device can execute the operation steps of the method according to any one of the first aspect or possible implementation forms of the first aspect.

[0023] According to a tenth aspect, there is provided a computer program product. When the computer program product is executed on a computer, the computing device can execute the operation steps of the method according to any one of the first aspect or possible implementation forms of the first aspect.

[0024] In the present application, based on the implementation forms according to the above aspects, implementation forms can be combined to provide more implementation forms.

Brief Description of the Drawings

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Embodiments for Carrying out the Invention

[0033] For ease of explanation, the terms in the present application will be briefly explained first.

[0034] Memory device: A memory device is a memory component for storing programs and various data. The access speed is the data transmission speed when data is written to the memory device or read from the memory device. The access speed can also be referred to as the read / write speed. Based on the access speed of the memory device, the main memory device connected to the processor in the computer device can be classified into far memory and near memory. The main memory device can be abbreviated as main memory or memory. The access speed of near memory is higher than that of far memory. For example, near memory can be Dynamic Random Access Memory (DRAM) or double data rate synchronous dynamic random access memory (DDR SDRAM). Far memory can be storage class memory (SCM).

[0035] Hot Data: Hot data refers to data that is frequently accessed by a processor. When hot data is stored in near-memory, the processor can obtain the data as quickly as possible. This improves the data processing speed of the system, reduces the delay in data processing, and significantly improves the access performance of the system.

[0036] Cold Data: Cold data refers to data that is not frequently accessed by a processor. When cold data is stored in far-memory, the data reliability can be improved, and more hot data can be stored in near-memory. This improves the resource utilization rate of near-memory and reduces the system cost.

[0037] Cache Line: A cache line is a unit used by a computer device to perform a read or write operation on a storage space in memory. The size of a cache line can be 64 bytes (B).

[0038] Page: A page is a unit used by a computer device to manage a storage space in memory. For example, the page size can be 4 kilobytes (KB), 2 megabytes (MB), or another byte size. A 4KB page can be referred to as a small page. A 2MB page can be referred to as a huge page. A smaller page indicates that more resources are required by the computer device to manage the memory, and a larger page indicates that fewer resources are required by the computer device to manage the memory. A page can contain multiple cache lines. Specifically, the page size is a multiple of the cache line size.

[0039] Interleave: Interleave refers to evenly distributing the data accessing the memory across multiple memory channels based on a unit of memory space (e.g., cache line). The interleaving method can be configured by the system administrator, and interleaving can be executed among multiple memory channels connected to one processor, or interleaving can be executed among multiple memory channels of multiple processors.

[0040] Memory Channel: Memory channel refers to multiple memories connected to a processor within a computer device. The processor can execute operations on the memory by using interleaving technology. For example, based on the size of the cache line, the processor evenly distributes the data to be written to the memory across multiple memory channels. Further, the processor reads data from multiple memory channels based on the size of the cache line. Data processing is executed based on multiple memory channels, and as a result, the memory bandwidth utilization rate and processing performance of the computer device are improved.

[0041] To improve the accuracy of memory access popularity statistics, the present application provides a method for memory access popularity statistics. Specifically, based on the operations performed on the memory of a computer device by an application program executed by a processor in the computer device, statistics regarding the access frequency at which the processor accesses data blocks in the memory are collected, the access popularity of the data blocks is determined based on the access frequency, and data migration is triggered based on the access popularity. The access frequency intuitively represents the frequency at which the application program accesses a data block. The fact that the application program accesses a data block more frequently indicates that the access frequency of the application program to the data block is higher and the access popularity of the data block is higher. The fact that the application program accesses a data block less frequently indicates that the access frequency of the application program to the data block is lower and the access popularity of the data block is lower. Therefore, when data migration is triggered based on the access popularity of a data block, hot data can be migrated to near memory and cold data can be migrated to far memory. As a result, the processor can obtain the frequently accessed data from the near memory as quickly as possible. Thereby, the data processing speed of the system is improved, the delay in data processing is reduced, and the access performance of the system is significantly improved.

[0042] The size of a data block is a multiple of the unit memory space in the memory accessible to the processor. For example, the size of a data block is the page size used by the computer device to manage the memory. As another example, the size of a data block is the size of the interleaved data blocks in the memory accessible in an interleaved manner to the processor in the computer device.

[0043] Hereinafter, with reference to the accompanying drawings, the method for memory access popularity statistics provided in the present application will be described in detail.

[0044] FIG. 1 is a schematic diagram of the structure of a computer device according to the present application. In this specification, an example in which the computer device includes a near memory is used for explanation. As shown in FIG. 1, the computer device 100 includes a processor 110 and a memory 120. The processor 110 is connected to the memory 120 by using a bus 130.

[0045] The processor 110 can be an XPU used for data processing, such as a central processing unit (CPU), a graphics processing unit (GPU), a data processing unit (DPU), a neural processing unit (NPU), and an embedded neural network processing unit (NPU). The processor 110 can also be another general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or a system on chip (SoC) or another programmable logic device, discrete gate or transistor logic device, discrete hardware component, or the like. The general-purpose processor can be a microprocessor, or any conventional processor, or the like. For ease of explanation, in the following embodiments, an example in which the processor 110 is a CPU is used for explanation.

[0046] The computer device 100 of FIG. 1 may include one or more processors. The processor may be a multi-core processor. A processor herein may be one or more devices, circuits, and / or processing units configured to process data (e.g., computer program instructions).

[0047] The processor 110 is configured to execute an application program to perform a read or write operation on the memory 120 and trigger data transfer based on the frequency of access to the memory 120.

[0048] The bus 130 may include a channel configured to transmit data between the above-described components (e.g., the processor 110 and the memory 120). For example, the processor 110 sends an access request to the memory 120, and the memory 120 feeds back to the processor 110 the access frequency to access the data block. In addition to the data bus, the bus 130 may further include a power bus, a control bus, a status signal bus, and the like. For example, the bus 130 is a DDR bus. However, for clarity of explanation, in the figure, various types of buses are shown as the bus 130.

[0049] Memory 120 can be a volatile memory pool or a non-volatile memory pool, or can include both volatile memory and non-volatile memory. The non-volatile memory can be a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM) used as an external cache. By way of non-limiting example, many forms of RAM, such as static RAM (SRAM), DRAM, synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and direct rambus RAM (DR RAM), can be used.

[0050] Memory 120 includes a memory device 121, a data buffer (DB) 122, and a register clock driver (RCD) 123. DB 122 is connected to memory device 121 and RCD 123.

[0051] Memory device 121 is configured to store application data of an application program executed by processor 110. For example, memory device 121 can be a DRAM.

[0052] DB122 is configured to drive the data signal generated by the memory controller in the processor 110, write the data transmitted by the processor 110 to the memory device 121, transmit the application data stored in the memory device 121 to the processor 110, or transmit to the processor 110 the access frequency of accessing the data block stored in the RCD123.

[0053] RCD123 is configured to drive the clock signal, address signal, and command signal generated by the memory controller in the processor 110 to implement operations on a plurality of memory devices 121. Based on the access request of the processor 110, RCD123 executes a read operation or a write operation on the memory device 121 in the memory 120, counts the access frequency of accessing the data block in the memory device 121 in the memory 120, and is configured to store the access frequency of accessing the data block. RCD123 is further configured to obtain the access frequency of accessing the data block from the storage medium 124. Optionally, RCD123 may determine the access popularity of the data block based on the access frequency and trigger data migration.

[0054] RCD123 includes a storage medium 124, and the storage medium 124 is configured to store the access frequency of accessing the data block. In this way, it is avoided that the storage space of the memory device 121 is occupied to store the access frequency of accessing the data block, and the resource utilization rate of the memory device 121 is improved. The storage medium 124 may be a volatile memory pool or a non-volatile memory pool, or may include both a volatile memory and a non-volatile memory. For example, the storage medium 124 may be a RAM or a ROM. The storage capacity of the storage medium 124 is related to the size of the data block used to collect statistics on the access frequency. The storage capacity of the storage medium 124 can be determined in the following two ways.

[0055] Method 1: Determine the capacity of the storage medium for storing the access frequency of accessing a page based on the capacity of the memory, the page size, and the bit width of the counter for counting the access frequency.

[0056] When statistics regarding the access frequency of accessing a page are collected, the capacity of the storage medium used to store the access frequency of accessing a page can be determined based on the capacity of the memory, the page size, and the bit width of the counter for counting the access frequency. The capacity of the storage medium is shown in the following formula (1). n 1 capacity =(n capacity / X page size )*W count Formula (1)

[0057] n 1 capacity represents the capacity of the storage medium used to store the access frequency of accessing a page, n capacity represents the capacity of the memory, X page size represents the page size, and W count represents the bit width of the counter for counting the access frequency. The bit width of the counter can be determined based on empirical values. A larger bit width of the counter indicates that a larger value is recorded by the counter; and a smaller bit width of the counter indicates that a smaller value is recorded by the counter.

[0058] Example 1: Assume that the capacity of the memory is 64 GB, the page size is 4 KB, the bit width of the counter is 4 B, and the capacity of the storage medium is (64 GB / 4 KB) * 4 B = 64 MB.

[0059] Example 2: Assume that the capacity of the memory is 64 GB, the page size is 2 MB, the bit width of the counter is 4 B, and the capacity of the storage medium is (64 GB / 2 MB) * 4 B = 128 KB.

[0060] It can be understood that the larger the page size, the smaller the capacity of the storage medium, and it indicates that it is necessary to store less data regarding the access frequency to the page. The smaller the page size, the larger the capacity of the storage medium, and it indicates that it is necessary to store more data regarding the access frequency to the page.

[0061] In addition, when a computer device manages memory by using 4KB pages, the storage medium 124 requires a large storage space. In some embodiments, the RCD 123 may be further connected to an external storage medium to expand the capacity of the RCD 123 for storing the access frequency to the page. For example, as shown in FIG. 1, the RCD 123 is further connected to the storage medium 125. The storage medium 124 may be configured to cache the access frequency of frequently accessed pages. The storage medium 125 is configured to store the access frequency to the page. Optionally, when the RCD 123 updates the access frequency to the page stored in the storage medium 125, two operations performed by the storage medium 125 are involved. The RCD 123 may meet the requirements for storing the access frequency by expanding the bandwidth of the storage medium or increasing the access frequency to the storage medium. For example, the RCD 123 may be connected to at least two storage media to expand the bandwidth of the storage medium and increase the access frequency to the storage medium.

[0062] Method 2: Determine the capacity of the storage medium for storing the access frequency to the interleaved data block based on the capacity of the memory, the page size, the bit width of the counter for counting the access frequency, and the number of interleaved internal channels.

[0063] When statistics regarding the access frequency for accessing interleaved data blocks are collected, the capacity of the storage medium used to store the access frequency for accessing the interleaved data blocks can be determined based on the capacity of the memory, the page size, the bit width of the counter for counting the access frequency, and the number of interleaved internal channels.

[0064] There are N channel memory channels in the computer device, the page size is X page size bytes, and the data is interleaved among N channel memory channels based on the cache line granularity, and the size of the interleaved data block (sub-page) that is distributed within each memory channel is X page size / N channel bytes. Specifically, the controller of each memory channel manages the memory unit based on X page size / N channel bytes, and the controller of each memory channel records the access frequency for accessing the data block based on X page size / N channel bytes. The capacity of the storage medium is shown in Equation (2) below. n 1 capacity =(n capacity / (X page size / N channel )*W count ) Equation (2)

[0065] n 1 capacity represents the capacity of the storage medium for storing the access frequency for accessing the interleaved data block, n capacity represents the capacity of the memory, X page size represents the page size, and W count represents the bit width of the counter for counting the access frequency. N channel represents the number of memory channels.

[0066] Example 1: The page size is 2 MB (X page size = 2 MB), the data is interleaved into 8 memory channels based on the cache line granularity (N channel = 8), the size of the interleaved data block for each memory channel is 256 KB, the memory capacity is 64 GB (n capacity = 64 GB), the bit width of the counter for counting the access frequency is 4 B (W count = 4 B), and it is assumed that the capacity of the storage medium is 1 MB. The physical address space of the storage medium that needs to be ensured by the computer device for 8 memory channels is 8 MB. The processor can obtain the access frequency based on 256 - KB units for accessing 8 memory channels, obtain the access frequency for accessing the complete 2 - MB page by combining the said access frequencies, and execute data migration. For example, the processor can add 8 pieces of data.

[0067] Example 2: The page size is 4 KB (X page size = 4 KB), the data is interleaved into 8 memory channels based on the cache line granularity (N channel = 8), the size of the interleaved data block for each memory channel is 512 B, the memory capacity is 64 GB (n capacity = 64 GB), the bit width of the counter for counting the access frequency is 4 B (W count = 4 B), and it is assumed that the capacity of the storage medium is 0.5 GB. The RCD of each memory channel needs to record the access frequency based on 512 - B units. The physical address space of the storage medium that the computer device needs to ensure for 8 memory channels is 4 GB.

[0068] It should be understood that the components included in the computer device 100 shown in FIG. 1 are merely examples for explanation. In a specific embodiment, the quantity of components can be determined based on service requirements.

[0069] Hereinafter, with reference to FIG. 2, as shown in the figure, the memory access popularity statistical method according to the present application will be described.

[0070] Step 210: RCD 123 determines the storage space to be accessed by the access request sent by the processor 110.

[0071] RCD 123 receives the access request sent by the processor 110 by using a memory bus (for example, a DDR bus), decodes the access request to obtain a physical address and an operation instruction. RCD 123 determines whether the processor 110 accesses the memory device 121 or the storage medium 124 in the memory 120 based on the physical address.

[0072] When the physical address indicates the storage space of the memory device 121, it means that RCD 123 determines that the application program executed by the processor 110 accesses the memory device 121, and based on the operation instruction, determines to execute a read operation or a write operation on the memory device 121. Steps 220 and 230 are executed.

[0073] When the physical address indicates the storage space of the storage medium 124, it means that RCD 123 determines to obtain the access frequency of the processor 110 accessing the storage medium 124 to access the data block, and based on the operation instruction, determines to execute a read operation on the storage medium 124. Steps 240 and 250 are executed.

[0074] Step 220: RCD 123 executes an operation on the memory device 121 in the memory 120.

[0075] When the operation command instructs to perform a write operation on the storage space indicated by the physical address in the memory device 121, the RCD 123 writes the data obtained by using the DB 122 to the storage space indicated by the physical address.

[0076] When the operation command instructs to perform a read operation on the storage space indicated by the physical address in the memory device 121, the RCD 123 reads the data stored in the storage space indicated by the physical address and transmits the data to the processor 110 by using the DB 122.

[0077] Step 230: The RCD 123 collects statistics on the access frequency for accessing the data block where the first address is located.

[0078] Since the cache line as the minimum granularity is used for the operations performed on the memory 120 by the application program executed by the processor 110, the access request transmitted by the processor 110 indicates that the application program executed by the processor 110 performs a read operation or a write operation on the cache line. The RCD 123 performs a read operation or a write operation based on the cache line indicated by the physical address. When a cache line is read or written once, the access frequency for accessing the page to which the cache line belongs increases by 1. The RCD 123 can set a counter for each page and collect statistics on the access frequency for accessing the page. Each time the application program executed by the processor 110 accesses a page, the counter corresponding to the page is incremented by 1. Therefore, in order to improve the accuracy of collecting statistics on the memory access popularity, the memory access popularity statistics are collected by using the pages of the storage space of the memory managed by the computer device as the granularity.

[0079] For example, as shown in Fig. 3(a), the size of the physical address space of the memory is 2 N+1 and the size of the cache line is 64 bytes. The page size can be 4KB or 2MB.

[0080] As shown in Fig. 3(b), assume that the size of the cache line is 64 bytes and the page size is 4KB. A 4KB page contains 64 consecutive cache lines. The physical address 0x000 represents the start address of the first page. The physical address 0x1000 represents the start address of the second page. The first page contains 64 consecutive cache lines between the physical address 0x000 and the physical address 0x1000. The second page contains 64 consecutive cache lines between the physical address 0x1000 and the physical address 0x2000.

[0081] When RCD123 collects statistics on the access frequency per page, the address segment for statistics is determined based on the page size. For example, if the page size is 4KB and RCD123 collects statistics on the access frequency of accessing the pages included in the address segment [N:12]. N represents the capacity of the memory 120. For example, if the capacity of the memory 120 is 64GB and N = 35. Assume that the capacity of the memory 120 is 64GB. The address segment [N:12] contains pages of 64GB / 4KB = 16MB, and RCD123 collects statistics on the access frequency of accessing the 16MB pages included in the address segment [N:12].

[0082] As another example, if the page size is 2MB and RCD123 collects statistics on the access frequency of accessing the pages included in the address segment [N:21]. Assume that the capacity of the memory 120 is 64GB. The address segment [N:21] contains pages of 64GB / 2MB = 32KB, and RCD123 collects statistics on the access frequency of accessing the 32KB pages included in the address segment [N:21].

[0083] The physical address included in the access request indicates the first address, and it is assumed that the application program executed by the processor 110 accesses the cache line indicated by the first address in the memory device 121. The first address can be the address of the cache line or the address segment within the address segment for which statistics are collected regarding it. The RCD 123 identifies a second address based on the address of the page where the first address is located and the address mapping relationship, and based on the second address, reads out the access frequency of the accessed page from the storage medium 124 and updates the access frequency of accessing the page. In other words, the access frequency of accessing the page is increased by 1, and the updated access frequency of accessing the page is written back to the storage medium 124. The second address indicates the position of the storage space where the access frequency of accessing the page is stored. The second address can be the page number of the page or the address of the page. The address mapping relationship indicates the mapping relationship between the address of the page and the address of the storage space where the access frequency is stored. For example, when the first address indicates an address, the RCD 123 determines the page number of the page where the cache line indicated by the first address is located based on the first address, and based on the page number of the page, reads out the access frequency of the accessed page from the storage medium 124. When the first address indicates an address segment, the RCD 123 determines the page numbers of all the pages where the cache line indicated by the address segment is located based on the first address, and then reads out the access frequency of the accessed page from the storage medium 124 based on the page numbers of the pages.

[0084] Step 240: The RCD 123 executes an operation on the storage medium 124 in the memory 120.

[0085] The computer device pre-allocates the capacity of the memory device 121 in the memory 120. When the processor 110 accesses the storage medium 124, the computer device allocates to the storage medium 124 a physical address space corresponding to the capacity of the storage medium 124 from the capacity of the memory device 121 in the memory 120, and the RCD 123 maps the physical address for accessing the storage medium 124 to the storage medium 124. In this way, the corresponding capacity in the memory device 121 cannot be used, resulting in waste of the storage space of the memory device 121. For example, when the page size is 4 KB, 64 MB of the memory storage space is wasted.

[0086] Based on the page number (page address) of a page, RCD123 can determine the physical address of the storage medium 124 and store a field formed by a part of the bits of the page number and the access frequency in the corresponding address space within the storage medium 124. As shown in FIG. 4, the bit width of the counter for each page is 4B (32 bits) and is divided into two parts. One part is used to record the access frequency of accessing the page, and the other part is used to record any 8 bits of the page number of the page. The positions for recording the access frequency of accessing the page and the positions for recording any 8 bits of the page number of the page are not limited. Bits 23 to 0 are used to record the access frequency of accessing the page, and bits 32 to 24 are used to record any 8 bits of the page number of the page. For example, bits 32 to 24 represent the least significant 8 bits of the page number of the page. Further, the page number of the page is accessed by the processor 110 and is used to generate the corresponding address space where the access frequency of accessing the page is stored in the storage medium 124, obtain the mapping relationship between the address of the data block and the address of the storage space used to store the access frequency, and as a result, the address space reserved for the memory 120 can be saved, and by using a small amount of address space, the purpose of mapping the address space of the storage medium for storing the access frequency is achieved. This helps the RCD123 to determine the physical address for the processor 110 to access the storage medium 124 based on the address mapping relationship and improve the storage space utilization rate of the memory device 121.

[0087] In some embodiments, some bits of the page number of a page are accessed by the processor 110 and are used to generate a corresponding address space in which the access frequency of accessing the page is stored in the storage medium 124. For example, the remaining bits obtained by deleting any bits within the page number of a page are accessed by the processor 110 and are used as a corresponding address space in which the access frequency of accessing the page is stored in the storage medium 124. If a larger number of arbitrary bits of the page number of a page are deleted, it indicates that the corresponding address space accessed by the processor 110 and storing the access frequency of accessing the page in the storage medium 124 is smaller. Conversely, if a smaller number of arbitrary bits of the page number of a page are deleted, it indicates that the corresponding address space accessed by the processor 110 and storing the access frequency of accessing the page in the storage medium 124 is larger. For example, after RCD123 executes an operation on a page in the memory device 121, it stores the least significant 8 bits of the page number of the page in bits 32 to 24 of a counter and increments only the access frequency recorded in bits 23 to 0 by 1.

[0088] The physical address obtained by RCD123 indicates the storage space of the storage medium 124, which indicates that RCD123 has determined that the processor 110 accesses the storage medium 124 to obtain the access frequency of accessing the data block, and has determined to execute a read operation on the storage medium 124 based on the operation instruction. The physical address can be the remaining bits obtained by deleting any bits within the page number of a page. For example, RCD123 obtains a third address, determines the storage space of the storage medium 124 indicated by the third address, extracts the most significant 8 bits after reading 32-bit data, then adds the third address to obtain a page number, where the corresponding 24-bit data bits are the access frequency of accessing the page corresponding to the page number.

[0089] Step 250: RCD123 determines the access popularity of data blocks based on the access frequency.

[0090] If the access frequency is greater than or equal to the threshold, the data block is determined to be hot data; or if the access frequency is less than the threshold, the data block is determined to be cold data. RCD123 can feedback the page number and the access popularity of the page indicated by the page number to the processor 110 to trigger data migration.

[0091] In this way, the processor executes operations on the memory by using cache lines as the granularity, and the cache lines belong to the managed pages. Therefore, when an operation is executed on a cache line in the memory once, the page to which the cache line belongs is read and written once. The controller collects statistics on the access frequency of accessing the page to which the cache line where the operation is executed belongs. Thereby, the accuracy of identifying the access popularity of the page is effectively improved. In addition, the controller collects statistics on the access frequency of accessing the page by using the page as the granularity, which is compatible with the method of memory page management executed by the computer device. The memory access popularity statistics method is easy to use. In addition, when data migration is triggered based on the access popularity of the data block, hot data can be migrated to the near memory, and cold data can be migrated to the far memory. As a result, the processor can obtain the frequently accessed data from the near memory as quickly as possible. Thereby, the data processing speed of the system is improved, the delay of data processing is reduced, and the access performance of the system is greatly improved.

[0092] In the above embodiments, 4KB pages (small pages) and 2MB pages (huge pages) are used to explain the memory access popularity statistics method.

[0093] In some other embodiments, when an application program executed by a processor operates on the memory of a computer device in an interleaved manner, the data accessed to the memory is evenly distributed among a plurality of memory channels based on a unit storage space (e.g., a cache line). When the controller of each memory channel collects statistics regarding the memory access popularity, the controller collects statistics regarding the access frequency to the interleaved data blocks. For how the controller of each memory channel collects statistics regarding the access frequency to the interleaved data blocks, refer to the above description regarding the access frequency to a page.

[0094] Compared with the non-interleaved scenario, the difference in collecting statistics regarding the access frequency to the interleaved data blocks is that the size of the interleaved data block is less than the page size, the corresponding address space accessed by the processor 110 and the access frequency to the page stored in the storage medium 124 is generated based on some bits within the address of the interleaved data block.

[0095] For example, as shown in FIG. 5, a 2MB page contains 512 4KB pages, the size of a cache line is 64B, and a 4KB page contains 64 cache lines. The 2MB page contains 512*64 cache lines evenly distributed among 8 memory channels, and 512*512B of cache lines are allocated to each memory channel. Each memory channel contains a 256KB interleaved data block.

[0096] For example, when the page size is 4KB (X page size =4KB) and the data is interleaved among 8 memory channels based on the cache line granularity (N channel=8), the size of the interleaved data block for each memory channel is 512B. The controller in each memory records the access frequency for accessing 64GB / 512B = 128MB of interleaved data blocks. The capacity of the storage medium that is in the controller in each memory and is used to store the access frequency for accessing the interleaved data block is 0.5GB. The physical address space of the storage medium that needs to be ensured by the computer device for 8 memory channels is 4GB.

[0097] As another example, the page size is 2MB (X page size = 2MB), the memory capacity is 64GB, and the bit width of the counter is 4B. The address space ensured in each memory is 1MB, and 8MB of memory address space is ensured for 8 memory channels.

[0098] In some embodiments, the controller may determine the address of the storage space used to store the access frequency for accessing the interleaved data block in the controller, which is accessed by the processor, based on the mapping relationship between the address of the interleaved data block and the address of the storage space for storing the access frequency. Specifically, the controller stores any 8 bits of the address of the interleaved data block in bits 32 to 24 of the counter of the interleaved data block, and increments by 1 the access frequency recorded in bits 23 to 0 for accessing the interleaved data block. The remaining bits of the address of the interleaved data block are accessed by the processor and used as the physical address for storing the access frequency for accessing the interleaved data block in the storage medium.

[0099] For example, when a controller in a memory records the access frequency of accessing 64GB / 512B = 128MB of interleaved data blocks, the physical address space for the processor to access the storage medium is reduced to 0.5GB / 256 = 2MB, and the bit width of the counter for counting the access frequency is 4B. The minimum data granularity of the counter for counting the access frequency of the accesses executed by the processor is 4B, and the 2MB physical address space can be further reduced to 2MB / 4B = 512KB. A total of 4MB of physical address space needs to be ensured for 8 memory channels, so only 4MB of memory capacity is wasted.

[0100] The controller determines a physical address within the storage medium for storing the access frequency of accessing a page based on the physical address indicated by the processor for accessing the storage medium. For example, for each memory, the processor periodically and continuously reads out the access frequency stored in the controller in the memory for accessing the interleaved data blocks. The controller detects an access to the corresponding 512KB address, where the physical address is addressed as PA[18:0]. The controller implements an 8-bit address counter AddrCnt[7:0]. When the 512KB address is accessed continuously once, the counter AddrCnt[7:0] is incremented by 1, and the controller generates a physical address MAT_Addr = {AddrCnt[7:0], PA[18:0]}. The controller accesses the access frequency stored in the controller for accessing the interleaved data blocks based on the physical address MAT_Addr.

[0101] After reading 32-bit data, the controller extracts the most significant 8 bits and then adds them to PA[18:0]. A total of 27 bits are the address of the interleaved data block (a sub-page), and the least significant 24 bits of the corresponding data bits are the access frequency for accessing the corresponding interleaved data block. The processor can obtain the 512B-based access frequencies for accessing 8 memory channels and combine the 512B-based access frequencies to obtain the access frequency for accessing a complete 4KB page. For example, the access frequencies for accessing 8 memory channels are added, or the average value, variance value, maximum value, and the like of the access frequencies for accessing 8 memory channels are obtained.

[0102] In the above embodiments, the processor 110 uses access requests as an example for explaining the memory access popularity statistics method. When an application program executed by the processor 110 sends multiple access requests for operations on the memory of the computer device, statistics regarding the data block where the physical address corresponding to each access request is located are collected. For the specific method, refer to the description in the above embodiments.

[0103] In the above embodiments, with reference to the accompanying drawings, the scenario of the connection relationship between the controller and the near memory included in the computer device and the memory access popularity statistics method of the near memory are described. The memory 120 described in the above embodiments may represent a near memory (which may also be referred to as a near memory), and the RCD123 may refer to a controller that controls the near memory to collect statistics regarding the memory access popularity.

[0104] In some other embodiments, the computer device may include a far memory (which may also be referred to as a far memory), and the controller collects statistics regarding the access frequency of accessing the far memory. The difference from the connection relationship between the near memory and the controller is that, compared with the memory controller in the processor, the controller that controls the far memory to collect statistics regarding the memory access popularity may be an extended controller.

[0105] Optionally, the computer device includes a far memory and a near memory. The RCD in the near memory collects statistics regarding the access frequency of accessing the near memory, and the extended controller connected to the far memory collects statistics regarding the access frequency of accessing the far memory.

[0106] The access frequency threshold is determined based on the application. Data whose access frequency is higher than the threshold is determined to be hot data and stored in the near memory, and data whose access frequency is less than the threshold is determined to be cold data and stored in the far memory. On the premise that the threshold setting does not affect the application performance, it is found that a very small amount of memory access data is hot data and most of the memory access data is cold data. The computer device may be configured with a higher proportion of far memory to reduce system costs. When the proportion of hot data decreases, the data transfer between the near memory and the far memory decreases, and the occupancy of the system memory bandwidth and the CPU overhead can be reduced.

[0107] In a possible implementation, the present application further provides a schematic diagram of the structure of another computer device. As shown in FIG. 6, based on the computer device 100 including a processor 110 and a memory 120, the computer device 100 further includes a memory 610. The memory 120 may be used as a near memory, and the memory 610 may be used as a far memory. The processor 110 is connected to the memory 610 by using a bus 620.

[0108] Memory 610 includes an expansion controller 611, a memory device 612, and a storage medium 613. The memory device 612 includes DRAM and SCM. The storage medium 613 can be DRAM.

[0109] The expansion controller 611 is configured to execute a read operation or a write operation within the memory device 612 based on an access request from the processor 110, count the access frequency of accessing data blocks within the memory device 612, and store the access frequency of accessing data blocks within the storage medium 613. The expansion controller 611 can be further connected to an external storage medium 614 to expand the storage capacity of the storage medium 613 and be configured to store the access frequency of accessing data blocks.

[0110] The expansion controller 611 is further configured to obtain the access frequency of accessing data blocks from the storage medium 613.

[0111] For the functions of the expansion controller 611 and the method for counting the access frequency of accessing data blocks within the memory device 612 in the memory 610 and obtaining the access frequency of accessing the data blocks obtained from the storage medium 613, please refer to the related description of the controller collecting statistics on the access frequency of accessing the near memory.

[0112] The memory 610 can be a volatile memory pool or a non-volatile memory pool, or can include both volatile memory and non-volatile memory. The non-volatile memory can be ROM, PROM, EPROM, EEPROM, or flash memory. The volatile memory can be RAM. By way of non-limiting example, many forms of RAM, such as SRAM, DRAM, SDRAM, DDR SDRAM, ESDRAM, SLDRAM, and DR RAM can be used.

[0113] Bus 620 may include channels configured to transmit data between the above-described components (e.g., processor 110 and memory 610). For example, processor 110 may send an access request to memory 610, and memory 610 may feedback to processor 110 the access frequency for accessing a data block. In addition to the data bus, bus 620 may further include a power bus, a control bus, a status signal bus, and the like. For example, bus 620 may be a DDR bus. However, for clarity of explanation, in the figure, various types of buses are shown as bus 620. Bus 620 may be a Peripheral Component Interconnect Express (PCIe) bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a Compute Express Link (CXL), a cache coherent interconnect for accelerators (CCIX), or the like. Bus 620 may be classified into an address bus, a data bus, a control bus, and the like.

[0114] In this embodiment of the present application, the structures of the near memory and the far memory included in the computer device are described. For the method of statistically analyzing the memory access popularity of the near memory and the far memory, refer to the above description of collecting statistics regarding the memory access popularity of the near memory. The RCD in the near memory collects statistics regarding the access frequency of accessing the near memory, and the expansion controller connected to the far memory collects statistics regarding the access frequency of accessing the far memory, which consumes little CPU performance. In addition, the processor executes operations on the memory by using cache lines as the granularity, and the cache lines belong to the managed pages. Therefore, when an operation is executed on a cache line in the memory once, the page to which the cache line belongs is read and written once. The controller collects statistics regarding the access frequency of accessing the page to which the cache line where the operation is executed belongs. Thereby, the accuracy of identifying the access popularity of the page is effectively improved. In addition, the controller collects statistics regarding the access frequency of accessing the page by using the page as the granularity, which is compatible with the method of memory page management executed by the computer device. The method of statistically analyzing the memory access popularity is easy to use. In addition, the threshold value of the access frequency is determined based on the application, and the data whose access frequency is higher than the threshold value is determined as hot data and stored in the near memory, and the data whose access frequency is less than the threshold value is determined as cold data and stored in the far memory. On the premise that the threshold setting does not affect the application performance, it is found that a very small amount of memory access data is hot data, and most of the memory access data is cold data. The computer device can be configured with a higher proportion of far memory to reduce the system cost. When the proportion of hot data decreases, the data transfer between the near memory and the far memory decreases, and the occupancy of the system memory bandwidth and the CPU overhead can be reduced.

[0115] To implement the functions in the above embodiments, the controller includes corresponding hardware structures and / or software modules for executing the functions. A person skilled in the art should easily recognize that, in combination with the units and method steps in the examples described in the embodiments disclosed in this application, this application can be implemented by using hardware, or a combination of hardware and computer software. Whether a certain function is executed by using either hardware or hardware driven by computer software depends on the specific application scenario and the design constraints of the technical solution.

[0116] Referring to FIGS. 1 to 6, in the above, the memory access popularity statistical method according to this application has been described in detail. Referring to FIG. 7, hereinafter, the memory access popularity statistical device according to this application will be described.

[0117] FIG. 7 is a schematic diagram of the structure of a possible memory access popularity statistical device according to this application. These memory access popularity statistical devices can be configured to implement the functions of the controller in the above method embodiments, and thus can also implement the beneficial effects of the above method embodiments. In this embodiment, the memory access popularity statistical device can be the controller shown in FIG. 2, or can be a module (such as a chip) applied to a computer device.

[0118] As shown in FIG. 7, the memory access popularity statistical device 700 includes a communication module 710, a statistical module 720, and a storage module 730. The memory access popularity statistical device 700 is configured to implement the functions of the controller in the method embodiment shown in FIG. 2.

[0119] The communication module 710 is configured to determine a first address based on the acquired access request, where the access request indicates an operation to be performed on the memory of the computer device by an application program executed by a processor within the computer device where the controller is located, and the first address is a physical address within the memory.

[0120] The statistics module 720 is configured to collect statistics regarding the access frequency of accessing the data block where the first address is located, where the size of the data block is a multiple of the unit storage space within the memory accessible by the processor. For example, the statistics module 720 is configured to execute steps 210 to 250 in FIG. 2.

[0121] The statistics module 720 is particularly configured to collect statistics regarding the access frequency of accessing the data block where the unit storage space to which the first address belongs is located.

[0122] The memory module 730 is configured to store the access frequency. As a result, the statistics module 720 determines the access popularity of the data block based on the access frequency and triggers data migration.

[0123] The memory access popularity statistic device 700 in this embodiment of the present application can be implemented by using an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The PLD can be a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), a DPU, a SoC, or any combination thereof. When the memory access popularity statistic method shown in FIG. 2 can also be implemented using software, the modules of this method can also be software modules, and the memory access popularity statistic device 700 and the modules of the device 700 can also be software modules.

[0124] The memory access popularity statistic device 700 according to this embodiment of the present application can execute the method described in the embodiment of the present application accordingly, and the above-described operations and other operations and / or functions of the units in the memory access popularity statistic device 700 are respectively used to implement the corresponding procedures of the method in FIG. 2. For the sake of brevity, the details will not be described again in this specification.

[0125] FIG. 8 is a schematic diagram of the structure of the controller 800 according to the present application. As shown in the figure, the controller 800 includes a processing unit 810, a bus 820, a storage unit 830, and a communication interface 840. The processing unit 810, the storage unit 830, and the communication interface 840 are connected by using the bus 820.

[0126] In this embodiment, the processing unit 810 can be a CPU, or the processing unit 810 can be another general-purpose processor, a digital signal processor (DSP), an ASIC, an FPGA, or another programmable logic device, discrete gate, or transistor logic device, discrete hardware component, or the like. The general-purpose processor can be a microprocessor, or any conventional processor or the like.

[0127] The communication interface 840 is configured to implement communication between the controller 800 and an external device or component. In this embodiment, when the controller 800 is configured to implement the functions of the controller shown in FIG. 2, the communication interface 840 is configured to obtain an access request.

[0128] The bus 820 can include a channel configured to transmit information between the above-described components (e.g., the processing unit 810 and the storage unit 830). In addition to the data bus, the bus 820 can further include a power bus, a control bus, a status signal bus, and the like. However, for clarity of explanation, in the figure, various types of buses are shown as the bus 820. The bus 820 can be a Peripheral Component Interconnect Express (PCIe) bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a Compute Express Link (CXL), a cache coherent interconnect for accelerators (CCIX), or the like. The bus 820 can be classified into an address bus, a data bus, a control bus, and the like.

[0129] In one example, the controller 800 may include a plurality of processors. The processor may be a multi-core (multi-CPU) processor. A processor herein may be one or more devices, circuits, and / or processing units configured to process data (e.g., computer program instructions). In this embodiment, when the controller 800 is configured to implement the functions of the controller shown in FIG. 2, the processing unit 810 collects statistics regarding the access frequency of accessing the data block where the first address is located.

[0130] Optionally, a method for collecting statistics regarding the access frequency of accessing a data block may also be incorporated into the processing unit 810, and as a result, the processing unit 810 collects statistics regarding the access frequency of accessing the data block.

[0131] In FIG. 8, only one example where the controller 800 includes one processing unit 810 and one storage unit 830 is used. In this specification, the processing unit 810 and the storage unit 830 are separately configured to indicate the types of components or devices. In a particular embodiment, the quantity of each type of component or device may be determined based on service requirements.

[0132] The memory unit 830 can correspond to the embodiments of the above-described method and is configured to store information such as access frequency. The memory unit 830 can be a volatile memory pool or a non-volatile memory pool, or can include both volatile memory and non-volatile memory. The non-volatile memory can be a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM) used as an external cache. By way of non-limiting example, many forms of RAM, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and direct rambus RAM (DR RAM), can be used.

[0133] The memory unit 830 can further correspond to a storage medium configured to store information such as computer instructions in the embodiments of the above-described method, for example, a magnetic disk such as a mechanical hard disk drive or a solid state disk.

[0134] The controller 800 can be a general-purpose device or a dedicated device. For example, the controller 800 can also be a server or another device having computing capabilities.

[0135] The controller 800 according to this embodiment may correspond to the memory access popularity statistic device 700 in this embodiment and may correspond to an entity that executes any method according to FIG. 2. In addition, the above-described operations and other operations and / or functions of the modules in the memory access popularity statistic device 700 are each used to implement the corresponding procedures of the method in FIG. 2. For the sake of brevity, details are not described again in this specification.

[0136] The controller 800 in this embodiment of the present application may be an RCD controller in the memory of a computer device. Alternatively, the controller 800 is an expansion controller connected to the memory of a computer device.

[0137] One embodiment of the present application further provides a chip including a processor and a power supply circuit, where the power supply circuit is configured to supply power to the processor, and the processor is configured to execute the memory access popularity statistic method in the above-described embodiment.

[0138] One embodiment of the present application further provides a memory. The memory includes a storage device and a controller. The storage device is configured to store a group of computer instructions. When the controller executes a group of computer instructions, the memory access popularity statistic method in the above-described embodiment is executed.

[0139] One embodiment of the present application further provides a motherboard. The motherboard includes a controller, and the controller executes the memory access popularity statistic method in the above-described embodiment.

[0140] The method steps in this embodiment can be implemented in a hardware manner or can be implemented by a processor executing software instructions. The software instructions can include corresponding software modules. The software modules can be stored in a random access memory (RAM), a flash memory, a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), a register, a hard disk drive, a removable hard disk drive, a CD-ROM, or any other form of storage medium well-known in the art. For example, the storage medium is coupled to the processor, whereby the processor can read information from the storage medium and write information to the storage medium. It is obvious that the storage medium can be a component of the processor. The processor and the storage medium can be disposed in an ASIC. In addition, the ASIC can be located within a computing device. It is obvious that the processor and the storage medium can alternatively exist within the computing device as discrete components.

[0141] All or some of the above-described embodiments may be implemented by using software, hardware, firmware, or any combination thereof. When software is used to implement an embodiment, all or some of the embodiments may be implemented in the form of a computer program product. A computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, all or part of the procedures or functions in the embodiments of the present application are executed. The computer may be a general-purpose computer, a dedicated computer, a computer network, a network device, a user device, or another programmable device. The computer program or instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer program or instructions may be transmitted in a wired or wireless manner from a website, a computer, a server, or a data center to another website, a computer, a server, or a data center. The computer-readable storage medium may be any usable medium accessible by a computer or a data storage device such as a server or a data center integrating one or more usable media. The usable medium may be a magnetic medium, such as a floppy disk, a hard disk drive, or a magnetic tape, an optical medium, such as a digital video disc (DVD), or a semiconductor medium, such as a solid-state drive (SSD).

[0142] The above description is only a specific embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification or substitution that can be easily conceived by those skilled in the art within the technical scope disclosed in the present application shall fall within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method for statistically analyzing memory access popularity, which is executed by a controller: Determining a first address based on an obtained access request, where the access request indicates an operation performed on the memory of the computer device by an application program executed by a processor in the computer device where the controller is located, and the first address is a physical address in the memory; Collecting statistics on the access frequency of accessing a data block where the first address is located, where the size of the data block is a multiple of a unit storage space in the memory accessible by the processor; and Determining the access popularity of the data block based on the access frequency A method for statistically analyzing memory access popularity, comprising the above steps.

2. The step of collecting statistics on the access frequency of accessing a data block where the first address is located includes: Collecting statistics on the access frequency of accessing the data block where the unit storage space to which the first address belongs is located The method according to claim 1, having the above step.

3. The method further includes: Identifying a second address based on the address and the address mapping relationship of the data block where the first address is located, where the second address indicates a position in the controller where the access frequency of accessing the data block is stored, and the address mapping relationship indicates a mapping relationship between the address of the data block and the address of the storage space where the access frequency is stored The method according to claim 2, further comprising the above step.

4. The method further includes: Identifying the second address based on a third address indicated by the processor and the address mapping relationship, and obtaining the access frequency of accessing the data block, where the third address is determined based on the second address The method according to claim 3, further comprising the above step.

5. The method according to any one of claims 1 to 4, wherein the size of the data block is the size of one page in the memory accessible by the processor.

6. The size of the data block is the size of an interleaved data block in the memory that is accessible to the processor in an interleaved manner, where the interleaved manner means that the processor in the computer device distributes the data of the operations executed by the application program being executed for the operations to a plurality of memories with respect to the memory of the computer device. The method according to any one of claims 1 to 4.

7. The size of the unit storage space is the size of a cache line when the processor accesses the memory. The method according to any one of claims 1 to 6.

8. A communication module configured to determine a first address based on the acquired access request, where the access request indicates an operation to be executed on the memory of the computer device by an application program executed by a processor in the computer device where the controller is located, and the first address is a physical address in the memory; and A statistical module configured to collect statistics regarding the access frequency to the data block where the first address is located, where the size of the data block is a multiple of the unit storage space in the memory accessible to the processor comprising the statistical module is further configured to determine the access popularity of the data block based on the access frequency Memory access popularity statistical device.

9. When collecting the statistics regarding the access frequency to the data block where the first address is located, the statistical module: Specifically configured to collect statistics regarding the access frequency to the data block where the unit storage space to which the first address belongs is located. The device according to claim 8.

10. The statistical module: Based on the address of the data block where the first address is located and the address mapping relationship, identify a second address, where the second address indicates a position in the controller where the access frequency for accessing the data block is stored, and the address mapping relationship indicates a mapping relationship between the address of the data block and the address of the storage space where the access frequency is stored. The apparatus according to claim 9, further configured as described above.

11. The statistical module is: Based on the third address indicated by the processor and the address mapping relationship, identify the second address and obtain the access frequency for accessing the data block, where the third address is determined based on the second address. The apparatus according to claim 10, further configured as described above.

12. The size of the data block is the size of one page in the memory accessible by the processor. The apparatus according to any one of claims 8 to 11.

13. The size of the data block is the size of an interleaved data block in the memory accessible by the processor in an interleaved manner. The interleaved manner means that the processor in the computer device distributes the data of the operations executed by the running application program for the operations to a plurality of memories with respect to the memory of the computer device. The apparatus according to any one of claims 8 to 11.

14. The size of the unit storage space is the size of a cache line when the processor accesses the memory. The apparatus according to any one of claims 8 to 13.

15. A controller comprising a storage unit and a processing unit. The storage unit is configured to store a group of computer instructions. When executing the group of computer instructions, the processing unit executes the operation steps of the method according to any one of claims 1 to 7, and identifies the access frequency of an application program accessing a data block in the memory.

16. The controller according to claim 15, which is a register clock driver RCD in the memory of the computer device.

17. The controller according to claim 15, which is an expansion controller in the memory of the computer device.

18. A chip comprising a processor and a power supply circuit, the power supply circuit being configured to supply power to the processor, and the processor being configured to execute the operation steps of the method according to any one of claims 1 to 7.

19. A memory comprising a storage device and a controller according to any one of claims 15 to 17, the storage device being configured to store a group of computer instructions, and when executing the group of computer instructions, the controller executes the operation steps of the method according to any one of claims 1 to 7 and identifies the access frequency at which an application program accesses a data block in the memory.

20. A main board comprising a controller according to any one of claims 15 to 17, the controller executing the operation steps of the method according to any one of claims 1 to 7 and identifying the access frequency at which an application program accesses a data block in the memory.

21. A computer device comprising the main board according to claim 20.

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