High-Speed LCR Meter with Leakage Correction

Abstract

An LCR meter that uses a high-speed balancing method and can balance voltage measurement with only one unit. The LCR meter uses time-separated measurements of the device under test (DUT) and other parasitic component impedances (including leakage impedance) to speed up the balancing. The LCR meter is used to speed up balancing, separation of the measurement time of the device under test (DUT), and other parasitic impedances including leakage impedance. The leakage impedance and other parasitic impedances of the fixture and the LCR meter are measured during open / short calibration and stored in memory. The DUT is measured during measurement using known parasitic impedances. This makes it possible to calculate the balance condition with only one measurement of voltage.

Description

Technical Field

[0001] The present invention relates to an apparatus for measuring impedance over a wide frequency range.

Background Art

[0002] The main parameters of an LCR meter are the accuracy and speed of measurement. When an LCR meter is used as part of an impedance analyzer or in manufacturing, the measurement speed is important. Impedance measurement is based on measuring the voltage drop in a device under test (DUT) arranged in series with a range resistor having a known impedance. The impedance of the DUT is calculated by knowing the current through the DUT and the voltage drop.

[0003] In this case, the main cause of the error [Figure 1] is that a leakage current flows through the leakage impedance between the midpoint of the DUT and the range resistor to the ground. The leakage current is the reason why the currents through the range resistor and the DUT are not equal.

[0004] Various methods are used to reduce the leakage current.

[0005] One of them is the guard method, which helps to reduce the voltage between the midpoint and the shield in the cable from the low potential (LP) terminal of the LCR meter to the DUT by applying a voltage to the shield through a voltage follower. This method is used in the digital impedance meter ESI model 251, "A History of Impedance Measurements by Henry P. Hall", p. 49.

[0006] Another method is an automatic balance bridge using a transimpedance amplifier (TIA). This method is used in the digital impedance meter GR type 1685 - A, "A History of Impedance Measurements by Henry P. Hall", p. 49

[0007] Both of these methods respond immediately to balancing, but at high frequencies the gain is low, resulting in low common voltage suppression between the midpoint of the cable and the shield. There may also be stability issues.

[0008] An LCR meter equipped with a modem-type automatic balance bridge has good balance accuracy at high frequencies. For example, the Hewlett Packard 4271A LCR meter, "A History of Impedance Measurements by Henry P. Hall", p. 49. However, it includes a slow integrator and requires a stabilization time of several cycles of the signal frequency, resulting in long measurement times at low and medium frequencies. It is also expensive. A digital version of the modem-type automatic balancing bridge exists in U.S. Patent No. 7,616,008 B1, Rayman et al. (2009). However, it has the same drawbacks as the analog version. Slow at low and medium frequencies.

[0009] Other digital methods also exist, for example, U.S. Patent No. 10,013,015 B2, Ida et al. (2018), Chinese Patent Application Publication No. 110320410 A, Fajie et al. (2019), "A Novel Fast Balance Technique for the Digital AC Bridge", Zhang et al. (1998). However, all of them require at least two voltage measurements and at least two signal frequency cycles for balancing. SUMMARY OF THE INVENTION

[0010] The present invention uses a high-speed balancing method that includes a small number of components to obtain high precision and high measurement speed.

[0011] First, it is the time separation of the measurement of the DUT and other parameters necessary for high-speed balancing. These parameters are the leakage impedance of the fixture and the LCR meter, and the series impedance of the fixture and the voltage source. These parameters are constants, measured only once during calibration, and then used during the measurement of the DUT.

[0012] Second, measure the DUT impedance with medium accuracy without the balance condition. In this case, the leakage current causing the measurement error is corrected by the value of this current calculated using the unbalanced voltage and the previously measured value of the leakage impedance.

[0013] Third, based on the medium accuracy value of the DUT and the previously measured series impedance of the fixture and the voltage source, calculate and set the voltage of the voltage source at once without iteration, and obtain a balancing condition close to zero voltage at the midpoint between the DUT and the range resistor. With the balancing condition, the DUT impedance can be measured with high accuracy. Using the latest high-speed processor, the measurement time does not increase.

Problems to be Solved by the Invention

[0014] Some LCR meters use balancing to exclude the current through the leakage impedance and use a modem-type balancing method. LCR meters have the highest accuracy at high frequencies but are slow at low and medium frequencies.

Means for Solving the Problems

[0015] Using a high-speed balancing method, the present invention solves the low-speed problem. This method requires only one measurement of the voltage for balancing, and its balancing speed is limited only by the entire period of the signal frequency. This method uses the previously measured leakage impedance and other impedances of the fixture and the LCR meter to calculate the required voltage and perform high-speed balancing to set it in one step.

Effects of the Invention

[0016] The present invention features high-speed measurement and low-cost manufacturing. There are no stability issues. The hardware structure enables the expansion of the frequency range by mutually calibrating the voltage channels.

Brief Description of the Drawings

[0017]

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Description of the Reference Numerals

[0018] 1002 First voltage source (VoltSrc1) 1004 High Current (HC) Terminal 1006 High Potential (HP) Terminal 1008 Device Under Test (DUT) 1010 Low Potential (LP) Terminal 1012 Intermediate Point between DUT and Range Register 1014 Leakage Impedance (Zleak) 1016 Low Current (LC) Terminal 1018 Set of Range Register and Reference Register (Zrange) 1020 Voltage at the Second Terminal of the Range Register (Vrr) 1022 Second Voltage Source (VoltSrc2) 3002 Output Impedance of the First Voltage Source (Zout1) 3004 Impedance of the Series Current Limiting Register (Zser_res) 3006 Output Impedance of the Buffer of the First Voltage Source (Zbuff1) 3008 Impedance of the Cable Wire between the High Current Terminal and the Device Under Test (Zwire1) 3010 Capacitance of the Cable between the HP Terminal and the DUT (Ccable1) 3012 Impedance of the Cable Wire between the LC Terminal and the Device Under Test (Zwire2) 3014 Parasitic Capacitance of the Range Register Multiplexer (Cmux) 3016 Impedance of the Range Register Multiplexer (Zmux) 3018 Output Impedance of the Second Voltage Source (Zout2) 3020 Output Impedance of the Second Voltage Source Buffer (Zbuff2) 9004 Switch of the High Potential Buffer for Calibration 9006 Switch of the Low Potential Buffer for Calibration 9008 Switch of the Low Current Buffer for Calibration 9010 Switch of the Range Register Buffer for Calibration 9012 Switch for Providing the Calibration Voltage to the Input Buffer 9016 High Potential Voltage Input Buffer 9018 Low-Potential Voltage Input Buffer 9020 Low-Current Voltage Input Buffer 9022 Range Register Voltage Input Buffer 9024 First Voltage Source Output Buffer 9026 Second Voltage Source Output Buffer 9028 First Low-Pass Filter (LPF1) 9030 Input Multiplexer 9032 Output Multiplexer Buffer 9033 Multiplexer Control Interface 9034 Second Low-Pass Filter (LPF2) 9036 First Digital-to-Analog Converter (DAC) (DAC1) 9038 First Analog-to-Digital Converter (ADC) (ADC1) 9040 Second DAC (DAC2) 9042 Digital Signal to the First DAC 9044 Digital Signal from the First ADC 9046 Digital Signal to the Second DAC 9048 Processor 10002 Second ADC (ADC2) 10004 Third ADC (ADC3) 10006 Fourth ADC (ADC4) 11002 First Memory Buffer Set 11004 Second Memory Buffer Set 11006 Direct Fourier Transform (DFT) Block 11008 Cosine Multiplier 11010 Sine Multiplier 11012 Demultiplexer and Accumulator 11014 Software Direct Digital Synthesizer (DDS) 11016 Control and Processing Core 12002 Common Direct Memory Access (DMA) Flowchart 12004 Direct Fourier Transform Processing Flowchart for ADC Data Flow DMA data preparation flowchart for 12006 DAC and reference buffer.

DETAILED DESCRIPTION OF THE INVENTION

[0019] In order to improve the measurement accuracy, the prior art only eliminates or reduces the voltage drop in the leakage impedance.

[0020] Also, except for the guard and trans-impedance auto-balancing method, at least two measurements are required in the prior art to achieve balancing. This is because there are at least two important unknown parameters in the measurement circuit, namely the impedance of the device under test and the leakage impedance. However, according to the science of mathematics, two unknowns are required for at least two equations, and therefore two sets of measured voltages are required.

[0021] The leakage impedance and other parasitic parameters of the fixtures and LCR meters used are constant and can be measured only once during calibration. This information can be automatically applied to save measurement time. Also, if these values are known, their influence can be corrected in the calculation result of the DUT impedance.

[0022] The present invention improves accuracy and speeds up measurements by pre-measuring the leakage impedance and series impedance of fixtures and voltage sources during calibration. Knowledge of parasitic impedance enables more accurate and rapid measurements. The series impedance includes leakage impedance, the output impedance of the voltage source, and the series impedance of the cable. This separates the measurement of the device under test from the measurement of parasitic impedance in time. The series impedance can be measured during the calibration of the fixtures used and stored in the on-board memory. The LCR meter can automatically use the relevant series impedance if it can recognize the fixture, or the user can manually select the data from previously stored values. The calibration of leakage impedance and series impedance can be combined with standard open / short calibration.

[0023] Knowledge of leakage impedance and series impedance shortens the DUT measurement time. First, calculate a medium-accuracy value of the DUT without balancing and use it in a fast balancing method. Then, use the value of the leakage impedance to correct the leakage current caused by the residual unbalanced voltage.

[0024] For medium requirements for accuracy, at low and medium frequencies, the leakage impedance is relatively high, and even one-step balancing takes time and may fail. Only medium-accuracy measurements with leakage correction are possible. However, at high frequencies where the typical cable capacitance is about 100 pF / m and the capacitance of the range resistor multiplexer reaches several hundred picofarads, balancing is necessary.

[0025] Another cause of errors at high frequencies is the inequality of the gain and phase delay of the operational amplifiers used in input buffers 9016, 9018, 9020, and 9022. [Figure 8] shows the possibility of gain error and phase delay inequality of the operational amplifier used as an input buffer with unity gain of about 100 MHz and a tolerance of ±20%. Even at a relatively low signal frequency of 1 MHz, the gain error between two channels can reach ±0.4% and ±0.8% between the DUT and the range voltage, which is unacceptable for a precision LCR meter.

[0026] Details are described in the description of the embodiments. These embodiments are for illustrative purposes only and do not limit the present invention.

[0027] First Embodiment The first embodiment [Figure 9] includes a processor 9048, which provides digital signals 9042 and 9046 to a first 1002 and a second 1022 voltage source. These voltage sources include digital-to-analog converters (DACs) 9036 and 9040, low-pass filters 9028 and 9034, output buffers 9024 and 9026. The processor also receives a digital signal 9044 from an analog-to-digital converter (ADC) 9038 and controls an analog multiplexer 9030.

[0028] The output of the first voltage source 1002 is connected to the HC terminal and the DUT 1008 through its output impedance 3002 [Figure 3]. The output impedance 3002 includes the output impedance 3006 of buffer 9024 [Figure 9], series resistor 3004, wire impedance 3008, and the capacitance of cable 3010 between the HC terminal 1004 of the LCR meter and the DUT 1008.

[0029] One side of the DUT 1008 connected to the HC terminal 1004 is also connected to the HP terminal 1006. The other side of the DUT 1008 is connected to the LP terminal 1010 and the LC terminal 1016.

[0030] The output of the second voltage source 1022 is connected to the second terminal of the range register 1018 through its output impedance 3018. The first terminal of the range register is connected to the DUT 1008 via the LC terminal 1016 and the cable between the LC terminal and the DUT 1008. The output impedance 3018 of the second voltage source 1022 includes the output impedance 3020 of the [Figure 3] buffer 9026, the impedance of the range register multiplexer 3016, and the capacitance of the multiplexer 3014.

[0031] The HP terminal 1006 is connected to the normally closed input of the switch 9004, and its output is connected to the input buffer 9016. The LP terminal 1010 is connected to the normally closed input of the switch 9006, and its output is connected to the input buffer 9018. The LC terminal 1016 is connected to the normally closed input of the switch 9008, and its output is connected to the input buffer 9020. The LC terminal on the opposite side of the range register 1018 is connected to the normally closed input of the switch 9010, and its output is connected to the input buffer 9022. The outputs of the input buffers 9016, 9018, 9020, and 9022 are connected to the inputs of the multiplexer 9030, and its output is connected to the ADC 9038 via the buffer 9032. The normally open inputs of the switches 9004, 9006, 9008, and 9010 are connected to the output of the switch 9012. The normally closed input of the switch 9012 is connected to ground, and the normally open input is connected to the output of the second voltage source 1022.

[0032] In the first embodiment, a guard can also be used to reduce the voltage between the midpoint and the cable shield. In this case, all the equations are the same. The only difference is that the leakage impedance is high.

[0033] Operation of the First Embodiment Leakage impedance measurement, series impedance measurement, and input buffer equalization are performed during the open / short calibration in the first embodiment [Figure 9].

[0034] Leakage Calibration and Correction [Fig. 2] shows a method for measuring leakage impedance. The method includes the following. Remove the DUT and set the fixture to the open state, Apply a predetermined voltage through a range register of a predetermined impedance, Measure the voltage of the open fixture, To eliminate the influence of the open fixture, set the same voltage on the HP terminal and the LP terminal, and adjust to obtain the closest value of these voltages with a predetermined number of repetitions to reduce the current passing through the open fixture, Measure the leakage impedance and the voltage of the range register, Calculate the leakage impedance.

[0035] To set the required voltage on the HP terminal, use the methods of Equations 22 and 23 to calculate the value of the input signal of the first voltage source.

[0036] [Equation 1] Leakage impedance, Zleak = Vlp * Zrange / (Vlc - Vrr) All values are complex numbers.

[0037] When measuring the parameters of the DUT, use the leakage impedance to calculate the leakage current, and subtract the current value from the current passing through the range register to correct its influence. Calibration of Series Impedance

[0038] [Fig. 3] shows a method for measuring the series impedance including the output impedances of the first voltage source 3002 and the second voltage source 3018 and the impedance of the wire between the DUT and the LC terminal 3012. The impedance of the cable wire 3012 between the DUT and the LC terminal and the output impedances of both voltage sources are necessary to bring the balanced voltage close to zero. To measure and calculate the series impedance, both the open and short - circuit states of the measurement circuit are required. In the calibration process, all measured voltage sets for both open and short - circuit are saved and used to calculate the series impedance.

[0039] [Equation 2] Current change of the first voltage source, dI1=(Vlc_short - Vrr_short) / Zrange+Vlp_short / Zleak

[0040] [Equation 3] Current change of the second voltage source, dI2=(Vlc_short - Vrr_short) / Zrange - Vrr_open / (Zleak + Zrange)

[0041] [Equation 4] Output impedance of the first voltage source, Zout1=(Vrr_open - Vrr_short) / dI1

[0042] [Equation 5] Output impedance of the second voltage source, Zout2=(Vrr_open - Vrr_short) / dI2

[0043] [Equation 6] Impedance of the wire between the DUT and the LC terminal, Zwire2=(Vlp_short - Vlc_short) / dI2 All values are complex numbers.

[0044] Equalization method The first embodiment [Figure 9] can perform equalization calibration to automatically eliminate the gain and phase non-uniformity of the input buffer without user participation. The structure of the first embodiment with voltages measured independently for the input terminal and the range register enables equalization calibration by simultaneously providing the same predetermined voltage to all input buffers. [Figure 9] shows the initial normally closed positions of switches 9004, 9006, 9008, 9010, and 9012. For equalization, the calibration needs to set the opposite positions of these switches and connect the input buffers to a common point with a voltage common to all channels. Then, a predetermined voltage needs to be applied from the second voltage source, the voltage is measured at the input buffer or the voltage channel, and the correction factor is calculated and saved. It is necessary to assign one of the input channels as a reference. For example, the LP channel.

[0045] [Equation 7] Correction factor for the HP input buffer 9016, Chp = Vlp / Vhp

[0046] [Equation 8] Correction factor for the LP input buffer 9018, Clp = Vlp / Vlp

[0047] [Equation 9] Correction factor for the LC input buffer 9020, Clc = Vlp / Vlc

[0048] [Equation 10] Correction factor for the range register input buffer 9022, Crr = Vlp / Vrr

[0049] [Equation 11] Next, the voltage corrected during measurement is, Vxx_corr = Vxx_raw * Cxx

[0050] Low-level processing The first embodiment uses one ADC and a 4-channel multiplexer, has a structure for switching voltage channels, and reduces costs. [Figure 4] shows the input voltage, and [Figure 5] shows the voltage at the ADC input. Since switching the multiplexer channels generates commutation noise, the noisy time intervals after switching need to be excluded from the ADC signal processing. [Figure 6] shows the noisy time intervals and the appropriate time intervals.

[0051] According to the Nyquist theorem, the sampling frequency must be at least twice the signal bandwidth. To measure the vector voltage directly by discrete Fourier transform (DFT), at least one period of the signal frequency is required. Therefore, the minimum vector voltage measurement time is limited by one period of the signal frequency and at least three ADC samples for each measured voltage. Therefore, all voltages must be measured simultaneously [Figure 5], and at least three sample groups are required. Equations 12 to 16 describe the low-frequency and medium-frequency conditions when the minimum measurement time is required.

[0052] [Equation 12] Sampling period, Tsample = 1 / Fsample

[0053] [Equation 13] Signal period, Tsignal = 1 / Fsignal

[0054] [Equation 14] Buffer time interval, Tbuffer = Tsample * BufferSize

[0055] [Equation 15] Sample group interval, Tsamplegroup = Tbuffer * Nchannels

[0056] [Equation 16] Minimum measurement time, Tmeas_min = Tsignal = M * Tsamplegroup (M ≥ 3)

[0057] BufferSize, Nchannels, and M are integers. BufferSize is the size of the direct memory access (DMA) buffer, Nchannels is the number of voltage channels, and M is the number of sample groups.

[0058] [Figure 11] shows the signal processing of the first embodiment in more detail. The control and processing core 9048 includes low-level processing of the instantaneous digital values of the input and output voltages and high-level processing of the digital representations of these voltages, and calculates the results with the control and processing core 11016.

[0059] The low-level processing includes a direct digital synthesizer 11014, a first set 11002 and a second set 11004 of memory buffers for storing samples of the input and output voltages, multipliers for the DFTs 11008 and 11010, a demultiplexer and accumulator 11012 for separating input voltage samples from different voltage channels and accumulating them in the DFT process, an interface for transferring the digital signals S1 and S2 to the DACs 9042, 9046, and an interface for transferring digital signals from the ADC 9038 to the memories 11002 and 11004. To speed up the processing, DMA is used to transfer data from the memory to the DACs 9036 and 9040 and from the ADC 9038 to the memories 11002 and 11004.

[0060] [Figure 12]'s flowchart shows the data processing flow. First, the data from the ADC and the reference data already filled in the previous DMA cycle are processed. These data are used for the DFT. Next, the data for the next DMA cycle are prepared. These data are used for the DAC and the DFT. The reference data are filled with DAC data to save the time of the DFT process. The "SetVoltageChannel()" procedure switches the multiplexer 9030 to the next channel.

[0061] This process is described in terms of implementation on a processor, but it can also be implemented on a microcontroller, DSP, FPGA, ASIC, and other hardware.

[0062] High-Speed Balancing Method For balancing, the first embodiment uses a high-speed balancing method. If the leakage impedance is already known from a previous calibration, the balancing conditions can be calculated with just one measurement of the voltage. However, the known leakage impedance has limited accuracy because there can be some variations in the geometry from the cable to the fixture, and as a result, the capacitance of the cable can change. Also, the leakage impedance depends on the ambient temperature. Therefore, the initial calculation of the DUT impedance without balancing has limited accuracy. It reaches a balance, which is used to calculate the DUT impedance after balancing, and furthermore, a high degree of accuracy can potentially be achieved by applying a leakage correction method. Equations 17 - 34 show a method for calculating the rapid balancing conditions.

[0063] [Equation 17] Current through the range register, Irange=(Vlc - Vrr) / Zrange

[0064] [Equation 18] Current through the leakage impedance, Ileak=-Vlp / Zleak

[0065] [Equation 19] Current through the DUT, Idut = Irange + Ileak

[0066] [Equation 20] Approximate impedance of the DUT, Zdut=(Vhp - Vlp) / Idut

[0067] [Equation 21] Electromotive force (EMF) of the first voltage source, EMF1 = Vhp+Idut*Zout1

[0068] [Equation 22] EMF of the second voltage source, EMF2 = Vrr - Current Range * Zout2

[0069] The balance condition of the first voltage source is the unregulated voltage, and the balance condition of the second voltage source is the regulated voltage (LCR is in the constant voltage mode).

[0070] [Equation 23] Balance condition Vlp = 0

[0071] [Equation 24] New current through the DUT Idut_new = EMF1 / (Zdut + Zout1)

[0072] [Equation 25] New current through the range resistor Irange_new = Idut_new

[0073] [Equation 26] New EMF of the second voltage source EMF2new = Irange_new * (Zwire2 + Zrange + Zout2)

[0074] [Equation 27] Correction coefficient of the EMF of the second voltage source CorrCoeff = EMF2new / EMF2

[0075] [Equation 28] New value of the digital signal of the second voltage source S2new = CorrCoeff * S2

[0076] The balance condition of the second voltage source as the unregulated voltage and the balance condition of the first voltage source as the regulated voltage (LCR is in the constant current mode).

[0077] [Equation 29] Balance condition Vlp = 0

[0078] [Equation 30] New current through the range resistor Irange_new = -EMF2 / (Zwire2 + Zrange + Zou2)

[0079] [Equation 31] New current passing through the DUT, Idut_new = Irange_new

[0080] [Equation 32] New EMF of the first voltage source, EMF1new = Idut_new * (Zdut + Zout1)

[0081] [Equation 33] Correction coefficient of the EMF of the first voltage source, CorrCoeff = EMF1new / EMF1

[0082] [Equation 34] New value of the digital signal of the first voltage source, S1new = CorrCoeff * S1 All values are complex numbers.

[0083] Calculating the correction coefficient (CorrCoeff) as the relationship between the old and new EMFs is an implicit replacement for the explicit calculation of the frequency response of the low-pass filter (LPF). [Figure 7] shows an example of the high-order LPF amplitude and phase frequency response of an LCR meter with a maximum signal frequency of 1 MHz and a sampling frequency of 3 Msps. By calculating the correction coefficient, the need for calibration of the LPF with a very steep slope at high frequencies can be eliminated.

[0084] After setting the balance condition, the control and processing unit needs to wait for the voltage to stabilize and start the measurement under the balance condition. After accurately measuring at the voltage balance condition, equations 17 to 20 are used to repeat the calculation of the parameters of the DUT.

[0085] Advantages of the First Embodiment Compared with any other method, the balancing time is reduced by at least twice. Exclude the transimpedance amplifier and the guard. A single ADC keeps the manufacturing cost low. Channel equalization allows the use of low-cost and high-frequency signals.

[0086] Disadvantages of the First Embodiment The measurement of three-terminal capacitors requires multiple balancing cycles or a special calibration with leakage calibration for each three-terminal capacitor [Figure 2]. This is because there is an input capacitance to ground that is not included in the stored leakage impedance.

[0087] Second Embodiment The second embodiment [Figure 10], unlike the first embodiment, includes additional ADCs 10002, 10004, and 10006 and additional digital signals 10008, 10010, and 10012. It includes four parallel channels for voltage measurement without multiplexing, improving the measurement speed at high frequencies. The second embodiment uses the high-speed balancing method as in the first embodiment and functions similarly.

[0088] The advantages of the second embodiment are that it can simplify low-level processing, improve the signal-to-noise ratio, and increase the measurement speed by excluding direct memory access.

Industrial Applicability

[0089] The present invention can be used in any industry that requires impedance measurement. The present invention can significantly reduce the cost of manufacturing impedance measuring instruments and improve the measurement speed. List of Prior Art Documents

[0090] The list of prior art documents is as follows.

Table 1

Claims

【Claim 1】 A high-speed balancing method for impedance measurement using leakage impedance compensation, a high-current (HC) terminal, a high-potential (HP) terminal, a low-potential (LP) terminal, a low-current (LC) terminal, a fixture for connecting to a device under test (DUT), a reference resistor set having first and second terminals, wherein the first terminal is connected to the LC terminal, the set of reference resistors; a first voltage source including an output connected to the HC terminal, a second voltage source including an output connected to the second terminal of the reference resistor set, a processor including a memory, wherein the processor can measure voltages on the HP terminal, the LP terminal, the LC terminal, the second terminal of the reference resistor set, and the output of the second voltage source, a processor; and providing an LCR meter including; attaching the fixture to the HC, HP, LP, and LC terminals, setting the impedance of the reference resistor set to a first predetermined value, setting the output of the first voltage source to a first predetermined voltage, setting the output of the second voltage source to a second predetermined voltage, measuring a first measured value of the leakage impedance of the fixture and the LCR meter, storing the first measured value in the memory of the processor, setting the impedance of the reference resistor set to a second predetermined value, measuring a second measured value of the series impedance of the fixture, the first voltage source, and the second voltage source, storing the second measured value in the memory of the processor, attaching a DUT to the fixture, Setting the impedance of the reference resistor set to a third predetermined value; Setting the output of the first voltage source to a third predetermined voltage; Setting the output of the second voltage source to a fourth predetermined voltage; Measuring a third measured value of the voltage at the HP terminal, the LP terminal, the LC terminal, and the second terminal of the reference resistor set; Calculating the impedance value of the DUT using the first measured value; Calculating a specific voltage that produces a zero voltage at the LP terminal when applied to the outputs of the first and second voltage sources using the second measured value; Setting the outputs of the first and second voltage sources to the specific voltage; Measuring a fourth measured value of the voltage at the HP terminal, the LP terminal, the LC terminal, and the second terminal of the reference resistor set; A method including calculating the impedance value of the DUT at the zero voltage on the LP terminal using the fourth measured value.

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