Semiconductor Package

Abstract

The semiconductor package according to the embodiment includes an insulating layer including an upper surface and a lower surface, a protective layer disposed on the upper surface of the insulating layer, a connecting member embedded in the insulating layer, and a wiring electrode embedded in the insulating layer. The wiring electrode includes an upper pad portion disposed between the insulating layer and the protective layer. The upper pad portion penetrates a partial region of the insulating layer and is electrically connected to the connecting member. The wiring electrode includes a first via electrode having a width narrower than the width of the upper pad portion, a second via electrode embedded in the insulating layer and disposed closer to the lower surface of the insulating layer than the connecting member, and a bonding portion including a protruding portion disposed on the protective layer and a penetrating portion that penetrates the protective layer through the protruding portion and is in direct contact with the upper pad portion. The bonding portion includes a first bonding portion overlapping the connecting member in a vertical direction and a second bonding portion not overlapping the connecting member vertically. Each of the inclination angles of the penetrating portion of the first bonding portion and the penetrating portion of the second bonding portion with respect to the upper surface of the insulating layer is closer to vertical than the inclination angle of the second via electrode with respect to the upper surface of the insulating layer.

Description

Technical Field

[0001] The embodiments relate to semiconductor packages.

Background Art

[0002] As the performance of electrical / electronic products improves, technologies for arranging more semiconductor elements on a semiconductor package substrate of limited size have been proposed and studied. However, since a general semiconductor package is basically designed to mount one semiconductor element, there are limitations in obtaining the desired performance.

[0003] Accordingly, recently, semiconductor packages have been provided that arrange a large number of semiconductor elements using a plurality of substrates. Such semiconductor packages have a structure in which a plurality of semiconductor elements are connected to each other in the horizontal and / or vertical directions on the substrate. As a result, the semiconductor package efficiently uses the mounting area of the semiconductor elements and has the advantage of being able to transmit high-speed signals through short signal transmission paths between the semiconductor elements.

[0004] In addition, semiconductor packages applied to products providing the Internet of Things (IoT), self-driving vehicles, high-performance servers, etc. tend to increase the number and / or size of each semiconductor element or divide the functional parts of the semiconductor element into semiconductor chiplets (Chiplets) according to the trend of high integration.

[0005] As a result, the mutual communication between semiconductor elements and / or semiconductor chiplets (Chiplets) has become important, and accordingly, there is a tendency to arrange an interposer between the substrate of the semiconductor package and the semiconductor element.

[0006] The interposer can smooth the mutual communication between semiconductor elements and / or semiconductor chiplets (Chiplets), or function as a redistribution layer that gradually increases the width and size of the circuit pattern from the semiconductor element to the semiconductor package in order to interconnect the semiconductor element and the semiconductor package substrate, thereby enabling it to smooth the electrical signals between the semiconductor package substrate having a relatively large circuit pattern compared to the circuit pattern of the semiconductor element and the semiconductor element.

[0007] On the other hand, the package substrate and / or interposer applied to the semiconductor package are provided with a connecting member connected to the semiconductor element and / or semiconductor chiplet (Chiplet). The connecting member functions to horizontally connect between a plurality of semiconductor elements and / or semiconductor chiplets (Chiplets). As a result, the connecting member is embedded in the package substrate and / or interposer. At this time, the package substrate and / or interposer are provided with a plurality of bonding portions connected to the semiconductor element and / or semiconductor chiplet (Chiplet). The bonding portion can include a first bonding portion that does not overlap with the connecting member in the vertical direction and a second bonding portion that overlaps with the connecting member in the vertical direction and overlaps with the first bonding portion in the horizontal direction.

[0008] At this time, the first bonding portion and the second bonding portion can have different widths along the horizontal direction and / or different thicknesses along the vertical direction. That is, the width and / or thickness of the second bonding portion may depend on the width of the pad provided on the connecting member and the height of the upper surface of the pad, but the width and height of the first bonding portion do not depend on the width and / or height of the pad provided on the connecting member. That is, when the integration degree of the I / O (Input and Output) terminals of the connecting member increases, a difference occurs in the amount of current generated during the plating of the first and second bonding portions due to the diameter and density of the through holes of the insulating layer and / or protective layer disposed on the pad of the connecting member, and thereby the height of the second bonding portion becomes different from the height of the first bonding portion.

[0009] Therefore, the height deviation may occur in the first bonding portion and the second bonding portion according to the prior art due to the difference in width and / or thickness between them. Further, when the height deviation occurs in the first bonding portion and the second bonding portion, a problem may occur in that the semiconductor element and / or the semiconductor chiplet cannot be stably mounted on the first bonding portion and the second bonding portion. As a result, problems such as a decrease in the operating characteristics, reliability, and yield of the semiconductor element and / or the semiconductor chiplet may occur.

[0010] In addition, as the number of pads of the connecting member and the number of terminals of the semiconductor element increase, a fine pitch between two adjacent bonding portions among the first bonding portions connected thereto is required. However, according to the prior art, the pitch between two adjacent bonding portions exceeds 60 μm at a minimum. That is, the circuit board includes an electrode portion connected to the pad of the connecting member through the insulating layer and a bonding portion disposed between the terminal of the semiconductor element and the electrode portion through the protective layer. At this time, the electrode portion includes a via electrode penetrating the insulating layer and a pad electrode disposed on the via electrode. In addition, the bonding portion includes a penetrating portion penetrating the protective layer and a protruding portion disposed on the penetrating portion. At this time, the pitch between two adjacent bonding portions is determined by the width / spacing of the via electrode, the width / spacing of the pad electrode, the width / spacing of the penetrating portion, and the width / spacing of the protruding portion. At this time, conventionally, there is a limit to reducing the width of the via electrode and the penetrating portion, and thus the pitch between two adjacent bonding portions exceeds 60 μm. As a result, there is a limit to improving the circuit integration degree and miniaturizing the semiconductor package. SUMMARY OF THE INVENTION PROBLEMS TO BE SOLVED BY THE INVENTION

[0011] An embodiment provides a semiconductor package having a new structure.

[0012] Further, the embodiment provides a semiconductor package capable of controlling the height deviation between a plurality of bump portions connected to a semiconductor element.

[0013] Also, the embodiment provides a semiconductor package capable of miniaturizing the pitch between a plurality of bumps.

[0014] The technical problems to be solved by the proposed embodiments are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those having ordinary knowledge in the technical field to which the embodiments belong from the following description.

Means for Solving the Problems

[0015] The semiconductor package according to the embodiment includes an insulating layer including an upper surface and a lower surface, a protective layer disposed on the upper surface of the insulating layer, a connecting member embedded in the insulating layer, and a wiring electrode embedded in the insulating layer. The wiring electrode includes an upper pad portion disposed between the insulating layer and the protective layer. The upper pad portion penetrates a partial region of the insulating layer and is electrically connected to the connecting member. The semiconductor package further includes a first via electrode having a width narrower than the width of the upper pad portion, a second via electrode embedded in the insulating layer and disposed closer to the lower surface of the insulating layer than the connecting member, and a bonding portion including a protruding portion disposed on the protective layer and a penetrating portion that penetrates the protective layer through the protruding portion and is in direct contact with the upper pad portion. The bonding portion includes a first bonding portion overlapping the connecting member in a vertical direction and a second bonding portion not overlapping the connecting member vertically. The inclination angles of the penetrating portions of the first bonding portion and the second bonding portion with respect to the upper surface of the insulating layer are closer to vertical than the inclination angle of the second via electrode with respect to the upper surface of the insulating layer.

[0016] Also, a plurality of the first bonding portions are provided, and the horizontal isolation distance between two adjacent first bonding portions among the plurality of first bonding portions is 26 μm or less.

[0017] Further, each of the plurality of first bonding portions includes a plurality of first protrusions, and the horizontal width of each of the plurality of first protrusions is 29 μm to 34 μm.

[0018] Further, the protective layer includes a plurality of first fillers, and the through portion of the first bonding portion does not contact the plurality of first fillers.

[0019] Further, the first via electrode includes a first overlapping via electrode that overlaps the connecting member in the vertical direction, and the inclination angle of the first overlapping via electrode is the same as the inclination angle of the through portion of the first bonding portion.

[0020] Further, the insulating layer includes a plurality of laminated insulating layers disposed between the upper surface and the lower surface of the insulating layer. The plurality of laminated insulating layers include an upper insulating layer that forms the upper surface of the insulating layer and a lower insulating layer that forms the lower surface of the insulating layer. The wiring layer further includes a plurality of wiring electrodes respectively disposed in the plurality of laminated insulating layers, a plurality of via electrodes connecting the plurality of wiring electrodes, and a lower pad portion disposed on the lower surface of the insulating layer. The plurality of via electrodes further include a plurality of upper vias that overlap the connecting member in the horizontal direction and a plurality of lower vias disposed between the plurality of upper vias and the lower surface of the insulating layer. The inclination angle of the upper via is symmetric to the inclination angle of the lower via.

[0021] Further, the thickness of the upper insulating layer is thinner than the thickness of the lower insulating layer.

[0022] Further, the first through portion of the first bonding portion vertically overlaps at least a partial region of the first overlapping via electrode.

[0023] Further, the insulating layer includes a side surface located between the upper surface and the lower surface. The protective layer includes a lower surface facing the upper surface of the insulating layer, an upper surface corresponding to the lower surface, and a side surface located between the lower surface and the upper surface. The side surface of the protective layer includes an inner surface surrounding the first through portion and the second through portion respectively and an outer surface adjacent to the side surface of the insulating layer. The vertical length of the inner surface is different from the vertical length of the outer surface.

[0024] Also, the length of the inner surface in the vertical direction is greater than the length of the outer surface in the vertical direction.

Advantages of the Invention

[0025] The embodiment includes a protective layer and a bonding portion that penetrates a partial region from the upper surface of the protective layer. At this time, the protective layer is provided with a through hole corresponding to the bonding portion. The through hole of the protective layer is formed by a dry film pattern. That is, the through hole is formed to correspond to the width and pitch that the bonding portion provided in the semiconductor package should have. That is, the embodiment forms a dry film pattern in advance considering the width and pitch of the bonding portion. Thereby, the embodiment can minimize the pitch between a plurality of bonding portions. For example, the embodiment can be arranged such that the horizontal distance between the centers of two adjacent bonding portions is 40 μm or less. The embodiment can miniaturize the pitch of the bonding portion to 40 μm or less, whereby the embodiment can improve the circuit integration degree and miniaturize the circuit board and the semiconductor package. Also, the embodiment can reduce the distance between a plurality of bonding portions, thereby minimizing the transmission distance of the signal transmitted through the bump portion. Therefore, the embodiment can minimize the signal transmission loss increased by the signal transmission distance, thereby improving the electrical characteristics of the circuit board and the semiconductor package. Also, the embodiment can enable the semiconductor element arranged on the circuit board to operate stably, thereby enabling the electronic product such as a server to which the semiconductor package is applied to operate stably.

[0026] In addition, the embodiment includes an electrode portion disposed between the connecting member and the bonding portion. The electrode portion penetrates at least a partial region of the insulating layer. At this time, the insulating layer includes a through hole corresponding to the via electrode of the electrode portion. Further, the through hole of the insulating layer is provided by a dry film formed according to the width and pitch that the bonding portion of the embodiment should have. Thereby, the embodiment can form the electrode portion so as to correspond to the width and pitch that the bonding portion should have. Therefore, the embodiment can make the bonding portion have the target width and pitch. Further, the embodiment can form the electrode portion at a position corresponding to the bonding portion, thereby improving the positional alignment between the bonding portion and the electrode portion, and thus improving the electrical characteristics of the bonding portion and the electrode portion.

[0027] In addition, the embodiment can minimize the height deviation between a plurality of bonding portions. That is, the embodiment includes a first bonding portion overlapping the connecting member in the vertical direction and a second bonding portion not overlapping the connecting member in the vertical direction. At this time, the size of the first through portion of the first bonding portion is the same as the size of the second through portion of the second bonding portion. That is, the embodiment can use the dry film pattern to make the through portions of the first bonding portion and the second bonding portion have the same size as each other, thereby minimizing the height deviation between the first bonding portion and the second bonding portion caused by the size difference.

[0028] Therefore, the embodiment can minimize the height deviation between the first bonding portion and the second bonding portion, thereby enabling the semiconductor element to be stably disposed on the first bonding portion and the second bonding portion. Therefore, the embodiment can improve the reliability of the first and second semiconductor elements. Further, the embodiment can make the operations of the first and second semiconductor elements be performed smoothly, thereby enabling the operations of electronic products and servers to be performed smoothly.

[0029] In addition, in the embodiment, the first bonding portion and the second bonding portion have the same height, so that impedance changes and signal transmission loss problems caused by thickness changes of the first bonding portion and the second bonding portion, and problems caused by the semiconductor element being arranged in an inclined state can be prevented, and the electrical reliability can be further improved thereby.

[0030] In addition, in the embodiment, the surface roughness of the interface between each through-hole of the first bonding portion and the second bonding portion and the protective layer can be relatively reduced. Therefore, in the embodiment, the surface roughness of the through-hole can be reduced, and thereby the signal transmission loss that increases in proportion to the surface roughness can be minimized. Therefore, in the embodiment, the operating characteristics of the semiconductor element can be further improved.

[0031] On the other hand, the upper surface of the protective layer of the embodiment can include concave portions and convex portions that increase the surface area of the upper surface of the protective layer by a process of reducing the thickness. The concave portions and the convex portions can function to improve the reliability of the circuit board from heat cycles such as expansion and contraction of the circuit board due to heat generated during the operation of the semiconductor chip or other externally applied heat. Exemplarily, since the convex portions and the concave portions have different thicknesses, the volumes deformed during thermal expansion are different. That is, the thickness of the concave portion can be thinner than the thickness of the convex portion, and the overall thermal deformation of the semiconductor package can be suppressed by the difference between the thermal expansion rate of the convex portion and the thermal expansion rate of the concave portion. Therefore, in the embodiment, it is possible to prevent the semiconductor element coupled to the upper part of the semiconductor package from being electrically separated during thermal expansion, and thereby improve the product reliability.

[0032] In addition, the via electrodes located above the connecting member in the embodiment have different widths and / or inclination directions from the via electrodes located below the connecting member. That is, the via electrodes located above the connecting member have a more vertical side surface than the via electrodes located below the connecting member. That is, by arranging the via electrodes having a vertical side surface above the connecting member, it is possible to have the effect of improving the warping of the circuit board. When the via electrodes having a vertical side surface have a finer pattern than the via electrodes having an inclined side surface, the stress applied to the via electrodes can be relaxed, and the via electrodes having a vertical side surface can be embodied to be located above the connecting member so as to improve the electrical connection reliability between the semiconductor chip and the circuit board.

[0033] In addition, the upper surface of the protective layer in the embodiment is adjacent to the through hole and includes a first region including the through hole and a second region excluding the first region. The height of the first region of the protective layer is greater than the height of the second region. The first region of the protective layer includes a convex portion bulging in the upper direction. Specifically, the upper surface of the protective layer is connected to the inner surface of the through hole and includes a convex portion bulging in the upper direction. The convex portion can improve the process characteristics in the process of arranging a connection portion such as solder in the through hole of the protective layer. Specifically, the convex portion can function as a barrier that does not increase the overall thickness of the protective layer and prevents the diffusion of the connection portion. Thereby, the embodiment can prevent the diffusion of the connection portion arranged in the through hole, and thereby it is possible to miniaturize the width and pitch of the connection portion. In addition, the embodiment can solve the short circuit problem of connecting to adjacent pads due to the diffusion of the connection portion. Thereby, the physical and electrical reliability of the circuit board and the semiconductor package can be improved.

[0034] In addition, the convex portion of the protective layer in the embodiment can be located adjacent to the through hole and have a closed loop shape surrounding the periphery of the through hole. Thereby, the embodiment can more efficiently prevent the diffusion of the connection portion arranged in the through hole, and thereby improve the product reliability.

[0035] In addition, in the embodiment, by using the convex portion, the distance between the upper surface of the connection portion and the upper surface of the protective layer can be maintained to be the same as that of the POR, and a connection portion having a width corresponding to the width of the open region of the protective layer can be formed. Thereby, the embodiment can reduce the defect rate of solder bridges that may occur during the solder joint process.

[0036] In addition, in the embodiment, the photoinitiator provided in the protective layer can be removed. At this time, the photoinitiator acts as a factor that degrades the physical and electrical characteristics of the semiconductor package. At this time, in the embodiment, since the protective layer does not contain a photoinitiator, the physical and electrical characteristics of the circuit board can be improved. In addition, in the embodiment, since the protective layer does not contain a photoinitiator, the types of insulating layers that can be used as the protective layer can be expanded, and thus the cost required for the development of the protective layer can be reduced. In addition, in the embodiment, the tolerance between the center of the through hole of the protective layer and the center of the pad can be significantly reduced compared to the comparative example. Thereby, the embodiment can improve the mountability of the semiconductor element, and thereby improve the physical reliability and electrical reliability of the circuit board and the semiconductor package.

Brief Description of Drawings

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Mode for Carrying Out the Invention

[0069] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0070] However, the technical idea of the present invention is not limited to some of the described embodiments, and can be embodied in various different forms. As long as it is within the scope of the technical idea of the present invention, one or more of the components can be selectively combined and replaced among the embodiments for use.

[0071] Also, the terms (including technical and scientific terms) used in the embodiments of the present invention are construed to have a meaning generally understood by those having ordinary knowledge in the technical field to which the present invention pertains, unless specifically defined and described. Terms generally used like those defined in a dictionary can be construed in light of the meaning in the context of the relevant technology. Also, the terms used in the embodiments of the present invention are for explaining the embodiments and are not intended to limit the present invention.

[0072] In this specification, the singular form can include the plural form as well, unless otherwise specifically mentioned in the text. When described as "at least one (or one or more) of A and B, C", it can include one or more of all the combinations that can be combined with A, B, and C. Also, in the description of the components of the embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. can be used.

[0073] Such terms are used to distinguish their components from other components, and do not limit the essence or order of such components by the terms. When a component is referred to as being "coupled" or "connected" to another component, it should be understood that it is not only directly "coupled" or "connected" to the other component, but other components may exist therebetween. On the contrary, when a component is referred to as being "directly coupled" or "directly connected" to another component, it should be understood that no other component exists therebetween.

[0074] The terms used in this application are merely used to describe specific embodiments and are not intended to limit the present invention. Singular expressions include plural expressions unless clearly limited in context. In this application, terms such as "comprising" or "having" are intended to specify the presence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, and are not to be construed as precluding the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0075] Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the technical field to which the present invention belongs. Terms defined as in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning in the context of the related art, and should not be interpreted in an idealized or overly formal sense unless clearly defined in this application.

[0076] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Components that are the same or corresponding regardless of the reference numerals will be given the same reference numerals, and redundant descriptions thereof will be omitted.

[0077] Before describing the embodiments, a brief description will be given of the electronic device to which the semiconductor package of the embodiments is applied. The electronic device includes a main board (not shown). The main board is physically and / or electrically connected to various components. For example, the main board is connected to the semiconductor package of the embodiment. Also, the semiconductor package includes a circuit board, a semiconductor chip, a bonding portion for electrically connecting the semiconductor chip and the circuit board, a resin portion for filling the space between the semiconductor chip and the circuit board, and a molding portion for entirely covering the semiconductor chip. Here, various semiconductor chips are mounted on the semiconductor package.

[0078] The semiconductor chip can include active elements and / or passive elements. The active element may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions or more elements are integrated in one chip. The semiconductor chip may be a logic chip, a memory chip, etc. The logic chip may be a central processor (CPU), a graphics processor (GPU), etc. For example, the logic chip is an application processor (AP) semiconductor chip including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, or an analog-digital converter, an ASIC (application-specific IC), etc., or a chipset including a specific combination of the above.

[0079] The memory chip may be a stacked memory such as HBM. Also, the memory chip can include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, etc.

[0080] On the one hand, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0081] In addition, the electronic device may be a smart phone, PDA (personal digital assistant), digital video camera, digital still camera, vehicle, high-performance server, network system, computer, monitor, tablet, laptop, netbook, television, video game, smart watch, Automotive, etc. However, it is not limited thereto, and of course, it may be any other electronic device that processes data other than these.

[0082] FIG. 1a is a drawing showing a configuration diagram of a circuit board according to an embodiment, FIG. 1b is a drawing showing a plan view of a bonding portion shown in FIG. 1a, FIG. 1c is an enlarged view of a region R1 of FIG. 1a, FIG. 1d is a cross-sectional view for explaining the surface roughness of the first protective layer of FIG. 1c, FIGS. 2a and 2b are cross-sectional views for explaining a bonding portion according to the prior art, and FIG. 3 is an enlarged view of a modified example of FIG. 1c. Hereinafter, with reference to FIGS. 1a to 3, the semiconductor package of the embodiment will be described.

[0083] Referring to FIG. 1a, a semiconductor package according to an embodiment includes a circuit board 100 that electrically connects a main board of an electronic device and semiconductor chips 320 and 330, a plurality of semiconductor chips 320 and 330 mounted on the circuit board 100, and a connection portion 310 that electrically connects the plurality of semiconductor chips 320 and 3030 to the circuit board 100.

[0084] For ease of explanation of the embodiment, terms referring to the components included in the semiconductor package are described, and the description of each of the referred components will be described later.

[0085] The circuit board 100 illustrated in FIG. 1a includes an insulating layer 110, an electrode portion 140, protective layers 120 and 130, and a connection member 200. Exemplarily, the insulating layer 110 is provided with a structure in which first to fifth insulating layers 110b2, 110b1, 110a, 110c1, and 110c2 are sequentially stacked. The upper surface of the first insulating layer 110b2 is provided on the upper surface of the insulating layer 110, and the lower surface of the fifth insulating layer 110c2 is provided on the upper surface of the insulating layer 110. At this time, the first insulating layer 110b2 and the second insulating layer 110b1 can be referred to as upper insulating layers, and the fourth insulating layer 110c1 and the fifth insulating layer 110c2 can be referred to as lower insulating layers.

[0086] A first protective layer 120 is provided on the upper surface of the insulating layer 110, and a second protective layer 130 is provided on the lower surface of the insulating layer 110.

[0087] The electrode portion 140 includes a wiring electrode 140a, a via electrode 140b, and a bonding portion 150.

[0088] The wiring electrode 140a includes a first wiring electrode 140a1 disposed on the upper surface of the first insulating layer 110b2, a second wiring electrode 140a2 disposed on the upper surface of the second insulating layer 110b1, a third - 1 wiring electrode 140a3 disposed on the upper surface of the third insulating layer 110a, a third - 2 wiring electrode 140a4 disposed on the lower surface of the third insulating layer 110a, a fourth wiring electrode 140a5 disposed on the lower surface of the fourth insulating layer 110c1, and a fifth wiring electrode 140a6 disposed on the lower surface of the fifth insulating layer 110c2. The via electrode 140b includes a first via electrode 140b1 connecting the first wiring electrode 140a1 and the second wiring electrode 140a2, a second via electrode 140b2 connecting the second wiring electrode 140a2 and the third - 1 wiring electrode 140a3, a third via electrode 140b3 connecting the third - 1 wiring electrode 140a3 and the third - 2 wiring electrode 140a4, a fourth via electrode 140b4 connecting the third - 2 wiring electrode 140a4 and the fourth wiring electrode 140a5, and a fifth via electrode 140b5 connecting the fourth wiring electrode 140a5 and the fifth wiring electrode 140a6.

[0089] Also, each wiring electrode 140a includes a pad and / or a trace. The trace functions to transmit signals and / or power to the semiconductor element and can be referred to as a circuit pattern. The pad functions as a connection part for electrically connecting the semiconductor element and the trace or for connecting the traces disposed on each insulating layer. When the width of the trace is made sufficiently large to directly connect the semiconductor element to the trace, the pad becomes unnecessary. However, if the width of the trace is too large, there are problems such as an increase in impedance and an inability to increase the integration degree of the traces on the limited circuit board area. Therefore, generally, although the pad has the same function of electrical conduction as the trace, it is provided with a wider width than the trace in order to be arranged to further have the function of being able to contact the through - electrode or the semiconductor element. Also, FIG. 1a illustrates the pads of each wiring electrode 140a.

[0090] Exemplarily, the first wiring electrode 140a1 includes a first pad for connecting to the first via electrode 140b1 and / or the bonding portion 150. The second wiring electrode 140a2 includes a second pad connected to the first via electrode 140b1 and / or the second via electrode 140b2. The third - 1 wiring electrode 140a3 includes a third - 1 pad connected to the second via electrode 140b2 and / or the third via electrode 140b3 and a third - 2 pad 140a31 connected to the connecting member 200. The third - 2 wiring electrode 140a4 includes a third - 2 pad connected to the third via electrode 140b3 and / or the fourth via electrode 140b4. The fourth wiring electrode 140a5 includes a fourth pad connected to the fourth via electrode 140b4 and / or the fifth via electrode 140b5. The fifth wiring electrode 140a6 includes a fifth pad connected to the fifth via electrode 140b5 and / or the main board of the electronic device.

[0091] Also, the circuit board 100 includes a bonding portion 150 disposed on the first protective layer 120. The bonding portion 150 includes protruding portions 151b, 152b disposed on the first protective layer 120 and through - portions 151a, 152a penetrating through the first protective layer 120 and connected to the pads of the first wiring electrode 140a1. The connecting member 200 is embedded in the insulating layer 110. According to an embodiment, the connecting member 200 is disposed between the first insulating layer 110b1 and the second insulating layer 110b2, but the embedding position is not limited thereto and may be embedded in other insulating layers other than the first insulating layer 110b1 and the second insulating layer 110b2.

[0092] The stacked first to fifth insulating layers 110b2, 110b1, 110a, 110c1, and 110c2 may be made of an insulating material having functions such as ease of processing, excellent insulating properties, reducing the loss of signals transmitted through the electrode portion 140, and enabling the formation of fine intervals of the electrode portion 140. Also, they may all be made of the same insulating material, but are not limited thereto, and at least one or more layers may be made of an insulating material different from other insulating layers. Exemplarily, ABF (Ajinomoto Build-up Film) manufactured by Ajinomoto Co., Inc. can be used, and FR-4, BT (Bismaleimide Triazine), PID (Photo Image-able Dielectric resin), etc. can be used.

[0093] Exemplarily, the third insulating layer 110a may include a reinforcing member including at least one of glass fiber and GCP (Glass Core Primer). The reinforcing member can function to prevent the circuit board 100 and / or the semiconductor package from warping in a specific direction by improving the rigidity of the insulating layer. When the insulating layer 110 warps in a specific direction during the process of the circuit board 100, the positioning accuracy decreases during the process of arranging the electrode portion 140, but by improving the rigidity of the circuit board 100, such problems can be solved. Also, when semiconductor chips 320 and 330 are mounted on the circuit board 100, it is possible to prevent problems such as electrical short circuits and open circuits of the semiconductor chips 320 and 330 due to the warping of the circuit board 100. Furthermore, since the warping problem due to the heat cycle generated during the operation of the semiconductor package can also be prevented, products such as servers to which the semiconductor package of the embodiment is applied can operate stably, and the overall reliability of the product can be improved.

[0094] According to FIG. 1a, an insulating member 110d is provided in the third insulating layer 110a including a reinforcing member. The insulating member 110d penetrates the third insulating layer 110a including the reinforcing member. The insulating member 110d may be provided with hole plugging ink, but is not limited thereto. The insulating member 110d is provided surrounded by a third via electrode 142b3 penetrating the third insulating layer 110a. When the third insulating layer 110a is thick, a problem may occur that the third via electrode 142b3 penetrating the third insulating layer 110a does not densely fill the through holes of the third insulating layer 110a. Such a problem induces a problem that each pad of the third-1 wiring electrode 140a3 and / or the third-2 wiring electrode 140a4 is not plated flatly, or voids are generated inside the third via electrode 142b3. Therefore, the arrangement of the insulating member 110d can solve the electrical reliability problem and / or mechanical reliability problem that may occur due to the through holes of the third insulating layer 103a not being filled entirely. Exemplarily, the third insulating layer 110a can have a thickness in the range of 0.4T to 1.5T to ensure ease of process and rigidity.

[0095] Exemplarily, at least one of the first insulating layer 110b2, the second insulating layer 110b1, the fourth insulating layer 110c1, and the fifth insulating layer 110c2 can contain a filler composed of an inorganic substance. This filler differs in size and / or shape from the reinforcing member contained in the third insulating layer 110a. The diameter and content of the filler can be adjusted in consideration of the respective coefficients of thermal expansion rate, rigidity, etc. of the first insulating layer 110b2, the second insulating layer 110b1, the fourth insulating layer 110c1, and the fifth insulating layer 110c2 to solve problems such as light scattering during the laser process for densely arranging the electrode portion 140. Exemplarily, to solve the above-described problems, a filler diameter of 0.1 μm to 5.0 μm and a filler content of 30 wt% to 40 wt% or 78 wt% to 85 wt% can be applied, but it is not limited thereto. Also, without being limited thereto, the first insulating layer 110b2, the second insulating layer 110b1, the fourth insulating layer 110c1, and the fifth insulating layer 110c2 can contain a reinforcing member containing at least one or more of glass fiber and GCP (Glass Core Primer).

[0096] The circuit board 100 includes a first protective layer 120 disposed on the upper surface of the first insulating layer 110b2 and a second protective layer 130 disposed on the lower surface of the fifth insulating layer 110c2 to protect its surface. The first and second protective layers 120 and 130 can function to protect the pads from external moisture and contaminants, and during the bonding between the semiconductor chip and the circuit board 100 and / or between the main board and the circuit board 100, to prevent short - circuit problems between connection parts 310 such as solder and wires. Exemplarily, the first and second protective layers 120 and 130 are provided with a photosensitive material and / or a solder resist. Also, a photosensitive solder resist can be applied exemplarily. According to this embodiment, a plurality of terminals for connecting the semiconductor chips 320, 330 and / or the main board of the electronic device etc. are arranged at a high density. When the bonding part 150 between the plurality of terminals and the circuit board 100 is bonded, solder can be used. When using solder, a solder short - circuit problem between terminals with a high density may occur. To solve such a short - circuit problem, by arranging a solder resist with poor wettability with solder, the diffusion and movement of solder can be prevented, and the solder short - circuit problem between terminals can be prevented. The first protective layer 120 and the second protective layer 130 may be arranged with different thicknesses in consideration of the warping of the circuit board 100 and the coefficient of thermal expansion rate. Although it varies depending on the area and thickness of the circuit board 100, according to this embodiment, the thickness of the first protective layer 120 can have a portion thicker than the thickness of the second protective layer 130. Here, the portion means at least one region of the upper surface of the first protective layer 120, which can mean that the thickness of the first protective layer 120 is not necessarily arranged uniformly, or it can mean that the thickness of the first protective layer 120 is arranged uniformly and is thicker than the second protective layer 130.

[0097] The traces of the first to fifth wiring electrodes 140a1, 140a2, 140a3, 140a4, 140a5, 140a6 can be designed in various forms considering impedance and the warpage of the circuit board 100 for signal and power transmission between the semiconductor chips 320, 330 and the main board of the electronic device. The traces of the first to fifth wiring electrodes 140a1, 140a2, 140a3, 140a4, 140a5, 140a6 can be arranged with a high density considering signals and impedance, and the width and spacing can be designed and arranged within 2 μm to 10 μm respectively to ensure the adhesion force with each insulating layer 110 and prevent the problem of peeling. That is, the traces of the first to fifth wiring electrodes 140a1, 140a2, 140a3, 140a4, 140a5, 140a6 can be arranged to have various widths and spacings, from a design with a width of 2 μm and a spacing of 2 μm to a design with a width of 10 μm and a spacing of 10 μm.

[0098] At this time, in order to arrange the first to fifth via electrodes 140b1, 140b2, 140b3, 140b4, 140b5 for vertically connecting the first to fifth wiring electrodes 140a1, 140a2, 140a3, 140a4, 140a5, 140a6 respectively, since the widths and intervals of the above-described first to fifth wiring electrodes 140b1, 140b2, 140b3, 140b4, 140b5 are very fine, to ensure the positional alignment of the first to fifth via electrodes 140b1, 140b2, 140b3, 140b4, 140b5 or to form the first to fifth via electrodes 140b1, 140b2, 140b3, 140b4, 140b5, the widths of the above-described wiring electrodes 140a1, 140a2, 140a3, 140a4, 140a5, 140a6 are too narrow. Here, "vertical" means the direction in which the first to fifth insulating layers 110b2, 110b1, 110a, 110c1, 110c2 are laminated, and "vertical" and "vertical direction" can be used with the same meaning. Also, the same definition applies to the vertical relationship of the components described later. Therefore, in order to ensure the positional alignment of the first to fifth via electrodes 140b1, 140b2, 140b3, 140b4, 140b5 and arrange the first to fifth via electrodes 140b1, 140b2, 140b3, 140b4, 140b5, each of the first to fifth wiring electrodes 140a1, 140a2, 140a3, 140a4, 140a5, 140a6 includes the first to fifth pads respectively. Each pad of the first to fifth wiring electrodes 140a1, 140a2, 140a3, 140a4, 140a5, 140a6 has a width wider than the width of the respective traces of the above-described first to fifth wiring electrodes 140a1, 140a2, 140a3, 140a4, 140a5, 140a6 in order to be connected to the first to fifth via electrodes 140b1, 140b2, 140b3, 140b4, 140b5. Exemplarily, each pad of the first to fifth wiring electrodes 140a1, 140a2, 140a3, 140a4, 140a5, 140a6 can have a circular structure, and its diameter can be within 30 μm to 100 μm.However, without being limited thereto, due to the technical limitations of the process for arranging the first to fifth via electrodes 140b1, 140b2, 140b3, 140b4, and 140b5, each pad of the first to fifth wiring electrodes 140a1, 140a2, 140a3, 140a4, 140a5, and 140a6 can have the same width as the width of each trace of the first to fifth wiring electrodes 140a1, 140a2, 140a3, 140a4, 140a5, and 140a6.

[0099] Exemplarily, in order to arrange the first via electrode 140b1, a through hole is processed by a laser in a partial region of the first insulating layer 110b2. At this time, the through hole has a size corresponding to the size of the laser beam. Thereafter, by arranging the pad and the trace of the first via electrode 140b1 and the first wiring electrode 140a1 integrally, productivity and yield can be improved. Therefore, the first via electrode 140b1 can have a lower surface located on the same plane as the upper surface of the pad of the second wiring electrode 140a2. That is, exemplarily, the first via electrode 140b1 can be referred to as a protruding portion in which a part of the pad of the first wiring electrode 140a1 protrudes toward the pad of the second wiring electrode 140a2. Here, it should be understood that the upper surface of the pad of the second wiring electrode 140a2 does not necessarily mean a flat surface, but includes a concave surface or a convex surface presented by various processes.

[0100] Exemplarily, the upper surface of the second wiring electrode 140a2 that contacts the lower surface of the first via electrode 140b1 has a recessed concave surface. In the process of forming the first via electrode 140b1, when the pad of the second wiring electrode 140a2 is exposed to the atmosphere, the surface of the pad of the second wiring electrode 140a2 may be oxidized, or the adhesive force for the surface of the pad of the second wiring electrode 140a2 to contact the first via electrode 140b1 may decrease due to a chemical reaction between the first insulating layer 110b2 and the pad of the second wiring electrode 140a2, or the impedance may increase. Therefore, before arranging the first via electrode 140b1, by removing a part of the surface of the pad of the second wiring electrode 140a2 exposed in the through hole of the first insulating layer 110b2 and then arranging the first via electrode 140b1, problems such as cracks, peeling, and an increase in impedance between the first via electrode 140b1 and the pad of the second wiring electrode 140a2 can be prevented. Also, since the first via electrode 140b1 is arranged integrally with the first wiring electrode 140a1, it can be said that it is located on the same plane as the lower surface of the pad of the first wiring electrode 140a1. Since the first via electrode 140b1 has a width smaller than the width of the pad of the first wiring electrode 140a1, in order to distinguish it from the pad of the first wiring electrode 140a1, the first via electrode 140b1 can be referred to as described above. The second to fifth via electrodes 140b2, 140b3, 140b4, 140b5 can also be referred to in the same way as the above-described first via electrode 140b1.

[0101] The connecting member 200 functions to electrically connect a plurality of semiconductor chips 320, 330 to each other. In FIG. 1a, the semiconductor chips 320, 330 are exemplarily shown as two chips, but are not limited thereto, and more semiconductor chips may be mounted. Also, although the connecting member 200 is similarly shown as connecting two chips to each other electrically, it is not limited thereto, and more semiconductor chips can be connected. Here, the semiconductor chips 320, 330 may be logic chips such as memories, processors, GPUs, etc., or may be chiplets due to a functional division of each logic chip.

[0102] According to FIG. 1a, the connecting member 200 includes a plurality of pads 210 and is embedded and disposed in the circuit board 100. The plurality of pads 210 of the connecting member 200 are electrically connected to the electrode portion 140 of the circuit board 100. The electrode portion 140 of the circuit board 100 connected to the plurality of pads 210 of the connecting member 200 is electrically connected to the terminals 325 and 335 of the semiconductor chips 320 and 330 via the bonding portion 150, thereby performing a communication function between the semiconductor chips 320 and 330.

[0103] In FIG. 1a, the connecting member 200 is illustrated as being embedded and disposed in the circuit board 100, but is not limited thereto, and may be disposed so as not to be embedded on the circuit board 100. That is, the connecting member 200 can be embedded in the circuit board 100 for thinning the circuit board 100. However, in order to solve problems such as height deviation between the bonding portions 150 of the circuit board 100 and errors in the process of disposing the connecting member 200 at a fixed position during embedding, the connecting member 200 can be disposed so as not to be embedded on the circuit board 100. In this case, although not shown, a molding member (not shown) is disposed on the circuit board 100, and the connecting member 200 is embedded in the molding member. The molding member (not shown) is made of a resin such as EMC (Epoxy Molding Compound). In such a case, the connecting member 200 is electrically connected to the semiconductor chips 320 and 330 via electrodes passing through the molding member.

[0104] The connecting member 200 is made of at least one of silicon, organic matter, and glass, and is disposed on the circuit board 100, and can function as an interposer. When the connecting member 200 functions as an interposer, by having a smaller interval than the interval of the electrode portions 140 of the circuit board 100, a finer pattern than the circuit board 100 is provided, and a pattern buffer function can be achieved between the patterns of the semiconductor chips 320 and 330 and the pattern of the circuit board 100. Here, the pattern can refer not only to the shapes of wirings and terminals for electrical connection such as the electrode portions 140 of the circuit board 100, the terminals 325 and 335 of the semiconductor chips 320 and 330, and the pads 210 of the connecting member 200, but also to the size, width, and interval. Also, in FIG. 1a, the connecting member 200 is disposed so as to have a width smaller than the sum of the horizontal widths of the semiconductor chips 320 and 330, but is not limited thereto, and can have a wide width so that the semiconductor chips 320 and 330 can all be disposed on the connecting member 200. When the connecting member 200 is made of silicon and has a wide width capable of disposing all of the semiconductor chips 320 and 330, the connecting member 200 can be referred to as a silicon interposer.

[0105] According to FIG. 1c, which is an enlarged view of a region in FIG. 1a, a bonding portion 150 is disposed on the first protective layer 120. The bonding portion 150 includes protruding portions 151b and 152b disposed on the first protective layer 120 and through portions 151a and 152a that are in direct contact with pads 141a and 142a of the first wiring electrode 140a1 disposed on the first insulating layer 110b2 of the circuit board 100 through the first protective layer 120. The bonding portion 150 includes the protruding portions 151b and 152b disposed on the first protective layer 120 to reduce the volume of solder by using thermal compression bonding and to prevent an electrical short circuit between two adjacent bonding portions 150. Also, the bonding portion 150 includes the through portions 151a and 152a that are in direct contact with the pads 141a and 142a of the first wiring electrode 140a1 on the first insulating layer 110b2 to connect the above-described protruding portions 151b and 152b to the circuit board 100.

[0106] At this time, since the pads 141a and 142a of the first wiring electrode 140a1 on the first insulating layer 110b2 have a fine pattern interval, there is also a method of forming the first via electrode 140b1 that penetrates a partial region of the first insulating layer 110b2 and then performing a polishing process. However, when the polishing process is performed, there are problems such as a decrease in yield due to warping and wrinkles of the circuit board 100, and in particular, there is a problem that it is difficult to ensure the positional accuracy during the process of connecting the through portions 151a and 152a of the bonding portion 150 to the circuit board 100. Therefore, in the present invention, the technical idea and means according to the embodiments are described within a range where the polishing process is not performed.

[0107] Referring to FIG. 1a, the bonding portion 150 can include a first bonding portion 151 that vertically overlaps the connecting member 200 and a second bonding portion 152 that does not vertically overlap. Since the connecting member 200 has an electrode pattern finer than the electrode portion 140 of the circuit board 100 as described above, the first bonding portion 151 has an electrode pattern finer than the second bonding portion 152. Specifically, among the bonding portions 150, the first bonding portion 151 located between the connecting member 200 and the semiconductor chips 320 and 330 has an electrode pattern finer than the second bonding portion 152. Exemplarily, referring to FIG. 1a, the bonding portion 150 includes a first bonding portion 151 and a second bonding portion 152, and the first bonding portion 151 has a finer pattern than the second bonding portion 152. Similarly, the first wiring electrode 140a1 and the first via electrode 140b1 of the electrode portion 140 connected to the bonding portion 150 also include a first portion 141 and a second portion 142. Exemplarily, the first wiring electrode 140a1 includes a first portion 141a that vertically overlaps the connecting member 200 and a second portion 142a that does not vertically overlap the first portion 141a, and the first portion 141a of the first wiring electrode 140a1 can have a finer pattern than the second portion 142a of the first wiring electrode 140a1. Also, the first via electrode 140b1 similarly includes a first portion 141b and a second portion 142b, and the first portion 141b can have a finer pattern than the second portion 142b. By providing a buffer function for the pattern for electrically connecting the circuit board 100 and the connecting member 200, the electrical connection reliability between the connecting member 200, the circuit board 200, and the semiconductor chips 320 and 330 can be improved. Also, according to the embodiment, the third - 1 wiring electrode 140a3, the third - 2 wiring electrode 140a4, the fourth wiring electrode 140a5, the fifth wiring electrode 140a6, the second via electrode 140b2, the third via electrode 140b3, the fourth via electrode 140b4, and the fifth via electrode 140b5 are located below the connecting member 200 (exemplarily, below the pad of the connecting member), so they are not connected to the fine pattern of the connecting member 200.Therefore, regardless of whether each of the third - 1 wiring electrode 140a3, the third - 2 wiring electrode 140a4, the fourth wiring electrode 140a5, the fifth wiring electrode 140a6, the second via electrode 140b2, the third via electrode 140b3, the fourth via electrode 140b4, and the fifth via electrode 140b5 overlaps the connecting member 200 in the vertical direction, the degree of pattern fineness is the same. Hereinafter, the first part 141 of the electrode part 140 refers to the electrode part 140 located between the connecting member 200 and the semiconductor chips 320 and 330 and overlapping the connecting member 200 vertically. Also, the second part 142 of the electrode part 140 refers to the electrode part 140 located between the connecting member 200 and the semiconductor chips 320 and 330, not overlapping the connecting member 200 vertically, and overlapping the first part 141 in the horizontal direction.

[0108] Referring to FIG. 1a, the size of the first bonding portion 151 is shown to be smaller than the size of the second bonding portion 152. This is because the density of the first bonding portion 151 for connection to the connecting member 200 is higher than the density of the second bonding portion 152. Therefore, by arranging the size of the first bonding portion 151 to be smaller than the size of the second bonding portion 152, the electrical connection reliability between the connecting member 200 and the semiconductor chips 320 and 330 can be improved. FIG. 1b shows the upper surfaces of the first bonding portion 151 and the second bonding portion 152 of the circuit board 100. Exemplarily, FIG. 1b shows the upper surfaces of the protruding portion 151b of the first bonding portion 151 and the protruding portion 152b of the second bonding portion 152.

[0109] As shown in FIG. 1b, the size and spacing of the first bonding portion 151 are smaller than those of the second bonding portion 152. The first bonding portion 151 connects the connecting member 200 to the semiconductor chips 320 and 330 to each other. As a region where they vertically overlap, in order to correspond to the fine patterns of the pads 210 of the connecting member 200 and the terminals 325 and 335 of the semiconductor chips 320 and 330, it is arranged to be smaller than the size and spacing of the second bonding portion 152 of the bonding portion. At this time, a part of the first bonding portion 151 is arranged between the first semiconductor chip 320 and the connecting member 200, and the remaining part of the first bonding portion 151 is arranged between the second semiconductor chip 330 and the connecting member 200. Also, a part of the second bonding portion 152 does not overlap the connecting member 200 in the vertical direction and overlaps the first semiconductor chip 320 in the vertical direction, and the remaining part of the second bonding portion 152 does not overlap the connecting member 200 in the vertical direction and overlaps the second semiconductor chip 330 in the vertical direction.

[0110] Referring to FIG. 1a, the through portions 151a and 152a of the bonding portion 150 gradually decrease in width toward the connecting member 200, penetrate the first protective layer 120, and contact the pads 141a and 142a of the first wiring electrode 140a1. To arrange the first bonding portion 151 and the second bonding portion 152, a process of processing the first and second through holes 120a and 120b in the first protective layer 120 is performed. Recently, the number of pads 210 of the connecting member 200 has increased, the number of terminals 325 and 335 of the semiconductor chips 320 and 330 has increased, or the number of semiconductor chips 320 and 330 to be connected has increased. In such a trend, the first through hole 120a is required to have a width of 20 μm or less, and the second through hole 120b may be required to have a width exceeding 30 μm. At this time, the first protective layer 120 is provided with a photosensitive material, and conventionally, the first protective layer 120 was exposed and developed to form through holes. However, due to the limit of the resolution of the exposure process, it is difficult to process the width of the first through hole 120a to a width of 20 μm or less. Therefore, conventionally, a laser process was used to form the first through hole 120a. When both the first through hole 120a and the second through hole 120b are processed by a laser process, the yield is greatly reduced, such as wrinkles being generated on the surface of the circuit board 100 during the process due to the stress caused by the laser. Therefore, in the prior art, the first through hole 120a was processed by a laser process, and the second through hole 120b was formed using an exposure process. However, in such a case, due to the difference in the resolution between the exposure process and the laser process, a difference in the width between the first through hole 120a and the second through hole 120b occurs. As a result, in the plating process for arranging the first bonding portion 151 and the second bonding portion 152, a plating deviation occurs due to the difference in the amount of current applied to the first through hole 120a and the second through hole 120b, respectively, and a height deviation between the first bonding portion 151 and the second bonding portion 152 occurs.

[0111] Also, when forming the first through-hole 120a using a laser process, since the laser beam has a Gaussian distribution, the inner wall of the first through-hole 120a has a portion that extends vertically and a curved portion that narrows in width at a portion adjacent to the pads 141a and 142a of the first wiring electrode 140a1. Specifically, as shown in FIG. 2a, in the prior art, a through-hole is formed in the protective layer 12 by a laser process, thereby narrowing the width of the bonding portion 20. However, when forming a through-hole in the protective layer 12 by a laser process, due to the characteristics of the laser beam having a Gaussian distribution, it includes a curved portion where the width narrows at a portion adjacent to the pad 40. Therefore, the through portion 21 of the bonding portion 20 disposed in the through-hole of the protective layer 12 includes a curved portion 21a where the width rapidly narrows at a portion adjacent to the pad 40. At this time, the bonding portion that does not overlap with the connecting member 200 in the vertical direction has a larger width than the bonding portion that overlaps with the connecting member 200 in the vertical direction. Therefore, even if it includes a curved portion, no significant problems occur in terms of physical reliability and / or electrical reliability. However, in the case of the bonding portion that overlaps with the connecting member 200 in the vertical direction, since it has a relatively fine width, the heat cycle of the protective layer 12 due to the heat generated during the operation of the semiconductor chips 320 and 330, and stress is applied to the curved portion 21a by subsequent processes. As a result, cracks may occur at the interface between the through portion 21 of the bonding portion 20 and the pad 40, or reliability problems such as peeling of the through portion 21 of the bonding portion 20 from the pad 40 may occur. To solve this problem, when increasing the width of the bonding portion 20, it becomes difficult to adjust the pitch between the plurality of bonding portions to 40 μm or less, thereby increasing the area of the semiconductor package and making it difficult to thin it. Furthermore, when forming a through-hole in the protective layer 12 by a laser process, the process time increases and productivity decreases. Furthermore, when forming a through-hole having a relatively small width by a laser process, it is difficult to align the laser beam at an accurate position, thereby causing defects such as misalignment of the through-hole position and reducing the product yield.

[0112] Here, the pitch means the distance between the center lines of the plurality of first bonding portions 151 of the bonding portion 150, and can be defined by the horizontal distance W6 shown in FIG. 1c. A manufacturing method for realizing a fine pitch and improving the reliability of the plurality of first bonding portions 151 of the bonding portion 150 according to the embodiment will be described later.

[0113] In contrast, the embodiment shown in FIG. 1a is provided such that the inner wall of the first through hole 120a is vertical. That is, the first through hole 120a of the embodiment has a width of 20 μm or less, and the inner wall does not include a curved portion as in the prior art. Thereby, even if the width of the first through hole 120a is miniaturized, the width of the first through hole 120a in the region closest to the pads 141a and 142a can be increased compared to the prior art, thereby ensuring the contact area between the pads 141a and 142a and the bonding portion 150 and improving the adhesion.

[0114] In contrast, the embodiment shown in FIG. 1a is provided such that the inner wall of the first through hole 120a is vertical. Specifically, the inner wall of the first through hole 120a of the first protective layer 120 disposed on the pads 141a and 142a of the first wiring electrode 140a1 is provided to be perpendicular to the upper surfaces of the pads 141a and 142a. A part of the upper surfaces of the pads 141a and 142a is in contact with the lower surface of the first protective layer 120a, and the inner wall of the first through hole 120a is provided to be perpendicular to a part of the upper surfaces of the pads 141a and 142a in contact with the lower surface of the first protective layer 120a described above. Here, perpendicular does not mean that the angle formed by the inner wall of the first through hole 120a and a part of the upper surfaces of the pads 141a and 142a described above is only 90° (degree), but considering process errors and the like, an inclination angle in the range of 85° (degree) to 90° (degree) should be regarded as perpendicular. Thereby, the problem of cracks occurring at the interface between the first bonding portion 151 and the pads 141a and 142a can be prevented.

[0115] Referring to FIG. 1c, the widths of the first through hole 120a and the second through hole 120b of the first protective layer 120 are formed to be the same as each other. Thereby, the current amount can be applied identically during the plating process, the deviation in the heights of the first protrusion 151b of the first bonding portion 151 and the second protrusion 152b of the second bonding portion 152 can be reduced, and the semiconductor chips 320 and 330 can be mounted with high reliability so as not to tilt during the mounting of the semiconductor chips 320 and 330 in subsequent processes.

[0116] Also, exemplarily, the widths of the first protrusion 151b and the second protrusion 152b may be arranged to be different from each other. As illustrated in FIG. 1c, the size and the interval of the second protrusion 152b are larger than the size and the interval of the first protrusion 151b arranged in the region where the connecting member 200 is located. Therefore, it is possible to secure a tolerance of the positional alignment for improving the yield during the mounting of the semiconductor chips 320 and 330, and the impedance can be reduced by arranging the size of the second protrusion 152b to be large. Also, although not shown, in order to ensure a certain degree of uniformity in the density of the first through hole 120a and the second through hole 120b during the plating process of the first bonding portion 151 and the second bonding portion 152 and to improve the impedance of the second bonding portion 152, a plurality of second through portions 152a connected to one second protrusion 152b may be arranged at intervals in the horizontal direction.

[0117] According to the embodiment illustrated in FIG. 1c, at this time, the width W1 of the first through-hole 151a can satisfy the range of 12 μm to 20 μm. If the width W1 of the first through-hole 151a is less than 12 μm, the allowable current of the signal transmitted through the first through-hole 151a decreases. Also, if the width W1 of the first through-hole 151a is less than 12 μm, the impedance of the first through-hole 151a increases, and the contact area with the pad 141a of the first wiring electrode 140a1 decreases, resulting in a mechanical reliability problem that the first bonding portion 151 may peel off from the pad 141 of the first wiring electrode 140a1. Further, if the width W1 of the first through-hole 151a of the first bonding portion 150 is greater than 20 μm, it becomes difficult to arrange all the plurality of first through-holes 151a that vertically overlap the connecting member 200 within the limited space. That is, if the width W1 of the first through-hole 151a is greater than 20 μm, it becomes difficult to adjust the pitch between the plurality of first bonding portions 151 to 40 μm or less, and the circuit integration degree decreases accordingly.

[0118] On the other hand, the width W2 of the second through-hole 152a can correspond to the width W1 of the first through-hole 151a. For example, the width W1 of the first through-hole 151a may be the same as the width W2 of the second through-hole 152a.

[0119] Each of the first through-hole 151a and the second through-hole 152a can have a maximum width and a minimum width. The maximum width can mean the width of the region having the largest width in the entire region in the thickness direction of each of the first through-hole 151a and the second through-hole 152a. Also, the minimum width can mean the width of the region having the smallest width in the entire region in the thickness direction of each of the first through-hole 151a and the second through-hole 152a. And each maximum width can be embodied to be 105% or less of the minimum width. Hereinafter, it will be described assuming that the maximum width is the width of the upper surface of each through-hole and the minimum width is the width of the lower surface of each through-hole. However, the embodiment is not limited thereto, and each through-hole can also have a maximum width and a minimum width in other regions between the upper surface and the lower surface.

[0120] The first through-hole portion 151a can include an upper surface and a lower surface. The upper surface and the lower surface of the first through-hole portion 151a can have corresponding or the same width. For example, the width of the upper surface of the first through-hole portion 151a may correspond to or be the same as the width of the lower surface of the first through-hole portion 151a. For example, the width of the upper surface of the first through-hole portion 151a can be embodied to be 105% or less of the width of the lower surface of the first through-hole portion 151a. Similarly, the width of the upper surface of the second through-hole portion 152a can be embodied to be 105% or less of the width of the lower surface of the second through-hole portion 152a.

[0121] In the embodiment, the first through-hole portions 151a and the second through-hole portions 152a of the first bonding portions 151 and the second bonding portions 152 are disposed in the first through-holes 120a and the second through-holes 120b of the first protective layer 120 formed using a dry film pattern. Therefore, corresponding to the shape of the dry film pattern, the inclination of the inner wall of the first through-hole portion 151a and / or the second through-hole portion 152a becomes nearly vertical as described above. That is, the width of the first through-hole portion 151a can have 20 μm or less and can have an inclination of the inner wall that is nearly vertical, and the inclination of the inner wall of the second through-hole portion 151b also becomes nearly vertical.

[0122] The width W3 of the first protruding portion 151b can satisfy the range of 29 μm to 34 μm. When the width W3 of the first protruding portion 151b is less than 29 μm, the allowable error with respect to the alignment at that position may deviate during the mounting of the semiconductor chips 320 and 330, and the semiconductor chips 320 and 330 may not be stably bonded onto the first protruding portion 151b. For example, when the width W3 of the first protruding portion 151b is less than 29 μm, the semiconductor chips 320 and 330 may not be stably mounted on the first protruding portion 151b, and a problem of peeling from the first protruding portion 151b may occur. Further, when the width W3 of the first protruding portion 151b exceeds 34 μm, it becomes difficult to embody the pitch between the plurality of first bonding portions 151 to be 40 μm or less. As a result, the number of the first protruding portions 151b cannot be ensured, and smooth electrical connection between the semiconductor chips 320 and 330 and the connection member 200 becomes difficult.

[0123] As a result, the first protruding portion 151b is provided with a constant width W4 along the circumferential direction of the first through portion 151a on the first through portion 151a. That is, the first protruding portion 151b is provided with a width W4 in the range of 5 μm to 10 μm along the circumferential direction of the first through portion 151a on the first through portion 151a. When the constant width W4 of the first protruding portion 151b described above is less than 5 μm, it becomes difficult to ensure the alignment accuracy at that position during patterning for arranging the first bonding portion 151 on the first through hole 120a of the first protective layer 120. Further, when the width W4 of the first through portion 151a exceeds 10 μm, it becomes difficult to implement the pitch between the plurality of first bonding portions 151 to be 40 μm or less as described above. As a result, the number of the first protruding portions 151b cannot be ensured, and it becomes difficult to achieve smooth electrical connection between the semiconductor chips 320 and 330 and the connecting member 200.

[0124] The distance W5 between the protruding portions of two adjacent first bonding portions among the plurality of first bonding portions 151 in the embodiment can be 5 μm to 11 μm. When the distance W5 between the protruding portions of two adjacent first bonding portions is less than 5 μm, a problem may occur in that the adjacent first bonding portions are electrically short-circuited due to a process error in the process of forming the first bonding portion 151. Further, when the distance W5 between the protruding portions of two adjacent first bonding portions exceeds 11 μm, it becomes difficult to implement the pitch between the plurality of first bonding portions 151 to be 40 μm or less. As a result, the number of the first protruding portions 151b cannot be ensured, and it becomes difficult to achieve smooth electrical connection between the semiconductor chips 320 and 330 and the connecting member 200.

[0125] Therefore, the horizontal distance W6 between the centers of the first through-holes 151a of two adjacent first bonding portions 151 among the plurality of first bonding portions 151 of the embodiment can be 40 μm or less. At this time, the horizontal distance W6 can mean the pitch between the plurality of first bonding portions 151 as described above, and can correspond to W1 + W4 + W5. The embodiment can make the mutual communication between the semiconductor chips 320 and 330 smoother by arranging a large number of the plurality of first bonding portions 151 in a limited space. Thereby, by enabling an electronic product such as a server to which the semiconductor package is applied to process a large amount of data, the above-described electronic product can have a core technical linkage.

[0126] Also, according to the embodiment illustrated in FIG. 1e, the first via electrode 140b1 includes a first-1 via electrode 141b and a first-2 via electrode 142b. The first-1 via electrode 141b has a smaller width and a shorter vertical length than the first-2 via electrode 142b. That is, since the upper surface of the connecting member 200 is positioned higher than the second wiring electrode 140a2, the vertical length of the first-1 via electrode 141b can be shortened, the signal transmission length can be shortened, and the impedance with respect to the length can be reduced, thereby making the electrical connection between the semiconductor elements 320 and 330 and the connecting member 200 smoother.

[0127] According to this embodiment, the first through hole 120a is formed using a dry film pattern. Also, the second through hole 120b can be formed by applying the same method as the first through hole 120a. Further, the embodiment can make the first through hole 120a and the second through hole 120b have the same width as each other. Thereafter, the first and second bonding portions 151 and 152 are formed by a plating process. At this time, by controlling the width and / or density of the first through hole 120a and the second through hole 120b, the height deviation of the first and second bonding portions 151 and 152 during the plating process can be reduced. Also, by forming the first and second through holes 120a and 120b using a dry film pattern, the pitch of the first and second bonding portions 151 and 152 can be miniaturized.

[0128] Referring to FIG. 1d, the first protective layer 120 includes a predetermined filler. The filler may be provided with inorganic particles and may be exemplified by a silica filler. When the first and second through holes 120a and 120b are implemented by a conventional laser process and / or exposure process, the filler may be exposed in the first and second through holes 120a and 120b. Therefore, when the first and second bonding portions 151 and 152 are disposed by a subsequent plating process, a portion where the filler exposed in the first and second through holes 120a and 120b contacts the first and second through portions 151a and 152b occurs. The first and second bonding portions 151 and 152 including the first and second through portions 151a and 152b are disposed of a material that can function for electrical conduction. It is exemplified by being provided with a metal material, and specifically, a copper metal can be used. Therefore, the filler exposed in the first and second through holes 120a and 120b and the first and second through portions 151a and 152b have poor mutual adhesion, which affects locally reducing the width of the first and second through portions 151a and 152b. Also, problems such as peeling and cracking due to the difference in the coefficient of thermal expansion rate are caused.

[0129] Therefore, according to this embodiment, a dry film pattern is arranged on the pads 141a and 142a of the first wiring electrode 140a1 so as to correspond to the pitch W6 of the plurality of first bonding portions 151 and the width of the first through portion 151a, and the first protective layer 120 is arranged so as to cover the dry film pattern on the first insulating layer 110b2. Thereafter, the thickness of the first protective layer 120 is thinned by etching using a chemical solution and / or plasma or the like so that the dry film pattern is exposed. Thereafter, by separating the dry film pattern, the first and second through holes 120a and 120b are formed.

[0130] When implementing the first and second through-holes 120a and 120b using a dry film pattern according to this embodiment, since the preferentially performed dry film pattern is preferentially arranged, the filler of the first protective layer 120 cannot penetrate into the dry film pattern. Therefore, the filler of the first protective layer 120 is not exposed in the first and second through-holes 120a and 120b, thereby preventing the contact between the first and second through-holes 151a and 152b and the filler, and greatly improving the electrical and / or mechanical reliability. In addition, since the filler of the first protective layer 120 is evenly dispersed, the coefficient of thermal expansion rate of the first protective layer 120 will also be evenly distributed. That is, a partial region of the first and second protrusions 151a and 152a overlaps perpendicularly with the filler of the first protective layer 120, and the filler of the first protective layer 120 that overlaps perpendicularly with a partial region of the first and second protrusions 151a and 152a does not contact the first and second through-holes 151a and 152b, thereby suppressing the peeling and cracking between the first and second protrusions 151a and 152a and the first protective layer 120 due to the shrinkage and expansion of the first protective layer 120 caused by the heat cycle, and greatly improving the electrical and / or mechanical reliability as described above. In addition, in order to further improve the above-described effects, the filler can include fillers having various different diameters, and some fillers can have a diameter smaller than a certain width W4 of the first protrusion 151b arranged along the circumferential direction of the first through-hole 151a on the first through-hole 151a.

[0131] In addition, in the process of etching and thinning the first protective layer 120, the surface roughness of the first protective layer 120 increases. Therefore, in the subsequent process in which the first and second bonding portions 151 and 152 are arranged, when the first and second protrusions 151b and 152b contact the surface of the first protective layer 120 described above, the contact area increases and the bonding force can be improved. Thereby, peeling and cracking of the first and second bonding portions 151 and 152 can be prevented by the stress caused by the shrinkage and / or expansion of the first protective layer 120 due to the heat cycle.

[0132] Also, the surface roughness of the first protective layer 120 and the roughness of the first and second through holes 120a and 120b may be different from each other. Specifically, the inner surface of the first protective layer 120 forming the first and second through holes 120a and 120b has the same roughness as the side surface roughness of the dry film pattern by the above-described process. During subsequent processes, the surface of the first protective layer 120 is etched by and / or plasma or the like, and the surface roughness increases, but no change in roughness occurs on the inner surface of the first protective layer 120 forming the first and second through holes 120a and 120b. As a result, the surface roughness of the first protective layer 120 is different from the roughness of the first and second through holes 120a and 120b. Therefore, the adhesive force between the first and second protruding portions 151b and 152b and the first protective layer 120 is improved, and the widths of the first and second through portions 151a and 152a can be made uniform, thereby improving electrical adverse effects such as signal loss. Here, the roughness of the first and second through holes 120a and 120b and the roughness of the inner surface of the first protective layer 120 refer to the same thing.

[0133] At this time, referring to FIG. 2b, in the prior art, a through hole is formed in the protective layer 20 by an exposure and development process or a through hole is formed in the protective layer 20 by a laser process.

[0134] Referring to FIG. 2b(a), in the first prior art, the protective layer 12 was exposed and developed to form a through hole. However, due to the limit of the resolution of the exposure process, the width W6 of the through hole penetrating the first protective layer 12 exceeded 20 μm, and thus exceeded 35 μm. Therefore, when forming a through hole in the protective layer 12 using the exposure and development process, it is difficult to miniaturize the width and interval of the bonding portion 20, and thus it is difficult to miniaturize the pitch between a plurality of bonding portions arranged adjacent to each other.

[0135] Referring to (b) of FIG. 2b, in the second prior art, a through hole penetrating the protective layer 12 is formed by laser processing, so that the width W1 of the through hole is 20 μm or less. However, in the second prior art, the protective layer 12 is provided with a through hole by laser processing and / or an exposure process, and the through portion 21 of the bonding portion 20 is disposed in the through hole. As a result, the through portion 21 in the second prior art includes a bottleneck portion (or a curved portion) having a difference in width in the thickness direction, so that the bonding force between the through portion 21 and the pad 40 at the bottleneck portion is reduced. In addition, cracks may occur in the lower region of the through portion 21 due to various factors (e.g., thermal stress). Therefore, according to the second prior art illustrated in (b) of FIG. 2b, the through portion 21 may include a first metal layer 21-1 and a second metal layer 21-2 disposed on the first metal layer 21-1. At this time, the pad 40 may include a concave recess 40C on the upper surface for disposing the second metal layer 21-2, and the recess may mean a clevis. That is, the contact area between the bonding portion 20 and the pad 40 is reduced at the bottleneck portion, thereby reducing the bonding force. To complement this, the recess 40C is filled with the first metal layer 21-1 of the through portion 21. At this time, since the through portion 21 includes a bottleneck portion, the through portion 21 must include a plurality of metal substances including different metal substances from each other, which complicates the manufacturing process or increases the manufacturing cost.

[0136] In contrast, in the embodiment, the widths of the first through portion 151a and the second through portion 152a are formed to be 20 μm or less, and the upper and lower surfaces of the first through portion 151a and the second through portion 152a can have corresponding widths to each other. Therefore, the embodiment can maintain the bonding strength of the first through portion 151a and the second through portion 152a even if the step of forming the recess 40C and the steps of forming the first metal layer and the second metal layer thereby are omitted, and thereby can reduce the manufacturing cost and the manufacturing expense. However, the embodiment is not limited thereto.

[0137] Referring to FIG. 3, in order to further improve the bonding strength between the first through-hole portion 151a and the second through-hole portion 152a, recesses 40C are formed in the pads 141a and 142a, and the first through-hole portion 151a and the second through-hole portion 152a can be configured to include first metal layers 151a1 and 152a1 that fill the recesses 40C, respectively. In addition, each of the first through-hole portion 151a and the second through-hole portion 152a can be configured to include second metal layers 151a2 and 152a2 disposed on the first metal layers 151a1 and 152a1.

[0138] Exemplarily, the second metal layers 151a2 and 152a2 may be hard metals. Specifically, the first metal layers 151a1 and 152a1 containing nickel and the second metal layers 151a2 and 152a2 containing a metal substance different from nickel can also be included. In the step of disposing the first and second bonding portions 151 and 152 on the pads 141a and 142a of the first wiring electrode 140a1, oxidation may occur when the upper surfaces of the pads 141a and 142a of the first wiring electrode 140a1 are partially exposed from the first protective layer 120. As a result, the bonding force between the pads 141a and 142a of the first wiring electrode 140a1 and the first and second bonding portions 151 and 152 decreases, cracks and peeling occur, or the electrical characteristics deteriorate due to the surface of the oxidized pads 141a and 142a. Further, when the widths of the first through-hole portion 151a and the second through-hole portion 152a are 30 μm or less, it is possible to prevent the problem of peeling between the pads 141a and 142a of the first wiring electrode 140a1 and the first and second bonding portions 151 and 152 due to thermal stress such as shrinkage and / or expansion of the first protective layer 120.

[0139] FIG. 4a is a cross-sectional view showing a semiconductor package according to the second embodiment, FIG. 4b is an enlarged view of a region R1 in FIG. 4a, and FIG. 4c is a cross-sectional view for explaining the surface roughness and structure of the first insulating layer 110b2 according to the second embodiment.

[0140] Hereinafter, the semiconductor package according to the second embodiment will be described with reference to FIGS. 4A to 4C. The components of the semiconductor package of the second embodiment that are substantially the same as those of the semiconductor package of the first embodiment are denoted by the same reference numerals.

[0141] Referring to FIGS. 4A to 4C, the circuit board 1000 according to the second embodiment has a difference in the shape of the first via electrode 1140b compared to the circuit board 100 according to the first embodiment. The first via electrode 140b in FIG. 1A has an inclined side surface structure in which the width gradually decreases from the upper surface to the lower surface of the circuit board 100, while the side surface of the first via electrode 1140b of the circuit board 1000 according to this embodiment has a vertical side surface structure. That is, the inclination angles of the first and second through portions 151a and 152a and the inclination angle of the first via electrode 1140b are arranged similarly to each other. Specifically, the first via electrode 1140b according to this embodiment also has a first-1 via electrode 1141b and a first-2 via electrode 1142b that overlap the connecting member 200 perpendicularly, similar to the first and second bonding portions 151 and 152. As described above, for the electrical connection between the semiconductor elements 320 and 330, the pitch of the pads 210 of the connecting member 200 has a finer pitch than the pitch of the pads 143a of the second wiring electrode 140a2. Thus, in the process of arranging the pads 1141a and 1142a of the first wiring electrode, it is difficult to arrange the pitch of the pads 1141a and 1142a finely by the existing laser processing. Also, when the first insulating layer 110b2 is provided with an insulating layer containing an inorganic filler such as ABF and a through hole is formed in the first insulating layer 110b2 by a laser process, the inorganic filler contained in the first insulating layer 110b2 is exposed in the through hole, and thus the side surfaces of the first via electrodes 1141b and 1142b have corresponding recesses. Therefore, the bonding force between the first via electrodes 1141b and 1142b and the first insulating layer 110b2 is reduced, and there are not only electrical adverse effects such as signal loss, but also the problem that it is difficult to arrange the pitch of the pads 1141a and 1142a finely. Therefore, according to the second embodiment, the above-described problems can be solved by arranging the inclination angles of the first via electrodes 1141b and 1142b to be the same as the inclination angles of the side surfaces of the first and second through portions 151a and 152a.

[0142] According to this embodiment, a dry film pattern is arranged on the pad 143a of the second wiring electrode 140a2 and on the pad 210 of the connecting member 200 so as to correspond to the pitches of the plurality of pads 1141a, 1142a of the first wiring electrode and the first via electrodes 1141b, 1142b. Thereafter, a first insulating layer 110b2 is arranged so as to cover the dry film pattern. Thereafter, the first insulating layer 110b2 is etched using a chemical solution and / or plasma or the like to reduce its thickness and make the dry film pattern exposed. Thereafter, by separating the dry film pattern, a through hole in which the first via electrodes 1141b, 1142b are arranged is formed in the first insulating layer 110b2, and thereafter, the first via electrodes 1141b, 1142b and the pads 1141a, 1142a are arranged at a desired pitch.

[0143] Referring to FIG. 4b, the width of the first - 1 via electrode 1141b can correspond to the width W1 of the first through - portion 151a of the first bonding portion 151. Also, the horizontal width of the first - 1 via electrode 1141b can satisfy the range of 12 μm to 20 μm. When the width of the first - 1 via electrode 1141b is smaller than 12 μm, the allowable current of the signal transmitted through the first - 1 via electrode 1141b decreases or the impedance increases. Also, when the width W1 of the first - 1 via electrode 1141b is larger than 20 μm, it becomes difficult to miniaturize the pitch of the pad 1141a. Also, the widths of the first - 1 via electrode 1141b and the first - 2 via electrode 1142b may be the same as each other. That is, the pitches of the pads 1141a, 1142a can be miniaturized more easily. Also, although not shown, by providing a plurality of first - 2 via electrodes 1142b connected to one pad 1142a so as to be horizontally separated, the impedance can be improved.

[0144] The width of pad 1141a can satisfy the range of 29 μm to 34 μm. If the width of pad 1141a is less than 29 μm, the contact area between the first bonding portion 151 and the first through portion 151a of the first bonding portion 151 decreases, thereby reducing the adhesion strength. Therefore, peeling may occur between the first bonding portion 151 and the pad 1141a. In addition, due to process deviation in the process of forming the pad 1141a, at least a part of the first via electrode 1141b does not overlap with the pad 1141a in the vertical direction, which may cause electrical reliability and / or mechanical reliability problems. Also, if the width of the pad 1141a exceeds 34 μm, the effect of improving the positional alignment with the first bonding portion 151 and more easily adjusting the pitch of the first bonding portion 151 to the target value becomes negligible.

[0145] Also, referring to FIG. 4b, the interval between a plurality of adjacent pads 1141a and 1142a can have a value between 5 μm and 11 μm. As a result, the horizontal distance W6 between the centers of a plurality of adjacent pads 1141a and 1142a can be 40 μm or less. Although FIG. 4b defines the horizontal distance W6 between the centers of the pads 1141a, it is not limited thereto, and it can be understood as the horizontal distance between the centers of the pad 1142a and the pad 1141a. According to FIG. 4b, the first via electrode 1141a and the first through portion 151a are mutually aligned, and the first via electrode 1142a and the second through portion 152a are mutually aligned. Thereby, voltage drop can be prevented. However, due to process error, an alignment error within 10 μm may occur between the respective center lines.

[0146] Referring to FIG. 4c, roughness is formed on the upper surface of the first insulating layer 110b2. Similar to the first protective layer 120, the surface roughness of the first insulating layer 110b2 is formed during the process in which the first insulating layer 110b2 is etched and thinned by a chemical solution and / or plasma or the like. Thereby, the adhesive force between the first protective layer 120 and the first insulating layer 110b2 can be improved. Although not shown, due to the roughness formed on the upper surface of the first insulating layer 110b2, recesses are formed on the upper surface of the first insulating layer 110b2, and the filler of the first protective layer 120 can fill the recesses formed on the upper surface of the first insulating layer 110b2. Therefore, the adhesive force between the first protective layer 120 and the first insulating layer 110b2 is further improved. Also, the filler of the first protective layer 120 and the filler of the first insulating layer 110b2 may be provided with the same substance and / or the same diameter as each other, but are not limited thereto.

[0147] FIG. 5a is an enlarged view of an area R1 of the semiconductor package of FIG. 4a according to the third embodiment.

[0148] Referring to FIG. 5a, the semiconductor package according to the third embodiment is different in the structure of the bonding portion compared to the semiconductor package of the second embodiment. Hereinafter, for convenience of explanation, the description will be made based on the first bonding portion overlapping the connecting member 200 in the vertical direction.

[0149] On the connecting member 200, a first electrode portion 2141 including a first via electrode 2141b and a first wiring electrode 2141a is disposed. Also, on the first electrode portion 2141, a first bonding portion 2151 is disposed.

[0150] The first bonding portion 2151 includes a first through portion 2151a penetrating the first protective layer 120 and a first protruding portion 2151b protruding on the first through portion 2151a.

[0151] At this time, the first through portion and the first protruding portion in the previous embodiments were provided with different widths from each other.

[0152] In contrast, according to the third embodiment, the first through-hole 2151a can have the same width as the first protrusion 2151b. Also, each of the first through-hole 2151a and the first protrusion 2151b can have the same width as the first wiring electrode 2141a of the first electrode portion 2141.

[0153] The third embodiment can increase the volume of the first bonding portion 2151 without affecting the pitch of the first bonding portion 2151, thereby enabling a semiconductor element to be more stably arranged on the first bonding portion 2151. Also, the embodiment can increase the volume of the first bonding portion 2151 to improve the rigidity of the semiconductor package, thereby preventing the circuit board from warping significantly in a specific direction.

[0154] FIG. 5b is an enlarged view of an area R1 of the semiconductor package of FIG. 4a according to the fourth embodiment.

[0155] Referring to FIG. 5b, a first through-hole 3141 is provided on the connecting member 200. The first through-hole 3141 has no change in width from the upper surface to the lower surface and can penetrate the first insulating layer 110b2.

[0156] A first protrusion 3151 is disposed on the first through-hole 3141. The first protrusion 3151 has no change in width from the upper surface to the lower surface and can penetrate the first protective layer 120. That is, after the first protrusion 3151 and the first through-hole 3141 are integrally arranged, the first protective layer 120 is etched using a chemical solution and / or plasma, etc., to reduce its thickness and thin it, so that the first protrusion 3151 is exposed. Therefore, by making it possible to embody the pitch of the first protrusion 3151 more finely, the mutual communication between the semiconductor chips 320, 330 and the circuit board 100 can be made smoother.

[0157] FIG. 6 is a drawing showing a semiconductor package according to the fifth embodiment.

[0158] Referring to FIG. 6, the semiconductor package according to the fifth embodiment includes a circuit board manufactured by the ETS (Embedded Trace Substrate) method. According to the above description, the circuit board according to the fifth embodiment can be classified as a coreless board.

[0159] Referring to FIG. 6, the semiconductor package includes an insulating layer 4110, a first protective layer 4120, a second protective layer 4130, an electrode portion 4140, and a bonding portion 4150. A connecting member 200 is embedded in the insulating layer 4110. Also, a connecting member 220 is disposed between the connecting member 200 and the electrode portion 4140. Thus, the first protective layer 4120 in FIG. 6 is laminated with a dry film pattern disposed on the wiring electrode 4140a of the uppermost electrode portion 4140 embedded in the insulating layer 4110, whereby through-holes corresponding to the dry film pattern are provided. That is, in the fifth embodiment, before laminating the first protective layer 4120 in the process of manufacturing the circuit board using the ETS method, a process of disposing a dry film pattern can be performed so as to correspond to the pitch that the bonding portion 4150 should have. For example, the fifth embodiment can be manufactured by applying the process of forming through-holes in the first protective layer using the dry film pattern described in the first embodiment and the process of forming the bonding portion.

[0160] The embodiment includes a protective layer and a bonding portion that penetrates a partial region from the upper surface of the protective layer. At this time, the protective layer is provided with a through hole corresponding to the bonding portion. The through hole of the protective layer is formed by a dry film pattern. That is, the through hole is formed to correspond to the width and pitch that the bonding portion provided in the semiconductor package should have. That is, the embodiment forms a dry film pattern in advance considering the width and pitch of the bonding portion. Thereby, the embodiment can minimize the pitch between a plurality of bonding portions. For example, the embodiment can be arranged such that the horizontal distance between the centers of two adjacent bonding portions is 40 μm or less. The embodiment can miniaturize the pitch of the bonding portion to 40 μm or less, whereby the embodiment can improve the circuit integration degree and miniaturize the circuit board and the semiconductor package. Also, the embodiment can reduce the distance between a plurality of bonding portions, thereby minimizing the transmission distance of the signal transmitted through the bump portion. Therefore, the embodiment can minimize the signal transmission loss increased by the signal transmission distance, thereby improving the electrical characteristics of the circuit board and the semiconductor package. Also, the embodiment can enable the semiconductor element disposed on the circuit board to operate stably, thereby enabling the electronic product such as a server to which the semiconductor package is applied to operate stably.

[0161] In addition, the embodiment includes an electrode portion disposed between the connecting member and the bonding portion. The electrode portion penetrates at least a partial region of the insulating layer. At this time, the insulating layer includes a through hole corresponding to the via electrode of the electrode portion. Further, the through hole of the insulating layer is provided by a dry film formed according to the width and pitch that the bonding portion of the embodiment should have. Thereby, the embodiment can form the electrode portion so as to correspond to the width and pitch that the bonding portion should have. Therefore, the embodiment can make the bonding portion have the target width and pitch. Further, the embodiment can form the electrode portion at a position corresponding to the bonding portion, thereby improving the positional alignment between the bonding portion and the electrode portion, and thus improving the electrical characteristics of the bonding portion and the electrode portion.

[0162] In addition, the embodiment can minimize the height deviation between a plurality of bonding portions. That is, the embodiment includes a first bonding portion overlapping the connecting member in the vertical direction and a second bonding portion not overlapping the connecting member in the vertical direction. At this time, the size of the first through portion of the first bonding portion is the same as the size of the second through portion of the second bonding portion. That is, the embodiment can make the through portions of the first bonding portion and the second bonding portion have the same size as each other by using a dry film pattern, thereby minimizing the height deviation between the first bonding portion and the second bonding portion generated by the size difference.

[0163] Therefore, the embodiment can minimize the height deviation between the first bonding portion and the second bonding portion, thereby enabling the semiconductor elements to be stably disposed on the first bonding portion and the second bonding portion. Therefore, the embodiment can improve the reliability of the first and second semiconductor elements. In addition, the embodiment can make the operations of the first and second semiconductor elements be performed smoothly, thereby making the operations of electronic products and servers be performed smoothly.

[0164] In addition, in the embodiment, the first bonding portion and the second bonding portion are made to have the same height, so as to prevent impedance change and signal transmission loss problems caused by thickness changes of the first bonding portion and the second bonding portion, and problems caused by the semiconductor element being arranged in an inclined state, thereby further improving the electrical reliability.

[0165] In addition, in the embodiment, the surface roughness of the interface between each through-hole of the first bonding portion and the second bonding portion and the protective layer can be relatively reduced. Therefore, the embodiment can reduce the surface roughness of the through-hole, thereby minimizing the signal transmission loss that increases in proportion to the surface roughness. Therefore, the embodiment can further improve the operating characteristics of the semiconductor element.

[0166] On the other hand, the upper surface of the protective layer of the embodiment can be provided with concave portions and convex portions that increase the surface area of the upper surface of the protective layer by a process of thinning the thickness. The concave portions and the convex portions can function to improve the reliability of the circuit board from heat cycles such as expansion and contraction of the circuit board due to heat generated during the operation of the semiconductor chip or other externally applied heat. Exemplarily, since the convex portions and the concave portions have different thicknesses, the volumes deformed during thermal expansion are different. That is, the thickness of the concave portion can be made thinner than the thickness of the convex portion, and the overall thermal deformation of the semiconductor package can be suppressed by the difference between the thermal expansion rate of the convex portion and the thermal expansion rate of the concave portion. Therefore, the embodiment can prevent the semiconductor element bonded to the upper part of the semiconductor package from being electrically separated during thermal expansion, thereby improving the product reliability.

[0167] Referring to the first to fifth embodiments, the via electrodes located on the upper side of the connecting member 200 have different widths and / or inclination directions from the via electrodes located below the connecting member 200. That is, the via electrodes located on the upper side of the connecting member 200 have a more vertical side surface than the via electrodes located below the connecting member 200. That is, by arranging the via electrodes having a vertical side surface above the connecting member 200, it is possible to have an effect of improving the warpage of the circuit board 100. When the via electrodes having a vertical side surface have a finer pattern than the via electrodes having an inclined side surface, the stress applied to the via electrodes can be relaxed, and the via electrodes having a vertical side surface are arranged above the connecting member 200 so as to improve the electrical connection reliability between the semiconductor chips 320 and 330 and the circuit board 100.

[0168] Furthermore, in the above, it has been described that the through holes are formed in the first protective layer 120 using a dry film to have a width of 20 μm or less and a pitch of 40 μm or less between two adjacent through holes, but it is not limited thereto. Exemplarily, in the embodiment, through holes can also be formed in the second protective layer 130 in the same manner as the step of forming through holes in the first protective layer 120.

[0169] Also, although it has been described that the first protective layer 120 includes a plurality of through holes and the bonding portion 150 is provided in the plurality of through holes, it is not limited thereto.

[0170] Exemplarily, at least one of the through holes provided in the first protective layer 120 is not provided with a bonding portion. Further, the through hole not provided with the bonding portion is filled with a molding member (not shown) for molding the semiconductor chip. Therefore, the embodiment can improve the adhesive force between the circuit board and the molding member. Further, the embodiment can control the density of the first protective layer in the edge region of the circuit board or cause the molding member and the circuit board to be firmly bonded, thereby preventing the circuit board from warping in a specific direction or, when the circuit board warps in a specific direction, firmly fixing the circuit board to improve its rigidity.

[0171] Figures 8a to 8q are cross-sectional views for explaining the manufacturing method of the circuit board according to the second embodiment of Figure 4a in the order of steps.

[0172] Referring to Figure 8a, the embodiment prepares a third insulating layer 110a. Further, the embodiment can perform a process of forming an electrode portion on the third insulating layer 110a. For example, the embodiment can perform a process of forming wiring electrodes on the upper and lower surfaces of the third insulating layer 110a and a process of forming via electrodes and insulating members 110d penetrating the third insulating layer 110a.

[0173] Next, the embodiment performs a process of laminating a second insulating layer 110b1 on the third insulating layer 110a. Further, the embodiment performs a process of forming via electrodes penetrating the second insulating layer 110b1 and wiring electrodes on the second insulating layer 110b1.

[0174] Referring to Figure 8b, the embodiment performs a process of forming a cavity C in the second insulating layer 110b1. At this time, a dummy electrode 141a31 is provided on the third insulating layer 110a, and the cavity C overlaps the dummy electrode 141a31 in the vertical direction.

[0175] Next, referring to FIG. 8c, the embodiment can apply an adhesive member onto the dummy electrode 141a31, and thereby perform a step of attaching the connecting member 200 to the cavity C. At this time, the connecting member 200 includes pads 210, and the pads 210 are arranged to face upward.

[0176] Next, referring to FIG. 8d, the embodiment performs a step of laminating a first dry film DF1 onto the second insulating layer 110b1 and the connecting member 200.

[0177] Next, referring to FIG. 8e, the embodiment performs a step of exposing and developing the first dry film DF1 so as to correspond to the widths and pitches that the first bonding portion 151 and the second bonding portion 152 should have. Thereby, on the pads 210 of the connecting member 200, a first dry film pattern DFP1-1 corresponding to the region where the first via electrode 141b of the first electrode portion 141 is arranged is formed. Also, on the wiring electrode, a second dry film pattern DFP1-2 corresponding to the region where the second via electrode 142b of the second electrode portion 142 is arranged is formed.

[0178] Next, referring to FIG. 8f, the embodiment performs a step of laminating the first insulating layer 110b2. At this time, the first insulating layer 110b2 is arranged while filling the cavity C in which the connecting member 200 is embedded. Also, the first insulating layer 110b2 is arranged to have a height larger than that of the first dry film pattern DFP1-1 and the second dry film pattern DFP1-2.

[0179] Next, referring to FIG. 8g, the embodiment performs a step of thinning the thickness of the first insulating layer 110b2. As a result, the upper surface of the first insulating layer 110b2 is positioned lower than the upper surfaces of the first dry film pattern DFP1-1 and the second dry film pattern DFP1-2. Further, by the step of thinning the thickness of the first insulating layer 110b2, the filler provided in the second layer 110b2 of the second insulating layer 110b can escape or be exposed through the upper surface of the first insulating layer 110b2. Thereby, the upper surface of the first insulating layer 110b2 is provided with concave portions and / or convex portions corresponding to the filler provided in the first insulating layer 110b2. Furthermore, at least a part of the filler provided in the first insulating layer 110b2 can be exposed through the upper surface of the first insulating layer 110b2.

[0180] Next, referring to FIG. 8h, the embodiment performs a step of removing the first dry film pattern DFP1-1 and the second dry film pattern DFP1-2. As a result, in the second layer 110b2 of the second insulating layer 110b, a first through hole TH1 and a second through hole TH2 corresponding to the space from which the first dry film pattern DFP1-1 and the second dry film pattern DFP1-2 are removed are formed. Thus, the embodiment forms the first through hole TH1 and the second through hole TH2 by using the first dry film pattern DFP1-1 and the second dry film pattern DFP1-2, so that the filler provided in the first insulating layer 110b2 does not escape through the first through hole TH1 and the second through hole TH2, and the filler provided in the second layer 110b2 of the second insulating layer 110b is not exposed through the first through hole TH1 and the second through hole TH2. Also, the embodiment forms the first through hole TH1 and the second through hole TH2 by using the first dry film pattern DFP1-1 and the second dry film pattern DFP1-2, so that the upper surface of the pad 210 of the connecting member 200 is not provided with a concave portion.

[0181] Next, referring to FIG. 8i, the embodiment forms a second dry film DF2 on the first insulating layer 110b2. At this time, the second dry film DF2 has an opening in which the region where the wiring electrode is disposed is opened. Next, the embodiment performs a plating process to fill the first through hole TH1, the second through hole TH2 of the first insulating layer 110b2, and the opening of the second dry film DF2. Thereby, the embodiment can form an electrode portion 1140 including a wiring electrode 1140a and a via electrode 1140b.

[0182] Next, referring to FIG. 8j, the embodiment performs a process of laminating a third dry film DF3 on the first insulating layer 110b2.

[0183] Next, referring to FIG. 8k, the embodiment performs a process of exposing and developing the third dry film DF3 so as to correspond to the widths and pitches that the first bonding portion 151 and the second bonding portion 152 should have. Thereby, on the wiring electrode 1140a, a third dry film pattern DFP3-1 corresponding to the first bonding portion 151 and a fourth dry film pattern DFP3-2 corresponding to the second bonding portion 152 are formed.

[0184] Next, referring to FIG. 8l, the embodiment performs a process of laminating a first protective layer 120 on the first insulating layer 110b2. At this time, the first protective layer 120 is disposed with a height larger than that of the third dry film pattern DFP3-1 and the fourth dry film pattern DFP3-2.

[0185] Next, referring to FIG. 8m, the embodiment performs a step of thinning the thickness of the first protective layer 120. As a result, the upper surface of the first protective layer 120 is positioned lower than the upper surfaces of the third dry film pattern DFP3-1 and the fourth dry film pattern DFP3-2. Also, by the step of thinning the thickness of the first protective layer 120, the filler provided in the first protective layer 120 can come out or be exposed to the outside. As a result, the upper surface of the first protective layer 120 is provided with concave portions and / or convex portions corresponding to the filler provided in the first protective layer. Further, at least a part of the filler provided in the first protective layer 120 can be exposed through the upper surface of the first protective layer 120.

[0186] Next, referring to FIG. 8n, the embodiment performs a step of removing the third dry film pattern DFP3-1 and the fourth dry film pattern DFP3-2. As a result, a first through hole 120a and a second through hole 120b are formed in the first protective layer 120. Thus, the embodiment forms the first through hole 120a and the second through hole 120b by using the third dry film pattern DFP3-1 and the fourth dry film pattern DFP3-2, so that the filler provided in the first protective layer 120 does not come out through the first through hole 120a and the second through hole 120b, and the filler provided in the first protective layer 120 is not exposed through the first through hole 120a and the second through hole 120b. Also, the embodiment forms the first through hole 120a and the second through hole 120b by using the third dry film pattern DFP3-1 and the fourth dry film pattern DFP3-2, so that the upper surface of the wiring electrode 140a is not provided with a recess.

[0187] Next, referring to FIG. 8o, the embodiment performs a plating step of filling the first through hole 120a and the second through hole 120b to form a first bonding portion 151 and a second bonding portion 152.

[0188] Next, referring to FIG. 8p, the embodiment performs a step of disposing a connection portion 310 on the first bonding portion 151 and the second bonding portion 152.

[0189] On the other hand, a circuit board according to a further embodiment and a semiconductor package including the same will be described below. The circuit board and the semiconductor package of the further embodiment include a protective layer, and are similar to the circuit board and the semiconductor package of the previous embodiment in that through holes are formed in the protective layer. However, hereinafter, a dry film is used to form through holes in the protective layer and protrusions are provided on the surface of the protective layer.

[0190] Before describing the embodiment, the structure of the protective layer according to the prior art to be compared therewith will be described.

[0191] FIG. 9 is a cross-sectional view showing a circuit board according to a comparative example.

[0192] Referring to FIG. 9, the circuit board of the comparative example includes an insulating layer 10, a circuit pattern layer, and a protective layer 30. The circuit pattern layer includes a first pad 21, a second pad 22, and a trace 23. The protective layer 30 includes a first through hole 31 that vertically overlaps the first pad 21. The first through hole 31 partially opens the upper surface of the first pad 21. The width W1 of the first through hole 31 exceeds at least 50 μm according to the exposure resolution (for example, high resolution) of the protective layer 30. Specifically, the width W1 of the first through hole 31 exceeds at least 70 μm according to the exposure resolution (for example, general resolution) of the protective layer 30. Therefore, the width of the first pad 21 that vertically overlaps the first through hole 31 exceeds 70 μm, which is larger than the width W1 of the first through hole 31. For example, the width of the first pad 21 exceeds 90 μm, which is larger than the width W1 of the first through hole 31. This is in consideration of the process deviation in the process of forming the first through hole 31.

[0193] As described above, the first through-hole 31 exceeds a minimum of more than 50 μm or more than 70 μm, whereby the width of the first pad 21 exceeds 70 μm or exceeds 90 μm. As a result, the comparative example has a limit in reducing the interval between the plurality of first pads. That is, the comparative example has a limit in miniaturizing the width W1 of the first through-hole 31, and thus has a limit in miniaturizing the width of the first pad 21.

[0194] The protective layer 30 includes a second through-hole 32 that vertically overlaps the second pad 22. The second through-hole 32 entirely opens the upper surface of the second pad 22. That is, the second through-hole 32 is a through-hole of the NSMD type. The width W2 of the second through-hole 32 exceeds 50 μm or 70 μm according to the exposure resolution of the protective layer 30. That is, the protective layer 30 has a limit in miniaturizing the width W2 of the second through-hole 32.

[0195] Furthermore, the protective layer 30 forms the first through-hole 31 and the second through-hole 32 by performing an exposure and curing process. At this time, in the process of exposing and curing the protective layer 30, there is a problem that the lower region of the protective layer 30 is not completely cured. And when it is not completely cured, in the process of forming the second through-hole 32, a problem occurs in that an undercut 33 is formed in the lower region of the side wall of the second through-hole 32.

[0196] At this time, the horizontal distance W3 of the undercut 33 of the comparative example exceeds 15 μm or exceeds 20 μm. The horizontal distance W3 of the undercut 33 means the horizontal distance between the innermost end and the outermost end in the lower region of the side wall of the second through-hole 32.

[0197] At this time, the circuit pattern layer includes a trace 23 arranged adjacent to the second pad 22. And in the comparative example, the horizontal distance W3 of the undercut 33 must be considered when arranging the trace 23. That is, in the comparative example, if the horizontal distance W3 of the undercut 33 is not considered, the side portion of the trace 23 may be exposed through the undercut 33. In this case, the solder ball arranged on the second pad 22 diffuses to the undercut 33, thereby causing a circuit short problem of contacting the trace 23. Therefore, in the comparative example, the separation interval between the second pad 22 and the trace 23 is determined in consideration of the width W2 of the second through hole 32 and the horizontal distance W3 of the undercut 33. Therefore, in the comparative example, the separation interval increases, resulting in a problem of a decrease in circuit integration degree.

[0198] Also, as the performance of electrical / electronic products has been improving recently, technologies for attaching more semiconductor elements to a substrate of limited size have been studied, and thus miniaturization of circuit patterns has been required. In the case of a semiconductor package using the circuit board of the comparative example, the minimum width limit of the through holes that can be formed in the protective layer 30 and the horizontal distance of the undercut must be considered, and thus there is a limit to miniaturizing the circuit pattern.

[0199] Furthermore, recently, the functions processed by logic chips such as application processors (APs) have been increasing. This makes it difficult to implement all functions with one logic chip. Therefore, the circuit board requires a space for mounting a plurality of logic chips. However, it is difficult to mount a plurality of logic chips having different functions from each other in a limited space using the circuit board of the comparative example.

[0200] Also, the upper surface of the protective layer 30 of the comparative example is substantially formed in a flat plane. Thus, in order to prevent the diffusion of connection parts such as solder arranged in the through holes of the protective layer 30, the thickness of the protective layer 30 must be increased.

[0201] That is, the protective layer 30 of the comparative example does not include a barrier structure for preventing the diffusion of solder. As a result, in the case where the thickness of the protective layer 30 is reduced in the comparative example, a solder short problem due to the diffusion of solder occurs.

[0202] Also, in the case where the thickness of the protective layer 30 is increased in the comparative example, there may be a problem that the design distance is deviated during the filling of the epoxy molding compound after chip mounting, resulting in an unfilled region problem.

[0203] The embodiment is for solving such problems, and a barrier structure capable of preventing the diffusion of solder is provided on the upper surface of the protective layer. That is, the protective layer of the embodiment is provided adjacent to the through hole and includes a convex portion surrounding the upper region of the through hole. Then, the embodiment can improve the reliability of the solder disposed in the through hole by using the convex portion. Also, the embodiment can significantly reduce the width of the through hole that can be formed in the protective layer compared to the comparative example. Also, the embodiment can minimize the horizontal distance of the undercut formed on the side wall of the through hole of the protective layer or remove the undercut. Also, the embodiment can reduce the tolerance (SRR: Solder Resist Registration) between the center of the through hole of the protective layer and the center of the pad. Also, the embodiment can improve the electrical and mechanical properties and improve the bonding force with the molding layer.

[0204] FIG. 10 is a cross-sectional view showing a circuit board according to the sixth embodiment, FIG. 11 is a cross-sectional view specifically showing one region of the circuit board of FIG. 10, FIG. 12 is a cross-sectional view specifically showing another region of the circuit board of FIG. 11, FIG. 13 is a cross-sectional view of one region of the circuit board for explaining the convex portion of the embodiment, FIG. 14 is a plan view of one region of the circuit board for explaining the convex portion of the embodiment, FIG. 15 is a scanning electron microscope image showing one region of the circuit board of FIGS. 13 and 14, FIG. 16 is a scanning electron microscope image showing the upper surface of the first protective layer of FIG. 12, FIG. 17 is a scanning electron microscope image showing the inner surface of the through hole of the first protective layer of FIG. 12, and FIG. 18 is a drawing showing a resist pattern used to form the through hole of the first protective layer of the embodiment.

[0205] Hereinafter, with reference to FIGS. 10 to 18, the circuit board according to the sixth embodiment will be specifically described.

[0206] The circuit board 4100 of the sixth embodiment includes an insulating layer 4110, an upper wiring electrode 4120, and a lower wiring electrode 4130. The upper wiring electrode 4120 can mean the upper wiring electrode 140a1 disposed at the uppermost part of the insulating layer in the previous embodiment. Also, the lower wiring electrode 4130 can mean the fifth wiring electrode 140a6 disposed at the lowermost part of the insulating layer in the previous embodiment.

[0207] The upper wiring electrode 4120 includes a first pad 4120-1, a second pad 4120-2, and a third pad 4120-3. The first pad 4120-1, the second pad 4120-2, and the third pad 4120-3 of the upper wiring electrode 4120 can be classified by their widths. For example, the first pad 4120-1 can have a width larger than the width of the second pad 4120-2 and smaller than the width of the third pad 4120-3. For example, the second pad 4120-2 can have a width smaller than the width of the first pad 4120-1 and the width of the third pad 4120-3. For example, the third pad 4120-3 can have a width larger than the widths of the first pad 4120-1 and the second pad 4120-2.

[0208] The upper wiring electrode 4120 is required to be miniaturized, which reduces the spacing between a plurality of pads. Also, when the miniaturization is realized and the spacing between the plurality of pads is reduced, the circuit integration degree can be improved, but solder shorts may occur due to the diffusion of solder during solder placement. Accordingly, the embodiment includes a barrier structure in the protective layer that can prevent the diffusion of solder.

[0209] The upper wiring electrode 4120 and the lower wiring electrode 4130 can each have a plurality of layer structures.

[0210] The upper wiring electrode 4120 can include a first metal layer 4121 and a second metal layer 4122. That is, each of the first pad 4120-1, the second pad 4120-2, and the third pad 4120-3 of the upper wiring electrode 4120 can include the first metal layer 4121 and the second metal layer 4122.

[0211] The first metal layer 4121 of the upper wiring electrode 4120 can protrude on the upper surface of the insulating layer 4110. The first metal layer 4121 of the upper wiring electrode 4120 may be an electroless metal layer. The thickness of the first metal layer 4121 of the upper wiring electrode 4120 can satisfy the range of 0.2 μm to 3.0 μm. Preferably, the thickness of the first metal layer 4121 of the upper wiring electrode 4120 can satisfy the range of 0.3 μm to 2.8 μm. More preferably, the thickness of the first metal layer 4121 of the upper wiring electrode 4120 can satisfy the range of 0.5 μm to 2.5 μm. When the thickness of the first metal layer 4121 of the upper wiring electrode 4120 is less than 0.2 μm, the first metal layer 4121 of the upper wiring electrode 4120 may not be able to function as a seed layer. When the thickness of the first metal layer 4121 of the upper wiring electrode 4120 is less than 0.2 μm, it becomes difficult to form the first metal layer 4121 with a uniform thickness on the upper surface of the insulating layer 4110. When the thickness of the first metal layer 4121 of the upper wiring electrode 4120 exceeds 3.0 μm, the process time for forming the first metal layer 4121 of the upper wiring electrode 4120 increases, and the yield thereby decreases. Also, when the thickness of the first metal layer 4121 of the upper wiring electrode 4120 exceeds 3.0 μm, the etching time of the first metal layer 4121 in the forming process of the upper wiring electrode 4120 increases. Also, when the thickness of the first metal layer 4121 of the upper wiring electrode 4120 exceeds 3.0 μm, deformation of the second metal layer 4122 of the upper wiring electrode 4120 may occur during etching of the first metal layer 4121. Here, the deformation of the second metal layer 4122 of the upper wiring electrode 4120 can mean that the difference between the width of the upper surface and the width of the lower surface of the second metal layer 4122 becomes large because the side portion of the second metal layer 4122 is also etched together during etching of the first metal layer 4121. For example, the deformation of the second metal layer 4122 of the upper wiring electrode 4120 can mean that the shape of the vertical cross-section of the second metal layer 4122 changes from a rectangle to a trapezoid. Also, when the thickness of the first metal layer 4121 of the upper wiring electrode 4120 exceeds 3.0 μm, the etching amount in the etching process of the first metal layer 4121 increases, and thereby the depth of the depressions (for example, undercuts) formed on the side portions of the first metal layer 4121 and the side portions of the second metal layer 4122 increases.For example, when the etching amount in the etching process of the first metal layer 4121 increases, the difference between the width of the first metal layer 4121 and the width of the second metal layer 4122 becomes larger. And when the difference between the width of the first metal layer 4121 and the width of the second metal layer 4122 becomes larger, the electrical characteristics deteriorate due to an increase in signal transmission loss. Also, when the difference between the width of the first metal layer 4121 and the width of the second metal layer 4122 becomes larger, resin dendrites are formed by electromigration, thereby deteriorating the electrical and / or physical characteristics of the upper wiring electrode 4120. The second metal layer 4122 of the upper wiring electrode 4120 may be an electrolytic plating layer electrolytically plated using the first metal layer 4121 as a seed layer. The second metal layer 4122 of the upper wiring electrode 4120 is formed on the first metal layer 4121 with a certain thickness. The second metal layer 4122 of the upper wiring electrode 4120 can include the same metal as the first metal layer 4121 of the upper wiring electrode 4120, but is not limited thereto. As an example, the first metal layer 4121 and the second metal layer 4122 of the upper wiring electrode 4120 can each include copper.

[0212] The thickness of the second metal layer 4122 of the upper wiring electrode 4120 may be greater than the thickness of the first metal layer 4121 of the upper wiring electrode 4120. The thickness of the second metal layer 4122 of the upper wiring electrode 4120 can satisfy the range of 3.5 μm to 25 μm. Preferably, the thickness of the second metal layer 4122 of the upper wiring electrode 4120 can satisfy the range of 4.0 μm to 23 μm. More preferably, the thickness of the second metal layer 4122 of the upper wiring electrode 4120 can satisfy the range of 4.5 μm to 22 μm. When the thickness of the second metal layer 4122 of the upper wiring electrode 4120 is less than 3.5 μm, the second metal layer 4122 will also be etched together in the etching process of the first metal layer 4121. When the thickness of the second metal layer 4122 of the upper wiring electrode 4120 is less than 3.5 μm, the allowable current of the signal transmitted through the upper wiring electrode decreases, resulting in a decline in electrical characteristics. When the thickness of the second metal layer 4122 of the upper wiring electrode 4120 exceeds 25 μm, it becomes difficult to miniaturize the upper wiring electrode 4120. For example, when the thickness of the second metal layer 4122 of the upper wiring electrode 4120 exceeds 25 μm, the width and spacing of the patterns constituting the upper wiring electrode 4120 cannot meet the required conditions. As a result, the circuit integration degree decreases, or the volume of the circuit board and the semiconductor package increases.

[0213] The lower wiring electrode 4130 can include a first metal layer 4131 and a second metal layer 4132 so as to correspond to the upper wiring electrode 4120.

[0214] The circuit board 4100 can include via electrodes 4140. The via electrodes 4140 can penetrate the insulating layer 4110. Preferably, the via electrodes 4140 can penetrate the insulating layer 4110 so as to electrically connect between the upper wiring electrode 4120 and the lower wiring electrode 4130. At this time, when the insulating layer 4110 has a multi-layer structure, the via electrodes 4140 can be vertically separated to electrically connect between adjacent wiring electrodes.

[0215] Also, the via electrodes 4140 include a first metal layer 4141 and a second metal layer 4142 so as to correspond to the upper wiring electrode and the lower wiring electrode.

[0216] On the insulating layer 4110, a first protective layer 4150 can be included. For example, the circuit board 4100 can include a second protective layer 4160 disposed under the insulating layer 4110.

[0217] The first protective layer 4150 includes at least one through hole. Also, the second protective layer 4160 includes at least one through hole. At this time, although not shown in the drawings, the through hole of the first protective layer 4150 is provided with a bonding portion 150 as shown in FIGS. 1a to 1d.

[0218] Also, the first protective layer 4150 and the second protective layer 4160 can include convex portions 4150P and 4160P. The convex portions 4150P and 4160P are provided on the surfaces of the first protective layer 4150 and the second protective layer 4160. Also, the convex portion 4150P of the first protective layer 4150 is provided surrounding the periphery of the through portion of the bonding portion 150. That is, the convex portion 4150P of the first protective layer 4150 is provided on the first protective layer 120 shown in FIGS. 1a to 1d, whereby the bonding portion 150 can include a portion surrounded by the convex portion 4150 of the first protective layer 4150.

[0219] That is, the insulating layer 4100 includes a side surface located between the upper surface and the lower surface. Also, the first protective layer 4150 includes a lower surface facing the upper surface of the insulating layer 4100, an upper surface corresponding to the lower surface of the first protective layer 4150, and a side surface between the upper surface and the lower surface of the first protective layer 4150. At this time, the side surface of the first protective layer 4150 includes an inner surface surrounding the through portion of the bonding portion 150 and an outer surface adjacent to the side surface of the insulating layer 4100. Also, the vertical length of the inner surface of the first protective layer 4150 is different from the vertical length of the outer surface of the first protective layer 4150. Exemplarily, the vertical length of the inner surface of the first protective layer 4150 is greater than the vertical length of the outer surface. Thereby, the embodiment can make the bonding portion 150 be more stably supported by the first protective layer 4150, thereby improving the physical reliability and / or electrical reliability of the bonding portion 150.

[0220] That is, the first protective layer 4150 includes a convex portion 4150P. Further, the second protective layer 4160 includes a convex portion 4160P.

[0221] The convex portion 4150P of the first protective layer 4150 can bulge upward from the upper surface of the first protective layer 4150. Preferably, the convex portion 4150P of the first protective layer 4150 can protrude upward from the upper surface of the first protective layer 4150 adjacent to the through hole.

[0222] Specifically, the first protective layer 4150 is divided into a plurality of regions in the horizontal direction. For example, the first protective layer 4150 includes a through hole and a first region R1 adjacent to the through hole. Further, the first protective layer 4150 includes a second region R2 other than the first region R1. And the first region R1 of the first protective layer 4150 can have a first height. At this time, the first height can mean the vertical distance from the upper surface of the insulating layer 4110 to the upper surface of the first region R1 of the first protective layer 4150. Also, the second region R2 of the first protective layer 4150 can have a second height different from the first height. The second height can mean the vertical distance from the upper surface of the insulating layer 4110 to the upper surface of the second region R2 of the first protective layer 4150. And the first height may be greater than the second height. That is, the upper surface of the first protective layer 4150 in the embodiment can include a region where the height increases as it is adjacent to the through hole. For example, in the first region R1 of the first protective layer 4150, a convex portion 4150P is formed which is located higher than the second region R2 of the first protective layer 4150 and bulges upward.

[0223] The convex portion 4160P of the second protective layer 4160 can bulge downward from the lower surface of the second protective layer 4160. Preferably, the convex portion 4160P of the second protective layer 4160 can protrude downward from the lower surface of the second protective layer 4160 adjacent to the through hole. Also, the second protective layer 4160 can include a first region and a second region so as to correspond to the first protective layer 4150. And the first height of the first region of the second protective layer 4160 may be greater than the second height of the second region. At this time, the first height of the first region of the second protective layer 4160 can mean the vertical distance from the lower surface of the insulating layer 4110 to the lower surface of the first region of the second protective layer 4160. Also, the second height of the second region of the second protective layer 4160 can mean the vertical distance from the lower surface of the insulating layer 4110 to the lower surface of the second region of the second protective layer 4160.

[0224] The first protective layer 4150 includes a first through hole 4151. For example, the first protective layer 4150 can include a first through hole 4151 that vertically overlaps with the first pad 4120-1 of the upper wiring electrode 4120.

[0225] The first through hole 4151 of the first protective layer 4150 can partially overlap vertically with the upper surface of the first pad 4120-1. The width W1 of the first through hole 4151 of the first protective layer 4150 may be smaller than the width of the upper surface of the first pad 4120-1. For example, the first protective layer 4150 can include a first through hole 4151 that covers at least a part of the upper surface of the first pad 4120-1 and exposes the remaining part of the upper surface of the first pad 4120-1.

[0226] The width W1 of the first through hole 4151 of the first protective layer 4150 can satisfy the range of 10 μm to 20 μm. Preferably, the width W1 of the first through hole 4151 of the first protective layer 4150 can satisfy the range of 12 μm to 20 μm. More preferably, the width W1 of the first through hole 4151 of the first protective layer 4150 can satisfy the range of 13 μm to 20 μm.

[0227] At this time, when the first through-hole 4151 of the first protective layer 4150 has a width change in the thickness direction, the width W1 of the first through-hole 4151 can mean the width of the region having the maximum width in the entire region.

[0228] When the width W1 of the first through-hole 4151 of the first protective layer 4150 is less than 10 μm, the coating amount of a connection part such as a solder ball disposed in the first through-hole 4151 decreases, and thereby the bonding force with the semiconductor element decreases. When the width W1 of the first through-hole 4151 of the first protective layer 4150 exceeds 20 μm, the width of the first pad 4120-1 also increases correspondingly, and thereby the circuit integration degree decreases.

[0229] The first through-hole 4151 of the first protective layer 4150 has almost no width change from the region adjacent to the upper surface of the first protective layer 4150 to the region adjacent to the lower surface of the first protective layer 4150. Here, having almost no width change can mean that the inclination of the first inner surface 4151S of the first protective layer 4150 constituting the first through-hole 4151 is close to vertical. For example, having almost no width change can mean that in the entire region of the first through-hole 4151 in the thickness direction, the difference between the width of the region having the maximum width and the width of the region having the minimum width is 3 μm or less, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1 μm or less, or 0.5 μm or less. The first through-hole 4151 of the first protective layer 4150 is formed using a resist pattern as described in the previous embodiments.

[0230] The upper surface 4150T of the first protective layer 4150 can have a surface roughness different from the surface roughness of the first inner surface 4151S of the first through-hole 4151.

[0231] That is, the upper surface 4150T of the first protective layer 4150 is different from the roughness of the inner surface 4150S of the through-hole of the first protective layer 4150 (see FIG. 17). The inner surface 4150S of the through-hole can include the first inner surface 4151S of the first through-hole 4151 and the second inner surface 4152S of the second through-hole 4152. The surface roughness of the upper surface 4150T of the first protective layer 4150 may be greater than the surface roughness of the inner surface of the through-hole of the first protective layer 4150.

[0232] Referring to FIG. 16, the first protective layer 4150 includes a resin and a filler 4150F dispersed in the resin. At this time, when the first protective layer 4150 is etched using a chemical solution and / or plasma, etc., the filler 4150F disposed in the first protective layer 4150 can be exposed on the upper surface 4150T of the first protective layer 4150. On the contrary, the filler 4150F may not be exposed on the inner surface 4150S of the through-hole of the first protective layer 4150, or a smaller amount of filler may be exposed than on the upper surface 4150T. Therefore, the upper surface 4150T of the first protective layer 4150 can have a surface roughness greater than that of the inner surface of the through-hole of the first protective layer 4150 due to the filler 4150F.

[0233] The surface roughness of the upper surface 4150T of the first protective layer 4150 can be increased through the filler 4150F exposed through the upper surface 4150T of the first protective layer 4150. Thereby, in the molding process after mounting the semiconductor element on the circuit board in the embodiment, the bonding area between the first protective layer 4150 and the molding layer can be increased, and thereby the bonding force can be improved.

[0234] The first protective layer 4150 includes a second through-hole 4152. For example, the first protective layer 4150 can include a second through-hole 4152 that vertically overlaps with the second pad 4120-2 of the upper wiring electrode 4120.

[0235] At this time, the second through-hole 4152 of the first protective layer 4150 can entirely overlap perpendicularly with the upper surface of the second pad 4120-2. That is, the width W2 of the second through-hole 4152 of the first protective layer 4150 may be larger than the width of the upper surface of the second pad 4120-2. For example, the first protective layer 4150 can entirely expose the upper surface and the inner surface of the second pad 4120-2. For example, the second inner surface 4152S of the second through-hole 4152 of the first protective layer 4150 can be separated from and not in contact with the second pad 4120-2. For example, the second pad 4120-2 may not be in contact with the first protective layer 4150.

[0236] At this time, instead of exposing and developing the protective layer itself such as a solder resist, the example exposes and develops a photosensitive film capable of relatively finely forming a pattern to form a resist pattern. Then, the example uses the resist pattern to form a through-hole in the first protective layer 4150. Therefore, the example can reduce the size of the through-hole formed in the first protective layer 4150 compared to the comparative example, thereby improving the circuit integration density.

[0237] At this time, since the example does not expose and develop the first protective layer 4150, the first protective layer 4150 may not contain a photoinitiator. For example, a general solder resist contains a photoinitiator for exposure and development. At this time, the photoinitiator acts as a factor that degrades the physical and electrical characteristics of the circuit board.

[0238] Here, since the example does not expose and develop the first protective layer 4150, the first protective layer 4150 does not contain a photoinitiator. Thereby, the example can improve the physical and electrical characteristics of the circuit board because the first protective layer 4150 does not contain a photoinitiator.

[0239] In addition, since the example does not contain a photoinitiator in the first protective layer 4150, the types of insulating layers that can be used as the first protective layer 4150 can be expanded, and thus the cost required for the development of the protective layer can be reduced.

[0240] For example, the first protective layer 4150 of the embodiment may be a solder resist without a photoinitiator. Alternatively, the first protective layer 4150 of the embodiment may use an insulating layer that does not contain glass fibers but has inorganic fillers such as silica or alumina disposed in a thermosetting resin or a thermoplastic resin. For example, the first protective layer 4150 can use ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), PID (Photo Imagable Dielectric resin), etc.

[0241] However, it is also possible to implement the first protective layer 4150 and the second protective layer 4160 of the present application by directly using the solder resist used in a general circuit board according to the embodiment. For example, according to the embodiment, the first protective layer 4150 and the second protective layer 4160 can also contain a photoinitiator.

[0242] A convex portion 4150P is provided on the upper surface 4150T of the first protective layer 4150.

[0243] For example, in the first protective layer 4150, the first height in the first region R1 may be greater than the second height in the second region R2 due to the convex portion 4150P.

[0244] The first region R1 of the first protective layer 4150 is a region adjacent to the through hole formed in the first protective layer 4150. For example, in the first region R1 of the first protective layer 4150, a convex portion 4150P that bulges upward is formed.

[0245] At this time, the convex portion 4150P is formed so as to be adjacent to the through hole on the upper surface of the first protective layer 4150. For example, the convex portion 4150P can bulge upward in the upper region of the through hole of the first protective layer 4150. For example, the convex portion 4150P can be connected to the through hole of the first protective layer 4150 and bulge upward.

[0246] Preferably, the convex portion 4150P is formed surrounding the inner edge portion of the through hole of the first protective layer 4150. The convex portion 4150P is connected to the through hole of the first protective layer 4150. Thus, the inner region of the convex portion 4150P connected to the through hole can also be regarded as a part of the through hole.

[0247] At this time, the convex portion 4150P does not follow the profile of the surface of the upper wiring electrode 4120 disposed on the upper surface of the insulating layer 4110. Exemplarily, a general protective layer is formed following the profile of the wiring electrode. For example, a general protective layer has a large height in the region overlapping the wiring electrode vertically and a small height in the region not overlapping the wiring electrode. This is a structural feature manifested by the difference in surface height in the process of forming the protective layer. That is, the region of the protective layer overlapping the wiring electrode has a larger height than the region not overlapping the wiring electrode, and thus this region can also be referred to as a convex portion. However, this is different from the structural feature of the convex portion 4150P of the present application.

[0248] That is, a general protective layer formed following the profile of the wiring electrode: 1) the entire region overlapping the wiring electrode bulges; 2) the entire region not overlapping the wiring electrode does not bulge.

[0249] In contrast, the first protective layer 4150 of the present application in which the convex portion 4150P is formed with reference to the through hole of the present application: 1) the region adjacent to the through hole bulges; 2) at this time, the bulging region includes not only the region overlapping the wiring electrode vertically but also the region not overlapping vertically; 3) the region separated from the through hole among the regions overlapping the wiring electrode vertically does not bulge.

[0250] At this time, the filler 4150F described above is exposed on the upper surfaces 4150T of the first region R1 and the second region R2 of the first protective layer 4150. That is, the convex portion 4150P of the present application is not a structure naturally formed by the profile of the wiring electrode, but a structural feature provided in the process of forming the through hole of the first protective layer 4150 of the present application. And the convex portion 4150P of the embodiment can function as a barrier structure for preventing the diffusion of a connection portion such as a solder ball in the packaging process.

[0251] Referring to FIGS. 11, 14(a), and 15, the first protective layer 4150 includes a first convex portion 4151P. The first convex portion 4151P is formed in a region adjacent to the first through hole 4151 on the upper surface of the first protective layer 4150. For example, the first convex portion 4151P is formed in the first region R1 of the first protective layer 4150 adjacent to the first through hole 4151. The first convex portion 4151P is provided so as to surround the inner edge portion of the upper surface of the first through hole 4151. The first convex portion 4151P is positioned adjacent to the first through hole 4151. At this time, the first inner surface 4151S of the first through hole 4151 vertically overlaps the first pad 4120-1. And the first convex portion 4151P is connected to the first inner surface 4151S of the first through hole 4151. Thereby, the first convex portion 4151P can vertically overlap the first pad 4120-1. At this time, the upper surface of the upper surface 4150T of the first protective layer 4150 that is adjacent to the first convex portion 4151P and vertically overlaps the first pad 4120-1 may be flat without bulging. At this time, being flat can mean that the height deviation in the entire region of the upper surface is 1 μm or less, 0.8 μm or less, 0.5 μm or less, or 0.2 μm or less. At this time, the height deviation can be divided into the height deviation in the portion where the filler 4150F is exposed and the height deviation in the portion where the filler 4150F is not exposed.

[0252] The first convex portion 4151P of the first through hole 4151 can partially overlap the first pad 4120-1 vertically. This can mean that the first region R1 of the first protective layer 4150 adjacent to the first through hole 4151 partially overlaps the first pad 4120-1 vertically. For example, the second region R2 of the first protective layer 4150 may not overlap the first pad 4120-1 vertically. The first convex portion 4151P or the first region R1 can include an overlapping region that overlaps the first pad 4120-1 vertically and a non-overlapping region that does not overlap the first pad 4120-1 vertically.

[0253] Referring to FIGS. 11 and 14(b), the first protective layer 4150 includes a second convex portion 4152P. The second convex portion 4152P is formed in the first region R1 of the first protective layer 4150 adjacent to the second through hole 4152 on the upper surface of the first protective layer 4150. Preferably, the second convex portion 4152P is provided to surround the periphery of the inner edge portion of the upper surface of the second through hole 4152. At this time, the second inner surface 4152S of the second through hole 4152 does not overlap the second pad 4120-2 vertically. And the second convex portion 4152P is connected to the second inner surface 4152S of the second through hole 4152. Thereby, the second convex portion 4152P may not overlap the second pad 4120-2 vertically. That is, the second convex portion 4160P arranged adjacent to the second through hole 4152 may not overlap the upper wiring electrode 4120 vertically unlike the first convex portion 4151P.

[0254] That is, the second convex portion 4152P or the first region R1 of the first protective layer 4150 adjacent to the second through hole 4152 may not overlap the upper wiring electrode 4120 including the second pad 4120-2 vertically.

[0255] Referring to FIG. 12, the first protective layer 4150 may include a third convex portion. The first protective layer 4150 may include a third through hole 4153 that vertically overlaps with the third pad 4120-3 of the upper wiring electrode 4120. At this time, the third through hole 4153 can be divided into a plurality of sub-through holes. The third pad 4120-3 may be a ground pad. For example, the third pad 4120-3 may be a large area pad.

[0256] Accordingly, the first protective layer 4150 includes a third through hole 4153 including a plurality of sub-through holes that partially expose the third pad 4120-3. The third through hole 4153 may include a first sub-through hole 4153-1 that partially exposes the third pad 4120-3. Also, the third through hole 4153 may include a second sub-through hole 4153-2 that is separated from the first sub-through hole 4153-1 and partially exposes the third pad 4120-3.

[0257] The first protective layer 4150 may include a third convex portion adjacent to the third through hole 4153. For example, the third convex portion of the first protective layer 4150 includes a 3-1 convex portion 4153-1P that surrounds the upper part of the first sub-through hole 4153-1 of the third through hole 4153. Also, the third convex portion of the first protective layer 4150 includes a 3-2 convex portion 4153-2P that surrounds the upper part of the second sub-through hole 4153-2 of the third through hole 4153. At this time, the upper surface 153F of the first protective layer 4150 that vertically overlaps with the third pad 4120-3 and is between the 3-1 convex portion 4153-1P and the 3-2 convex portion 4153-2P may be flat without bulging. That is, the upper surface 153F between the 3-1 convex portion 4153-1P and the 3-2 convex portion 4153-2P can be positioned lower than the 3-1 convex portion 4153-1P and the 3-2 convex portion 4153-2P.

[0258] The first convex portion 4151P will be specifically described. Also, the second convex portion 4152P and the third convex portion 4153P may have a structure corresponding to the first convex portion 4151P described below.

[0259] Referring to FIG. 5, the first convex portion 4151P is provided so as to surround the upper region of the first through hole 4151 in a closed loop shape. That is, the first region R1 of the first protective layer 4150 is disposed in the upper region of the first through hole 4151 so as to surround the periphery of the first through hole 4151.

[0260] The first convex portion 4151P can have a shape in which the width decreases or remains the same from the lower surface to the upper surface. The width of the first convex portion 4151P can mean the horizontal distance of the first convex portion 4151P. For example, the height of the first region R1 of the first protective layer 4150 including the first convex portion 4151P can decrease as it is adjacent to the second region R2. The vertical cross-sectional shape of the first convex portion 4151P may be triangular, but is not limited thereto. For example, the vertical cross-sectional shape of the first convex portion 4151P may be provided in various shapes such as a stepped shape, a fan shape, a polygonal shape, etc.

[0261] At this time, the first convex portion 4151P is formed in the process of etching the first protective layer 4150 using the resist pattern DFR1-F. That is, when etching the first protective layer 4150 using the resist pattern DFR1-F, it can be formed by adjusting the etching conditions in the region adjacent to the resist pattern DFR1-F. Then, by adjusting the etching conditions, the shape, width, thickness, and outer inclination of the first convex portion 4151P can be controlled.

[0262] The first convex portion 4151P includes an inner surface 4151PS1 and an outer surface 4151PS2. The inner surface 4151PS1 of the first convex portion 4151P is connected to the first inner surface 4151S of the first through hole 4151. Thereby, the inner surface 4151PS1 of the first convex portion 4151P can also be said to be a part of the first inner surface 4151S of the first through hole 4151. The inner surface 4151PS1 of the first convex portion 4151P can have a certain inclination. For example, the inner surface 4151PS1 of the first convex portion 4151P can have an inclination corresponding to the inclination of the first inner surface 4151S of the first through hole 4151.

[0263] The inner surface 4151PS1 of the first convex portion 4151P can have a constant height. For example, the inner surface 4151PS1 of the first convex portion 4151P can have a vertical length T1 corresponding to the thickness of the first convex portion 4151P. The vertical length T1 can mean any one of the vertical length of the inner surface 4151PS1 of the first convex portion 4151P, the vertical length of the outer surface 4151PS2, and the thickness of the first convex portion 4151P. Also, the vertical length T1 can mean the difference between the first height of the first region R1 and the second height of the second region R2 of the first protective layer 4150.

[0264] The vertical length T1 or the thickness of the first convex portion 4151P can satisfy the range of 1.0 μm to 4.0 μm. Preferably, the vertical length T1 or the thickness of the first convex portion 4151P can satisfy the range of 1.2 μm to 3.8 μm. The vertical length T1 or the thickness of the first convex portion 4151P can satisfy the range of 1.5 μm to 3.5 μm. When the vertical length T1 or the thickness of the first convex portion 4151P is less than 1.0 μm, the effect represented by the first convex portion 4151P becomes negligible. For example, when the vertical length T1 or the thickness of the first convex portion 4151P is less than 1.0 μm, the solder diffusion prevention effect or the solder short prevention effect becomes negligible. When the vertical length T1 or the thickness of the first convex portion 4151P exceeds 4.0 μm, the distance between the first pad 4120-1 and the semiconductor element at the position where the first convex portion 4151P is disposed increases, and thus the signal transmission loss due to the increase in the signal transmission distance increases. Also, when the vertical length T1 or the thickness of the first convex portion 4151P exceeds 4.0 μm, in order for the first convex portion 4151P to maintain a certain strength, the width of the first convex portion 4151P has to increase, and an unfilled region is generated during the formation of the molding layer thereby.

[0265] The width W3 of the first convex portion 4151P can satisfy the range of 0.5 μm to 2.5 μm. Preferably, the width W3 of the first convex portion 4151P can satisfy the range of 0.7 μm to 2.3 μm. More preferably, the width W3 of the first convex portion 4151P can satisfy the range of 0.9 μm to 2.0 μm. The width W3 of the first convex portion 4151P can mean the maximum width in the entire region in the thickness direction of the first convex portion 4151P. For example, the width W3 of the first convex portion 4151P can mean the width of the first region R1 of the first protective layer 4150 adjacent to the first through hole 4151. When the width W3 of the first convex portion 4151P is less than 0.5 μm, the strength of the first convex portion 4151P decreases. And when the width W3 of the first convex portion 4151P is less than 0.5 μm, there may occur a problem that the first convex portion 4151P collapses due to the pressure applied in the process of arranging a connection portion such as a solder ball in the first through hole 4151. Also, when the width W3 of the first convex portion 4151P exceeds 2.5 μm, the molding layer in the region is not filled, and thus physical and / or electrical reliability problems may occur due to non-molding.

[0266] The outer surface 4151PS2 of the first convex portion 4151P can have a constant inclination angle θ. The inclination angle θ of the outer surface 4151PS2 of the first convex portion 4151P can mean the inclination of a virtual straight line connecting the uppermost end and the lowermost end of the outer surface 4151PS2 of the first convex portion 4151P. Specifically, the inclination angle θ of the outer surface 4151PS2 of the first convex portion 4151P can mean the inner angle formed by the outer surface 4151PS2 of the first convex portion 4151P and the lower surface of the first convex portion 4151P. For example, the inclination angle θ of the outer surface 4151PS2 of the first convex portion 4151P can mean the inclination angle of the upper surface of the first region R1 of the first protective layer 4150. For example, the inclination angle θ of the outer surface 4151PS2 of the first convex portion 4151P can mean the inner angle between the upper surface and the lower surface of the first region R1 of the first protective layer 4150. The inclination angle θ of the outer surface 4151PS2 of the first convex portion 4151P can satisfy the range between 50 degrees and 75 degrees. Preferably, the inclination angle θ of the outer surface 4151PS2 of the first convex portion 4151P can satisfy the range between 52 degrees and 73 degrees. More preferably, the inclination angle θ of the outer surface 4151PS2 of the first convex portion 4151P can satisfy the range between 55 degrees and 70 degrees. If the inclination angle θ of the outer surface 4151PS2 of the first convex portion 4151P is less than 50 degrees, the width W3 of the first convex portion 4151P increases, and reliability problems may occur in the filling process of the molding layer due to this. Also, if the inclination angle θ of the outer surface 4151PS2 of the first convex portion 4151P exceeds 75 degrees, the rigidity of the first convex portion 4151P becomes weak or the vertical length T1 of the first convex portion 4151P increases.

[0267] FIG. 19 is a plan view for explaining the tolerance (SRR: Solder Resist Registration) according to the comparative example, and FIG. 20 is a drawing for explaining the tolerance according to the sixth embodiment.

[0268] Referring to Fig. 19(a), in the case of the comparative example, the first pad 21 includes a first portion 21a exposed through the first through-hole 31 of the protective layer 30 and a second portion 21b covered by the protective layer 30. At this time, in the comparative example, the protective layer 30 is exposed and developed to form the first through-hole 31. At this time, the exposure resolution of the protective layer 30 is significantly lower than that of the DFR. Accordingly, in the comparative example, it can be confirmed that the center 21C of the first pad 21 and the center 31C of the first through-hole 31 are displaced by a first tolerance d1. Specifically, the first tolerance d1 between the center 21C of the first pad 21 and the center 31C of the first through-hole 31 in the comparative example exceeds 12.5 μm or exceeds 14 μm or exceeds 15 μm. Accordingly, in the comparative example, an alignment reliability problem may occur in which at least a part of the first through-hole 31 does not overlap perpendicularly with the first pad 21.

[0269] Referring to Fig. 19(b), in the case of the comparative example, the second pad 22 is entirely exposed through the second through-hole 32 of the protective layer 30. At this time, in the comparative example, the protective layer 30 is exposed and developed to form the second through-hole 32. At this time, the exposure resolution of the protective layer 30 is significantly lower than that of the DFR. Accordingly, in the comparative example, it can be confirmed that the center 22C of the second pad 22 and the center 32C of the second through-hole 32 are displaced by a second tolerance d2. Specifically, the second tolerance d2 between the center 22C of the second pad 22 and the center 32C of the second through-hole 32 in the comparative example exceeds 12.5 μm or exceeds 14 μm or exceeds 15 μm. Accordingly, in the comparative example, an alignment reliability problem may occur in which at least a part of the upper surface of the second pad 22 is covered by the protective layer 30.

[0270] In contrast, the embodiment can significantly reduce the tolerance compared to the comparative example.

[0271] For example, referring to FIG. 20(a), in the case of the embodiment, the first pad 4120-1 includes a first portion 4120-1a exposed through the first through hole 4151 of the first protective layer 4150 and a second portion 4120-1b covered by the first protective layer 4150. At this time, in the embodiment, instead of exposing and developing the first protective layer 4150 to form the first through hole 4151, the resist pattern DFR1-F formed by DFR is used. Thereby, in the embodiment, it can be confirmed that the center 4120-1C of the first pad 4120-1 and the center 4151C of the first through hole 4151 are deviated by a third tolerance d1 which is significantly smaller than the first tolerance d1 of the comparative example. Specifically, the third tolerance d1 between the center 4120-1C of the first pad 4120-1 and the center 4151C of the first through hole 4151 in the embodiment is 10 μm or less or 9 μm or less or 8 μm or less. Therefore, the embodiment can improve the alignment accuracy between the first through hole 4151 and the first pad 4120-1. Thereby, the embodiment can further improve the electrical reliability and / or physical reliability of the circuit board.

[0272] Also, referring to FIG. 20(b), in the case of the embodiment, the second pad 4120-2 is entirely exposed through the second through hole 4152 of the first protective layer 4150. At this time, in the embodiment, instead of exposing and developing the first protective layer 4150 to form the second through hole 4152, the resist pattern DFR1-F formed by DFR is used. Thereby, in the embodiment, it can be confirmed that the center 4120-2C of the second pad 4120-2 and the center 4152C of the second through hole 4152 are deviated by a fourth tolerance d2 which is significantly smaller than the second tolerance d2 of the comparative example. Specifically, the fourth tolerance d2 between the center 4120-1C of the second pad 4120-2 and the center 4152C of the second through hole 4152 in the embodiment is 10 μm or less or 9 μm or less or 8 μm or less. Therefore, the embodiment can improve the alignment accuracy between the second through hole 4152 and the second pad 4120-2. Thereby, the embodiment can further improve the electrical reliability and / or physical reliability of the circuit board.

[0273] Figure 21 is a cross-sectional view showing a circuit board according to the seventh embodiment.

[0274] Referring to FIG. 21, the circuit board according to the seventh embodiment includes an insulating layer 4210, an upper wiring electrode 4220, a lower wiring electrode 4230, a via electrode 4240, a first protective layer 4250, and a second protective layer 4260. The upper wiring electrode 4220, the lower wiring electrode 4230, and the via electrode 4240 include first metal layers 4221, 4231, 4241 and second metal layers 4222, 4232, 4242, respectively.

[0275] At this time, the inner surface of the through hole in the seventh embodiment had an inclination substantially perpendicular to the upper surface of the insulating layer. In contrast, the inner surface of the through hole in the eighth embodiment can have an inclination with respect to the upper surface of the insulating layer.

[0276] For example, the upper wiring electrode 4220 includes a first pad 4220-1 and a second pad 4220-2. The first protective layer 4250 includes a first through hole 4251 that overlaps the first pad 4220-1 perpendicularly. The first protective layer 4250 also includes a second through hole 4252 that overlaps the second pad 4220-2 perpendicularly.

[0277] At this time, the basic structures of the first through hole 4251 and the second through hole 4252 are the same as those in the sixth embodiment, and detailed descriptions thereof are omitted.

[0278] The width of the first through-hole 4251 can change as it goes from the upper surface to the lower surface of the first protective layer 4250. For example, the first inner surface 4251S of the first protective layer 4250 of the first protective layer 4250 can have an inclination in which the width decreases in the downward direction. That is, in the seventh embodiment, the photosensitive film used to form the first through-hole 4251 is of the negative type, and the resist pattern DFR1-F can be formed using the negative-type photosensitive film. As a result, the resist pattern DFR1-F can have a shape in which the width decreases in the downward direction. Then, the first inner surface 4251S of the first through-hole 4251 of the first protective layer 4250 formed by the resist pattern DFR1-F can have an inclination in which the width decreases in the downward direction. The negative-type photosensitive film has the property that the portions that do not receive light during exposure and development are developed and removed.

[0279] Correspondingly, the second inner surface 4252S of the second through-hole 4252 of the first protective layer 4250 can also have an inclination in which the width decreases in the downward direction.

[0280] At this time, the embodiment does not include an undercut on the first inner surface 4251S and the second inner surface 4252S. Accordingly, each of the first inner surface 4251S and the second inner surface 4252S has an inclination in which the width decreases from the upper end to the lower end. At this time, the first through hole 4251 and the second through hole 4252 each include only an inclination in which the width decreases from the upper end to the lower end of the first inner surface 4251S and the second inner surface 4252S, and do not include an inclination in which the width is maintained or an inclination in which the width increases. That is, an inclination in which the width is maintained or an inclination in which the width increases can mean an undercut. And, since the embodiment does not include an undercut, each of the first inner surface 4251S and the second inner surface 4252S of the first through hole 4251 and the second through hole 4252 includes only an inclination in which the width decreases, and does not include an inclination in which the width is maintained or an inclination in which the width increases. At this time, the embodiment forms a through hole in the first protective layer 4250 using a negative-type photosensitive film as described above. Thereby, in the process of removing the resist pattern DFR1-F after forming the through hole in the first protective layer 4250, the removal of the resist pattern DFR1-F can be performed smoothly. Thereby, the embodiment can solve the problem that the first protective layer 4250 is separated from the insulating layer 4210 in the process of removing the resist pattern DFR1-F.

[0281] The first protective layer 4250 includes a first convex portion 4251P surrounding the upper portion of the first through hole 4251. And, the inclination of the inner surface of the first convex portion 4251P can have an inclination corresponding to the inclination of the first inner surface 4251S of the first through hole 4251. And, the inclination of the inner surface of the first convex portion 4251P can mean a portion overlapping horizontally with the first convex portion 4251P, and the first inner surface 4251S of the first through hole 4251 can mean a region overlapping horizontally with the second region R2 of the first protective layer 4250.

[0282] The first protective layer 4250 includes a second convex portion 4252P surrounding the upper portion of the second through hole 4252. And, the inclination of the inner surface of the second convex portion 4252P can have an inclination corresponding to the inclination of the second inner surface 4252S of the second through hole 4252.

[0283] FIG. 22 is a cross-sectional view showing a circuit board according to the eighth embodiment.

[0284] Referring to FIG. 22, the circuit board of the eighth embodiment includes an insulating layer 4310, an upper wiring electrode 4320, a lower wiring electrode 4330, a via electrode 4340, a first protective layer 4350, and a second protective layer 4360. The upper wiring electrode 4320, the lower wiring electrode 4330, and the through electrode 4340 include a first metal layer 4321, 4331, 4341 and a second metal layer 4322, 4332, 4342, respectively.

[0285] At this time, the inner surface of the through hole in the sixth embodiment has an inclination substantially perpendicular to the upper surface of the insulating layer, and the inner surface of the through hole in the seventh embodiment has an inclination in which the width decreases as it goes in the downward direction. Further, the inner surface of the through hole of the eighth embodiment can have an inclination in which the width increases as it goes in the downward direction.

[0286] For example, the upper wiring electrode 4320 includes a first pad 4320-1 and a second pad 4320-2. The first protective layer 4350 includes a first through hole 4351 that overlaps the first pad 4320-1 perpendicularly. The first protective layer 4350 also includes a second through hole 4352 that overlaps the second pad 4320-2 perpendicularly.

[0287] The width of the first through hole 4351 can change as it goes from the upper surface to the lower surface of the first protective layer 4350. For example, the first inner surface 4351S of the first protective layer 4350 of the first protective layer 4350 can have an inclination with an increasing width in the downward direction. That is, in the eighth embodiment, the photosensitive film used to form the first through hole 4351 is of the positive type, and the resist pattern DFR1-F can be formed using the positive type photosensitive film. As a result, the resist pattern DFR1-F can have a shape with an increasing width in the downward direction. And the first inner surface 4351S of the first through hole 4351 of the first protective layer 4350 formed by the resist pattern DFR1-F can have an inclination with an increasing width in the downward direction. The positive type photosensitive film has the characteristic that the portion exposed to light during exposure and development is developed and removed.

[0288] Correspondingly, the second inner surface 4352S of the second through hole 4352 of the first protective layer 4350 can also have an inclination with a decreasing width in the downward direction. At this time, in the eighth embodiment, as the width of the through hole increases in the downward direction, when arranging a connection part such as a solder ball in the through hole, the through hole can function as an anchor. Thereby, the embodiment can improve the bonding property with the connection part.

[0289] Further, the first protective layer 4350 includes a first convex portion 4351P surrounding the upper portion of the first through hole 4351. And the inclination of the inner surface of the first convex portion 4351P can have an inclination corresponding to the inclination of the first inner surface 4351S of the first through hole 4351.

[0290] Further, the first protective layer 4350 includes a second convex portion 4352P surrounding the upper portion of the second through hole 4352. And the inclination of the inner surface of the second convex portion 4352P can have an inclination corresponding to the inclination of the second inner surface 4352S of the second through hole 4352.

[0291] FIG. 23 is a drawing showing various modified examples of the circuit board of the embodiment.

[0292] In the circuit board of the sixth embodiment, the first convex portion 4151P formed in the first region R1 of the first protective layer 4150 partially overlapped perpendicularly with the first pad 4120-1.

[0293] On the contrary, referring to Fig. 23(a), the entire region of the first convex portion 151P1 formed in the first region R1 of the first protective layer 4150 can overlap perpendicularly with the first pad 4120-1. For example, the boundary between the first region R1 and the second region R2 of the first protective layer 4150 can overlap perpendicularly with the first pad 4120-1.

[0294] Also, referring to Fig. 23(b), in the first convex portion 151P2 formed in the first region R1 of the first protective layer 4150, a sub-convex portion 4151PC is formed in a region that overlaps perpendicularly with the edge region of the first pad 4120-1. The sub-convex portion 4151PC is a portion that protrudes according to the height of the first pad 4120-1 in the process of applying the first protective layer 4150.

[0295] On the other hand, the convex portions in the previous embodiments had an inclination with a certain slope. For example, the convex portions in the previous embodiments had a shape in which the width changed from the upper side to the lower side. For example, the height of the first region R1 of the first protective layer 4150 gradually decreased towards the second region R2.

[0296] On the contrary, referring to Fig. 23(c), the first convex portion 4151P3 formed in the first region R1 of the first protective layer 4150 can have a shape without a change in width. For example, the upper surface of the first region R1 of the first protective layer 4150 has no change in height. For example, the vertical cross-sectional shape of the first convex portion 4151P3 can have a rectangular shape.

[0297] On the other hand, in Fig. 23, although the modified examples of the first convex portion were described, the second convex portion and the third convex portion in the sixth embodiment can also be deformed with the same structure.

[0298] FIG. 24 is a cross-sectional view showing a semiconductor package according to still another embodiment, and FIG. 25 is a drawing showing the placement reliability of the first connection portions in the embodiments and comparative examples.

[0299] Referring to FIGS. 24 and 25, a semiconductor package of still another embodiment can have a PoP (Package On package) structure.

[0300] The first connection portion 4410 is disposed on the circuit board. Further, a semiconductor chip 4420 is mounted on the first connection portion 4410. Terminals 4425 of the semiconductor chip 4420 are connected to wiring electrodes of the circuit board via the first connection portion 4410.

[0301] At this time, referring to FIG. 25(a), in the first comparative example, a through hole is formed in the protective layer 30 having the same thickness T2 as the thickness of the first protective layer of the present application, and a certain amount of solder balls SB are disposed. At this time, in the first comparative example, since the thickness T2 of the protective layer is relatively small, the diffusion of the solder balls SB cannot be efficiently prevented. As a result, in the first comparative example, the degree of diffusion of the solder balls SB is large, and thus the width W4 of the solder balls SB is relatively large. And in the first comparative example, as the diffusion of the solder balls SB increases, the thickness T3 of the solder balls SB also appears to be relatively low.

[0302] Further, referring to FIG. 25(b), in the second comparative example, a through hole is formed in the protective layer 30 having a thickness T2-1 greater than the thicknesses of the first protective layer of the present application and the protective layer 30 of the first comparative example, and a certain amount of solder balls SB are arranged. At this time, in the second comparative example, the thickness T2-1 of the protective layer is greater than the thickness T2 of the protective layer of the first comparative example, whereby the diffusion of the solder balls SB is prevented to a certain extent. However, it can be confirmed that even if the thickness T2-1 of the protective layer 30 is increased as in the second comparative example, the diffusion of the solder balls SB occurs, and thereby it can be confirmed that the width W4-1 due to the diffusion of the solder balls SB is larger than the through hole of the protective layer 30. As a result, it can be confirmed that the thickness T3-1 of the solder balls SB in the second comparative example increases compared to the first comparative example but does not have the target level thickness. Also, in the second comparative example, since the entire region of the protective layer 30 has a thickness T2-1 as a whole, the fluidity of the EMC during the EMC filling for the shape of the molding layer decreases, and thereby a region where the EMC is not filled occurs.

[0303] In contrast, referring to FIG. 25(c), the protective layer 4150 of the embodiment has the thickness T2 that the protective layer 30 of the first comparative example has, and forms convex portions 4150P so as to be adjacent to the through holes.

[0304] As a result, it can be confirmed that in the embodiment, the width W4-2 of the first connection portion 4410 corresponds to the width of the through hole by the convex portions 4150P. Thereby, the embodiment can efficiently reduce the pitch between the plurality of first connection portions.

[0305] Also, it can be confirmed that in the embodiment, the height of the first connection portion 4410 is maintained by the convex portions 4150P. As a result, it can be confirmed that the first connection portion 4410 is arranged with a thickness T3-2 larger than that of the first comparative example and the second comparative example even when the same amount of solder is applied.

[0306] In addition, the semiconductor package can include an underfill 4430. The underfill 4430 is disposed while covering the periphery of the semiconductor chip 4420 on the circuit board. However, the underfill 4430 may be selectively omitted. For example, in the semiconductor package, the underfill 4430 can be omitted, and the function of the underfill 4430 can be performed by the molding layer 4450.

[0307] The semiconductor package can include a second connection portion 4440. The second connection portion 4440 is disposed on the wiring electrode of the circuit board. The second connection portion 4440 may be a bump. As an example, the second connection portion 4440 may be a solder bump, but is not limited thereto. For example, the second connection portion 4440 may be a post bump. For example, the second connection portion 4440 can include a copper post and a solder bump disposed on the copper post. The upper surface of the second connection portion 4440 can be positioned higher than the upper surface of the semiconductor chip 4420. Thereby, it is possible to prevent the semiconductor element 4420 from being damaged in the bonding process of the external substrate 4500 disposed on the second connection portion 4440.

[0308] The semiconductor package can include a molding layer 4450. The molding layer 4450 can mold the configuration disposed on the circuit board. The molding layer 4450 can include an opening. For example, the molding layer 4450 can include an opening that overlaps the upper surface of the second connection portion 4440 in the vertical direction.

[0309] The semiconductor package includes a third connection portion 4460.

[0310] The third connection portion 4460 is disposed under the wiring electrode disposed on the lowermost side of the circuit board. The third connection portion 4460 may be solder for connecting the semiconductor package of the embodiment to a separate external substrate (for example, the main board of an electronic device), but is not limited thereto.

[0311] The semiconductor package includes an external substrate 4500. The external substrate 4500 can mean a separate substrate coupled to the circuit board of the embodiment. For example, the semiconductor chip 4420 disposed on the circuit board may be a logic chip such as a CPU or a GPU, and the external substrate 4500 can mean a memory substrate on which a memory chip coupled to the logic chip is disposed. The external substrate 4500 may be an interposer that connects between the memory substrate on which the semiconductor chip 4420 corresponding to the memory chip is disposed and the circuit board.

[0312] The external substrate 4500 can include an insulating layer 4510, a circuit layer 4520, a through electrode 4530, an upper protective layer 4540, and a lower protective layer 4550. And the external substrate 4500 can include a fourth connection portion 4560. The fourth connection portion 4560 is disposed between the external substrate 4500 and the third connection portion 4440.

[0313] Also, the semiconductor package can include a fifth connection portion 4570. The fifth connection portion 4570 is disposed on the external substrate 4500.

[0314] The semiconductor package can include a semiconductor chip 4580. The semiconductor chip 4580 is mounted on the external substrate 4500 via the fifth connection portion 4570.

[0315] FIGS. 26A to 26H are cross-sectional views for explaining the manufacturing method of the circuit board illustrated in FIG. 10 in order of steps.

[0316] Referring to FIG. 26A, in the embodiment, an insulating layer 4110 is prepared. Thereafter, the embodiment forms a through hole VH that penetrates the upper and lower surfaces of the insulating layer 4110.

[0317] Next, referring to FIG. 26b, in the embodiment, a via electrode 4140 filling the through hole VH can be formed on the insulating layer 4110. Also, in the embodiment, an upper wiring electrode 4120 including a first pad 4120-1 and a second pad 4120-2 can be formed on the upper surface of the insulating layer 4110. Also, in the embodiment, a lower wiring electrode 4130 can be formed on the lower surface of the insulating layer 4110.

[0318] Thereafter, referring to FIG. 26c, in the embodiment, a first dry film DFR1 is formed on the insulating layer 4110. At this time, the first dry film DFR1 is disposed while entirely covering the upper wiring electrode 4120. Also, in the embodiment, a second dry film DFR2 is formed under the insulating layer 4110. At this time, the second dry film DFR2 is disposed while entirely covering the lower wiring electrode 4130.

[0319] Next, referring to FIG. 26d, in the embodiment, a process of exposing and curing the first dry film DFR1 to form a first exposed pattern ER1 can be performed. At this time, the first dry film DFR1 may be of a negative type. Thereby, the portion not receiving light is later removed by development, and the first exposed pattern ER1 receiving light is not removed. Also, in the embodiment, a process of exposing and curing the second dry film DFR2 to form a second exposed pattern ER2 can be performed. At this time, the second dry film DFR2 may be of a negative type. Thereby, the portion not receiving light is later removed by development, and the second exposed pattern ER2 receiving light is not removed.

[0320] Next, referring to FIG. 26e, the embodiment can perform a step of removing the region excluding the first exposure pattern ER1 from the first dry film DFR1 to form the first resist pattern DFR1-F. At this time, the first resist pattern DFR1-F is formed to correspond to the region where the through hole of the first protective layer 4150 is formed on the insulating layer 4110. Also, the embodiment can perform a step of removing the region excluding the second exposure pattern ER2 from the second dry film DFR2 to form the second resist pattern DFR2-F. At this time, the second resist pattern DFR2-F is formed to correspond to the region where the through hole of the second protective layer 4160 is formed on the insulating layer 4110.

[0321] Next, referring to FIG. 26f, the embodiment can form a first protective layer 4150R covering the first resist pattern DFR1-F on the insulating layer 4110. Also, the embodiment can form a second protective layer 4160R covering the second resist pattern DFR2-F under the insulating layer 4110.

[0322] Next, referring to FIG. 26g, the embodiment can perform a step of removing the first protective layer 4150R by etching to reduce the first protective layer 4150R to a target thickness.

[0323] The etching process can be performed using an organic alkaline compound containing tetramethylammonium hydroxide (TMAH) or trimethyl-2-hydroxyethylammonium hydroxide (choline), etc.

[0324] In addition, in the embodiment, the second protective layer 4160R can be removed by etching to reduce the second protective layer 4160R to a target thickness. At this time, the embodiment adjusts the etching conditions in the regions adjacent to the first resist pattern DFR1-F and the regions adjacent to the second resist pattern DFR2-F. For example, in the embodiment, the etching degree of the first protective layer 150R in the region adjacent to the first resist pattern DFR1-F is adjusted. Thereby, the first protective layer 4150R can include the convex portion 4150P formed to be adjacent to the first resist pattern DFR1-F. Correspondingly, in the embodiment, the etching degree of the second protective layer 4160R in the region adjacent to the second resist pattern DFR2-F is adjusted. Thereby, the second protective layer 4160R can include the convex portion 4160P formed to be adjacent to the second resist pattern DFR2-F.

[0325] Next, referring to FIG. 26h, the embodiment can perform a step of removing the first resist pattern DFR1-F and the second resist pattern DFR2-F. Thereby, in the embodiment, through holes and convex portions are formed in the first protective layer 4150 and the second protective layer 4160, respectively, corresponding to the first resist pattern DFR1-F and the second resist pattern DFR2-F.

[0326] Hereinafter, a method for manufacturing a semiconductor package according to still another embodiment will be described.

[0327] FIGS. 27a to 28n are cross-sectional views for explaining a method for manufacturing a circuit board according to still another embodiment in the order of steps. The embodiment described below is similar to the structure of the circuit board illustrated in FIG. 1a. However, the position of the cavity C and the number of insulating layers in the circuit board described below are different from those of the circuit board illustrated in FIG. 1a.

[0328] Referring to FIG. 27a, the embodiment prepares one layer of the insulating layer 5110. One layer of the insulating layer 5110 can correspond to the third insulating layer 110a of the first embodiment in FIG. 1a.

[0329] Thereafter, the embodiment can perform a step of forming an electrode portion on one layer of the insulating layer 5110. For example, the embodiment can form wiring electrodes 5140a on the upper and lower surfaces of one layer of the insulating layer 5110 respectively, can form via electrodes 5140b penetrating one layer of the insulating layer 5110, and can perform a step of forming an insulating member 5110d surrounded by the via electrodes 5140b.

[0330] Referring to FIG. 27b, the embodiment can perform a step of forming a cavity C penetrating one layer of the insulating layer 5110. Exemplarily, the cavity C in the first embodiment of FIG. 1a is provided in the second insulating layer 110b1, while in other embodiments, the cavity C is provided in one layer of the insulating layer 5110 which is the third insulating layer disposed in the center. Also, although FIG. 27b illustrates that the cavity C is provided penetrating one layer of the insulating layer 5110, it is not limited thereto, and the cavity C can also have a non-penetrating groove shape in the insulating layer 5110.

[0331] Referring to FIG. 27c, the embodiment can perform a step of attaching a carrier film CB to the lower part of the insulating layer 5110. The carrier film CB is provided while closing the lower region of the cavity C in the insulating layer 5110.

[0332] Referring to FIG. 27d, the embodiment can perform a step of attaching a connecting member 200 on the carrier film CB overlapping perpendicularly with the cavity C.

[0333] Referring to FIG. 27e, the embodiment can laminate a laminated insulating layer (for example, an upper insulating layer) filling the cavity C on the insulating layer 5110.

[0334] Referring to FIG. 27f, the embodiment can perform a step of removing the carrier film CB.

[0335] Referring to FIG. 27g, in the embodiment, an additional stacked insulating layer can be stacked under the insulating layer 5110. Exemplarily, the embodiment can perform a step of stacking a lower insulating layer. At this time, the number of layers of the upper insulating layer and the lower insulating layer may be different. Exemplarily, as illustrated in FIG. 27h, the number of layers of the upper insulating layer may be smaller than the number of layers of the lower insulating layer.

[0336] Referring to FIG. 27h, in the embodiment, steps of forming wiring electrodes and via electrodes on the upper insulating layer and the lower insulating layer respectively can be performed. At this time, on the upper insulating layer, a first electrode portion 5141 including a first pad 5141a and a first via electrode 5141b overlapping the connecting member 5200 in the vertical direction, and a second electrode portion 5142 including a second pad 5142a and a second via electrode 5142b not overlapping the connecting member 5200 in the vertical direction are formed.

[0337] Referring to FIG. 27i, in the embodiment, a step of forming a dry film DF1 covering the first pad 5141a and the second pad 5142a on the upper insulating layer of the insulating layer 5110 can be performed.

[0338] Referring to FIG. 27j, in the embodiment, a step of exposing and developing the dry film DF1 to form an exposure pattern corresponding to positions where the first and second through holes of the protective layer are formed can be performed. At this time, the exposure pattern may have substantially the same width on the upper surface and the lower surface, and thus the width of each of the upper surface and the lower surface can be 20 μm or less.

[0339] Referring to FIG. 27k, in the embodiment, a step of forming a first protective layer 5120 covering the exposure pattern on the upper insulating layer can be performed.

[0340] Referring to FIG. 27l, in the embodiment, a step of removing the first protective layer 5120 by etching can be performed, so that the upper surface of the first protective layer 5120 can have a height below the upper surface of the exposure pattern.

[0341] 27m, in an embodiment, a process of removing the exposure pattern may be performed, and thus, in an embodiment, through holes TH are formed in the first protective layer 5120 corresponding to the positions where the exposure pattern has been removed.

[0342] 27n, in the embodiment, a process of forming a first bonding part 5151 and a second bonding part 5152 in a through hole of a first protective layer 5120 may be performed. Exemplarily, in the embodiment, the first bonding part 5151 may be formed including a first through part 5151a and a first protrusion 5151b that vertically overlap the connecting member 5200. In addition, in the embodiment, the second bonding part 5152 may be formed including a second through part 5152a and a second protrusion 5152b that do not vertically overlap the connecting member 5200.

[0343] Meanwhile, when the circuit board having the above-mentioned inventive features is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when the circuit board having the features of the present invention functions as a semiconductor package, it can safely protect the semiconductor chip from external moisture or contaminants, and can solve the problems of leakage current or electrical short circuit between terminals, or electrical open of terminals supplying power to the semiconductor chip. In addition, when it functions as a signal transmission, it can solve the noise problem. As a result, the circuit board having the above-mentioned inventive features can maintain stable functions of IT devices and home appliances, and the entire product and the circuit board to which the present invention is applied can have functional integration or technical interrelationship with each other.

[0344] When a circuit board having the features of the above-described invention is used in a transportation device such as a vehicle, it is possible to solve the problem of signal distortion in the transportation device, or to safely protect a semiconductor chip that controls the transportation device from external leakage current, electrical short-circuit problems between terminals, or electrical open problems of the terminals supplying the semiconductor chip, thereby further improving the stability of the transportation device. Therefore, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical linkage with each other.

[0345] The features, structures, effects, etc. described in the above embodiments are included in at least one embodiment of the present invention and are not necessarily limited to one embodiment. In addition, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified for other embodiments by those with ordinary knowledge in the field to which the embodiment belongs. Therefore, the content related to such combinations and modifications should be construed as being included in the scope of the present invention.

[0346] In the above, the description has been centered around the embodiments, but this is merely an illustration and does not limit the present invention. Those with ordinary knowledge in the field to which the present invention belongs can make various modifications and applications not exemplified above without departing from the essential characteristics of this embodiment. For example, each component specifically presented in the embodiment can be implemented with modifications. And the differences related to such modifications and applications should be construed as being included in the scope of the present invention defined by the appended claims.

Claims

1. An insulating layer including an upper surface and a lower surface; A protective layer disposed on the upper surface of the insulating layer; A connecting member embedded in the insulating layer; A wiring electrode embedded in the insulating layer, comprising: The wiring electrode includes an upper pad portion disposed between the insulating layer and the protective layer; A first via electrode that penetrates a partial region of the insulating layer at the upper pad portion and is electrically connected to the connecting member, and has a width narrower than the width of the upper pad portion; A second via electrode embedded in the insulating layer and disposed closer to the lower surface of the insulating layer than the connecting member; A bonding portion including a protruding portion disposed on the protective layer and a penetrating portion that penetrates the protective layer at the protruding portion and is in direct contact with the upper pad portion; The bonding portion includes a first bonding portion overlapping the connecting member in a vertical direction and a second bonding portion not overlapping the connecting member vertically; A semiconductor package, wherein an inclination angle of each of the penetrating portion of the first bonding portion and the penetrating portion of the second bonding portion with respect to the upper surface of the insulating layer is closer to vertical than an inclination angle of the second via electrode with respect to the upper surface of the insulating layer.

2. A plurality of the first bonding portions are provided; The semiconductor package according to claim 1, wherein a horizontal isolation distance between two of the first bonding portions that are closest to each other among the plurality of first bonding portions is 26 μm or less.

3. Each of the plurality of first bonding portions includes a plurality of first protruding portions; The semiconductor package according to claim 2, wherein a horizontal width of each of the plurality of first protruding portions is 29 μm to 34 μm.

4. The protective layer includes a plurality of first fillers; The semiconductor package according to claim 1, wherein the penetrating portion of the first bonding portion does not contact the plurality of first fillers.

5. The first via electrode includes a first overlapping via electrode overlapping the connecting member in a vertical direction; The semiconductor package according to claim 1, wherein an inclination angle of the first overlapping via electrode is the same as an inclination angle of the penetrating portion of the first bonding portion.

6. The insulating layer includes a plurality of laminated insulating layers disposed between the upper surface and the lower surface of the insulating layer; The plurality of laminated insulating layers include an upper insulating layer forming the upper surface of the insulating layer and a lower insulating layer forming the lower surface of the insulating layer. The wiring layer further includes a plurality of wiring electrodes respectively disposed in a plurality of stacked insulating layers, a plurality of via electrodes connecting the plurality of wiring electrodes, and a lower pad portion disposed on the lower surface of the insulating layer. The plurality of via electrodes further include a plurality of upper vias overlapping with the connecting member along a horizontal direction, and a plurality of lower vias disposed between the plurality of upper vias and the lower surface of the insulating layer. The semiconductor package according to claim 1, wherein an inclination angle of the upper via is symmetric with an inclination angle of the lower via.

7. The semiconductor package according to claim 6, wherein a thickness of the upper insulating layer is thinner than a thickness of the lower insulating layer.

8. The semiconductor package according to claim 7, wherein a first through portion of the first bonding portion overlaps at least a partial region of the first stacked via electrode perpendicularly.

9. The insulating layer includes a side surface located between an upper surface and a lower surface. The protective layer includes a lower surface facing the upper surface of the insulating layer, an upper surface corresponding to the lower surface, and a side surface located between the lower surface and the upper surface. The side surface of the protective layer includes an inner surface surrounding the first through portion and the second through portion respectively and an outer surface adjacent to the side surface of the insulating layer. The semiconductor package according to claim 1, wherein a vertical length of the inner surface is different from a vertical length of the outer surface.

10. The semiconductor package according to claim 9, wherein a vertical length of the inner surface is greater than a vertical length of the outer surface.

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