Semiconductor Package

Abstract

The semiconductor package according to the embodiment includes an insulating layer, a pad portion disposed on the insulating layer, and a protective layer disposed on the insulating layer and including an open region that overlaps the pad portion in a vertical direction. The horizontal width of the open region of the protective layer satisfies the range of 10 μm to 30 μm, and the surface roughness of the upper surface of the protective layer is different from the surface roughness of the inner surface of the open region of the protective layer.

Description

Technical Field

[0001] The embodiments relate to a circuit board and a semiconductor package including the same.

Background Art

[0002] Generally, a printed circuit board (PCB) is a laminated structure in which insulating layers and conductor layers are alternately laminated, and the conductor layer can be formed into a circuit pattern by patterning.

[0003] Such a printed circuit board protects the circuit formed on the outermost side of the laminate, prevents oxidation of the conductor layer, and serves as insulation when making electrical connections with chips or other substrates mounted on the printed circuit board. A solder resist (SR) is provided.

[0004] In a normal solder resist, connection means such as solder or bumps are combined to form an open region (SRO: Solder Resist Opening) that serves as an electrical connection path. As the input / output (I / O) performance of the printed circuit board improves with high performance and high density, more open regions are required for the open regions of the solder resist. As a result, a small bump pitch for the open regions of the solder resist is required. At this time, the bump pitch of the open region of the solder resist means the center distance between adjacent open regions.

[0005] On the other hand, the open region (SRO) of the solder resist includes an SMD (Solder Mask Defined type) type and an NSMD (Non-Solder Mask Defined type).

[0006] The NSMD type is characterized in that the width of the open region (SRO) is smaller than the width of the pad exposed through the open region (SRO). Thus, in the SMD type, at least a part of the upper surface of the pad is covered by the solder resist.

[0007] Also, the NSMD type is characterized in that the width of the open region SRO is larger than the width of the pad exposed through the open region SRO. Thus, in the NSMD type, the solder resist is arranged at a certain interval from the pad, and thus has a structure in which both the upper surface and the side surface of the pad are exposed.

[0008] However, in the case of the SMD type, after the semiconductor package is coupled to the main board, there is a problem that the solder ball is separated from the pad exposed through the open region SRO during the Solder Ball Joint Reliability test for the bonding force of the solder ball. Also, in the case of the NSMD type, there is a problem that the pad on which the solder ball is arranged is separated from the substrate. Thus, conventionally, the SMD type and the NSMD type have been appropriately combined and applied to one circuit board.

[0009] Also, in the case of a conventional circuit board including the NSMD type and the open region SRO, in the process of exposing the solder resist layer, light is not sufficiently transmitted to the lower region of the exposed region of the solder resist layer, and thus there is a problem that the lower region of the exposed region cannot be sufficiently cured. And when the development process is performed in a state where the lower region of the exposed region cannot be sufficiently cured, there is a problem that an undercut occurs in which the lower region of the exposed region is removed together. Furthermore, as the thickness of the solder resist layer increases, the width of the undercut becomes even larger, and there is a problem that the reliability of the circuit board is lowered due to this.

[0010] Also, when forming an open region by exposing the solder resist layer, the size of the open region is determined according to the exposure resolution of the solder resist layer. However, the size of the open region that can be formed in the solder resist layer is about 70 μm in the case of general resolution, and can be formed up to 50 μm in the case of high resolution.

[0011] However, due to technological advancements, the amount of data processed tends to increase rapidly. In response, the number of terminals of semiconductor elements mounted on semiconductor packages is increasing. Therefore, there is a need for a new structure that can reduce the size of the open area that can be formed in the solder resist layer while removing the undercut.

Summary of the Invention

Problems to be Solved by the Invention

[0012] Embodiments provide a circuit board capable of reducing the size of the open area that can be formed in the protective layer and a semiconductor package including the same.

[0013] Also, embodiments provide a circuit board capable of removing the undercut formed on the sidewall of the open area within the protective layer and a semiconductor package including the same.

[0014] Also, embodiments provide a circuit board capable of reducing the tolerance SRR (Solder Resist Registration) between the center of the open area of the protective layer and the center of the pad and a semiconductor package including the same.

[0015] Also, embodiments provide a circuit board with improved electrical and mechanical characteristics and a semiconductor package including the same.

[0016] Also, embodiments provide a circuit board capable of improving the bonding strength with the molding layer and a semiconductor package including the same.

[0017] In the proposed embodiments, the technical problems to be solved are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those with ordinary knowledge in the technical field to which the proposed embodiments belong from the following description.

Means for Solving the Problems

[0018] The semiconductor package according to the embodiment includes an insulating layer, a pad portion disposed on the insulating layer, and a protective layer disposed on the insulating layer and including an open region that overlaps the pad portion in a vertical direction. The horizontal width of the open region of the protective layer satisfies the range of 10 μm to 30 μm, and the surface roughness of the upper surface of the protective layer is different from the surface roughness of the inner surface of the open region of the protective layer.

[0019] Also, the surface roughness of the upper surface of the protective layer is greater than the surface roughness of the inner surface of the open region of the protective layer.

[0020] Also, the protective layer includes a resin and a plurality of fillers dispersed in the resin, and at least one of the plurality of fillers is exposed through the upper surface of the protective layer.

[0021] Also, the pad portion includes a first pad, the open region includes a first open region that partially overlaps the first pad in a vertical direction, and the width of the first open region is smaller than the width of the first pad.

[0022] Also, the pad includes a second pad, the open region includes a second open region that entirely overlaps the second pad in a vertical direction, and the width of the second open region is larger than the width of the second pad.

[0023] Also, the inner surface of the open region has an inclination in which the width of the open region decreases from the upper surface of the protective layer toward the lower surface of the protective layer.

[0024] Also, the inner surface of the open region has an inclination in which the width of the open region increases from the upper surface of the protective layer toward the lower surface of the protective layer.

[0025] Also, the difference between the maximum width and the minimum width in the thickness direction of the open region is 3 μm or less.

[0026] Further, the center of the open region and the center of the pad portion are displaced in the vertical direction.

[0027] Also, the horizontal width between the center of the open region and the center of the pad portion is 10 μm or less.

Advantages of the Invention

[0028] The embodiment includes an insulating layer, a pad disposed on the insulating layer, and a protective layer disposed on the insulating layer and including an open region vertically overlapping the pad.

[0029] At this time, the width of the open region of the protective layer of the embodiment is 30 μm or less. For example, the width of the open region of the protective layer of the embodiment can satisfy the range of 10 μm to 30 μm, the range of 12 μm to 28 μm, or the range of 13 μm to 25 μm.

[0030] Furthermore, in the open region of the protective layer of the embodiment, there is almost no change in width as going in the thickness direction. For example, in the entire region of the open region of the embodiment in the thickness direction, the difference in width between the region having the maximum width and the region having the minimum width may be 3 μm or less, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1 μm or less, or 0.5 μm or less. That is, in the embodiment, the undercut at the lower end of the inner surface of the open region of the protective layer can be removed, or the horizontal distance of the undercut can be significantly reduced compared to the comparison.

[0031] This is because the open area of the protective layer is not formed by exposing and developing the protective layer, but by using another resist pattern. That is, in the embodiment, the protective layer is disposed in a state where a resist pattern is formed using a photosensitive film. Therefore, an open area corresponding to the resist pattern can be formed in the protective layer. At this time, the photosensitive film does not contain a filler inside. As a result, generally, the minimum size of a resist pattern formed by exposing and developing the photosensitive film is smaller than that of a resist pattern formed by exposing and developing a solder resist containing a filler.

[0032] Accordingly, in the embodiment, instead of exposing and developing the protective layer itself such as a solder resist, a photosensitive film capable of realizing a relatively fine pattern is exposed and developed to form a resist pattern. And in the present embodiment, an open area is formed in the protective layer using the resist pattern. Therefore, the embodiment can reduce the size of the open area formed in the protective layer as compared with the comparative example, thereby improving the circuit integration degree.

[0033] Furthermore, in the embodiment, since the protective layer is not exposed and developed, an undercut formed on the inner surface of the open area of the protective layer can be removed. Through this, the embodiment can further reduce the separation interval of the circuit pattern layer.

[0034] On the other hand, in the embodiment, after the thickness of the protective layer is made larger than the thickness of the resist pattern in a state where the resist pattern is disposed, a thinning process is performed. That is, in the embodiment, the protective layer can be made to have a target thickness through the thinning process. At this time, without performing the thinning process, a process of coating the protective layer so as to have a target thickness can also be performed. However, if the thinning process is not performed, there is a problem that the deviation of the thickness of the protective layer becomes large, and the flatness of the protective layer is thereby reduced.

[0035] In contrast, in the embodiment, since the thinning process is performed, the flatness of the protective layer can be improved. Through this, the embodiment can improve the overall physical reliability and electrical reliability of the circuit board and the semiconductor package.

[0036] Also, on the upper surface of the protective layer in the embodiment, the filler can be entirely exposed by the thinning process. And the exposed filler increases the surface roughness of the upper surface of the protective layer. Through this, in the molding process after mounting the semiconductor element on the circuit board, the bonding area between the protective layer and the molding layer can be increased in the embodiment, thereby improving the bonding strength. Through this, the embodiment can further improve the reliability of the product.

[0037] On the other hand, in the embodiment, since the protective layer is not exposed and developed, the protective layer may not contain a photoinitiator. For example, a general solder resist contains a photoinitiator for exposure and development. At this time, the photoinitiator acts as a factor that degrades the physical and electrical characteristics of the circuit board. At this time, since the protective layer in the embodiment does not contain a photoinitiator, the physical and electrical characteristics of the circuit board can be improved.

[0038] Furthermore, since the embodiment does not contain a photoinitiator in the protective layer, the types of insulating layers that can be used as the protective layer can be expanded, and the unit price required for the development of the protective layer can be further reduced.

[0039] Furthermore, the embodiment can significantly reduce the tolerance between the center of the open area of the protective layer and the center of the pad compared to the comparative example. Through this, the embodiment can improve the mountability of the semiconductor element, and through this, improve the physical reliability and electrical reliability of the circuit board and the semiconductor package.

Brief Description of the Drawings

[0040]

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[0041] Hereinafter, with reference to the attached drawings, the embodiments disclosed in this specification will be described in detail. However, the same or similar components regardless of the reference numerals will be given the same reference numbers, and duplicate explanations thereof will be omitted. The suffixes "module" and "section" for the components used in the following description are given or mixed for the purpose of facilitating the preparation of the specification, and do not have meanings or roles that are mutually distinguishable by themselves. Further, in the description of the embodiments disclosed in this specification, if it is determined that the specific description of the related known technology obstructs the gist of the embodiments disclosed in this specification, the detailed description thereof will be omitted. Also, the attached drawings are for the purpose of facilitating the understanding of the embodiments disclosed in this specification, and the technical idea disclosed in this specification is not limited by the attached drawings, and should be understood to include all modifications, equivalents, and alternatives included in the idea and technical scope of the present invention.

[0042] Terms including ordinal numbers such as first and second can be used to describe various components, but the components are not limited by the terms. The terms are used only for the purpose of distinguishing one component from another component.

[0043] When it is mentioned that a certain component is "connected" or "joined" to another component, it should be understood that it may be directly "connected" or "joined" to the other component, or other components may exist therebetween. On the other hand, when it is mentioned that a certain component is "directly connected" or "directly joined" to another component, it should be understood that no other component exists therebetween.

[0044] The singular expression includes plural expressions unless the context clearly has a different meaning.

[0045] In this application, terms such as "comprising" or "having" are intended to specify the presence of the features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, and should be understood not to preclude in advance the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0046] Hereinafter, with reference to the accompanying drawings, embodiments of the present invention will be described in detail as follows.

[0047] - Comparative Example - Prior to the description of the embodiments, a comparative example to be compared with the circuit board of the embodiments of the present application will be described.

[0048] FIG. 1 is a cross-sectional view showing a circuit board according to a comparative example.

[0049] Referring to FIG. 1, the circuit board of the comparative example includes an insulating layer 10, a circuit pattern layer, and a protective layer 30.

[0050] The circuit pattern layer is disposed on the upper surface of the insulating layer 10.

[0051] The circuit pattern layer includes a plurality of circuit patterns spaced apart from each other. The circuit patterns include pads and traces.

[0052] For example, the circuit pattern layer includes a first pad 21, a second pad 22, and a trace 23.

[0053] The protective layer 30 includes a plurality of open regions.

[0054] For example, the protective layer 30 includes a first open region 31 that vertically overlaps the first pad 21.

[0055] The first open region 31 partially opens the upper surface of the first pad 21. For example, the first open region 31 is an SMD type open region.

[0056] The width w1 of the first open region 31 exceeds at least 50 μm according to the exposure resolution (e.g., high resolution) of the protective layer 30. Specifically, the width w1 of the first open region 31 exceeds at least 70 μm according to the exposure resolution (e.g., general resolution) of the protective layer 30. Therefore, the width of the first pad 21 overlapping perpendicularly with the first open region 31 exceeds 70 μm, which is larger than the width w1 of the first open region 31. For example, the width of the first pad 21 exceeds 90 μm, which is larger than the width w1 of the first open region 31. This takes into account the process deviation in the process of forming the first open region 31.

[0057] As described above, the first open region 31 exceeds at least 50 μm or exceeds 70 μm, whereby the width of the first pad 21 exceeds 70 μm or exceeds 90 μm. Thereby, the comparative example has a limit in reducing the interval between a plurality of first pads. That is, in the comparative example, there is a limit in miniaturizing the width w1 of the first open region 31, and further there is a limit in miniaturizing the width of the first pad 21.

[0058] The protective layer 30 includes a second open region 32 that overlaps perpendicularly with the second pad 22. The second open region 32 entirely opens the upper surface of the second pad 22. That is, the second open region 32 is an NSMD type open region.

[0059] The width w2 of the second open region 32 exceeds 50 μm or 70 μm according to the exposure resolution of the protective layer 30. That is, the protective layer 30 has a limit in miniaturizing the width w2 of the second open region 32.

[0060] Furthermore, the protective layer 30 undergoes an exposure and curing process to form the first open region 31 and the second open region 32. At this time, in the process of exposing and curing the protective layer 30, there is a problem that complete curing of the lower region of the protective layer 30 is not achieved. And when the complete curing is not performed, in the process of forming the second open region 32, there is a problem that an undercut 33 is formed in the lower region of the side wall of the second open region 32.

[0061] At this time, the horizontal distance w3 of the undercut 33 in the comparative example exceeds 15 μm or exceeds 20 μm. The horizontal distance w3 of the undercut 33 means the horizontal distance from the innermost end to the outermost end in the lower region of the side wall of the second open region 32.

[0062] At this time, the circuit pattern layer includes a trace 23 disposed adjacent to the second pad 22. And in the comparative example, the horizontal distance w3 of the undercut 33 must be considered when arranging the trace 23. That is, in the comparative example, if the horizontal distance w3 of the undercut 33 is not considered, the side portion of the trace 23 may be exposed through the undercut 33. In this case, the solder ball disposed on the second pad 22 diffuses into the undercut 33, thereby causing a problem of circuit short - circuiting in contact with the trace 23. Therefore, in the comparative example, the separation interval between the second pad 22 and the trace 23 is determined in consideration of the width w2 of the second open region 32 and the horizontal distance w3 of the undercut 33. Therefore, in the comparative example, there is a problem that the separation interval increases, resulting in a decrease in circuit integration degree.

[0063] In addition, recently, as the performance of electrical / electronic products has been improving, technologies for attaching more semiconductor elements to a substrate of limited size have been studied, and as a result, miniaturization of circuit patterns has been demanded. In the case of a semiconductor package using a circuit board of a comparative example, the limit of the minimum width of the open region that can be formed in the protective layer 30 and the horizontal distance of the undercut must be considered, and thus there is a limit to miniaturizing the circuit pattern.

[0064] Furthermore, recently, the functions processed by logic chips such as application processors AP (Application Processors) have been increasing. As a result, it has become difficult to implement all functions on a single logic chip. Therefore, the circuit board requires a space for mounting a plurality of logic chips. However, it is difficult to mount a plurality of logic chips that perform different functions within a limited space using the circuit board of the comparative example.

[0065] The embodiments are for solving such problems, and enable the width of the open region that can be formed in the protective layer to be significantly reduced compared to the comparative example. Also, the embodiments minimize the horizontal distance of the undercut formed on the sidewall of the open region of the protective layer or enable the undercut to be removed. Furthermore, the embodiments enable the tolerance SRR (Solder Resist Registration) between the center of the open region of the protective layer and the center of the pad to be reduced. Also, the embodiments enable the bonding force with the molding layer to be improved while improving electrical and mechanical characteristics.

[0066] - Electronic Device - Prior to the description of the embodiments, an electronic device including the semiconductor package of the embodiments will be briefly described. The electronic device includes a main board (not shown). The main board can be physically and / or electrically connected to various components. For example, the main board can be connected to the semiconductor package of the embodiments. Various semiconductor elements can be mounted on the semiconductor package.

[0067] The semiconductor device can include active devices and / or passive devices. The active device can be an integrated circuit (IC)-type semiconductor chip in which hundreds to millions or more devices are integrated in one chip. The semiconductor chip can be a logic chip, a memory chip, etc. The logic chip can be a central processor (CPU), a graphics processor (GPU), etc. For example, the logic chip is an AP including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller, or an analog-digital converter, an application-specific IC (ASIC), etc., or a chipset including a specific combination of those listed so far.

[0068] The memory chip can be a stacked memory such as HBM. Also, the memory chip can include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory.

[0069] On the other hand, the product group to which the semiconductor package of the embodiment is applied can be any one of a Chip Scale Package (CSP), a Flip Chip-Chip Scale Package (FC-CSP), a Flip Chip Ball Grid Array (FC-BGA), a Package On Package (POP), and a System In Package (SIP), but is not limited thereto.

[0070] In addition, the electronic device can be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, Automotive, etc. However, it is not limited thereto, and it goes without saying that it can be any other electronic device that processes data in addition to these.

[0071] Hereinafter, the circuit board of the embodiment will be described.

[0072] - Circuit board -

[0073] The circuit board means a board before a semiconductor element or chip is mounted.

[0074] FIG. 2 is a cross-sectional view showing a circuit board according to the first embodiment, FIG. 3 is a cross-sectional view more specifically showing the circuit pattern layer of FIG. 2, FIG. 4 is a scanning electron microscope image showing the upper surface of the first protective layer of FIG. 3, FIG. 5 is a scanning electron microscope image showing the side wall of the open region of the first protective layer of FIG. 3, and FIG. 6 is a diagram showing a resist pattern used to form the open region of the first protective layer of the embodiment.

[0075] Hereinafter, the circuit board according to the first embodiment will be specifically described with reference to FIGS. 2 to 6.

[0076] The circuit board of the first embodiment provides a mounting space capable of mounting at least one semiconductor element.

[0077] For example, the circuit board of the first embodiment can provide a mounting space for mounting one semiconductor element, whereas it can provide a plurality of mounting spaces for mounting two or more semiconductor elements.

[0078] Also, one logic chip can be mounted on the circuit board of the first embodiment. Also, at least two logic chips of different types can be mounted on the circuit board of the first embodiment. Also, at least one logic chip and at least one memory chip can be mounted on the circuit board of the first embodiment.

[0079] The circuit board 100 of the first embodiment includes an insulating layer 110. The insulating layer 110 can have one or more layers. Preferably, the insulating layer 110 can have a multilayer structure. At this time, in the drawing, the insulating layer 110 is shown as being composed of one layer, but it is not limited thereto. For example, the insulating layer 110 can include a plurality of insulating layers having a stacked structure in the vertical direction.

[0080] Hereinafter, for convenience of explanation, the insulating layer 110 will be described as being shown as one layer.

[0081] The insulating layer 110 can be rigid or flexible.

[0082] As an example, the insulating layer 110 can include a prepreg. For example, the insulating layer 110 can be a prepreg in which glass fibers are impregnated with a resin. The resin can be an epoxy resin, but is not limited thereto.

[0083] In addition, the insulating layer 110 can include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. For example, the insulating layer 110 can include reinforced or ductile plastics such as polyimide PI (Polyimide), polyethylene terephthalate PET (polyethylene terephthalate), propylene glycol PPG (propylene glycol), and polycarbonate (PC). For example, the insulating layer 110 can include an optically isotropic film. For example, the insulating layer 110 can include COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), optically isotropic polycarbonate PC (polycarbonate), or optically isotropic polymethyl methacrylate (PMMA), etc. For example, the insulating layer 110 can be formed of a material including an inorganic filler and an insulating resin. For example, the insulating layer 110 can have a structure in which inorganic fillers such as silica or alumina are disposed in a thermosetting resin or a thermoplastic resin. For example, ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), PID (Photo Imagable Dielectric resin), BT, etc. can be used for the insulating layer 110. For example, the insulating layer 110 can include RCC (Resin coated copper).

[0084] The insulating layer 110 can have a thickness in the range of 10 μm to 60 μm. For example, when the insulating layer 110 includes a plurality of layers, the thickness of each of the plurality of layers can satisfy the range of 10 μm to 60 μm. Preferably, the insulating layer 110 can satisfy a thickness in the range of 15 μm to 55 μm. More preferably, the insulating layer 110 can satisfy a thickness in the range of 18 μm to 52 μm.

[0085] The thickness of the insulating layer 110 can mean the vertical distance between a plurality of circuit pattern layers arranged adjacent to each other in the thickness direction. For example, the thickness of the insulating layer 110 can mean the vertical distance between the first circuit pattern layer and the second circuit pattern layer 130. For example, the thickness of the insulating layer 110 means the vertical distance between the lower surface of the first circuit pattern layer 120 and the upper surface of the second circuit pattern layer 130.

[0086] If the thickness of the insulating layer 110 is less than 10 μm, the warping characteristics of the circuit board 100 may deteriorate. For example, if the thickness of the insulating layer 110 is less than 10 μm, the first circuit pattern layer 120 and the second circuit pattern layer 130 disposed on the surface of the insulating layer 110 may not be stably protected, and problems with electrical reliability and / or physical reliability may occur. Also, if the thickness of the insulating layer 110 is less than 10 μm, the processability in the process of forming the first circuit pattern layer 120 or the second circuit pattern layer 130 on the insulating layer 110 may deteriorate.

[0087] Also, if the thickness of the insulating layer 110 exceeds 60 μm, the overall thickness of the circuit board 100 increases, and thus the thickness of the semiconductor package can increase. Also, if the thickness of the insulating layer 110 exceeds 60 μm, it may be difficult to miniaturize the first circuit pattern layer and / or the second circuit pattern layer 130. For example, if the thickness of the insulating layer 110 exceeds 60 μm, it may be difficult to form the width of the first circuit pattern layer and / or the second circuit pattern layer 130 and the interval between adjacent patterns to be 12 μm or less, 10 μm or less, 8 μm or less, or 6 μm or less. And if it is difficult to miniaturize the first circuit pattern layer and / or the second circuit pattern layer 130, the integration degree of the circuit decreases, thereby increasing the signal transmission distance and increasing the signal transmission loss.

[0088] The circuit board 100 of the first embodiment includes a circuit pattern layer disposed on the insulating layer 110.

[0089] For example, the circuit board 100 of the first embodiment includes a first circuit pattern layer 120 disposed on the upper surface of the insulating layer 110. Further, the circuit board 100 includes a second circuit pattern layer 130 disposed on the lower surface of the insulating layer 110.

[0090] The first circuit pattern layer 120 may be divided into a plurality of circuit patterns according to position or function. For example, the first circuit pattern layer 120 may include a first pad 120-1 and a second pad 120-2. At least one of the first pad 120-1 and the second pad 120-2 is formed corresponding to the mounting region of the semiconductor element. For example, at least one of the first pad 120-1 and the second pad 120-2 may mean a mounting pad connected to the terminal of the semiconductor element. In contrast, at least one of the first pad 120-1 and the second pad 120-2 may mean a terminal pad coupled to an external substrate. For example, at least one of the first pad 120-1 and the second pad 120-2 may mean a terminal pad coupled to an interposer or the main board of an electronic device.

[0091] At this time, recently, with the increase in the functions provided by semiconductor elements, the number of terminals provided in the semiconductor elements and the number of mounted semiconductor elements have been increasing.

[0092] Therefore, miniaturization of the first pad 120-1 and the second pad 120-2 of the first circuit pattern layer 120 is required. However, in the comparative example, there was a limit to miniaturizing the first circuit pattern layer 120 due to the size limitation and undercut of the open region of the protective layer. At this time, the embodiment enables miniaturization of the first circuit pattern layer 120 by minimizing the size of the open region of the protective layer and the horizontal distance of the undercut. This can be achieved by the method for forming an open region in the protective layer described below.

[0093] On the one hand, when the insulating layer 110 of the circuit board 100 includes a plurality of layers, the first circuit pattern layer 120 may be disposed on the upper surface of the insulating layer disposed on the uppermost side among the plurality of layers of the insulating layer 110, and the second circuit pattern layer 130 may be disposed on the lower surface of the insulating layer disposed on the lowermost side among the plurality of layers of the insulating layer 110. For example, the first circuit pattern layer 120 and the second circuit pattern layer 130 may represent outer layer circuit pattern layers, but are not limited thereto.

[0094] On the other hand, when the insulating layer 110 includes a plurality of layers, additional inner layer circuit pattern layers may be disposed between the plurality of layers.

[0095] The first circuit pattern layer 120 and the second circuit pattern layer 130 can each have a plurality of layer structures.

[0096] The first circuit pattern layer 120 may include a first metal layer 121 and a second metal layer 122. That is, each of the first pad 120-1 and the second pad 120-2 of the first circuit pattern layer 120 may include the first metal layer 121 and the second metal layer 122.

[0097] The first metal layer 121 of the first circuit pattern layer 120 may be disposed on the upper surface of the insulating layer 110. For example, the first metal layer 121 of the first circuit pattern layer 120 may protrude above the upper surface of the insulating layer 110.

[0098] The first metal layer 121 of the first circuit pattern layer 120 may be formed by an electroless plating method. As an example, the first metal layer 121 may be formed by a chemical copper plating method, but is not limited thereto. For example, the first metal layer 121 may be formed by a sputtering method.

[0099] The thickness of the first metal layer 121 of the first circuit pattern layer 120 can satisfy the range of 0.2 μm to 3.0 μm. Preferably, the thickness of the first metal layer 121 of the first circuit pattern layer 120 can satisfy the range of 0.3 μm to 2.8 μm. More preferably, the thickness of the first metal layer 121 of the first circuit pattern layer 120 can satisfy the range of 0.5 μm to 2.5 μm.

[0100] If the thickness of the first metal layer 121 of the circuit pattern layer 120 is less than 0.2 μm, the first metal layer 121 of the first circuit pattern layer 120 may not function as a seed layer. If the thickness of the first metal layer 121 of the first circuit pattern layer 120 is less than 0.2 μm, it may be difficult to form a first metal layer 121 with a uniform thickness on the upper surface of the insulating layer 110.

[0101] If the thickness of the first metal layer 121 of the first circuit pattern layer 120 exceeds 3.0 μm, the process time for forming the first metal layer 121 of the first circuit pattern layer 120 increases, and the yield may decrease accordingly. Also, if the thickness of the first metal layer 121 of the first circuit pattern layer 120 exceeds 3.0 μm, the etching time of the first metal layer 121 in the forming process of the first circuit pattern layer 120 can increase. Further, when etching the first metal layer 121 of the first circuit pattern layer 120, deformation of the second metal layer 122 of the first circuit pattern layer 120 may occur. Here, the deformation of the second metal layer 122 of the first circuit pattern layer 120 can mean that the side portion of the second metal layer 122 is also etched together during the etching of the first metal layer 121, so the difference between the width of the upper surface and the width of the lower surface of the second metal layer 122 becomes large. For example, the deformation of the second metal layer 122 of the first circuit pattern layer 120 can mean that the shape of the vertical cross-section of the second metal layer 122 changes from a rectangular shape to a trapezoidal shape.

[0102] Further, when the thickness of the first metal layer 121 of the first circuit pattern layer 120 exceeds 3.0 μm, the etching amount in the etching process of the first metal layer 121 increases, whereby the depth of the depressions (e.g., undercuts) formed on the side portions of the first metal layer 121 and the side portions of the second metal layer 122 can increase. For example, when the etching amount in the etching process of the first metal layer 121 increases, the difference between the width of the first metal layer 121 and the width of the second metal layer 122 may become larger. And when the difference between the width of the first metal layer 121 and the width of the second metal layer 122 becomes larger, the electrical characteristics may deteriorate due to an increase in signal transmission loss. Also, when the difference between the width of the first metal layer 121 and the width of the second metal layer 122 becomes larger, dendrites may be formed by electromigration, whereby the electrical and / or physical characteristics of the first circuit pattern layer 120 may deteriorate.

[0103] The second metal layer 122 of the first circuit pattern layer 120 can be an electrolytic plating layer obtained by electrolytically plating the first metal layer 121 as a seed layer. The second metal layer 122 of the first circuit pattern layer 120 can be formed with a certain thickness on the first metal layer 121. The second metal layer 122 of the first circuit pattern layer 120 can include, but is not limited to, the same metal as the first metal layer 121 of the first circuit pattern layer 120. As an example, the first metal layer 121 and the second metal layer 122 of the first circuit pattern layer 120 can each include copper.

[0104] The thickness of the second metal layer 122 of the first circuit pattern layer 120 may be larger than the thickness of the first metal layer 121 of the first circuit pattern layer 120.

[0105] The thickness of the second metal layer 122 of the first circuit pattern layer 120 can satisfy the range of 3.5 μm to 25 μm. Preferably, the thickness of the second metal layer 122 of the first circuit pattern layer 120 can satisfy the range of 4.0 μm to 23 μm. More preferably, the thickness of the second metal layer 122 of the first circuit pattern layer 120 can satisfy the range of 4.5 μm to 22 μm.

[0106] When the thickness of the second metal layer 122 of the first circuit pattern layer 120 is less than 3.5 μm, the etching of the second metal layer 122 can also be carried out together in the etching process of the first metal layer 121. When the thickness of the second metal layer 122 of the first circuit pattern layer 120 is less than 3.5 μm, the allowable current of the signal transmitted through the first circuit pattern layer decreases, and the electrical characteristics may deteriorate accordingly. When the thickness of the second metal layer 122 of the first circuit pattern layer 120 exceeds 25 μm, it may be difficult to miniaturize the first circuit pattern layer 120. For example, when the thickness of the second metal layer 122 of the first circuit pattern layer 120 exceeds 25 μm, the width and interval of the patterns constituting the first circuit pattern layer 120 may not satisfy the required conditions. As a result, the circuit integration degree may decrease, or the volume of the circuit board and the semiconductor package may increase.

[0107] On the other hand, the second circuit pattern layer 130 of the circuit board 100 of the first embodiment can include a first metal layer 131 and a second metal layer 132 corresponding to the first circuit pattern layer 120. The first metal layer 131 of the second circuit pattern layer 130 of the circuit board 100 of the first embodiment corresponds to the first metal layer 121 of the first circuit pattern layer 120. Also, the second metal layer 132 of the second circuit pattern layer 130 of the circuit board 100 of the first embodiment corresponds to the second metal layer 122 of the first circuit pattern layer 120. Thereby, the second circuit pattern layer 120 of the circuit board 100 of the first embodiment can include the characteristics of the first circuit pattern layer 120 described above as they are. Therefore, a specific description of the second circuit pattern layer 130 of the first embodiment is omitted.

[0108] The circuit board 100 of the first embodiment can include a through electrode 140. The through electrode 140 can penetrate the insulating layer 110. Preferably, the through electrode 140 can penetrate the insulating layer 110 so as to electrically connect between the first circuit pattern layer 120 and the second circuit pattern layer 130. At this time, when the circuit board 100 has a multi-layer structure, the through electrode 140 can electrically connect between circuit pattern layers that are vertically spaced apart and adjacent to each other.

[0109] The through electrode 140 can be formed by filling the inside of a through hole penetrating the insulating layer 110 with a conductive material.

[0110] The through hole can be formed by any one of machining methods such as mechanical, laser, and chemical machining. Also, when the through hole is formed by mechanical machining, methods such as milling, drill, and routing can be used. Also, when the through hole is formed by laser machining, UV or CO2 laser methods can be used. Also, when the through hole is formed by chemical machining, chemicals including minosilane, ketones, etc. can be used. However, the embodiments are not limited thereto.

[0111] Exemplarily, a through hole for arranging the through electrode 140 can be formed by applying a method similar to the method for forming the open region provided in the first protective layer 150 of the embodiment. Therefore, the width of the through electrode 140 may be almost non-existent from the upper surface to the lower surface. Exemplarily, the width of the upper surface of the through electrode 140 may be the same as the width of the lower surface of the through electrode 140.

[0112] The through electrode 140 includes a plurality of metal layers.

[0113] The through electrode 140 includes a first metal layer 141 and a second metal layer 142. The first metal layer 141 of the through electrode 140 can correspond to the first metal layer 141 of the first circuit pattern layer 120. Also, the second metal layer 142 of the through electrode 140 can correspond to the second metal layer 122 of the first circuit pattern layer 120. Accordingly, specific descriptions of the first metal layer 141 and the second metal layer 142 of the through electrode 140 are omitted.

[0114] On the other hand, in the above, since the first circuit pattern layer 120 and the second circuit pattern layer 130 of the embodiment are manufactured by the SAP process, they have been described as including a first metal layer and a second metal layer, but are not limited thereto.

[0115] For example, the first circuit pattern layer 120 and the second circuit pattern layer 130 can be manufactured by the MSAP process. Accordingly, in each of the first circuit pattern layer 120 and the second circuit pattern layer 130, a third metal layer can be further disposed between the first metal layer and the insulating layer. The third metal layer can mean a copper foil layer attached during the lamination of the insulating layer, but is not limited thereto.

[0116] On the other hand, the circuit board 100 of the first embodiment can include a protective layer.

[0117] For example, the circuit board 100 can include a first protective layer 150 disposed on the insulating layer 110. For example, the circuit board 100 can include a second protective layer 160 disposed under the insulating layer 110.

[0118] The first protective layer 150 and the second protective layer 160 can be a resist layer. Preferably, the first protective layer 150 and the second protective layer 160 can be a solder resist layer including an organic polymer substance. As an example, the first protective layer 150 and the second protective layer 160 can include an epoxy acrylate-based resin. Specifically, the first protective layer 150 and the second protective layer 160 can include a resin, a curing agent, a pigment, a solvent, a filler, an additive, an acrylic monomer, and the like.

[0119] The thickness of each of the first protective layer 150 and the second protective layer 160 may be greater than the thickness of each of the first circuit pattern layer 120 and the second circuit pattern layer 130.

[0120] In other words, the thickness of the first protective layer 150 may be greater than the thickness of the first circuit pattern layer. It may be greater than the thickness. Also, the thickness of the second protective layer 160 may be greater than the thickness of the second circuit pattern layer 130.

[0121] The thickness of the first protective layer 150 can mean the vertical distance from the lower surface of the first protective layer 150 to the upper surface of the first protective layer 150. For example, the first protective layer 150 is disposed on the upper surface of the insulating layer 110. Thereby, the thickness of the first protective layer 150 can mean the vertical distance from the upper surface of the insulating layer 110 to the upper surface of the first protective layer 150.

[0122] The thickness of the first protective layer 150 can satisfy the range of 6.7 μm to 35.0 μm. Preferably, the thickness of the first protective layer 150 can satisfy the range of 7.3 μm to 32 μm. More preferably, the thickness of the first protective layer 150 can satisfy the range of 8.0 μm to 30 μm.

[0123] When the thickness of the first protective layer 150 exceeds 30 μm, the thickness of the circuit board and the thickness of the semiconductor package can increase. Also, when the thickness of the first protective layer 150 is less than 6.7 μm, the first circuit pattern layer may not be stably protected, thereby reducing electrical reliability or physical reliability.

[0124] Also, the second protective layer 160 can have a thickness corresponding to the thickness of the first protective layer 150, but is not limited thereto.

[0125] On the one hand, the first protective layer 150 includes at least one open region. Also, the second protective layer 160 includes at least one open region. At this time, the width of the open region formed in the first protective layer 150 and the second protective layer 160 of the embodiment may be smaller than the width of the open region of the comparative example. This can be achieved not by forming the open region by exposing and developing the first protective layer 150 and the second protective layer 160, but by forming the open regions of the first protective layer 150 and the second protective layer 160 using another resist pattern.

[0126] Hereinafter, the open region formed in the first protective layer 150 will be specifically described. However, hereinafter, the description of the open region formed in the second protective layer 160 will be omitted. For example, the open region formed in the second protective layer 160 can have a structure corresponding to the open region formed in the first protective layer 150 described later.

[0127] The first protective layer 150 includes an open region. The open region can be in the form of a through hole penetrating the upper and lower surfaces of the first protective layer 150.

[0128] The first protective layer 150 includes a first open region 151. For example, the first protective layer 150 can include a first open region 151 that vertically overlaps with the first pad 120-1 of the first circuit pattern layer 120.

[0129] At this time, the first open region 151 of the first protective layer 150 can partially overlap vertically with the upper surface of the first pad 120-1. For example, the first open region 151 of the first protective layer 150 can be an SMD type open region.

[0130] That is, the width W1 of the first open region 151 of the first protective layer 150 may be smaller than the width of the upper surface of the first pad 120-1. For example, the first protective layer 150 may cover at least a part of the upper surface of the first pad 120-1, and the remaining part of the upper surface of the first pad 120-1 may include the exposed open region 151.

[0131] At this time, the width W1 of the first open region 151 of the first protective layer 150 may be 30 μm or less. Preferably, the width W1 of the first open region 151 of the first protective layer 150 may be 28 μm or less. More preferably, the width W1 of the first open region 151 of the first protective layer 150 may be 25 μm or less.

[0132] For example, the width W1 of the first open region 151 of the first protective layer 150 can satisfy the range of 10 μm to 30 μm. Preferably, the width W1 of the first open region 151 of the first protective layer 150 can satisfy the range of 12 μm to 28 μm. More preferably, the width W1 of the first open region 151 of the first protective layer 150 can satisfy the range of 13 μm to 25 μm.

[0133] When the width W1 of the first open region 151 of the first protective layer 150 is less than 10 μm, the coating amount of a connection part such as a solder ball disposed in the first open region 151 decreases, and thus the bonding force with the semiconductor element may decrease. When the width W1 of the first open region 151 of the first protective layer 150 exceeds 30 μm, the width of the first pad 120-1 correspondingly increases, and thus the circuit integration degree may decrease.

[0134] At this time, the first open region 151 of the first protective layer 150 in the first embodiment may have almost no change in width from the region adjacent to the upper surface of the first protective layer 150 to the region adjacent to the lower surface of the first protective layer 150. Here, the fact that there is almost no change in width can mean that the inclination of the first inner surface 151S of the first protective layer 150 constituting the first open region 151 is close to vertical. For example, the fact that there is almost no change in width can mean that in the entire region in the thickness direction of the first open region 151, the difference in width between the region having the maximum width and the region having the minimum width is 3 μm or less, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1 μm or less, or 0.5 μm or less.

[0135] That is, the first open region 151 of the first protective layer 150 in the first embodiment does not include a region where the width rapidly increases from the upper region to the lower region. In other words, the lower end of the first inner surface 151S of the first open region 151 of the first protective layer 150 in the first embodiment does not include an undercut.

[0136] This is because the first open region 151 of the first protective layer 150 is not formed by exposing and developing the first protective layer 150, but by using another resist pattern. That is, in the first embodiment, before forming the first protective layer 150, a first resist pattern DFR1-F (see FIG. 6) corresponding to the first open region 151 is formed on the first pad 120-1. Then, in the first embodiment, the first protective layer 150 is formed in a state where the first resist pattern DFR1-F is disposed. Thereby, a first open region 151 corresponding to the first resist pattern DFR1-F is formed in the first protective layer 150.

[0137] Here, referring to FIG. 6, the first resist pattern DFR1 F can be formed using a photosensitive film. Thereby, the first resist pattern DFR1-F can form a finer pattern compared to forming a pattern on the solder resist.

[0138] In the first embodiment, when forming the first protective layer 150 in a state where the first resist pattern DFR1-F is preferentially disposed, the first protective layer 150 is made to entirely cover the first resist pattern DFR1-F. Thereafter, the first embodiment performs a process of thinning the first protective layer 150 to reduce the thickness of the first protective layer 150 to a target thickness. At this time, with the first resist pattern DFR1-F disposed, the first protective layer 150 may have a target thickness without covering the first resist pattern DFR1-F. That is, without performing the thinning process in a state where the first resist pattern DFR1-F is disposed, the first protective layer 150 may be made to have a certain thickness. However, when performing as described above, a thickness deviation may occur in the first protective layer 150 in a first region adjacent to the first resist pattern DFR1-F and a second region excluding the first region. For example, when not performing the thinning process as described above, the flatness of the upper surface 150T of the first protective layer 150 may decrease. Accordingly, the embodiment performs a process of thinning this with the target thickness in a state where the first protective layer 150 has a certain thickness.

[0139] Therefore, the upper surface 150T of the first protective layer 150 of the first embodiment can have a surface roughness different from the surface roughness of the first inner surface 151S of the first open region 151.

[0140] That is, the upper surface 150T of the first protective layer 150 is a surface thinned by the thinning process. In contrast, the first inner surface 151S of the first open region 151 of the first protective layer 150 is a surface that has not been thinned. For example, the first inner surface 151S of the first open region 151 of the first protective layer 150 can correspond to the surface roughness of the first resist pattern DFR1-F.

[0141] In other words, the upper surface 150T of the first protective layer 150 may be different from the roughness of the inner surface 150S (see FIG. 5) of the open region of the first protective layer 150. The inner surface 150S of the open region may include a first inner surface 151S of the first open region 151 and a second inner surface 152S of the second open region 152.

[0142] The surface roughness of the upper surface 150T of the first protective layer 150 may be greater than the surface roughness of the inner surface of the open region of the first protective layer 150.

[0143] That is, referring to FIG. 4, the first protective layer 150 includes a resin and a filler 150F dispersed in the resin. At this time, when the first protective layer 150 is thinned, the filler 150F disposed in the first protective layer 150 may be exposed on the upper surface 150T of the first protective layer 150. In contrast, the filler 150F may not be exposed on the inner surface 150S of the open region of the first protective layer 150, or a smaller amount of filler may be exposed than on the upper surface 150T. Therefore, the upper surface 150T of the first protective layer 150 can have a surface roughness greater than that of the inner surface of the open region of the first protective layer 150 due to the filler 150F. Preferably, the filler 150F may not be exposed on the inner surface 150S of the open region of the first protective layer 150.

[0144] On the other hand, on the upper surface 150T of the first protective layer 150, the filler 150F may be entirely exposed. That is, in the embodiment, thinning is performed over the entire area of the surface of the first protective layer 150. The entire area of the upper surface 150T of the first protective layer 150 may be a thinned surface. Accordingly, on the upper surface 150T of the first protective layer 150, the filler 150F may be entirely exposed. Then, in the embodiment, the surface roughness of the upper surface 150T of the first protective layer 150 can be increased through the filler 150F exposed through the upper surface 150T of the first protective layer 150. Through this, in the embodiment, the bonding area between the first protective layer 150 and the molding layer in the molding process after mounting the semiconductor element on the circuit board can be increased, thereby improving the bonding force.

[0145] On the other hand, the first protective layer 150 includes a second open region 152. For example, the first protective layer 150 may include a second open region 152 that vertically overlaps with the second pad 120-2 of the first circuit pattern layer 120.

[0146] At this time, the second open region 152 of the first protective layer 150 may entirely vertically overlap with the upper surface of the second pad 120-2. For example, the second open region 152 of the first protective layer 150 may be an NSMD type open region.

[0147] That is, the width W2 of the second open region 152 of the first protective layer 150 may be larger than the width of the upper surface of the second pad 120-2. For example, the first protective layer 150 may entirely expose the upper surface and the inner surface of the second pad 120-2. For example, the second inner surface 152S of the second open region 152 of the first protective layer 150 may be separated without contacting the second pad 120-2. For example, the second pad 120-2 may not contact the first protective layer 150.

[0148] At this time, the width W2 of the second open region 152 of the first protective layer 150 may be 30 μm or less. Preferably, the width W2 of the second open region 152 of the first protective layer 150 may be 28 μm or less. More preferably, the width W2 of the second open region 152 of the first protective layer 150 may be 25 μm or less.

[0149] For example, the width W2 of the second open region 152 of the first protective layer 150 can satisfy the range of 10 μm to 30 μm. Preferably, the width W2 of the second open region 152 of the first protective layer 150 can satisfy the range of 12 μm to 28 μm. More preferably, the width W2 of the second open region 152 of the first protective layer 150 can satisfy the range of 13 μm to 25 μm.

[0150] When the width W2 of the second open region 152 of the first protective layer 150 is less than 10 μm, the coating amount of a connection part such as a solder ball disposed in the second open region 152 may decrease, and thus the bonding force with the semiconductor element may decrease. When the width W2 of the second open region 152 of the first protective layer 150 exceeds 30 μm, the separation distance from a circuit pattern (for example, a trace) adjacent to the second pad 120-2 increases, and thus the integration degree of the circuit may decrease.

[0151] At this time, the second open region 152 of the first protective layer 150 in the first embodiment may have almost no change in width from the region adjacent to the upper surface of the first protective layer 150 to the region adjacent to the lower surface of the first protective layer 150. For example, the inclination of the second inner surface 152S of the first protective layer 150 constituting the second open region 152 may be close to vertical. For example, in the entire region in the thickness direction, the difference in width between the region having the maximum width and the region having the minimum width of the second open region 152 may be 3 μm or less, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1 μm or less, or 0.5 μm or less.

[0152] That is, the second open region 152 of the first protective layer 150 in the first embodiment does not include a region where the width rapidly increases from the upper region to the lower region. In other words, the lower end of the second inner surface 152S of the second open region 152 of the first protective layer 150 in the first embodiment does not include an undercut.

[0153] That is, in the first embodiment, before forming the first protective layer 150, a resist pattern DFR1-F can be formed in the second open region 152 corresponding to the first open region 151. Through this, the second open region 152 can be formed in the first protective layer 150 corresponding to the resist pattern DFR1-F.

[0154] Also, the second inner surface 152S of the second open region 152 is a surface where no thinning is performed. Thus, the surface roughness of the second inner surface 152S of the second open region 152 may be smaller than the surface roughness of the upper surface 150T of the first protective layer 150.

[0155] As described above, the first protective layer 150 in the first embodiment includes an open region. At this time, the open region can be formed in the first protective layer 150 using another resist pattern DFR1-F.

[0156] At this time, the resist pattern DFR1-F can be a dry film photoresist (DFR). At this time, the photosensitive film does not include a filler inside. Thus, generally, the minimum size of the resist pattern formed by exposing and developing the photosensitive film is smaller than the resist pattern formed by exposing and developing a solder resist containing a filler.

[0157] Accordingly, instead of exposing and developing the protective layer itself such as solder resist, the embodiments expose and develop a photosensitive film capable of realizing a relatively fine pattern to form a resist pattern. Then, the embodiments form an open region in the first protective layer 150 using the resist pattern. Therefore, the embodiments can reduce the size of the open region formed in the first protective layer 150 compared to the comparative example, thereby improving the circuit integration density.

[0158] At this time, since the embodiments do not expose and develop the first protective layer 150, the first protective layer 150 may not contain a photoinitiator. For example, general solder resist contains a photoinitiator for exposure and development. At this time, the photoinitiator acts as a factor that degrades the physical and electrical properties of the circuit board.

[0159] Here, in the embodiments, since the first protective layer 150 is not exposed and developed, the first protective layer 150 does not contain a photoinitiator. Thereby, since the first protective layer 150 does not contain a photoinitiator in the embodiments, the physical and electrical properties of the circuit board can be improved.

[0160] Furthermore, since the first protective layer 150 does not contain a photoinitiator in the embodiments, the types of insulating layers that can be used as the first protective layer 150 can be expanded, and the unit price required for the development of the protective layer can be further reduced.

[0161] For example, the first protective layer 150 of the embodiments can be a solder resist that does not contain a photoinitiator. Different from this, the first protective layer 150 of the embodiments can use an insulating layer in which an inorganic filler of silica or alumina is disposed in a thermosetting resin or a thermoplastic resin without containing glass fibers. For example, as the first protective layer 150, ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), PID (Photo Imagable Dielectric resin), BT, etc. can be used.

[0162] However, the solder resist generally used for a circuit board in the embodiment can also be directly used to realize the first protective layer 150 and the second protective layer 160 in this specification. For example, according to the embodiment, the first protective layer 150 and the second protective layer 160 can also contain a photoinitiator.

[0163] FIG. 7 is a plan view for explaining the tolerance SRR (Solder Resist Registration) according to a comparative example, and FIG. 8 is a diagram for explaining the tolerance according to the first embodiment.

[0164] Referring to FIG. 7(a), in the case of the comparative example, the first pad 21 includes a first portion 21a exposed through the first open region 31 of the protective layer 30 and a second portion 21b covered by the protective layer 30. At this time, in the comparative example, the protective layer 30 is exposed and developed to form the first open region 31. At this time, the exposure resolution of the protective layer 30 is significantly lower than that of the DFR. Thereby, in the comparative example, it can be confirmed that the center 21C of the first pad 21 and the center 31C of the first open region 31 are deviated by a first tolerance d1. Specifically, the first tolerance d1 between the center 21C of the first pad 21 and the center 31C of the first open region 31 in the comparative example exceeds 12.5 μm, or exceeds 14 μm, or exceeds 15 μm. Thereby, in the comparative example, there may occur an alignment reliability problem that at least a part of the first open region 31 does not overlap perpendicularly with the first pad 21.

[0165] Referring to FIG. 7(b), in the case of the comparative example, the second pad 22 is entirely exposed through the second open region 32 of the protective layer 30. At this time, in the comparative example, the protective layer 30 is exposed and developed to form the second open region 32. At this time, the exposure resolution of the protective layer 30 is significantly lower than that of the DFR. As a result, in the comparative example, it can be confirmed that the center 22C of the second pad 22 and the center 32C of the second open region 32 are deviated by a second tolerance d2. Specifically, the second tolerance d2 between the center 22C of the second pad 22 and the center 32C of the second open region 32 in the comparative example exceeds 12.5 μm, or exceeds 14 μm, or exceeds 15 μm. As a result, in the comparative example, there may occur an alignment reliability problem in which at least a part of the upper surface of the second pad 22 is covered by the protective layer 30.

[0166] In contrast, the embodiment can significantly reduce the tolerance compared to the comparative example.

[0167] For example, referring to FIG. 8(a), in the case of the embodiment, the first pad 120-1 includes a first portion 120-1a exposed through a first open region 151 of the first protective layer 150 and a second portion 120-1b covered by the first protective layer 150. At this time, in the embodiment, instead of exposing and developing the first protective layer 150 to form the first open region 151, a resist pattern DFR1-F formed through DFR is used. As a result, in the embodiment, it can be confirmed that the center 120-1C of the first pad 120-1 and the center 151C of the first open region 151 are deviated by a third tolerance D1 that is significantly less than the first tolerance d1 of the comparative example. Specifically, the third tolerance D1 between the center 120-1C of the first pad 120-1 and the center 151C of the first open region 151 in the embodiment is 10 μm or less, or 9 μm or less, or 8 μm or less. Therefore, the embodiment can improve the alignment accuracy between the first open region 151 and the first pad 120-1. Through this, the embodiment can further improve the electrical reliability and / or physical reliability of the circuit board.

[0168] Also, referring to FIG. 8(b), in the case of the embodiment, the second pad 120-2 is entirely exposed through the second open region 152 of the first protective layer 150. At this time, in the embodiment, instead of exposing and developing the first protective layer 150 to form the second open region 152, the resist pattern DFR1-F formed through the DFR is used. Thereby, in the embodiment, it can be confirmed that the center 120-2C of the second pad 120-2 and the center 152C of the second open region 152 are deviated by a fourth tolerance D2 that is significantly less than the second tolerance d2 of the comparative example. Specifically, the fourth tolerance D2 between the center 120-1C of the second pad 120-2 and the center 152C of the second open region 152 in the embodiment is 10 μm or less, or 9 μm or less, or 8 μm or less. Therefore, the embodiment can improve the alignment accuracy between the second open region 152 and the second pad 120-2. Through this, the embodiment can further improve the electrical reliability and / or physical reliability of the circuit board.

[0169] The embodiment includes an insulating layer, a pad disposed on the insulating layer, and a protective layer disposed on the insulating layer and including an open region that vertically overlaps the pad.

[0170] At this time, the width of the open region of the protective layer in the embodiment is 30 μm or less. For example, the width of the open region of the protective layer in the embodiment can satisfy the range of 10 μm to 30 μm, the range of 12 μm to 28 μm, or the range of 13 μm to 25 μm.

[0171] Furthermore, in the open region of the protective layer of the embodiment, there is almost no change in width as going in the thickness direction. For example, in the entire region in the thickness direction of the open region of the embodiment, the difference in width between the region having the maximum width and the region having the minimum width may be 3 μm or less, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1 μm or less, or 0.5 μm or less. That is, in the embodiment, it is possible to remove the undercut at the lower end of the inner surface of the open region of the protective layer, or to significantly reduce the horizontal distance of the undercut as compared with the comparative example.

[0172] This is because the open region of the protective layer is not formed by exposing and developing the protective layer, but by using another resist pattern. That is, in the embodiment, the protective layer is disposed in a state where a resist pattern is formed using a photosensitive film. Therefore, an open region corresponding to the resist pattern can be formed in the protective layer. At this time, the photosensitive film does not contain a filler inside. Thereby, generally, the minimum size of the resist pattern formed by exposing and developing the photosensitive film is smaller than the resist pattern formed by exposing and developing a solder resist containing a filler.

[0173] Thereby, the embodiment does not expose and develop the protective layer itself such as a solder resist, but forms a resist pattern by exposing and developing a photosensitive film capable of realizing a relatively fine pattern. And the embodiment forms an open region in the protective layer using the resist pattern. Therefore, the embodiment can make the size of the open region formed in the protective layer smaller than that of the comparative example, thereby improving the circuit integration degree.

[0174] Furthermore, since the embodiment does not expose and develop the protective layer, the undercut formed on the inner surface of the open region of the protective layer can be removed. Through this, the embodiment can further reduce the separation interval of the circuit pattern layer.

[0175] On the one hand, in the embodiment, after the thickness of the protective layer is made greater than the thickness of the resist pattern in the state where the resist pattern is disposed, a thinning process is performed thereon. That is, in the embodiment, the protective layer can be made to have a target thickness through the thinning process. At this time, without performing the thinning process, a process of coating the protective layer so as to have a target thickness can also be performed. However, when the thinning process is not performed, there is a problem that the deviation of the thickness of the protective layer becomes large, and the flatness of the protective layer is thereby reduced.

[0176] In contrast, in the embodiment, since the thinning process is performed, the flatness of the protective layer can be improved. Through this, the embodiment can improve the overall physical reliability and electrical reliability of the circuit board and the semiconductor package.

[0177] Also, the upper surface of the protective layer of the embodiment can entirely expose the filler by the thinning process. And the exposed filler increases the surface roughness of the upper surface of the protective layer. Through this, in the embodiment, in the molding process after mounting a semiconductor element on a circuit board, the bonding area between the protective layer and the molding layer can be increased, and thereby the bonding strength can be improved. Through this, the embodiment can further improve the reliability of the product.

[0178] On the one hand, in the embodiment, since the protective layer is not exposed and developed, the protective layer may not contain a photoinitiator. For example, a general solder resist contains a photoinitiator for exposure and development. At this time, the photoinitiator acts as a factor for reducing the physical properties and electrical properties of the circuit board. At this time, since the protective layer of the embodiment does not contain a photoinitiator, the physical properties and electrical properties of the circuit board can be improved.

[0179] Furthermore, since the photosensitizer is not included in the protective layer in the embodiment, the types of insulating layers that can be used as the protective layer can be expanded, and furthermore, the unit price required for the development of the protective layer can be reduced.

[0180] Furthermore, the embodiment can significantly reduce the tolerance between the center of the open area of the protective layer and the center of the pad compared to the comparative example. Through this, the embodiment can improve the mountability of the semiconductor element, and through this, the physical reliability and electrical reliability of the circuit board and the semiconductor package can be improved.

[0181] FIG. 9 is a cross-sectional view showing a circuit board according to a second embodiment.

[0182] Referring to FIG. 9, the circuit board according to the second embodiment will be described.

[0183] The circuit board of the second embodiment includes an insulating layer 210.

[0184] Also, the circuit board of the second embodiment includes a first circuit pattern layer 220 disposed on the insulating layer 210. Also, the circuit board of the second embodiment includes a second circuit pattern layer 230 disposed under the insulating layer 210. Also, the circuit board of the second embodiment includes a through electrode 240 penetrating the insulating layer 210. Also, the circuit board of the second embodiment includes a first protective layer 250 disposed on the insulating layer 210. Also, the circuit board of the second embodiment includes a second protective layer 260 disposed under the insulating layer 210.

[0185] The first circuit pattern layer 220, the second circuit pattern layer 230, and the through electrode 240 each include a first metal layer 221, 231, 241 and a second metal layer 222, 232, 242.

[0186] The first protective layer 250 and the second protective layer 260 each include at least one open area.

[0187] At this time, the circuit board of the second embodiment has a difference in the open regions formed in the first protective layer 250 and the second protective layer 260 compared to the circuit board of the first embodiment.

[0188] Accordingly, hereinafter, the description will be centered around the open region formed in the first protective layer 250.

[0189] The inner surface of the open region in the first embodiment had a substantially vertical inclination with respect to the upper surface of the insulating layer.

[0190] In contrast, the inner surface of the open region of the second embodiment can have an inclination with respect to the upper surface of the insulating layer.

[0191] For example, the first circuit pattern layer 220 includes a first pad 220-1 and a second pad 220-2. And the first protective layer 250 includes a first open region 251 that vertically overlaps the first pad 220-1. Also, the first protective layer 250 includes a second open region 252 that vertically overlaps the second pad 220-2.

[0192] At this time, the basic structures of the first open region 251 and the second open region 252 are the same as those in the first embodiment, and the detailed description thereof will be omitted.

[0193] The width of the first open region 251 can change from the upper surface to the lower surface of the first protective layer 250. For example, the first inner surface 251S of the first protective layer 250 of the first protective layer 250 can have an inclination in which the width decreases in the downward direction. That is, in the second embodiment, the photosensitive film used to form the first open region 251 is a negative type, and the resist pattern DFR1-F can be formed using the negative type photosensitive film. Thereby, the resist pattern DFR1-F can have a shape in which the width decreases in the downward direction. And the first inner surface 251S of the first open region 251 of the first protective layer 250 formed by the resist pattern DFR1-F can have an inclination in which the width decreases in the downward direction. The negative type photosensitive film has the property that the unexposed portion is developed and removed during exposure and development.

[0194] Correspondingly, the second inner surface 252S of the second open region 252 of the first protective layer 250 can also have an inclination in which the width decreases in the downward direction.

[0195] At this time, in the embodiment, the undercut is not included in the first inner surface 251S and the second inner surface 252S. Thereby, each of the first inner surface 251S and the second inner surface 252S has an inclination in which the width decreases from the upper end to the lower end. At this time, the first open region 251 and the second open region 252 each include only an inclination in which the width decreases from the upper end to the lower end direction of the first inner surface 251S and the second inner surface 252S, and do not include an inclination in which the width is maintained or an inclination in which the width increases. That is, an inclination in which the width is maintained or an inclination in which the width increases can mean an undercut. And since the embodiment does not include an undercut, each of the first inner surface 251S and the second inner surface 252S of the first open region 251 and the second open region 252 may include only an inclination in which the width decreases, and may not include an inclination in which the width is maintained or an inclination in which the width increases.

[0196] At this time, in the embodiment, an open region is formed in the first protective layer 250 by using a negative-type photosensitive film as described above. Through this, in the process of removing the resist pattern DFR1-F after forming the open region in the first protective layer 250, the embodiment can ensure that the removal of the resist pattern DFR1-F is performed smoothly. Through this, the embodiment can solve the problem that the first protective layer 250 is separated from the insulating layer 210 in the step of removing the resist pattern DFR1-F.

[0197] FIG. 10 is a cross-sectional view showing a circuit board according to a third embodiment.

[0198] Referring to FIG. 10, a circuit board according to a third embodiment will be described.

[0199] The circuit board of the third embodiment includes an insulating layer 310.

[0200] Also, the circuit board of the third embodiment includes a first circuit pattern layer 320 disposed on the insulating layer 310. Also, the circuit board of the third embodiment includes a second circuit pattern layer 330 disposed under the insulating layer 310. Also, the circuit board of the third embodiment includes a through electrode 340 penetrating the insulating layer 310. Also, the circuit board of the third embodiment includes a first protective layer 350 disposed on the insulating layer 310. Also, the circuit board of the third embodiment includes a second protective layer 360 disposed under the insulating layer 310.

[0201] The first circuit pattern layer 320, the second circuit pattern layer 330, and the through electrode 340 each include a first metal layer 321, 331, 341 and a second metal layer 322, 332, 342.

[0202] The first protective layer 350 and the second protective layer 360 each include at least one open region.

[0203] At this time, the circuit board of the third embodiment has a difference in the open regions formed in the first protective layer 350 and the second protective layer 360 compared to the circuit board of the first embodiment.

[0204] Accordingly, hereinafter, the description will be centered on the open region formed in the first protective layer 350.

[0205] The inner surface of the open region in the first embodiment has an inclination substantially perpendicular to the upper surface of the insulating layer, and the inner surface of the open region in the second embodiment has an inclination such that the width decreases as going in the downward direction.

[0206] In contrast, the inner surface of the open region of the third embodiment can have an inclination such that the width increases as going in the downward direction.

[0207] For example, the first circuit pattern layer 320 includes a first pad 320-1 and a second pad 320-2. And the first protective layer 350 includes a first open region 351 that vertically overlaps the first pad 320-1. Also, the first protective layer 350 includes a second open region 352 that vertically overlaps the second pad 320-2.

[0208] At this time, the basic structures of the first open region 351 and the second open region 352 are the same as those of the first embodiment, and the detailed description thereof will be omitted.

[0209] The first open region 351 can have a width that changes from the upper surface to the lower surface of the first protective layer 350. For example, the first inner surface 351S of the first protective layer 350 of the first protective layer 350 can have an inclination with an increasing width in the downward direction. That is, in the third embodiment, the photosensitive film used to form the first open region 351 is a positive type, and the resist pattern DFR1-F can be formed using the positive type photosensitive film. Through this, the resist pattern DFR1-F can have a shape with an increasing width in the downward direction. And the first inner surface 351S of the first open region 351 of the first protective layer 350 formed by the resist pattern DFR1-F can have an inclination with an increasing width in the downward direction. The positive type photosensitive film has the characteristic that the portion exposed to light is developed and removed during exposure and development.

[0210] Correspondingly, the second inner surface 352S of the second open region 352 of the first protective layer 350 can also have an inclination with a decreasing width in the downward direction. At this time, in the third embodiment, since the width of the open region increases in the downward direction, when arranging a connection part such as a solder ball in the open region, the open region can perform an anchor function. Through this, the embodiment can improve the bonding property with the connection part.

[0211] -Semiconductor Package-

[0212] FIG. 11 is a cross-sectional view showing a semiconductor package according to an embodiment.

[0213] Referring to FIG. 11, the semiconductor package of the embodiment can include any one of the circuit boards shown in FIGS. 2, 9, and 10. Also, the circuit board can have a multilayer structure.

[0214] The semiconductor package of the embodiment includes a first connection part 410. That is, the circuit pattern layer of the circuit pattern includes pads arranged corresponding to the mounting region of the semiconductor element 420. The pads can mean the first pads of the first circuit pattern layer, and differently, can mean the second pads.

[0215] The first connection part 410 can have a hexahedral shape. The cross-section of the first connection part 410 can include a quadrangular shape. The cross-section of the first connection part 410 can include a rectangular shape or a square shape. For example, the first connection part 410 can include a spherical shape. For example, the cross-section of the first connection part 410 can include a circular shape or a semi-circular shape. For example, the cross-section of the first connection part 410 can include a partially or wholly rounded shape. The cross-sectional shape of the first connection part 410 can be a plane on one side and a curved surface on the other side. The first connection part 410 can be a solder ball, but is not limited thereto.

[0216] The semiconductor package of the embodiment includes a configuration arranged on the first connection part 410. The configuration arranged on the first connection part 410 can be a semiconductor element, or differently, can be an interposer. Hereinafter, it will be described assuming that the configuration arranged on the first connection part 410 is the semiconductor element 420.

[0217] The semiconductor element 420 can be a logic chip, but is not limited thereto. For example, the semiconductor element 420 can be an application processor (AP) chip among a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller. The semiconductor element 420 includes terminals 425 on the lower surface. And the terminals 425 of the semiconductor element 420 are connected to the circuit pattern layer of the circuit board via the first connection part 410.

[0218] In addition, the semiconductor package can include an underfill 430. The underfill 430 can be disposed to cover the periphery of the semiconductor element 420 on the circuit board. However, the underfill 430 can be selectively omitted. For example, in the semiconductor package, the underfill 430 can be omitted, and the function of the underfill 430 can be fulfilled by the molding layer 450.

[0219] The semiconductor package can include a second connection portion 440. The second connection portion 440 is disposed on the circuit pattern layer of the circuit board.

[0220] The second connection portion 440 can be a bump. As an example, the second connection portion 440 can be a solder bump, but is not limited thereto. For example, the second connection portion 440 can be a post bump. For example, the second connection portion 440 can include a copper post and a solder bump disposed on the copper post. The upper surface of the second connection portion 440 can be positioned higher than the upper surface of the semiconductor element 420. Through this, it is possible to prevent the semiconductor element 420 from being damaged in the bonding process of the external substrate 500 disposed on the second connection portion 440.

[0221] The semiconductor package can include a molding layer 450. The molding layer 450 can mold the configuration disposed on the circuit board.

[0222] The molding layer 450 may be, but is not limited to, an EMC (Epoxy Mold Compound). The molding layer 450 can have a low dielectric constant. For example, the dielectric constant (Dk) of the molding layer 450 can be from 0.2 to 10. For example, the dielectric constant (Dk) of the molding layer 450 can be from 0.5 to 8. For example, the dielectric constant (Dk) of the molding layer 450 can be from 0.8 to 5. Thereby, in the embodiment, the molding layer 450 has a low dielectric constant, so that the heat dissipation characteristics of the heat generated by the semiconductor element 420 can be enhanced. The molding layer 450 can include an opening. For example, the molding layer 450 can include an opening that overlaps the upper surface of the second connection portion 440 in a vertical direction.

[0223] The semiconductor package includes a third connection portion 460.

[0224] The third connection portion 460 can be disposed under the circuit pattern layer disposed on the lowermost side of the circuit board. The third connection portion 460 can be, but is not limited to, solder for connecting the semiconductor package of the embodiment to another external substrate (for example, the main board of an electronic device).

[0225] The semiconductor package includes an external substrate 500. The external substrate 500 can mean another substrate coupled to the circuit board of the embodiment. For example, the semiconductor element 420 disposed on the circuit board may be a logic chip such as a CPU or a GPU, and the external substrate 500 can mean a memory substrate on which a memory chip coupled to the logic chip is disposed. The external substrate 500 can be an interposer that connects between the memory substrate on which the semiconductor element 420 corresponding to the memory chip is disposed and the circuit board.

[0226] The external substrate 500 may include an insulating layer 510, a circuit layer 520, a through electrode 530, an upper protective layer 540, and a lower protective layer 550. And the external substrate 500 may include a fourth connection part 560. The fourth connection part 560 may be disposed between the external substrate 500 and the third connection part 440.

[0227] Also, the semiconductor package may include a fifth connection part 570. The fifth connection part 570 may be disposed on the external substrate 500.

[0228] The semiconductor package may include a semiconductor element 580. The semiconductor element 580 may be mounted on the external substrate 500 via the fifth connection part 570. The semiconductor element 580 may be a memory chip, but is not limited thereto. Terminals 585 of the semiconductor element 580 may be electrically connected to the external substrate 500 via the fifth connection part 570. At this time, although the semiconductor element 580 is shown as being mounted in a flip chip manner, it is not limited thereto. The semiconductor element 580 may be a stacked memory chip, and thus may be electrically connected to the external substrate 500 via a connection member such as another wire.

[0229] -Manufacturing Method-

[0230] Hereinafter, a manufacturing method of a circuit board according to an embodiment will be described.

[0231] FIGS. 12 to 19 are cross-sectional views showing a manufacturing method of a circuit board according to an embodiment in the order of manufacturing steps.

[0232] Referring to FIG. 12, in the embodiment, the insulating layer 110 is prepared.

[0233] Thereafter, in the embodiment, a through hole VH penetrating the upper and lower surfaces of the insulating layer 110 is formed.

[0234] Next, referring to FIG. 13, the embodiment can form a through electrode 140 that fills the through hole VH on the insulating layer 110. Further, the embodiment can form a first circuit pattern layer 120 including a first pad 120-1 and a second pad 120-2 on the upper surface of the insulating layer 110. Further, the embodiment can form a second circuit pattern layer 130 on the lower surface of the insulating layer 120.

[0235] Next, referring to FIG. 14, the embodiment forms a first dry film DFR1 on the insulating layer 120. At this time, the first dry film DFR1 can be disposed to entirely cover the first circuit pattern layer 120.

[0236] Further, the embodiment forms a second dry film DFR2 under the insulating layer 120. At this time, the second dry film DFR2 can be disposed to entirely cover the second circuit pattern layer 130.

[0237] Next, referring to FIG. 15, the embodiment can perform a process of exposing the first dry film DFR1 to form a first exposure pattern ER1. At this time, the first dry film DFR1 can be of a negative type. Thereby, the portion not receiving light is removed by a later phenomenon, and the first exposure pattern ER1 that has received the light may not be removed.

[0238] Further, the embodiment can perform a process of exposing the second dry film DFR2 to form a second exposure pattern ER2. At this time, the second dry film DFR2 can be of a negative type. Thereby, the portion not receiving light is removed by a later phenomenon, and the second exposure pattern ER2 that has received the light may not be removed.

[0239] Next, referring to FIG. 16, the embodiment can perform a step of removing the region excluding the first exposure pattern ER1 from the first dry film DFR1 to form a first resist pattern DFR1-F. At this time, the first resist pattern DFR1-F can be formed corresponding to the region where the open region of the first protective layer 150 is formed on the insulating layer 120.

[0240] Also, the embodiment can perform a step of removing the region excluding the second exposure pattern ER2 from the second dry film DFR2 to form a second resist pattern DFR2-F. At this time, the second resist pattern DFR2-F may be formed corresponding to the region where the open region of the second protective layer 160 is formed on the insulating layer 120.

[0241] Next, referring to FIG. 17, the embodiment can form a first protective layer 150R covering the first resist pattern DFR1-F on the insulating layer 120. Also, the embodiment can form a second protective layer 160R covering the second resist pattern DFR2-F under the insulating layer 120.

[0242] Next, referring to FIG. 18, the embodiment can perform a step of removing the first protective layer 150R by thinning to reduce the first protective layer 150R to a target thickness.

[0243] The thinning process can be performed using an organic alkaline compound containing tetramethylammonium hydroxide (TMAH) or trimethyl-2-hydroxyethylammonium hydroxide (choline).

[0244] Also, the embodiment can perform a step of removing the second protective layer 160R by thinning to reduce the second protective layer 160R to a target thickness.

[0245] Next, referring to FIG. 19, the embodiment can perform a step of removing the first resist pattern DFR1-F and the second resist pattern DFR2-F. As a result, in the embodiment, open regions can be formed in the first protective layer 150 and the second protective layer 160 corresponding to the first resist pattern DFR1-F and the second resist pattern DFR2-F, respectively.

[0246] On the other hand, when a circuit board having the above-described features of the invention is used in IT devices such as smartphones, servers, and TVs, or home appliances, functions such as signal transmission or power supply can be stably performed. For example, when the circuit board having the features of the present invention functions as a semiconductor package, it can function to safely protect the semiconductor chip from external moisture and contaminants, and can solve problems such as leakage current or electrical short circuits between terminals, or electrical open problems of the terminals supplying power to the semiconductor chip. Further, when performing the function of signal transmission, the noise problem can be solved. Through this, the circuit board having the above-described features of the invention can maintain the stable functions of IT devices and home appliances, so that the entire product and the circuit board to which the present invention is applied can achieve functional integration or technical linkage with each other.

[0247] When a circuit board having the above-described features of the invention is used in a transportation device such as a vehicle, it is possible to solve the problem of signal distortion transmitted to the transportation device, or to safely protect the semiconductor chip that controls the transportation device from the outside, and to solve problems such as leakage current or electrical short circuits between terminals, or, different from this, the electrical open problem of the terminals supplying power to the semiconductor chip, thereby further improving the stability of the transportation device. Therefore, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical linkage with each other.

[0248] The features, structures, effects, etc. described in the above embodiments are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified and implemented for other embodiments by those with ordinary knowledge in the field to which the embodiments belong. Therefore, the content related to such combinations and modifications should be construed as being included within the scope of the embodiments.

[0249] As described above, the explanation has been centered around the embodiments, but this is merely an illustration and does not limit the embodiments. It can be understood that those with ordinary knowledge in the field to which the embodiments belong can make various modifications and applications not exemplified above without departing from the essential characteristics of the present embodiments. For example, each component specifically shown in the embodiments can be implemented with modifications. And the differences related to such modifications and applications should be construed as being included within the scope of the embodiments set in the appended claims.

Claims

1. An insulating layer, A pad portion disposed on the insulating layer, A protective layer disposed on the insulating layer and including an open region that overlaps the pad portion in a vertical direction, The horizontal width of the open region of the protective layer satisfies the range of 10 μm to 30 μm, A semiconductor package in which the surface roughness of the upper surface of the protective layer is different from the surface roughness of the inner surface of the open region of the protective layer.

2. The semiconductor package according to claim 1, wherein the surface roughness of the upper surface of the protective layer is greater than the surface roughness of the inner surface of the open region of the protective layer.

3. The protective layer includes a resin and a plurality of filler fillers dispersed in the resin, The semiconductor package according to claim 2, wherein at least one of the plurality of fillers is exposed through the upper surface of the protective layer.

4. The pad portion includes a first pad, The open region includes a first open region that partially overlaps the first pad in a vertical direction, The semiconductor package according to any one of claims 1 to 3, wherein the width of the first open region is smaller than the width of the first pad.

5. The pad includes a second pad, The open region includes a second open region that entirely overlaps the second pad in a vertical direction, The semiconductor package according to any one of claims 1 to 3, wherein the width of the second open region is larger than the width of the second pad.

6. The inner surface of the open region, The semiconductor package according to any one of claims 1 to 3, having an inclination in which the width of the open region decreases from the upper surface of the protective layer toward the lower surface of the protective layer.

7. The inner surface of the open region, The semiconductor package according to any one of claims 1 to 3, having an inclination in which the width of the open region increases from the upper surface of the protective layer toward the lower surface of the protective layer.

8. The difference between the maximum width and the minimum width in the thickness direction of the open region is 3 μm or less. The semiconductor package according to any one of claims 1 to 3.

9. The center of the open region and the center of the pad portion are displaced in the vertical direction. The semiconductor package according to any one of claims 1 to 3.

10. The horizontal width between the center of the open region and the center of the pad portion is 10 μm or less. The semiconductor package according to claim 9.

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