Transmitter and Receiver

Abstract

The subject matter of the present disclosure provides a transmitter for a master clock of an audio system. The transmitter includes an input configured to receive a message to be sent to a receiver of an audio device of the audio system and clock frequency information of a clock signal for synchronizing the audio device, a data stream generator configured to determine a data stream based on the message, a pulse shaper configured to generate an encoded clock signal in the form of a rectangular wave having a start edge timing based on the clock frequency and an end edge timing earlier or later than a half cycle of the encoded clock signal according to bit values of the data stream, and an output configured to transmit the encoded clock signal to the receiver.

Description

Technical Field

[0001] The subject matter of the present disclosure relates to a transmitter for a master clock of an audio system and a receiver for an audio device of an audio system. More particularly, the transmitter and receiver are capable of transmitting and receiving a clock signal for synchronizing audio devices within an audio system.

Background Art

[0002] Audio devices within an audio system need to be synchronized. Synchronization may be achieved using a clock signal. For example, in one approach, a master clock may be employed to synchronize two or more audio devices within an audio system.

[0003] An audio device receiving the clock signal can monitor its pulses and replicate the clock signal. However, additional information is required for the audio device to understand the timing of the pulses. This is because arbitrarily aligning the rising edge to the nearest clock pulse does not necessarily result in aligning the exact pulses of the clock signal between the devices being synchronized, due to the latency across the channel.

[0004] Prior art methods have been attempted, often associating audio devices with specific data transmission methods, such as using the Audio Engineering Society / European Broadcasting Union (AES / EBU) interface or the Sony / Philips Digital Interface Format (SPDIF).

Summary of the Invention

Problems to be Solved by the Invention

[0005] The aim of the present disclosure is to reduce such problems and improve the prior art.

Means for Solving the Problems

[0006] According to one aspect of the present disclosure, a transmitter for a master clock of an audio system is provided. The transmitter includes an input unit configured to receive a message to be sent to a receiver of an audio device of the audio system and clock frequency information of a clock signal for synchronizing the audio device, a data stream generator configured to determine a data stream based on the message, a pulse shaper configured to generate an encoded clock signal in the form of a rectangular wave having a start edge timing based on the clock frequency and an end edge timing earlier or later than a half cycle of the encoded clock signal according to the bit values of the data stream, and an output unit configured to transmit the encoded clock signal to the receiver. In this way, a message may be encoded in the encoded clock signal, so that both the clock timing and the message can be transmitted simultaneously without the need for a specific data transmission protocol.

[0007] In one embodiment, the transmitter may further include a pseudo-random number generator configured to generate a pseudo-random number key, and the data stream generator is configured to generate a data stream further based on the pseudo-random number key.

[0008] In one embodiment, the data stream may include a plurality of bits in the form of frames, where each frame includes a synchronization portion, a subsequent trigger portion, and a subsequent message portion. The message portion corresponds to the received message and has a length of m bits. The synchronization portion has a length of n + s bits, where n is the length of the pseudo-random number generator and s is the number of bits for synchronizing the receiver. The trigger portion has a length of t bits.

[0009] In one embodiment, s may be greater than m.

[0010] In one embodiment, the data stream generator may be configured to generate a data stream based on a payload of 0 and a pseudo-random number key during the synchronization portion, based on a payload of one or more 1s and a pseudo-random number key during the trigger portion, and based on a payload corresponding to the message and a pseudo-random number key during the message portion.

[0011] In one embodiment, the pseudo-random number generator may be a linear feedback shift register.

[0012] In one embodiment, the transmitter may further include a pulse narrower configured to generate a first rectangular wave having a pulse width shorter than a half cycle of the encoded clock signal, and a pulse widener configured to generate a second rectangular wave having a pulse width longer than a half cycle of the encoded clock signal. The pulse shaper may be configured to select the first rectangular wave or the second rectangular wave according to the bit value of the data stream.

[0013] In one embodiment, the pulse widener and the pulse narrower may be configured to generate the first rectangular wave and the second rectangular wave by combining pulses from a wave having a frequency that is a multiple of the encoded clock signal.

[0014] In one embodiment, the message may include a sample count or a timestamp.

[0015] In one embodiment, the start edge may be a rising edge and the end edge may be a falling edge.

[0016] According to one aspect of the present disclosure, a master clock device including the above-described transmitter is provided.

[0017] According to one aspect of the present disclosure, a receiver for an audio device of an audio system is provided. The receiver includes an input unit configured to receive an encoded clock signal from a transmitter for a master clock of the audio system, a clock signal generator configured to generate a square wave clock signal having a frequency based on the frequency of the encoded clock signal, and a data stream restorer configured to obtain a bit value of a data stream encoded in the encoded clock signal based on whether an end edge of the encoded clock signal is earlier or later than a half cycle of the encoded clock signal, and to obtain a message based on the bit value of the data stream.

[0018] In one embodiment, the receiver may further include a pseudo-random number generator configured to generate a pseudo-random number key, and the data stream restorer may be further configured to obtain a message based on the bit value of the data stream and the pseudo-random number key.

[0019] In one embodiment, the data stream may include a plurality of bits in the form of a frame. The frame includes a synchronization portion, a trigger portion following the synchronization portion, and a message portion following the trigger portion. The message portion corresponds to the received message and has a length of m bits. The synchronization portion has a length of n + s bits, where n is the length of the pseudo-random number generator and s is the number of bits for synchronizing the receiver. The trigger portion has a length of t bits.

[0020] In one embodiment, s may be greater than m.

[0021] In one embodiment, the receiver may further include a match counter configured to reset the pseudorandom number generator in response to detection of the trigger portion, and may be configured to output a message in response to counting of m bits after the trigger portion.

[0022] In one embodiment, the pseudorandom number generator may be a linear feedback shift register.

[0023] In one embodiment, the receiver may further include a pulse width detector configured to determine whether the end edge of the encoded clock signal is earlier or later than half a cycle of the encoded clock signal by sampling the encoded clock signal at a frequency that is a multiple of the frequency of the wave used to generate the encoded clock signal pulse.

[0024] In one embodiment, the message may further include a sample count or a timestamp.

[0025] In one embodiment, the clock signal generator may be configured to generate a square wave clock signal by dividing the frequency of the encoded clock signal by 2.

[0026] In one embodiment, the start edge may be a rising edge and the end edge may be a falling edge.

[0027] According to one aspect of the present disclosure, an audio device including the above-described receiver is provided.

[0028] According to one aspect of the present disclosure, a system including the above-described transmitter and the above-described receiver is provided.

[0029] According to one aspect of the present disclosure, an audio system is provided that includes the above-described master clock device and the above-described audio device. According to one aspect of the present disclosure, a method for encoding a clock signal is provided. The method includes receiving a message to be sent to a receiver of an audio device of the audio system and clock frequency information of a clock signal for synchronizing the audio device, determining a data stream based on the message, generating an encoded clock signal in the form of a rectangular wave having a start edge timing based on the clock frequency and an end edge timing earlier or later than a half cycle of the encoded clock signal according to the bit values of the data stream, and transmitting the encoded clock signal to the receiver.

[0030] In one embodiment, the start edge may be a rising edge and the end edge may be a falling edge.

[0031] According to one aspect of the present disclosure, a method for obtaining a message and a clock signal from an encoded clock signal is provided. The method includes receiving the encoded clock signal from a transmitter for a master clock of an audio system, generating a square wave clock signal having a frequency based on the frequency of the encoded clock signal, obtaining the bit values of a data stream encoded in the encoded clock signal based on whether the end edge of the encoded clock signal is earlier or later than a half cycle of the encoded clock signal, and obtaining a message based on the bit values of the data stream.

[0032] In one embodiment, the end edge may be a falling edge.

[0033] According to a further aspect of the present disclosure, a non-transitory computer-readable medium having instructions stored thereon that, when executed by a processor, cause the processor to execute any of the above methods is provided.

[0034] The subject matter of the present disclosure is best described with reference to the accompanying drawings.

Brief Description of the Drawings

[0035]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Modes for Carrying Out the Invention

[0036] Although various features are described herein with reference to one or more embodiments, it will be understood that features from different embodiments may be included within other embodiments without constituting an addition to the subject matter that expands beyond the content described herein.

[0037] Referring to FIG. 1, an audio system 10 is provided. The audio system 10 includes a clock source device 12, also known as a master clock or clock box, and one or more audio devices 14. The one or more audio devices may be devices suitable for generating audio. Examples of audio devices include a drive mechanism (e.g., a compact disc reader, or an MP3 player), a digital-to-analog converter (DAC), an upsampler, a headphone amplifier, and a user interface. A sound generation device including one or more speakers, headphones, etc. may be connected to the one or more audio devices to generate the sound provided by the drive mechanism.

[0038] The clock box 12 may be connected to each audio device using a cable.

[0039] The clock box 12 includes a transmitter 18 illustrated in FIG. 2.

[0040] Referring to FIG. 2, the transmitter 18 includes an input section 19, a clock signal generator 20, a frame counter 22, a data stream generator 24, a pulse expander 26, a pulse reducer 28, a pulse shaper 30, and an output section 32.

[0041] The input section 19 is configured to receive a clock signal. The clock signal is a square wave. The input square wave has a frequency f (where f may be used interchangeably with F herein to indicate frequency) intended to be used to synchronize the audio device 14 (FIG. 1). In this way, since information related to the clock frequency can be derived from the square wave itself, the input section is configured to receive the clock frequency information of the clock signal for synchronizing the audio device 14.

[0042] The clock signal generator 20 acquires an input square wave from the input unit 19. The clock signal generator 20 is configured to generate a modified square wave based on the input square wave. The clock signal generator 20 may be provided in the form of a phase-locked loop (PLL). The phase-locked loop generates a modified square wave by doubling the frequency of the input square wave. In this way, the modified square wave has a frequency of 2f (or 2F).

[0043] The modified square wave is then used as an input to the frame counter 22 (or counter), data stream generator 24, pulse amplifier 26, and pulse reducer 28.

[0044] The frame counter 22 recognizes the number of bits in a frame. The frame counter 22 may acquire the number of bits in a frame from a memory (not shown) of the clock source. The frame counter 22 is configured to count the number of pulses that form the modified square wave within a frame and generate a restart condition when the data stream generator 24 needs to be restarted to generate bits corresponding to another frame.

[0045] A frame is several bits required to send a message to an audio device. A frame includes a synchronization part, a trigger part following it, and a message part following the trigger part, and the message part corresponds to the received message. The message part may be m bits in length. The synchronization part is n + s bits in length, where n is the length of a pseudo-random number generator (see below) and s is the number of bits for synchronizing the receiver. The trigger part is t bits in length.

[0046] Referring to FIG. 3, a data stream generator 24 is connected to the input section 19. The data stream generator 24 is configured to generate a data stream based at least in part on the message. In other words, the data stream generator 24 is configured to generate a data stream representing the message in binary format.

[0047] To achieve this, the data stream generator 24 includes a payload generator 31, a frame synchronization detector 33, a shift register 34, a switch 36, a pseudo-random number generator 38, and a data stream combiner 40. Note that each of the payload generator 31, the frame synchronization detector 33, the shift register 34, the switch 36, and the pseudo-random number generator 38 has the modified square wave 2F as an input, and for the sake of brevity and to aid in the clarity of the drawing, this is not included in FIG. 3.

[0048] The input section 19 also receives the messages to be sent to the respective receivers of the audio devices 14. The messages may be in the form of sample counts or time stamps, and further auxiliary data. The input section 19 may be the same input section as shown in FIG. 2, or a different input section. The sample count may indicate the sequence order of samples in a data packet containing audio samples. The time stamp may be the time by the clock box 12. In practice, it may be either the time stamp or the sample count that is sent. The sample count and the time stamp are used by the audio devices, so that the audio devices have knowledge of which frame is being received. The auxiliary data may be any other data that can be a transmitter as a message to the audio device. For example, the name of the clock box, its part number or serial number, or technical specifications may be transmitted. The auxiliary data may be transmitted alternately with the sample count or the time stamp.

[0049] The payload generator 31 is configured to receive a message and generate a payload in response thereto. The payload may include the message in binary form. As described elsewhere in this disclosure, the payload may also be used to represent all binary values within a frame. In this way, the payload generator 31 may sometimes be referred to as a payload message part generator.

[0050] The shift register 34 is configured to convert the payload into serial data. In this way, the payload may be a bitstream. The shift register 34 also receives a signal from the frame synchronization detector 33 as to when to output the bitstream. That signal may sometimes be referred to as the load signal Load. When the frame synchronization detector 33 counts some bits of the frame that mean the end of the message, the Load signal is sent.

[0051] The frame synchronization detector 33 is configured to receive a frame count signal Frame Count from the frame counter 22 (FIG. 2). The frame count signal indicates to the frame synchronization detector when the frame counter 22 has counted all bits of the frame, and thus the frame count signal serves as a reset for the frame synchronization detector 33 to start counting again.

[0052] The frame synchronization detector 33 is also configured to output a synchronization signal Sync to the switch 36. The switch has two input parts. The first input part 42 is the output of the shift register 34, that is, the bitstream representing the message. The second input part 44 is also a bitstream and may sometimes be referred to as the payload. The payload generator 31 may generate this additional bitstream, or this additional bitstream may be generated by a different source. This additional payload may include two sub - payloads, namely, a synchronization payload and a trigger payload.

[0053] To avoid confusion, the input to switch 36 may be regarded as a payload overall. The payload may include a plurality of parts, each corresponding to a part of the frame. The payload may include a message part (output from shift register 34), which is input to the first input section 42. There may be an m-bit binary value (0 or 1) in the message part. The number of bits m is selected to be sufficient to define the message using binary notation. The payload may also include a synchronization part that is input to the second input section 44. The synchronization part may include an n + s-bit binary value. The binary values of n and s may all be 0. The number of bits n may be the length of the pseudo-random key generated by the pseudo-random number generator 38 (see below). The number of bits s may be more than the number of bits m. The reason for this is best understood by referring to the receiver (see below). However, in summary, it is theoretically possible for the message payload to have a large section that has only 0 and no 1. If the message part is larger than the synchronization part, in such a case, an incorrect reset of the pseudo-random number generator may occur. The payload may also include a trigger part having t bits. The trigger part may be input to the second input section 44. The number of bits t may be of a single-bit length and may have a value of 1.

[0054] When the frame synchronization detector 33 receives and resets the frame count signal Frame Count, it is configured to send the synchronization signal Sync to the switch 36. The synchronization signal Sync is configured to switch the switch to the second input section 44. In this way, when the synchronization signal Sync is active, the synchronization part and the trigger part of the payload are output to the data stream combiner 40. When the frame synchronization detector 33 counts n + s + t bits, the synchronization signal Sync ends. Without the synchronization signal Sync, the switch defaults to the first input section 42. When the first input section 42 is selected, the shift register 34 outputs the message part of the payload to the data stream combiner 40.

[0055] In some embodiments, n may be 24 bits in length, m may be 60 bits in length, s may be 61 bits in length, and t may be 1 bit in length. In this way, the frame may be 146 bits in length.

[0056] The pseudo-random number generator 38 is configured to generate a pseudo-random key (or, a pseudo-random key). A suitable pseudo-random number generator 38 progresses continuously through all of the n-bit numbers. The numbers are unique in the sense that they are not repeated until all of the other possible numbers have been used up.

[0057] To achieve this, the pseudo-random number generator 38 may include a linear feedback shift register LFSR. The LFSR can obtain a unique set of numbers except for 0.

[0058] When a series of n-bit numbers is regarded as a bit stream (without word boundaries), the LFSR generates a unique number at any point in the bit stream. There may be other types of pseudo-random number generators 38 that share this characteristic. Thus, if the pseudo-random number generator 38 can function in this way, the use of an LFSR is not essential. For the purposes of the embodiments described herein, the pseudo-random number generator 38 may be an LFSR for illustrative purposes.

[0059] The LFSR may be 24 bits in length. In this way, the pseudo-random key includes the 24 bits of 1s and 0s that appear in the random sequence, but their order is determined by the structure of the LFSR.

[0060] Although not shown in FIG. 3 for the sake of brevity, the synchronization signal Sync is also available for the LFSR. In this way, when the trigger part is sent, the pseudo-random number generator restarts to generate a pseudo-random key. Thus, the pseudo-random number generator 38 is configured to generate a 24-bit pseudo-random key once during the first n bits, and then two 24-bit keys during s before resetting between the third keys. The end of the third key occurs simultaneously with the trigger bit t. Then, the pseudo-random number generator 38 generates 2- and 1-bit pseudo-random keys when the load signal Load is active and the synchronization signal Sync is inactive.

[0061] The data stream combiner 40 is configured to combine the payload and the pseudo-random key. For example, the data stream combiner 40 may be an exclusive OR gate XOR. The output from the data stream combiner 40 may be a data stream. In other words, the data stream generator is configured to generate a data stream based on the pseudo-random key. During the synchronization part, when the payload is 0, it should be understood that the data stream is the pseudo-random key. During the trigger part, the data stream is the opposite value of the pseudo-random key. During the message part, the message appears to be encoded and is highly unlikely to match the pseudo-random key over all 60 bits. Note that the message part is shorter than the synchronization part, thus avoiding incorrect synchronization. If the message consists of or ends with a contiguous sequence of 0s by chance, synchronization is still detected at the trigger bit.

[0062] In this way, the data stream generator 24 is configured to generate a data stream based on a payload of 0 and a pseudo-random key during the synchronization part, based on a payload of one or more 1s and a pseudo-random key during the trigger part, and based on a payload corresponding to the message and a pseudo-random key during the message part.

[0063] Referring back to FIG. 2, the switch uses a data stream as a switching signal.

[0064] The pulse expander 26 and the pulse compressor 28 have as an input a modified clock signal, i.e., a modified square wave. Although not shown in FIG. 2 for the sake of brevity, a further input to the pulse expander 26 and the pulse compressor 28 is a high-speed clock. The high-speed clock may have a frequency that is a multiple of the modified clock. For example, the square wave for synchronizing an audio device may have a frequency of 48 kHz. The square wave frequency may correspond to the sample rate of the audio signal. The modified clock signal may have a frequency of 96 kHz. The high clock frequency may have a frequency that is a multiple of the frequency of the modified clock signal, for example, 32 times the frequency. The high clock frequency may be about 3.1 MHz (to two significant digits).

[0065] Referring to FIGS. 2 and 4, the pulse expander 26 may be configured to use pulses from a high clock frequency to construct a modified clock signal. For example, if the modified clock signal is a direct multiplication of the clock signal frequency f, it may be at a frequency of 2f or 2F. Thus, it is possible to construct a narrow pulse using 15 / 32 pulses from the high-speed clock. It is possible to construct a wide pulse using 17 / 32 pulses from the high-speed clock. In this way, the pulse expander 26 and the pulse compressor 28 are configured to generate a first rectangular wave and a second rectangular wave by combining pulses from a wave having a frequency that is a multiple of the encoded clock signal. As a result, the falling edge of the narrow pulse is earlier than 1 / 2 cycle of the modified clock signal, and the falling edge of the wide pulse is later than 1 / 2 cycle of the modified clock signal.

[0066] The output from the pulse expander 26 may be a first rectangular wave having a pulse width shorter than a half cycle of the encoded clock signal. The output from the pulse reducer 28 may be a second rectangular wave having a pulse width longer than a half cycle of the encoded clock signal. The pulse shaper 30 is configured to generate an encoded clock signal in the form of a rectangular wave having a start edge whose timing is based on the clock frequency information and an end edge that is earlier or later than a half cycle of the encoded clock signal depending on the bit value of the data stream. In some embodiments, the terms "start edge" and "end edge" may be more specifically defined as "rising edge" and "falling edge", respectively. More specifically, the pulse shaper 30 may be configured to select the first rectangular wave or the second rectangular wave depending on the bit value of the data stream. To achieve this, the pulse shaper 30 may be in the form of a switch. For example, when the bit value is 1, the pulse shaper 30 may select the output of the pulse expander 26, i.e., the first rectangular wave. When the bit value is 0, the pulse shaper 30 may select the output of the pulse reducer, i.e., the second rectangular wave. In this way, the modified clock signal has a value of 1 or high at 1 / 2 cycle of the encoded clock signal when the bit value from the data stream is 1. The modified clock signal has a value of 0 or low at 1 / 2 cycle of the encoded clock signal when the bit value from the data stream is 0.

[0067] The output from the pulse shaper 30 is the encoded clock signal. The output unit 32 is configured to transmit the encoded clock signal to the receiver.

[0068] Referring to FIG. 5, a further embodiment of the transmitter 18' is provided. The reference numbers used for this embodiment are the same as those used for the embodiment from FIG. 2, with a prime (') appended. The following description explains the differences between the embodiment of FIG. 5 and the embodiment of FIG. 2. All other features may be considered the same.

[0069] The input section 19' is configured to receive a high-speed clock. The high-speed clock (nf or nF) may have a frequency that is a multiple of the clock signal used to synchronize the audio device. For example, a square wave for synchronizing the audio device may have a frequency of 48 kHz. The modified clock signal may have a frequency of 96 kHz. The high clock frequency may be a multiple of the frequency of the modified clock signal, for example, 32 times the frequency. The high clock frequency may be about 3.1 MHz (up to two significant digits). In addition to the high-speed clock, the transmitter 18' may receive the clock frequency of the clock signal used to synchronize the audio device. The clock frequency may be provided in the form of clock frequency information.

[0070] In FIG. 5, "n" may be a power of 2 (e.g., 2, 4, 8, 16, 32, etc.). "n" may be a variable, but in practice it may have a fixed value. In other words, the clock frequency information may be stored in a database, may not be a variable, i.e., may be pre-determined and fixed. Alternatively, the clock frequency information may be embodied in a hardware circuit.

[0071] The clock signal generator 20' is configured to generate a modified square wave (2F) based on the high-speed clock (nF). The clock signal generator 20' may include one or more flip-flops. In this way, the modified clock signal has a frequency of 2f (or 2F). The modified clock signals are input to a frame counter 22', a data stream generator 24', a pulse expander 26', and a pulse reducer 28', each of which functions in a manner similar to the embodiments from FIG. 2.

[0072] Referring to FIG. 6, each audio device 14 (FIG. 1) includes a receiver 50.

[0073] The receiver 50 includes an input section 52, a clock signal generator 54, a pulse width detector 56, a data stream restorer 58, and an output section 64. The data stream restorer 58 includes frame restoration means 62 and data stream restoration means 60.

[0074] The input section 52 may be configured to receive an encoded clock signal from the transmitter 18.

[0075] The clock signal generator 54 may be in the form of a counter. The counter may be a frequency-dividing counter. The frequency-dividing counter may divide an encoded clock signal having a frequency of 2f by 2 to generate a clock signal having a frequency of f. Thus, the clock signal may be a square wave rather than a rectangular wave of the encoded clock signal. The square wave may then be output from the output section 64 to the processor of the audio device 14 for synchronization with other audio devices 14. In other words, the clock signal generator 54 may be configured to generate a square wave clock signal having a frequency based on the frequency of the encoded clock signal.

[0076] The pulse width detector 56 may be a wide and narrow detector. The pulse width detector 56 may be configured to determine whether the falling edge of the encoded clock signal is earlier or later than half a cycle of the encoded clock signal by sampling the encoded clock signal at a frequency that is a multiple of the frequency of the wave used to generate the encoded clock signal pulse. For example, a high-speed clock is used to generate the encoded clock signal pulse by the transmitter. The frequency used to monitor the timing of the falling edge may be a multiple of the high-speed clock. The frequency used to monitor the timing of the falling edge may be twice the frequency of the high-speed clock, for example, 6.1 MHz (up to two significant digits). In this way, when the value of the encoded clock signal is high or 1, a wide pulse is detected at 32 / 64 pulses. When the value of the encoded clock signal is low or 0, a narrow pulse is detected at 32 / 64 pulses. The outputs from the pulse width detector 56 may be bit streams of 1 and 0 corresponding to wide and narrow pulses, respectively. Alternatively, in other embodiments, the same resolution may be used to monitor the timing of the falling edge. For example, if the wide and narrow pulses are 15 and 17 high-speed clock cycles wide, respectively, it is possible to test at 16 cycles.

[0077] The data stream restorer 58 is configured to receive a bit stream from the pulse width detector 56. The operation of the data stream restorer 58 can be best understood with reference to FIG. 7. Briefly, the data stream restorer 58 is configured to obtain the bit values of the data stream encoded in the encoded clock signal based on whether the falling edge of the encoded clock signal is earlier or later than half a cycle of the encoded clock signal. In addition, the data stream restorer 58 may be configured to obtain a message based on the bit values of the data stream.

[0078] Referring to FIG. 7, the data stream restorer 58 includes a match counter 70, a pseudo-random number generator 72, a combiner 74, a shift register 76, and a payload latch 78. Broadly speaking, the match counter 70 corresponds to the frame restoration means 62 from FIG. 6, and the pseudo-random number generator 72, the combiner 74, the shift register 76, and the payload latch 78 correspond to the data stream restoration means 60 from FIG. 6.

[0079] The match counter 70 (or counter) is configured to count the number of bits in the bit stream. The match counter 70 is configured to count the number of bits in a frame, i.e., 146 bits. The match counter 70 has two inputs, namely, the bit stream from the pulse width detector and the output from the pseudo-random number generator 72. The match counter 70 has two outputs, one of which is the reseed signal Reseed and the sync signal Sync. The match counter 70 is configured to compare the bit values from the bit stream with the bit values from the pseudo-random key. In response to a mismatch, the reseed signal Reseed is sent to the pseudo-random number generator. Since 0 is used for the payload for those portions of the frame, it will be understood that for 64 bits, i.e., for message portions n and m, the bit stream matches the pseudo-random key. When the trigger bit t is compared, there is a mismatch since the payload for t is 1. Thus, the "exclusive OR" combination of the trigger bit (1) and the pseudo-random key value does not have the same value as the pseudo-random key. The reseed signal Reseed is then interrupted for 60 bits. The other output, i.e., the sync signal Sync, is output to the payload latch 78 at the last bit of the frame (the 60th bit after the reseed signal is output).

[0080] When the entire frame is decoded, encoding restarts with the subsequent frame.

[0081] The pseudo-random number generator 72 receives the bit stream output by the pulse width detector. The first bit of the frame is regarded as the seed signal Seed. In response to the seed signal Seed, the pseudo-random number generator 72 generates a pseudo-random key. The pseudo-random number generator 72 may include a linear feedback shift register (LFSR). The LFSR may be 24 bits in length. The LFSR may be the same as the LFSR in the transmitter. In this way, the pseudo-random number generator 72 generates the same pseudo-random key as in the transmitter. The pseudo-random number generator 72 repeatedly generates a 24-bit pseudo-random key until it receives the reseed signal Reseed, at which point it resets and starts generating the pseudo-random key again from bit 1. In this way, the match counter is configured to reset the pseudo-random number generator in response to the detection of the trigger portion. The pseudo-random key is output to the combiner 74 and the match counter 70.

[0082] The combiner 74 receives two inputs. The first input is the pseudo-random key. The second input is the bit stream output from the pulse width detector. The first input and the second input are combined by the combiner 74. The combiner 74 may be provided in the form of an exclusive OR gate. The combined bit stream is output from the combiner 74 to the shift register 76.

[0083] In this way, the data stream restorer is further configured to obtain a message based on the bit values of the data stream and the pseudo-random key.

[0084] In response to the reception of the synchronization signal Sync, the payload latch 78 is configured to latch the latest 60 bits in the shift register. The latest 60 bits correspond to bit m of the frame, which corresponds to the message. In this way, the match counter 70 is configured to output a message in response to the count of m bits after the trigger portion.

[0085] The message may be a timestamp or a sample count. The output from the payload latch 78 may be a sample count or a timestamp. In this way, the payload latch may also be referred to as a message latch.

[0086] Referring to FIG. 6, the output unit 64 is configured to output the decoded message (timestamp or sample count) to the processor of the audio device 14 (FIG. 1), so that as a result, the audio device can synchronize the clock signal to other devices.

[0087] The various features of the transmitter and receiver described in the above embodiments may be embodied as instructions stored on a computer-readable medium. The instructions may be executable by a processor to cause the processor to perform the functions described herein.

[0088] Referring to FIG. 8, the various features of the transmitter may be understood as method steps. The method may be a method of encoding a clock signal. In addition to the other details included above, the method includes receiving, in step S100, a message to be sent to the receiver of the audio device of the audio system and clock frequency information of the clock signal for synchronizing the audio device, determining, in step S102, a data stream based on the message, generating, in step S104, an encoded clock signal in the form of a rectangular wave having a rising edge timing based on the clock frequency and a falling edge timing earlier or later than a half cycle of the encoded clock signal according to the bit values of the data stream, and transmitting, in step S106, the encoded clock signal to the receiver.

[0089] Referring to FIG. 9, various features of the receiver may be understood as method steps. The method may be a method for obtaining a message and a clock signal from an encoded clock signal. The method includes receiving, in step S200, an encoded clock signal from a transmitter for a master clock of an audio system, generating, in step S202, a square wave clock signal having a frequency based on the frequency of the encoded clock signal, obtaining, in step S204, bit values of a data stream encoded in the encoded clock signal based on whether the falling edge of the encoded clock signal is earlier or later than a half cycle of the encoded clock signal, and obtaining, in step S206, a message based on the bit values of the data stream.

Explanation of Signs

[0090] 10 Audio system 12 Clock source device 14 Audio device 18 Transmitter 19 Input section 20 Clock signal generator 22 Frame counter 24 Data stream generator 26 Pulse expander 28 Pulse reducer 30 Pulse shaper 31 Payload generator 32 Output section 33 Frame synchronization detector 34 Shift register 36 Switch 38 Pseudo-random number generator 40 Data stream combiner 42 First input section 44 Second input section 50 Receiver 52 Input section 54 Clock signal generator 56 Pulse width detector 58 Data stream restorer 60 Data stream restoration means 62 Frame restoration means 64 Output unit 70 Match counter 72 Pseudo-random number generator 74 Combiner 76 Shift register 78 Payload latch

Claims

1. A transmitter for a master clock of an audio system, comprising: an input section configured to receive a message to be sent to a receiver of an audio device of the audio system and clock frequency information of a clock signal for synchronizing the audio device; a data stream generator configured to determine a data stream based on the message; a pulse shaper configured to generate the encoded clock signal in the form of a rectangular wave having a start signal edge timing based on the clock frequency and an end signal edge timing earlier or later than a half cycle of the encoded clock signal according to a bit value of the data stream; and an output section configured to transmit the encoded clock signal to the receiver. A transmitter comprising the above.

2. The transmitter according to claim 1, further comprising a pseudo-random number generator configured to generate a pseudo-random number key, wherein the data stream generator is configured to generate the data stream further based on the pseudo-random number key.

3. The data stream includes a plurality of bits in the form of a frame, the frame includes a synchronization part, a trigger part following it, and a message part following it, the message part corresponds to the received message and has a length of m bits, the synchronization part has a length of n + s bits, where n is the length of the pseudo-random number generator and s is the number of bits for synchronizing the receiver, and the trigger part has a length of t bits. The transmitter according to claim 2.

4. The transmitter according to claim 3, wherein s is greater than m.

5. The data stream generator is configured to generate the data stream based on a payload of 0 and the pseudo-random number key during the synchronization part, based on a payload of one or more 1s and the pseudo-random number key during the trigger part, and based on a payload corresponding to the message and the pseudo-random number key during the message part. The transmitter according to claim 3 or 4.

6. The transmitter according to any one of claims 2 to 5, wherein the pseudo-random number generator is a linear feedback shift register.

7. The transmitter according to any one of claims 1 to 6, further comprising a pulse reducer configured to generate a first rectangular wave having a pulse width shorter than a half cycle of the encoded clock signal, and further comprising a pulse expander configured to generate a second rectangular wave having a pulse width longer than a half cycle of the encoded clock signal, wherein the pulse shaper is configured to select the first rectangular wave or the second rectangular wave according to the bit value of the data stream.

8. The transmitter according to claim 7, wherein the pulse expander and the pulse reducer are configured to generate the first rectangular wave and the second rectangular wave by combining pulses from a wave having a frequency that is a multiple of the encoded clock signal.

9. The transmitter according to any one of claims 1 to 8, wherein the message comprises a sample count or a time stamp.

10. A master clock device comprising the transmitter according to any one of claims 1 to 9.

11. A receiver for an audio device of an audio system, an input unit configured to receive an encoded clock signal from a transmitter for a master clock of the audio system, a clock signal generator configured to generate a square wave clock signal having a frequency based on the frequency of the encoded clock signal, and a data stream restorer configured to obtain a bit value of a data stream encoded in the encoded clock signal based on whether an end signal edge of the encoded clock signal is earlier or later than a half cycle of the encoded clock signal, and to obtain a message based on the bit value of the data stream. A receiver comprising.

12. The receiver according to claim 11, further comprising a pseudo-random number generator configured to generate a pseudo-random number key, wherein the data stream restorer is further configured to obtain the message based on the bit value of the data stream and the pseudo-random number key.

13. The data stream includes a plurality of bits in the form of a frame, the frame includes a synchronization part, a trigger part following it, and a message part following it, the message part corresponds to the received message and has a length of m bits, the synchronization part has a length of n + s bits, where n is the length of the pseudo-random number generator and s is the number of bits for synchronizing the receiver, and the trigger part has a length of t bits, the receiver according to claim 12.

14. The receiver according to claim 13, wherein s is greater than m.

15. The receiver according to claim 13 or 14, further comprising a match counter configured to reset the pseudo-random number generator in response to detection of the trigger part, and configured to output the message in response to counting m bits after the trigger part.

16. The receiver according to any one of claims 12 to 15, wherein the pseudo-random number generator is a linear feedback shift register.

17. The receiver according to any one of claims 11 to 16, further comprising a pulse width detector configured to determine whether the end signal edge of the encoded clock signal is earlier or later than a half cycle of the encoded clock signal by sampling the encoded clock signal at a frequency that is a multiple of the frequency of the wave used to generate the encoded clock signal pulse.

18. The receiver according to any one of claims 11 to 17, wherein the message comprises a sample count or a time stamp.

19. The receiver according to any one of claims 11 to 18, wherein the clock signal generator is configured to generate the square wave clock signal by dividing the frequency of the encoded clock signal by 2.

20. An audio device comprising the receiver according to any one of claims 12 to 19.

21. A system comprising a transmitter according to any one of claims 1 to 9 and a receiver according to any one of claims 11 to 20.

22. A method for encoding an encoded clock signal, comprising: receiving a message to be sent to a receiver of an audio device of an audio system, and clock frequency information of a clock signal for synchronizing the audio device; Determining a data stream based on the message; Generating the encoded clock signal in the form of a rectangular wave having an initial signal edge timing based on a clock frequency and an end signal edge timing earlier or later than a half cycle of the encoded clock signal according to a bit value of the data stream; Transmitting the encoded clock signal to the receiver; A method comprising the steps of.

23. A method for obtaining a message and a clock signal from an encoded clock signal, comprising: Receiving an encoded clock signal from a transmitter for a master clock of an audio system; Generating a square wave clock signal having a frequency based on the frequency of the encoded clock signal; Obtaining a bit value of a data stream encoded in the encoded clock signal based on whether an end signal edge of the encoded clock signal is earlier or later than a half cycle of the encoded clock signal; Obtaining a message based on the bit value of the data stream; A method comprising the steps of.

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