Startup control method and apparatus for embedded system, storage medium, and electronic device

Abstract

The present invention discloses a startup control method and apparatus for an embedded system, a storage medium, and an electronic device. Here, the method is to control the operating state of a target device by controlling a hardware controller of the target device via a first bus by a first operating system running on a first processor core of a processor, where the embedded system includes the first operating system, and to guide a second operating system to be started on a second processor core of the processor, where the embedded system further includes the second operating system, the response speed of the first operating system is higher than that of the second operating system, the first operating system and the second operating system communicate via a second bus, and the bandwidth of the second bus is higher than that of the first bus, and after the second operating system is started, the second operating system takes over the control of the target device by taking over the hardware controller via the first bus.

Description

Technical Field

[0001] The present invention relates to the field of computers, and more specifically, to a startup control method and apparatus for an embedded system, a storage medium, and an electronic device.

Background Art

[0002] Devices such as servers, personal computers, and industrial control computers may be equipped with some specific devices that execute operations related to the operation of the device. For example, a fan may be installed for heat dissipation. In related technologies, generally, after the system is powered on, these specific devices start operating. After the system is powered on, the operating system running on the processor takes a certain amount of time to appropriately take over the specific device and be able to control the operating state of the specific device. During the startup process of the operating system, the specific device cannot be controlled.

[0003] In order to realize controlling the operating state of a specific device during the startup process of the operating system, generally, an additional chip is used to control the operating state of the specific device during the startup process of the operating system. However, since the above-mentioned startup control method of the operating system requires adding an additional chip, the cost of the device is increased. Therefore, the startup control method of the related technology operating system has a problem that the device cost is high because an additional chip needs to be added.

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of the present invention provide a startup control method and apparatus for an embedded system, a storage medium, and an electronic device that at least solve the problem that the device cost is high because an additional chip needs to be added in the startup control method of the related technology operating system.

Means for Solving the Problems

[0005] According to one aspect of an embodiment of the present invention, a method for starting up a built-in system is provided, which controls the operating state of a target device by controlling a hardware controller of the target device via a first bus by a first operating system running on a first processor core of a processor. Here, the built-in system includes the first operating system, and guides to start a second operating system on a second processor core of the processor. Here, the built-in system further includes the second operating system, the response speed of the first operating system is higher than that of the second operating system, the first operating system and the second operating system communicate via a second bus, and the bandwidth of the second bus is higher than that of the first bus. After the second operating system is started, the second operating system takes over the control of the target device by taking over the hardware controller via the first bus.

[0006] According to another aspect of an embodiment of the present invention, there is further provided a startup control device for an embedded system, which is a first control unit for controlling the operating state of a target device by controlling a hardware controller of the target device via a first bus by a first operating system running on a first processor core of a processor. Here, the embedded system includes a first control unit including the first operating system, and a startup unit for guiding the startup of a second operating system on a second processor core of the processor. Here, the embedded system further includes the second operating system, the response speed of the first operating system is higher than that of the second operating system, the first operating system and the second operating system communicate via a second bus, and the bandwidth of the second bus is higher than that of the first bus. A startup unit, and after the second operating system is started, a first execution unit for taking over the control right of the target device by the second operating system taking over the hardware controller via the first bus.

[0007] In one exemplary embodiment, the first control unit is a first execution module for executing a first control task of the first operating system on the first processor core. Here, the first control task includes a first execution module used for controlling the hardware controller, a reading module for reading sensor data of a predetermined sensor corresponding to the target device by the first processor core, and the first control task based on the sensor data of the predetermined sensor. A first transmission module for transmitting a device control command to the hardware controller via the first bus, and controlling the operating state of the target device based on the device control command by the hardware controller.

[0008] In one exemplary embodiment, the first transmission module includes a first determination sub-module for determining a target parameter value of the device operation parameter of the target device based on the sensor data of the predetermined sensor by the first control task, where the device operation parameter is a parameter for controlling the operation state of the target device, and a transmission sub-module for transmitting the device control command including the target parameter value to the hardware controller via the first bus by the first control task.

[0009] In one exemplary embodiment, when the target device is a fan, the first determination sub-module includes a determination sub-unit for determining a target parameter value of the fan operation parameter of the fan based on the sensor data of the predetermined sensor by the first control task. In one exemplary embodiment, when the target device is a fan and the predetermined sensor is a temperature sensor, the determination sub-unit is a determination second sub-unit for determining a target rotation speed value of the rotation speed of the fan based on the sensor data of the temperature sensor by the first control task, where the rotation speed of the fan has a positive correlation with the temperature detected by the temperature sensor.

[0010] In one exemplary embodiment, the first execution unit is a second transmission module for the second operating system to send a first inter-core interrupt to the first operating system via the second bus, where the first inter-core interrupt is used to request the second operating system to take over the hardware controller, and a second transmission module for receiving a second inter-core interrupt sent back by the first operating system in response to the first inter-core interrupt and instructing the second operating system to agree to take over the hardware controller. When the second operating system receives the second inter-core interrupt, a control module for the second control task of the second operating system to control the hardware controller via the first bus, where the second control task is a control module used to control the hardware controller.

[0011] In one exemplary embodiment, the device is a second control unit for controlling the third control task of the first operating system to sleep in response to the first inter-core interrupt obtained after the second operating system sends the first inter-core interrupt to the first operating system via the second bus as described above, where the third control task is a second control unit used to control the hardware controller, and when the third control task has already slept, the first operating system further includes a first transmission unit for sending the second inter-core interrupt to the second operating system via the second bus.

[0012] In one exemplary embodiment, when the third control task has already slept, the apparatus is a second execution unit for pushing the system operation data of the first operating system onto a stack, where the second inter-core interrupt further includes a second execution unit used to instruct the second operating system to take over the first processor core.

[0013] In one exemplary embodiment, before the apparatus controls a hardware controller of a target device via a first bus by a first operating system running on a first processor core of a processor, after the chip where the processor is located is powered on, the apparatus further includes a wake-up unit for waking up the first processor core by the processor, and an operating unit for guiding the first operating system to start on the first processor core by running a bootloader program of the first operating system by the first processor core.

[0014] In one exemplary embodiment, the startup unit includes a second execution module for waking up the second processor core by the second program loader executed by the first processor core, and an operating module for guiding the second operating system to start on the first processor core by running a general-purpose bootloader of the second operating system by the second processor core.

[0015] In one exemplary embodiment, when the second operating system attempts to restart after taking over the hardware controller via the first bus as described above, the second operating system wakes up the first operating system via the second bus, and the first operating system takes over the hardware controller via the first bus, the apparatus further includes a third execution unit for taking over the control right of the target device, and a third control unit for controlling the second operating system to restart the system.

[0016] In one exemplary embodiment, when the second operating system attempts to restart, the third execution unit includes a transmission module for transmitting a system wake-up interrupt for waking up the first operating system to the first operating system via the second bus by the second operating system.

[0017] In one exemplary embodiment, the apparatus is a first allocation unit for allocating a group of services to be allocated to a corresponding operating system among the first operating system and the second operating system according to a resource dynamic allocation rule, where the resource dynamic allocation rule includes performing resource dynamic allocation based on at least one of service response speed, service resource occupancy rate, service coupling degree, and service importance; a first determination unit for determining a resource allocation result corresponding to the group of services to be allocated, where the resource allocation result is used to indicate the processing resources corresponding to each service to be allocated among the services to be allocated in the group of services to be allocated in the processing resources of the processor, and the processing resources of the processor include processor cores; and a second allocation unit for allocating the processing resources of the processor to the first operating system and the second operating system based on the operating system corresponding to each service to be allocated and the resource allocation result.

[0018] In one exemplary embodiment, the first allocation unit includes at least one of: a first allocation module for allocating services to be allocated in the one group of services, where the service response speed requirement of the service to be allocated is greater than or equal to a set response speed threshold, to the first operating system, and allocating services to be allocated in the one group of services, where the service response speed requirement of the service to be allocated is less than the set response speed threshold, to the second operating system; a second allocation module for allocating services to be allocated in the one group of services, where the service resource occupancy rate of the service to be allocated is less than a first occupancy rate threshold, to the first operating system, and allocating services to be allocated in the one group of services, where the service resource occupancy rate of the service to be allocated is greater than or equal to the first occupancy rate threshold, to the second operating system; and a third allocation module for allocating services to be allocated in the one group of services, where sensitive information is included in the service to be allocated, to a target operating system, where the target operating system is at least one of the first operating system and the second operating system, and is the operating system with a lower interaction frequency with the user.

[0019] In one exemplary embodiment, the first allocation unit includes at least one of: a fourth allocation module for allocating services to be allocated in the one group of services, where the service coupling degree of the service to be allocated with the services already allocated to the first operating system is greater than or equal to a first coupling degree threshold, to the first operating system; and a fifth allocation module for allocating services to be allocated in the one group of services, where the service coupling degree of the service to be allocated with the services already allocated to the second operating system is greater than or equal to a second coupling degree threshold, to the second operating system.

[0020] In one exemplary embodiment, the first determination unit includes a generation module for generating a resource mapping table of the services to be assigned in the one group and the processing resources of the processor by associating the resource utilization status of the processing resources of the first operating system and the resource utilization status of the processing resources of the second operating system based on the assignment result of the services to be assigned in the one group.

[0021] In one exemplary embodiment, when the second assignment unit determines that there is a corresponding service to be assigned among the unassigned processing resources of the processing resources of the processor based on the resource assignment result, the second assignment unit includes a sixth assignment module for assigning the unassigned processing resources to the operating system to which the service to be assigned corresponding to the unassigned processing resources is assigned.

[0022] In one exemplary embodiment, the apparatus further includes a second transmission unit for transmitting target data to a target virtual channel in the memory of the processor by the first operating system, a third transmission unit for transmitting an interrupt notification message to the second operating system, and an acquisition unit for acquiring the target data from the target virtual channel in the memory when the second operating system responds to the interrupt notification message.

[0023] In one exemplary embodiment, the memory includes a data storage area and a metadata storage area. The data storage area is divided into a plurality of storage units, each storage unit is used to store service data, and the metadata storage area is used to store the size and occupied state of each storage unit in the data storage area. In one exemplary embodiment, the second transmission unit includes a third execution module that reads records in the metadata storage area by the first operating system and determines at least one storage unit that is in an idle state in the data storage area and whose total space is equal to or greater than the length of the target data based on the read records, and a fourth execution module that sets the state of at least one storage unit corresponding to the target virtual channel in the metadata storage area to an occupied state and stores the target data in the target virtual channel.

[0024] In one exemplary embodiment, the acquisition unit includes a fifth execution module that reads records in the metadata storage area by the second operating system and determines the target virtual channel based on the read records, and a sixth execution module that acquires the target data from at least one storage unit corresponding to the target virtual channel and sets the state of the at least one storage unit to an idle state.

[0025] In one exemplary embodiment, the data storage area includes a plurality of memory channels, each memory channel is composed of one or more storage units, the metadata storage area stores a plurality of records, each record is used to record the metadata of one memory channel, and the metadata of each memory channel includes at least the channel ID of the memory channel, the size of the memory channel, and the occupied state of the memory channel. The third execution module includes a first traversal sub-module for traversing the records stored in the metadata storage area to determine whether there is a first target record indicating that the memory channel is in an idle state and the size of the memory channel is greater than or equal to the length of the target data, and a second determination sub-module for determining the memory channel indicated by the channel ID recorded in the first target record as the target virtual channel when the first target record exists.

[0026] In one exemplary embodiment, when a memory channel is occupied, the metadata of the memory channel further includes the ID of the source CPU core of the target data and the ID of the destination CPU core of the target data. The fifth execution module includes a second traversal sub-module for traversing the records stored in the metadata storage area to determine whether there is a second target record, where the second target record indicates that the memory channel is in an occupied state, the ID of the destination CPU core is the ID of the CPU core of the second operating system, and the ID of the source CPU core is not the ID of the CPU core of the second operating system, and a third determination sub-module for determining the memory channel indicated by the channel ID recorded in the second target record as the target virtual channel when the second target record exists.

[0027] In one exemplary embodiment, the apparatus is a fourth execution unit for receiving a memory application command of the first operating system and performing a locking operation on the memory of the processor, where the memory application command is used to apply for using the memory of the processor, and a fifth execution unit for reading the occupied state of the memory when the locking of the memory is successful and determining whether there is a target memory space available in the memory based on the occupied state of the memory, where the size of the target memory space is not less than the size of the memory applied for by the memory application command, and further includes a feedback unit for, when there is a target memory space in the memory, feeding back the address information of the target memory space to the first operating system and updating the occupied state of the memory.

[0028] In one exemplary embodiment, the memory includes a metadata storage area for storing a state mapping table for storing the occupied state of the data storage area and a data storage area for storing service data, and the fifth execution unit includes a seventh execution module for reading a record in the state mapping table from the metadata storage area and determining whether there is a target memory space in the data storage area based on the record in the state mapping table.

[0029] In one exemplary embodiment, the apparatus further includes a determination unit for determining whether the memory is currently in a locked state before performing a locking operation on the memory of the processor, where the locked state indicates that the memory is in a state of being applied for use, and a sixth execution unit for performing a locking operation on the memory when the memory is not currently in a locked state.

[0030] In one exemplary embodiment, after the device reads the occupied state of the memory and determines whether there is any available target memory space in the memory based on the occupied state of the memory, if there is no available target memory space in the memory, the device further includes a release unit for releasing the lock on the memory.

[0031] According to another aspect of an embodiment of the present invention, the system further includes an embedded system, including a chip and at least two operating systems. Here, the chip includes a processor, a hardware controller, a first bus, and a second bus. Here, the bandwidth of the second bus is higher than that of the first bus, and the second bus is arranged in a multi-master multi-slave mode, and the first bus is arranged in a one-master multi-slave mode. The at least two operating systems are operated based on the processor. Here, the processing resources of the processor are dynamically allocated to the at least two operating systems. The processing resources of the processor include processor cores. The at least two operating systems communicate via the second bus. The at least two operating systems realize control over the hardware controller via the first bus. The at least two operating systems are used to implement the steps in the embodiments of any one of the above methods.

[0032] According to another aspect of an embodiment of the present application, a chip including at least one of a programmable logic circuit and executable commands is further provided. The chip is operated on an electronic device to implement the steps in the embodiments of any one of the above methods.

[0033] According to another aspect of the embodiments of the present application, there is further provided a BMC chip including a storage unit for storing a program and a processing unit for running the program to execute the steps in the embodiments of any one of the above methods, the processing unit being connected to the storage unit. According to another aspect of the embodiments of the present application, there is further provided a main board including at least one processor and at least one storage unit for storing at least one program, wherein when the at least one program is executed by the at least one processor, the at least one processor realizes the steps in the embodiments of any one of the above methods.

[0034] According to another aspect of the embodiments of the present application, there is further provided a server including a processor, a communication interface, a storage unit, and a communication bus. Here, the processor, the communication interface, and the storage unit realize communication with each other via the communication bus. The storage unit is used for storing a computer program, and when the processor executes the program stored in the storage unit, the processor is used to realize the steps in the embodiments of any one of the above methods.

[0035] According to another embodiment of the present application, there is further provided a computer-readable storage medium storing a computer program configured to execute the steps in the embodiments of any one of the above methods when running. According to another embodiment of the present application, there is further provided an electronic device including a storage unit and a processor, wherein a computer program is stored in the storage unit, and the processor is configured to execute the steps in the embodiments of any one of the above methods by running the computer program.

Advantages of the Invention

[0036] In an embodiment of the present invention, the method of running different operating systems of an embedded system on different processor cores of a processor is that the first operating system running on the first processor core of the processor controls the hardware controller of the target device through the first bus to control the operating state of the target device. Here, the embedded system includes the first operating system, and guiding the second operating system to start on the second processor core of the processor. Here, the embedded system further includes the second operating system, the response speed of the first operating system is higher than that of the second operating system, the first operating system and the second operating system communicate through the second bus, and the bandwidth of the second bus is higher than that of the first bus. After starting the second operating system, the second operating system takes over the hardware controller through the first bus to take over the control right of the target device, including running at least two operating systems of the embedded system on the processor, the response speeds of different operating systems are different, and the first operating system with a fast response speed controls the operating state of a specific device first, and after starting the second operating system, takes over the control right of the specific device. Therefore, there is no need to add additional chips, and since the control of the device is realized by software, the scalability is strong, and the technical effect of improving the utilization rate of core resources can be achieved, thereby solving the problem that the cost of the device is high because it is necessary to add additional chips in the startup control method of the operating system in the related art.

Brief Description of the Drawings

[0037] The drawings here are incorporated into the specification and form a part of the specification, showing embodiments that meet the present application, and are used to interpret the principle of the present application together with the specification. To more clearly explain the embodiments of the present application or the technical solutions of the prior art, the drawings necessary for describing the embodiments or the prior art are briefly introduced below. Obviously, those skilled in the art can also obtain other drawings based on these drawings without creative effort.

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Embodiments for Carrying Out the Invention

[0038] In order for those skilled in the art to better understand the technical solution of this application, hereinafter, the drawings in the embodiments of this application are combined to clearly and completely describe the technical solution in the embodiments of this application. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative efforts belong to the protection scope of this application.

[0039] It should be noted that the terms "first", "second", etc. in the specification, claims and the above drawings of this application do not necessarily need to be used to describe a specific order or first-come-first-served order, but are for distinguishing similar objects. It should be understood that the data used in this way can be appropriately interchanged, whereby the embodiments of this application described herein can be implemented in an order other than the order illustrated or described herein. Also, the terms "comprising", "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to the steps or units clearly listed, and may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0040] Examples of the method according to the embodiments of the present application may be executed on a server, a computer terminal, a device terminal, or a similar computing device. Taking the operation on the server as an example, FIG. 1 is a schematic diagram of the hardware environment of the startup control method of the embedded system according to the embodiments of the present application. As shown in FIG. 1, the server may include one or more (only one is shown in FIG. 1) processors 102 (the processor 102 may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a storage unit 104 for storing data. In one exemplary embodiment, the server may further include a transmission device 106 and an input / output device 108 used for communication functions. As can be understood by those skilled in the art, the structure shown in FIG. 1 is merely exemplary and does not constitute a limitation on the structure of the server. For example, the server may include more or fewer components than those shown in FIG. 1, or may have the same functions as those shown in FIG. 1, or different configurations with more functions than those shown in FIG. 1.

[0041] The storage unit 104 may be used to store a computer program, such as a software program and module of application software, for example, a computer program corresponding to the startup control method of the embedded system in the embodiments of the present invention. The processor 102 may execute various functional applications and data processing by running the computer program stored in the storage unit 104, that is, implement the above method. The storage unit 104 may include a high-speed random access storage unit and may also include a non-volatile storage unit, such as one or more magnetic storage devices, flash memories, or other non-volatile solid storage units. In some embodiments, the storage unit 104 may further include a storage unit provided remotely from the processor 102, and these remote storage units may be connected to the server via a network. Examples of the above network include, but are not limited to, the Internet, enterprise intranets, local area networks, mobile communication networks, and combinations thereof.

[0042] The transmission device 106 is used to transmit and receive data via one network. Specific examples of the above network may include a wireless network provided by a server communication provider. In one embodiment, the transmission device 106 includes one network adapter (abbreviated as Network Interface Controller, NIC) and can communicate with the Internet by connecting to other network devices via a base station. In one embodiment, the transmission device 106 may be a radio frequency (RF) module for communicating with the Internet in a wireless manner.

[0043] In this embodiment, a startup control method for an embedded system applied to the above server is provided. FIG. 2 is a schematic flowchart of a selective startup control method for an embedded system according to an embodiment of the present application. As shown in FIG. 2, this flow includes the following steps. Step S202: The operating state of the target device is controlled by controlling the hardware controller of the target device via the first bus by the first operating system running on the first processor core of the processor. Here, the embedded system includes the first operating system.

[0044] The startup control method of the embedded system in this embodiment can be applied to a scenario of controlling the operating state of specific devices by running an operating system on the processor core of a processor, and can correspond to the startup process of the embedded system. The above-mentioned embedded system may be an embedded heterogeneous multi-system. A heterogeneous multi-system means that a plurality of different operating systems (for example, a first operating system, a second operating system, etc.) are run on the multi-core processor of the embedded system, and these operating systems run simultaneously on the same embedded system. Different operating systems can be run on different processor cores, and the processor here may be a multi-core processor, for example, an 8-core processor, or a processor including other numbers of processor cores. In this embodiment, the number of cores included in the multi-core processor is not limited.

[0045] For devices such as servers, personal computers, and industrial control computers, some specific devices for performing operations related to the operation of the device may be arranged. In the related art, generally, after the system is powered on, these specific devices start to operate. On the other hand, after the system is powered on, the operating system running on the processor takes a certain amount of time to appropriately take over the specific device and control the operating state of the specific device, and the specific device cannot be controlled during the startup process of the operating system.

[0046] For example, after the system is powered on, the fan starts operating. After the system is powered on, the operating system running on the CPU (Central Processing Unit, the central processing device, which is the core of the computer system's computing and control. As the final execution unit for information processing and program running, the CPU) takes over the fan appropriately. Since it takes a certain amount of time until the rotation speed of the fan can be set, the fan cannot be controlled during the startup process of the operating system.

[0047] In related technologies, in order to control the operating state of a specific device during the startup process of the operating system, generally, an additional chip is used to control the operating state of the specific device during the startup process of the operating system. The additional chip may be a CPLD (Complex Programmable Logic Device), an EC (Embedded Controller) chip, a customized chip, etc. The main reason for using the additional chip is that the CPLD, EC chip, and customized chip can start within an extremely short time (e.g., within 1 second) after being powered on, and the real-time performance is relatively high. However, these three methods generally require an additional chip or a complex programmable logic device, resulting in increased costs, and since they are customized hardware, they do not have excellent scalability.

[0048] For example, in order to realize that the fan can be controlled during the startup process of the operating system, the server adopts a control method of connecting a CPLD to a BMC (Baseboard Management Controller, a management control chip in the server platform), the personal computer adopts a control method of an EC chip (the EC chip has a function of adjusting the rotation speed of the fan based on temperature), the industrial control computer adopts a control method of a customized chip. During the startup process of the operating systems of the server, personal computer, and industrial control computer, the CPLD, EC chip, and customized chip participate in controlling the rotation speed of the fan. After the operating system is fully started, the control right of the fan is transferred to the application program in the operating system.

[0049] To solve at least part of the above problems, a startup control method of a multi-core multi-system (for example, a multi-core dual system) can be adopted, different operating systems of the embedded system are run on different processor cores of the processor, the response speeds of different operating systems are different, and for other situations where the second operating system has not started, is restarting, or cannot control the operating state of a specific device, the operating state of the specific device can be controlled by the first operating system with a response speed higher than that of the second operating system, the situation where the operating state of the specific device cannot be controlled can be reduced, and since there is no need to add additional costs for expansion, it further has excellent scalability.

[0050] An embedded system can be run on a processor, and the processor may be a multi-core processor (e.g., an 8-core processor) and may include multiple processor cores. The embedded system may include a first operating system and a second operating system. The first operating system can be run on the first processor core of the processor, and the second operating system can be run on the second processor core of the processor. The first processor core may be at least one processor core of the processor, and the second processor core may be all or part of the processor cores other than the first processor core among the multiple processor cores of the processor. In addition to the processor cores, the processor resources for running each operating system may further include other types of resources, such as a controller logic unit. Also, the processor cores occupied by different operating systems can be dynamically adjusted.

[0051] The processor may be a processor on a certain chip, and this chip may include the above-mentioned processor, a hardware controller, a first bus, and a second bus. Here, the hardware controller may be used to control external devices connected to the corresponding external interface. The first bus may be arranged in a one-master multi-slave mode and may be a bus used by the processor to control between hardware controllers, such as an APB (Advanced Peripheral Bus) bus. The second bus may be arranged in a multi-master multi-slave mode and may be a bus used for communication between multiple cores of the processor 302, such as an AHB (Advanced High Performance Bus) bus. The bandwidth of the second bus is higher than that of the first bus.

[0052] Here, the fact that the second bus is arranged in a multi-master multi-slave mode means that the second bus can be used for data communication between a plurality of master devices and a plurality of slave devices. That is to say, a plurality of master devices and a plurality of slave devices may be connected to this second bus, and data communication can be carried out between master devices and between master devices and slave devices using this second bus. Data transmission across the entire second bus is all sent by master devices and responded to by slave devices. The fact that the first bus is arranged in a one-master multi-slave mode means that the first bus can be used for data communication between one master device and a plurality of slave devices. That is to say, one master device and a plurality of slave devices may be connected to this first bus, and data communication can be carried out between the master device and the slave devices using this first bus. A data request can only be sent from the master device to the slave device. After receiving the request, the slave device returns the corresponding response data to the master device, and this process can achieve one-to-many access.

[0053] In addition, by performing data communication between operating systems using a multi-master multi-slave mode bus, each operating system can easily send data requests spontaneously based on demand. On the other hand, since the hardware controller mainly controls the corresponding hardware based on the control by the operating system, communication is carried out between the operating system and the hardware controller using a one-master multi-slave mode bus, and all data requests are sent from the operating system to the hardware controller, which can improve the control efficiency of the hardware controller.

[0054] The aforementioned AHB bus has already been defined in AMBA (Advanced Microcontroller Bus Architecture). The AHB bus is mainly used as a system high-speed bus, applicable to high-performance and low-power system designs, and can be used for connections between high-performance modules. As the on-chip system bus of an SoC (System on Chip), high-performance modules may include a CPU, DMA (Direct Memory Access), DSP (Digital Signal Processing), etc. In the AMBA protocol, the AHB is mainly used for the interconnection design of high-bandwidth and high-performance systems at the system level, supporting single clock edge operation, a non-three-state implementation method, burst transmission, segment transmission, multi-master and multi-slave interconnection modes, arranging bus widths of 32 bits to 128 bits, and supporting the transmission of bytes, nibbles, and words. The AHB system includes three parts: a master module (i.e., a master device), a slave module (i.e., a slave device), and an infrastructure. All transmissions on the entire AHB bus are sent by the master module and responded to by the slave module. The infrastructure includes an arbiter, a multiplexer from the master module to the slave module, a multiplexer from the slave module to the master module, a decoder, a dummy slave module, and a dummy master module.

[0055] The APB is mainly used to connect low-bandwidth peripheral devices, such as UART (Universal Asynchronous Receiver / Transmitter), 1284, etc. Its bus architecture does not support multiple master modules like the AHB. The only master module in the APB is the APB bridge. Its features are (1) It can operate at high frequencies. (2) The protocol is simple and there is no complex casing. (3) It is a synchronous bus, and all transactions (reader / writer operations) on the bus depend on the rising edge of the clock. (4) It is a one-master multi-slave. Generally, the APB is connected to the AHB bus system, and the AHB-APB Bridge converts transactions between AHB bus systems. At this time, the Bridge is the master of the APB, and all other peripheral devices are slaves. (5) The interface is simple. Compared with AXI (Advanced eXtensible Interface) and AHB, the interface is relatively simple. (6) It has low power consumption. (7) It includes the ability to connect multiple peripheral devices, such as peripheral devices that can be controlled by the aforementioned hardware controller.

[0056] For the APB bus, data requests can only be sent from the Master to the Slave. After receiving the request, the Slave returns the corresponding response data to the Master. This process can achieve one-to-many access and the access does not involve arbitration and decoder analysis operations in the AHB bus. Here, the AHB bus has high-bandwidth characteristics and is used for interconnection between high-performance modules (such as CPU, DMA, etc.) in the system. The bandwidth of the APB bus is relatively low and is used for connection between peripheral devices (such as UART, I2C, etc.) in the system. The AHB bus logic circuit and bus protocol are complex, while the APB bus interface circuit and bus protocol are relatively simple.

[0057] Here, the above chip may be a BMC chip. The BMC chip may also be a SOC chip based on the ARM (Advanced RISC Machine) multi-core architecture, integrating multiple peripheral hardware IPs (Intelligent Peripherals). The BMC chip is arranged on the main board (server motherboard).

[0058] Optionally, based on the constraints on response time, the first operating system may be an operating system with clear and fixed time constraints, and all processing processes (task scheduling) need to be completed within a fixed time constraint; otherwise, the system will result in an error and may be called a Real Time Operating System (RTOS for short). The second operating system does not have this feature. Generally, the second operating system adopts a fairness task scheduling algorithm. When the number of threads / processes increases, it is necessary to share CPU time. Task debugging has uncertainty and may be called a non-real-time operating system. For example, it can be a Linux (registered trademark) (the official name is GNU / Linux) system or a Windows system. The Linux system is a Unix-based operating system that can be freely propagated, and it is an operating system that supports multi-user, multi-task, multi-thread, and multi-CPU based on POSIX (Portable Operating System Interface). The Windows system is an operating system developed based on a graphical user interface and is mainly applied to devices such as computers and smartphones.

[0059] For example, taking a processor chip of the ARM architecture as an example, this processor chip may be an ARM processor. This processor includes a multi-core CPU. The RTOS system can be run on the CPU0 core, and the Linux system can be run on the CPU cores (1, N) (N ≥ 2, and the total number of processor cores included in the processor is N + 1). (It is also possible to run Windows or other operating systems)

[0060] In this embodiment, when the second operating system is not started, needs to be restarted, or in other situations where the operating state of the target device cannot be controlled, the operating state of the target device can be controlled by the first operating system controlling the hardware controller of the target device via the first bus. Here, the target device may be a fan or other device that needs to operate when the system starts. For a fan, the corresponding hardware controller is a fan controller, such as a PWM (Pulse Width Modulation) controller or a FanTach (fan rotation speed) controller. Here, instead of using a conventional CPLD, EC chip, or customized chip, a first operating system (such as an RTOS system) is used to reduce the hardware cost and realize device control by software, so the scalability is relatively high.

[0061] For example, based on the BMC dual-core, a dual-system of the RTOS system and the Linux system is realized, a fan is realized based on the multi-core dual-system, and the high real-time property of the RTOS system is utilized. In the startup process of the Linux system, the RTOS system can control the fan instead of the CPLD, EC chip, or customized chip, that is, inherit the control right of the fan and control the operating state of the fan at a sufficiently fast speed. Step S204: Guide to start the second operating system on the second processor core of the processor.

[0062] When the system is powered on or when the second operating system is restarted, by guiding the second operating system to start on the second processor core of the processor, the second operating system can be run on the second processor core. Here, starting the second operating system on the second processor core means scheduling the second processor core to the second operating system, and the system files or mirror files of the operating system may be stored in a memory other than the chip where the processor is located, such as an external RAM (Random Access Memory). Step S206: After the second operating system is started, the second operating system takes over the hardware controller via the first bus, thereby taking over the control right of the target device.

[0063] After the startup of the second operating system is completed, the operating state of the target device can always be controlled by the first operating system. When multiple operating systems are running on a multi-core processor, it is necessary to perform data interaction between the multiple operating systems. Considering that it is easy to control the entire device by one operating system, the second operating system may take over the control right of the target device. For example, the second operating system may take over the hardware controller via the first bus. The method for the second operating system to take over the control right of the target device is that after the second operating system is started, a request to take over the device is sent from the second operating system to the first operating system, for example, by sending an interrupt request via the second bus, to request to take over the hardware controller of the target device. The first operating system may receive the request to take over the device sent by the second operating system and pass the control right of the target device to the second operating system, or may perform operations related to the transfer of the control right of the target device, for example, stop running the service (process) for controlling the operating state of the target device. For example, after the Linux system is completely started, the RTOS system passes the control right of the fan to the Linux system, and the Linux system controls the fan. The above process may be executed after the system is powered on, that is, adopting the startup method of a multi-core dual system. First, the RTOS system is started, and by controlling the fan, it contributes to participating earlier. After the Linux system is completely started, the RTOS system passes the control right of the fan to the Linux system for control.

[0064] Here, for the server, the server has at least the characteristics of high scalability and high stability. Here, since the enterprise network cannot remain unchanged for a long time, with the development of network information, if the server does not have a certain degree of scalability, it will affect the use of servers within the enterprise, and ultimately affect the future growth of the enterprise. Therefore, scalability becomes the most basic characteristic required for the server. As long as it has relatively high scalability, better subsequent utilization can be ensured. Scalability further includes software scalability in addition to hardware scalability. Since the functions of the server are very complex compared to a computer, not only the hardware configuration but also the software configuration is very important. When trying to implement more functions, complete software support is required.

[0065] In addition, since the server needs to process a large amount of data to support the continuous operation of the service, the server further has another very important characteristic, for example, the characteristic of high stability. If the data transmission by the server cannot operate stably, it will have an extremely large impact on the performance of the service.

[0066] The technical solution of this application utilizes the characteristic of high scalability of the server to introduce a dual software system of a first operating system and a second operating system to generate a hardware interface signal, and at the same time, hardware devices such as GPLD and BMC chips that adjust the transmission voltage of the hardware interface signal and monitor the operating status of other devices inside the server are introduced. Moreover, in this application, a method of generating a hardware interface signal corresponding to a request instruction by the first operating system is adopted. First, the first operating system obtains the request instruction, then determines a plurality of logic bit information corresponding to the request instruction, and finally generates a hardware interface signal corresponding to the request instruction based on the plurality of logic bit information and a timer. As can be seen from the above content, this application realizes the technical effect of generating a hardware interface signal by simulation using a software method by generating a hardware interface signal corresponding to a request instruction by the first operating system, and achieves the purpose that the chip itself does not need to have a hardware logic design of the related hardware interface signal, which can not only reduce the difficulty of chip design, but also reduce the chip design cost. This application achieves the purpose of generating a hardware interface signal by using a software system without the need to perform a hardware logic design of the hardware interface signal for the chip, thereby reducing the difficulty of chip design and solving the problem that in the related technology, the chip itself needs to have a hardware logic design of a controller and the chip design cost is relatively high.

[0067] In addition, a dual software system including a first operating system and a second operating system is introduced to further ensure the stability of the server. Since the service response speed of the second operating system is lower than that of the first operating system, the first operating system with a faster service response speed is used to generate a hardware interface signal, and it can be ensured that the generation of the hardware interface signal is not interrupted, thereby ensuring that the hardware interface signal is continuously and stably output.

[0068] Through the above steps S202 to S206, the first operating system running on the first processor core of the processor controls the hardware controller of the target device via the first bus, thereby controlling the operating state of the target device. Here, the embedded system includes the first operating system, and guides to start the second operating system on the second processor core of the processor. Here, the embedded system further includes the second operating system. The response speed of the first operating system is higher than that of the second operating system. The first operating system and the second operating system communicate via the second bus, and the bandwidth of the second bus is higher than that of the first bus. After the second operating system is started, the second operating system takes over the hardware controller via the first bus, thereby taking over the control right of the target device, solving the problem that the cost of the device is high because an additional chip needs to be added in the startup control method of the operating system in the related art, reducing the hardware cost, and improving the extensibility of the device control.

[0069] In one exemplary embodiment, before the first operating system running on the first processor core of the processor controls the hardware controller of the target device via the first bus, the method further includes the following steps. S11: After the chip where the processor is located is powered on, the first processor core is woken up by the processor.

[0070] S12: By running the bootloader program of the first operating system by the first processor core, guide the first operating system to start on the first processor core. The entire system may be divided into two stages, namely the initial startup stage and the real-time operation stage according to the operation period. The startup control method in this embodiment may be executed in the initial startup stage or the real-time operation stage. For the initial startup stage, the initial startup stage starts after the system is powered on, that is, after the chip where the processor is located is powered on and the system is powered on, wake up one core to execute the guiding operation for the operating system, and the remaining cores are temporarily in the sleep state. The core to be woken up may be the first processor core.

[0071] Optionally, after being powered on, the system first executes a preset core scheduling policy (startup guiding policy), that is, the core scheduling policy is executed by one processor core of the processor. The core scheduling policy may be stored in the RAM or Norflash (non-volatile flash memory) on the SOC chip. This scheduling policy may be flexibly arranged according to different design requirements. Its main functions include specifying the initial processing resources (processor cores) that need to be run by different operating systems and determining the guiding process of the heterogeneous operating system. The power-on of the chip may mean the power-on at the SOC chip level.

[0072] Optionally, the chip may be a BMC (Baseboard Management Controller, a management control chip in the server platform) chip, which means an SOC chip based on the ARM multi-core architecture, integrating multiple peripheral hardware IPs (Intelligent Peripheral, smart external devices). The BMC chip is arranged on the main board (server motherboard), and powering on the chip means powering on at the SOC chip level.

[0073] After waking up the first processor core, the bootloader program may guide the first operating system to run on the first processor core, and the first processor core can guide the first operating system to start on the first processor core through the bootloader program. The bootloader program may be located in a personal computer or other computer application, and refers to a program for guiding the loading of the operating system, for example, a specific program in the BootRom. The specific program refers to the code for guiding the startup of the operating system and belongs to the bootloader program. The BootRom is a small block of mask ROM (Read-Only Memory) or write-protected flash memory in the integrated processor chip on the CPU on-chip.

[0074] According to this embodiment, in the initial startup stage, by guiding the operating system to start on the corresponding processor core through the bootloader program, the success rate of starting the operating system can be improved and the preparation for the real-time operation stage can be carried out. In one exemplary embodiment, controlling the hardware controller of the target device via the first bus by the first operating system running on the first processor core of the processor includes the following steps.

[0075] S21: Execute a first control task of a first operating system on a first processor core, where the first control task is used to control a hardware controller. S22: Read sensor data of a predetermined sensor corresponding to the target device by the first processor core. S23: Based on the sensor data of the predetermined sensor by the first control task, send a device control command to the hardware controller via a first bus, so that the hardware controller controls the operating state of the target device according to the device control command.

[0076] In this embodiment, controlling the hardware controller of the target device by the operating system may be implemented by controlling the hardware controller by a control task (service) on the processor core operated by this operating system, where the control task here may refer to the corresponding control task. For the hardware controller of the target device, a first control task (first control process) of the first operating system may be executed on the first processor core, and the hardware controller is controlled by the first control task.

[0077] Controlling the hardware controller may be performed based on the sensor data of the sensor. For different target devices, the parameters affecting their operation may be different, and accordingly, the sensor data that needs to be acquired may also be different. The target device may be a device that starts running immediately after the chip is powered on, and the corresponding sensor is a predetermined sensor. The type of the predetermined sensor may be various and may include at least one of a temperature sensor, a humidity sensor, a noise sensor, etc., but is not limited thereto. Since the first control task runs on the first processor core, the first processor core may read the sensor data of the predetermined sensor. The sensor data of the predetermined sensor may be stored in the storage space within the predetermined sensor, or may be transmitted by the predetermined sensor into a predetermined storage space. In this embodiment, the reading position of the sensor data of the predetermined sensor is not limited.

[0078] The read sensor data of the predetermined sensor may be the sensor data within one time period, may be all the sensor data after the target device starts, or may be the sensor data that satisfies other time limit conditions. After acquiring the sensor data of the predetermined sensor, the first control task can control the operating state of the target device based on the sensor data of the predetermined sensor. Controlling the operating state of the target device may be realized by the first control task sending a device control command to the hardware controller of the target device, and the hardware controller controlling the operating state of the target device according to the device control command.

[0079] Optionally, the first control task can determine the desired operating state of the target device based on the sensor data of a predetermined sensor. If the current operating state of the target device is different from the desired operating state, the device control command can be generated, and the device control command can be used to control the operating state of the target device to be adjusted to the desired operating state. The device control command may be transmitted to the hardware controller of the target device via the first bus. Since the first bus is the same as that in the foregoing embodiments, it will not be described further here.

[0080] According to this embodiment, by reading the sensor data of a predetermined sensor and controlling the target device based on the sensor data to control its operating state, the utilization rate of resources is improved. In one exemplary embodiment, the first control task transmitting a device control command to the hardware controller via the first bus based on the sensor data of a predetermined sensor includes the following steps.

[0081] S31: The first control task determines the target parameter value of the device operation parameter of the target device based on the sensor data of a predetermined sensor, where the device operation parameter is a parameter for controlling the operating state of the target device. S32: The first control task transmits a device control command including the target parameter value to the hardware controller via the first bus.

[0082] In this embodiment, the first control task can determine the desired operating state of the target device based on the sensor data of a predetermined sensor. The desired operating state may be represented by the parameter values of the device operating parameters. The device operating parameters may be the parameters for controlling the operating state of the target device, and for different types of devices, the corresponding device operating parameters may be different. For example, for a fan, the corresponding device operating parameter may be the rotation speed, and for other types of devices, the device operating parameters may be other operating parameters. The desired operating state may correspond to the target parameter values of the device operating parameters of the target device.

[0083] After determining the target parameter values of the device operating parameters of the target device, the target parameter values may be included in the above device control command. That is, the first control task sends a device control command including the target parameter values to the hardware controller. The method of sending the device control command to the hardware controller is the same as that in the foregoing embodiments, so it will not be described further here.

[0084] According to this embodiment, it is possible to determine the parameter values of the device operating parameters of the target device based on the sensor data, include the determined parameter values in the device control command, and improve the accuracy of device control. In one exemplary embodiment, determining the target parameter values of the device operating parameters of the target device based on the sensor data of a predetermined sensor by the first control task includes the following steps.

[0085] S41: When the target device is a fan, the first control task determines the target parameter values of the fan operating parameters of the fan based on the sensor data of a predetermined sensor. In this embodiment, the target device may be a fan, which may be a fan for dissipating heat from the located server or other devices, i.e., a heat dissipation fan. In such a case, the device operation parameters may be fan operation parameters, and the fan operation parameters may include one or more, and may include at least one of the rotation speed, rotation period, and period switching time, but are not limited thereto, and may be other operation parameters. In this embodiment, this is not limited.

[0086] Accordingly, for the first control task to determine the target parameter value of the device operation parameters of the target device based on the sensor data of the predetermined sensor may be for the first control task to determine the target parameter value of the fan operation parameters of the fan based on the sensor data of the predetermined sensor. After obtaining the target parameter value, the first control task controls the operation state of the fan by transmitting a device control command including the target parameter value to the hardware controller of the fan via the first bus.

[0087] According to this embodiment, by controlling the operation state of the fan, for example, in the case of system power-on, system restart or other scenarios, the operation state of the fan can be quickly controlled, improving the immediacy of fan control.

[0088] In one exemplary embodiment, when the target device is a fan, for the first control task to determine the target parameter value of the fan operation parameters of the fan based on the sensor data of the predetermined sensor includes the following steps. S51: When the target device is a fan and the predetermined sensor is a temperature sensor, the first control task determines the target rotation speed value of the fan's rotation speed based on the sensor data of the temperature sensor, where the rotation speed of the fan has a positive correlation with the temperature detected by the temperature sensor.

[0089] For the scenario where the target device is a fan, the predetermined sensor may be a temperature sensor. The number of such temperature sensors may be one, or may be plural. The installation positions of the temperature sensors may be arranged as required, and different temperature sensors may be installed at different positions. Optionally, the sensor data of the temperature sensors is used to represent the temperature detected by the temperature sensors. In contrast, the first control task can determine a target rotation speed value of the fan's rotation speed based on the sensor data of the temperature sensors. Here, the rotation speed of the fan has a positive correlation with the temperature detected by the temperature sensor.

[0090] When the number of temperature sensors is plural, the maximum temperature detected by the plural temperature sensors may be determined based on the sensor data of each temperature sensor, and the rotation speed of the fan may be determined based on the maximum temperature detected by the plural temperature sensors. Compared with determining the rotation speed of the fan based on the average temperature detected by the plural temperature sensors, the safety of device operation can be ensured. For the scenario where the number of fans is plural, the rotation speed of each fan may be determined based on the maximum temperature or the average temperature detected by the temperature sensor matching each fan.

[0091] For example, instead of a processing unit such as a CPLD, an EC chip, or a customized chip, the rotation speed of the fan may be controlled using a first operating system (e.g., an RTOS system) (the fan may also be controlled by BMC in real time). Immediately after the system is powered on, a first processor core (e.g., CPU0, and the first processor core may be woken up by hardware) may be woken up, and a bootloader program (e.g., a predetermined program in BootRom) may be run by the first processor core to load the startup of the first operating system. The first processor core reads various sensor data related to temperature and performs fan control (e.g., fan rotation speed control), fully simulating the above processing unit to realize the function of coordinated control of the fan. When controlling the rotation speed of the fan, the first operating system may calculate a PWM value based on the temperature sensor and adjust the rotation speed of the fan. By the above method, in the startup process of the second operating system, the rotation speed of the fan can be controlled by the first operating system.

[0092] Exemplarily, the hardware of the fan controller is shown in FIG. 3. The multi-core processor includes CPUs from CPU0 to CPUN. The multi-core processor runs the system service programs of the system normally. Since there are relatively many system service programs run by the Linux system, the number of initially allocated CPU cores is relatively large. The core initially allocated to the RTOS system is CPU0, and the cores initially allocated to the Linux system are CPUs from CPU1 to CPUN. Immediately after the system is powered on, CPU0 is woken up, and CPU0 runs a predetermined program in the BootRom to load the startup of the RTOS system. CPU0 reads various sensor data related to temperature through IIC (Inter-Integrated Circuit), and controls the rotation speed of the brushed fan (or brushless fan) through a brushed controller (or brushless controller). Here, the relationship between the first bus, the second bus, and IIC is that the first bus may be a bus under the second bus, and IIC may also be a bus under the first bus. A bus under one bus may mean a bus connected to this bus.

[0093] According to this embodiment, instead of adding an additional processing unit, the operating system running on the processor core is used to control the rotation speed of the fan, ensuring the control force on the fan and reducing the operating cost of the system. In one exemplary embodiment, guiding the startup of a second operating system on a second processor core of a processor includes the following steps.

[0094] S61: By executing a second program loader by the first processor core, the second processor core is woken up by the second program loader. S62: Guide the second operating system to start on the first processor core by running the general-purpose bootloader of the second operating system by the second processor core.

[0095] In this embodiment, when starting the operating system, a second program loader (abbreviated as SPL) may be loaded into the internal memory, for example, the static random-access memory (SRAM) inside the SOC. On the other hand, the SPL may be responsible for loading the general-purpose bootloader program (abbreviated as U-Boot) into the random-access memory (abbreviated as RAM). The second program loader may guide to load the second operating system or may guide to load the first operating system.

[0096] Regarding the second operating system, the second processor core may be woken up by the second program loader by running the second program loader by the first processor core. The second processor core can run the general-purpose bootloader (general-purpose bootloader program) of the second operating system, thereby guiding the second operating system to start on the first processor core. Here, the second program loader guides to load the boot program of the second operating system, and the boot program of the second operating system may include the general-purpose bootloader.

[0097] Note that the second program loader is the code executed in the first stage of the general-purpose bootloader program, and it can be responsible for transporting and running the code of the second stage of the general-purpose bootloader program to the system memory (also called System RAM or off-chip memory). The general-purpose bootloader program is open-source software that follows the GPL (General Public License) protocol and can be regarded as a bare machine comprehensive routine.

[0098] For example, after the system is powered on, the processor first wakes up the CPU0 core so that the RTOS system can run as fast as possible, and then uses the program in the BootRom to guide the startup of the RTOS system. In the startup process of the RTOS system, until the Linux system starts up normally, the SPL continues to load U-Boot, and U-Boot guides the startup of the second operating system on CPU1.

[0099] Note that the Boot Rom is the internal ROM fixed program of the chip (for example, the SOC chip), and it is the guide code of uboot. The Boot Rom reads the startup information of the hardware (for example, the settings of the DIP switch), reads the uboot-spl code (that is, SPL) from a predetermined startup medium (for example, SD, MMC, etc.), and the SPL is mainly responsible for initializing the external RAM and the environment, loads the true uboot mirror into the external RAM and executes it. The external RAM may be DDR (Double Data Rate Synchronous Dynamic Random-Access Memory) or other RAM. According to this embodiment, the second processor core is woken up by the second program loader, and by running the general-purpose bootloader program on the second processor core, it guides to start the second operating system on the corresponding processor core, and can improve the convenience and success rate of starting the operating system.

[0100] As a selective example, hereinafter, taking the RTOS system and the Linux system as examples, the startup process of the multi-core dual system will be interpreted and described. In order to take over the fan management as quickly as possible, the RTOS system can be started to the maximum extent, and after the Linux system startup is completed, the Linux system can take over the control right of the fan. As shown in FIG. 4, the startup process of the multi-core dual system may include the following steps.

[0101] Step 1: Immediately after the system is powered on, wake up CPU0. Step 2: Run the predetermined program in the BootRom by CPU0 and load to start the RTOS system. Step 3: In the startup process of the RTOS system, wake up CPU1 to guide u-boot and start the fan control program (FanCtrl_RTOS_APP) in the first operating system.

[0102] Step 4: Guiding u-boot by CPU1 may include the SPL stage and the Uboot stage, and proceed to the SPL stage by calling SPL. Step 5: In the SPL stage, SPL guides to start Uboot. Step 6: In the Uboot stage, load the Linux core (CPU1~CPUN) and start the BMC service program and the fan control program (FanCtrl_Linux_APP) in the second operating system.

[0103] According to this selective exemplification, in the startup and operation process of the dual system, first, start the RTOS system to control the fan, and after starting the Linux system, transfer the control right of the fan by the second operating system, so as to ensure that the fan can be quickly controlled when the system is powered on, and the efficiency of fan control can be improved.

[0104] In one exemplary embodiment, the second operating system taking over the hardware controller via the first bus includes the following steps. S71: The second operating system sends a first inter-core interrupt to the first operating system via the second bus, where the first inter-core interrupt is used to request the second operating system to take over the hardware controller.

[0105] S72: When receiving a second inter-core interrupt sent back by the first operating system in response to the first inter-core interrupt and instructing to agree to the second operating system taking over the hardware controller, the second control task of the second operating system controls the hardware controller via the first bus, where the second control task is used to control the hardware controller.

[0106] In this embodiment, it is possible to realize the transfer of the control right of the target device between different operating systems by means of an inter-core interrupt, for example, SGI (Software Generated Interrupt, a trigger for an interrupt by software, which is an inter-core interrupt in the Linux system). One operating system can request to take over the hardware controller of the target device by issuing an inter-core interrupt to another operating system by means of IPI (Inter-Processor Interrupt), thereby obtaining the control right of the target device. Here, different from the interrupt by a normal external device, IPI is an interrupt triggered between multiple cores within the SOC, and the core reserves a part of the interrupt numbers dedicated to IPI. For example, in the ARM64 architecture, the reserved interrupt numbers are 16 interrupt numbers from 0 to 15.

[0107] Regarding the second operating system, when the second operating system needs to take over the hardware controller of the target device, it can request the second operating system to take over this hardware controller by sending a first inter-core interrupt to the first operating system. The first inter-core interrupt may be sent via the second bus. After receiving the first inter-core interrupt, the first operating system can determine whether to allow the second operating system to take over this hardware controller at present. If it allows, it can return a second inter-core interrupt to the second operating system, and this second inter-core interrupt is used to instruct the second operating system to agree to take over the hardware controller.

[0108] After receiving the second inter-core interrupt, the second operating system can control the hardware controller by the second control task, where the second control task is used to control the hardware controller, and the control of the second control task over the hardware controller may be realized via the first bus. The second control task may be constructed before sending the first inter-core interrupt, or may be constructed after receiving the second inter-core interrupt, and this is not limited in this embodiment.

[0109] For example, after the Linux system startup is completed, CPU1 starts to send an IPI interrupt to CPU0 and requests to obtain the control right of the fan. According to this embodiment, it is possible to realize the transfer of the control right of the target device between different operating systems through inter-core interrupts, and improve the reliability of device control.

[0110] In one exemplary embodiment, after the second operating system sends a first inter-core interrupt to the first operating system via the second bus, the above method further includes the following steps. S81: In response to the obtained first inter-core interrupt, control the third control task of the first operating system to sleep, where the third control task is used to control the hardware controller. S82: If the third control task has already slept, the first operating system sends a second inter-core interrupt to the second operating system via the second bus.

[0111] In this embodiment, for the first operating system, the task of controlling the hardware controller of the target device is the third control task, which may also be the first control task described above. The logic for controlling the hardware controller is the same as that in the foregoing embodiments. After obtaining the first inter-core interrupt, the first operating system can control the third control task to sleep, and since there is a control task for controlling the hardware controller in both of the two operating systems, it is possible to avoid causing confusion in device control.

[0112] After the third control task has already slept (i.e., the third control task is in a sleep state), the first operating system may send the above-mentioned second inter-core interrupt to the second operating system, and this second inter-core interrupt may be sent via the second bus. For example, after the RTOS system receives the IPI interrupt sent by CPU1, the RTOS system starts to successively sleep the related services on the RTOS system. After the related services on the RTOS system are completely asleep, CPU0 sends an IPI interrupt to CPU1 and notifies CPU1 that it can obtain the control right of the fan.

[0113] According to this embodiment, based on the received inter-core interrupt, the corresponding control task can be made to sleep. After the corresponding control task has slept, the device control right can be transferred by the inter-core interrupt, and the reliability of device control can be improved. In one exemplary embodiment, the above method further includes the following steps. S91: If the third control task has already slept, push the system operation data of the first operating system onto the stack. Here, the second inter-core interrupt is further used to instruct the second operating system to take over the first processor core.

[0114] In this embodiment, when the second operating system is unable to control the operating state of the target device, the first operating system can temporarily control the operating state of the target device. In such a case, all tasks running in the first operating system are tasks related to controlling the operating state of the target device, for example, the third control task. When the second operating system has already been able to control the operating state of the target device and the third control task has already entered the sleep state, no service process needs to be running in the first operating system, and the first processor core is not effectively utilized.

[0115] For example, in the startup process of the Linux system, the RTOS system has the control right of the fan. After Linux starts up normally, it takes over the control right of the fan from the RTOS system. At this time, no service process is running on the RTOS system, and the CPU0 core resource is not effectively utilized. In this embodiment, a resource recovery mechanism of the processor core (for example, the CPU0 core) of the first operating system may be adopted. When the third control task has already entered the sleep state, the fields of the first operating system may be saved, that is, the system operation data of the first operating system is pushed onto the stack. At the same time, an instruction may be given to the second operating system to take over the first processor core by means of an inter-core interrupt of the second core.

[0116] For example, the resource recovery mechanism of the CPU0 core may be adopted. After the Linux system is fully started (started on CPU1…CPUN), the RTOS system transfers the control right of the fan to the Linux system, controls it, releases the CPU0 core so that it can be scheduled by the Linux system, puts the CPU0 to sleep the RTOS system, releases all current services, pushes the running data onto the stack, and joins the queue where the Linux operating system runs itself to achieve the purpose of improving the utilization rate of the CPU core resources. For the Linux system, after taking over the control right of the fan by the Linux system, the RTOS system may be put to sleep, the CPU0 core may be released, the CPU0 core may be recovered, and the CPU0 core can be normally scheduled by the Linux system, and all cores of the CPU can achieve the purpose of providing services to the Linux system, saving resources, and improving the utilization rate of the CPU core resources.

[0117] According to this embodiment, by adopting the resource recovery mechanism of the processor core and taking over the control right of the target device by the second operating system, the data of the first operating system running on the processor core of the first operating system is pushed onto the stack, and the processor core of the first operating system is released to the second operating system, the resource utilization rate of the processor core can be improved.

[0118] As a selective example, hereinafter, taking the RTOS system and the Linux system as examples, the process of incorporating the control right of the fan by inter-core interrupt will be interpreted and described. As shown in Figure 5, after the Linux system triggers an interrupt requesting to take over the control of the fan, the FanCtrl_RTOS_APP process completes what it is currently processing, and after the RTOS system pushes the system operation data onto the stack, it returns an interrupt agreeing to take over the control of the fan. The Linux system takes over the CPU0 core and schedules the FanCtrl_Linux_APP process according to the scheduling balance algorithm to run on the CPU0 core or the CPU core of another Linux system.

[0119] According to this alternative exemplary embodiment, the control right of the fan can be incorporated by an inter-core interrupt, which can improve the convenience of information interaction and the reliability of device control. In one exemplary embodiment, after the second operating system takes over the hardware controller via the first bus, the method further includes the following steps.

[0120] S101: When attempting to restart the second operating system, the second operating system wakes up the first operating system via the second bus, and the first operating system takes over the control right of the target device by taking over the hardware controller via the first bus. S102: Control the second operating system to restart the system. In this embodiment, when it is necessary to restart due to reasons such as system shutdown and receiving a reboot command, the second operating system can first wake up the first operating system and take over the control right of the target device by having the first operating system take over the hardware controller. The wake-up of the first operating system via the second bus may be executed, or the first operating system may execute the takeover of the hardware controller via the first bus.

[0121] According to this embodiment, when a restart occurs in the second operating system, the first operating system can be woken up to take over the control right of the target device, thereby improving the reliability of device control. In one exemplary embodiment, when attempting to restart the second operating system, waking up the first operating system by the second operating system via the second bus includes the following steps. S111: When attempting to restart the second operating system, the second operating system transmits a system wake-up interrupt for waking up the first operating system to the first operating system via the second bus.

[0122] In this embodiment, it may also be possible to wake up the first operating system by an inter-core interrupt. When attempting to restart the second operating system (for example, system down, receiving a reboot command), the second operating system may wake up the first operating system by sending a system wake-up interrupt to the first operating system. This system wake-up interrupt may be a spontaneous wake-up interrupt. After the first operating system takes over the hardware controller, the second operating system can be controlled to restart the system. On the other hand, after the second operating system is restarted, the hardware controller can be taken over again. The process of taking over the hardware controller is the same as that in the foregoing embodiment and will not be described further here.

[0123] For example, as shown in FIG. 6, in the fan control workflow, when a restart (system shutdown, reboot command) occurs in the Linux system, a spontaneous wake-up interrupt is sent. After the restart occurs in the Linux system, the fan control flow may include the following steps. Step S602: The Linux system restarts due to reasons such as receiving a system shutdown or reboot command.

[0124] Step S604: The Linux system triggers a spontaneous wake-up interrupt. Step S606: Wake up the RTOS system, and the RTOS system takes over the control right of the fan. Step S608: Execute the restart process of the Linux system.

[0125] According to this embodiment, the spontaneous wake-up of the operating system is performed by the inter-core interrupt, which can improve the convenience and reliability of waking up the operating system. Hereinafter, in combination with optional examples, the startup control method of the embedded system in the embodiments of the present application will be interpreted and described. In this optional example, the first operating system is the RTOS system, the second operating system is the Linux system, and the target device is the fan.

[0126] This optional example provides a technical solution for real-time fan control by a multi-core dual system. As shown in FIG. 7, the flow of the startup control method of the embedded system in this optional example may include the following steps. Step 1: In the T0 - T1 stage, start powering on the system. CPU0 is woken up by the hardware and starts executing the code of the RTOS system part, and at the same time, wake up CPU1 so that CPU1 participates in the startup process of u-boot.

[0127] Step 2: Starting from time T1, the awakened CPU1 begins to execute the code of the u-boot part, starts initializing data related to some hardware, guides the start of the Linux operating system, and the tasks related to fan control in the RTOS system on CPU0 continuously run until time T5. Step 3: Starting from time T2, the Linux operating system begins to start.

[0128] Step 4: At time T3, the startup of the Linux system is completed. CPU1 starts to send an IPI interrupt to CPU0, requests to obtain the control right of the fan, stops the services related to the RTOS system on CPU0, and runs the service code related to the Linux system. Step 5: Starting from time T4, the RTOS system receives the IPI interrupt sent by CPU1, and begins to successively put the related services on the RTOS system to sleep. After the related services on the RTOS system are completely asleep, CPU0 sends an IPI interrupt to CPU1, notifying CPU1 that it can obtain the control right of the fan and CPU0 can participate in the service operation on the Linux system side.

[0129] Here, starting from time T5, CPU0 is recovered to the Linux system side, and the entire system is changed to the operating mode of a multi-core one system, and all subsequent codes run normally. According to this alternative exemplary embodiment, instead of hardware, by multiplexing one CPU core, the purpose of controlling the fan is achieved, the utilization rate of the resources of the CPU core is improved, there is no need to increase additional costs, and it further has excellent scalability.

[0130] In one exemplary embodiment, According to the resource dynamic allocation rule, allocate the services to be allocated in one group to the corresponding operating system in the embedded system, where the resource dynamic allocation rule includes performing dynamic resource allocation based on at least one of service response speed, service resource occupancy rate, service coupling degree, and service importance, and the embedded system includes a first operating system and a second operating system. Determine the resource allocation result corresponding to the services to be allocated in one group, where the resource allocation result is used to indicate the processing resources corresponding to each service to be allocated among the services to be allocated in one group among the processing resources of the processor, and the processing resources of the processor include processor cores. Based on the operating system and the resource allocation result corresponding to each service to be allocated, a method of allocating the processing resources of the processor to the first operating system and the second operating system can be adopted to allocate operating services and processing resources to each operating system, but not limited to those methods.

[0131] In the operation process of the processor, one group of services to be allocated, that is, the services to be allocated to the first operating system and the second operating system, may be obtained. Since dimensions such as the response speed, service resource occupancy rate, service coupling degree with other services, and service importance of different services to be allocated may be different, resource dynamic allocation rules can be pre-arranged. The resource dynamic allocation rules may include rules for allocating services. By allocating the services to the corresponding operating systems, the services allocated by the processing resources of the corresponding operating systems are executed. Optionally, the resource dynamic allocation rules may include performing dynamic resource allocation based on at least one of the service response speed, service resource occupancy rate, service coupling degree, and service importance. Different allocation rules may have corresponding priorities. For example, the priorities may be, in descending order, service importance, service coupling degree, service response speed, and service resource occupancy rate. According to the resource dynamic allocation rules, one group of services to be allocated (or tasks to be allocated, and different services to be allocated may correspond to different processes) can be allocated to the corresponding operating systems in the embedded system to obtain the service allocation result.

[0132] Optionally, based on the constraints on the response time, the first operating system may be an operating system with clear and fixed time constraints, and all processing processes (task scheduling) need to be completed within a fixed time constraint. Otherwise, the system will error, and it may be a real-time operating system, such as FreeRTOS, RTLinux, etc., or a real-time operating system in other embedded systems. The second operating system does not have this feature. Generally, the second operating system adopts a fair task scheduling algorithm. When the number of threads / processes increases, it is necessary to share the CPU time. Task debugging has uncertainty and may be called a non-real-time operating system, such as contiki, HeliOS, Linux, etc., or a non-real-time operating system in other embedded systems.

[0133] Accordingly, the services assigned to the first operating system are generally real-time services. A real-time service means a service that needs to be scheduled within a predetermined time, and it is necessary to process this service at a sufficiently fast speed by the processor, and the processing result can also control the production process or respond promptly to the processing system within a predetermined time. As a typical scenario, in industrial control, the control of a robot hand belongs to real-time services. The system needs to take prompt measures before detecting an incorrect operation of the robot hand. Otherwise, it may cause serious consequences. The services assigned to the second operating system are generally non-real-time services. A non-real-time service means a service that is not sensitive to the scheduling time and has a certain tolerance to scheduling delays, such as reading sensor data of a temperature sensor in a server.

[0134] Note that a real-time operating system can accept and process external events or data at a sufficiently fast speed when they occur, and the processing results can control the production process or promptly respond to the processing system within a predetermined time. It can also schedule all available resources to complete real-time services and control all real-time services to operate in coordination, and has the characteristics of timely response and high reliability.

[0135] Optionally, the service management module may execute to allocate a group of services to be allocated to the corresponding operating system. As shown in FIG. 8, this service management module may be a software module running on the first operating system or the second operating system. Taking the example of running on the second operating system, the service management module may be implemented by software in the Linux system. This service management module can allocate a group of services to be allocated to the corresponding operating system in the embedded system according to the resource dynamic allocation rule.

[0136] After allocating each service to be allocated to the corresponding operating system, based on the service allocation result, allocate the processing resources corresponding to each service to be allocated, and a resource allocation result corresponding to a group of services to be allocated can be obtained. When allocating processing resources to the service to be allocated, the processing resources of the first operating system may be allocated to the service allocated to the first operating system, or the processing resources of the second operating system may be allocated to the service allocated to the second operating system. At the same time, considering the load balance, if there are unallocated processing resources, some of the services may be allocated the unallocated processing resources.

[0137] The processing resources of the processor may perform dynamic allocation of the processing resources in time slice units. Considering that the operating system to which the processing resources belong is frequently switched, and the service processing time is not necessarily an integer multiple of the time slice, the response time of some services will be extended. The processor cores of the processor may be allocated to the first operating system and the second operating system in processor core units. That is, the processor cores of the processor are allocated to the corresponding operating system in the whole processor core unit, the number of processor cores allocated to each operating system is an integer, and the processor cores allocated to different operating systems are different from each other.

[0138] Optionally, the resource dynamic allocation module may execute to determine the resource allocation result corresponding to a group of services to be allocated. As shown in FIG. 8, this resource dynamic allocation module may be a software module running on the first operating system or the second operating system. Taking the case of running on the second operating system as an example, the resource dynamic allocation module may be realized by a software module in the second operating system. It can dynamically allocate the processing resources of the service based on the output of the service management module. Here, the software module may be a program module with a preset function. For example, the resource dynamic allocation module may be a program module with a resource dynamic allocation function, and the service management module may be a program module with a service management function. Each software module can be arranged and adjusted as a whole and can be applied in various application engineering.

[0139] Based on the operating system corresponding to each service to be allocated and the resource allocation result, the processing resources of the processor may be allocated to the first operating system and the second operating system. Optionally, the unallocated processing resources of the processor may be allocated to the corresponding operating system, and the unallocated processing resources may be determined based on the correspondence between the unallocated processing resources and the service to be allocated and the correspondence between the service to be allocated and the operating system.

[0140] Optionally, as shown in FIG. 8, the resource adaptation scheduling module (for example, the core adaptation scheduling module) may execute the allocation of the processing resources of the processor to the first operating system and the second operating system. This resource adaptation scheduling module may be a software module running on the first operating system or the second operating system. Taking the case of running on the second operating system as an example, the resource adaptation scheduling module may be realized by software in the Linux system, and based on the output of the service management module and the output of the resource dynamic allocation module, the actual scheduling operation of the processing resources of the processor (for example, the processor core resource) can be completed. For example, through the resource scheduling of the core resource adaptation module, M cores out of (M + N) cores are scheduled to the real-time operating system, and N cores are scheduled to the non-real-time operating system.

[0141] For example, heterogeneous operating systems (heterogeneous operating systems) may be run on different hardware cores of the same processor. The entire processor system has the ability to concurrently process real-time and non-real-time services, and by adaptively adjusting the processor hardware core resources (e.g., processor cores) occupied by different operating systems, it is possible to significantly improve the resource utilization rate of the processor. Here, heterogeneous means that the types of operating systems running on the same multi-core processor of an embedded system are different, and multi-system means that the number of operating systems running on the same multi-core processor of an embedded system is plural, and these operating systems run simultaneously in the time dimension.

[0142] Optionally, the above process further includes generating a rule structure by reading a rule profile, where the rule structure is used to record resource dynamic allocation rules. The resource dynamic allocation rules may be arranged based on the rule profile, and the read rule profile may be used to generate a rule structure for recording the resource dynamic allocation rules. Here, the rule profile may be a load balance policy file (payload_balance.config), and the load balance policy file may be used to arrange the classification method of various services (or processes) to be run, the evaluation principle of the real-time level, etc. In the load balance policy file, the resource dynamic allocation rules may be arranged according to different parameters. One example of the load balance policy profile is as follows.

[0143] classification kinds =2 / / When the value is 1, classify the processes according to attributes such as important and unimportant; otherwise, classify the processes according to a pre-arranged classification method (e.g., real-time and non-real-time). real-time grade evaluation = 2 / / When the value is 1, the average CPU occupancy rate within the past statistical minutes is used as the process real-time level evaluation principle; otherwise, it means using the pre-arranged priority as the process real-time level evaluation principle. statistic minutes = 5 / / represents the statistical time (unit: minute) of the average occupancy rate of each process, and is valid when real-time grade evaluation is 1.

[0144] Optionally, the resource dynamic allocation rule may be stored in the load balancing policy module. Here, the load balancing policy module may be a software module running on the first operating system or the second operating system (for example, a software module running on the Linux system), which can provide policy guidance to the service management module and includes classification methods for various services (or processes) running in the system, real-time level evaluation principles, etc. The service management module can classify and manage services in the system according to the real-time level, and further guide the resource adaptive scheduling module to reallocate the processor resources. Exemplarily, based on the output of the load balancing policy module, the actual classification of services can be executed, and a list including real-time services and non-real-time services can be generated.

[0145] Note that the above classification method and real-time level evaluation principle are open, and users can customize a certain method or principle. The rules for service management by the service management module may be dynamically arranged or additional rules may be set on top of the existing rules. Multiple rules with the same function may be set in the service management module, but there is no conflict between the rules. That is, based on the selection conditions of the rules such as the rule arrangement time and rule priority, the currently used rule among the rules with the same effect is determined, thereby avoiding the occurrence of conflicts between the rules. The profile load_balance.config describes one possible situation. In the profile, the classification_kinds variable indicates specific classification criteria (for example, according to the importance or real-time nature of the service) and classification classes (for example, important services and general services, real-time services and non-real-time services, etc.). On the other hand, the real-time_grade_evaluation variable indicates the real-time evaluation criteria (which may be according to the average CPU occupancy rate within the past statistic_minutes minutes or the pre-arranged service priority). The type of real-time level can be customized by the user and may be defined as three types: high, normal, and low, or may be further subdivided into more types.

[0146] The output of the load balance policy module is, that is, the arranged classification method, real-time level evaluation principle, etc. When implemented in software, it may be a specific profile (for example, the load_balance.config file) or a structure variable. These files or structure variables can ultimately all be accessed by the service management module, thereby obtaining the specific policy of the load balance.

[0147] According to this embodiment, by reading the rule profile to generate a rule structure and recording the resource dynamic allocation rules, the convenience of information arrangement can be improved. Optionally, the process is to obtain a rule update profile through the external interface of the second operating system, where the rule update profile is used to update the resource dynamic allocation rules of the already deployed resources, and further includes updating the rule structure using the rule update profile to update the resource dynamic allocation rules recorded in the rule structure.

[0148] The rule structure may be in a fixed format, that is, it is not allowed to be modified in the process of the embedded system running, or it may be in a flexibly deployable format, that is, the deployment may be changed by a profile of a specific format. In this embodiment, a rule update profile may be obtained, and this rule update profile is used to update the resource dynamic allocation rules of the already deployed resources, and the rule structure can be updated using the rule update profile, thereby updating the resource dynamic allocation rules recorded in the rule structure.

[0149] When updating the rule structure using the rule update profile, a new rule structure may be directly generated based on the rule update profile, and the existing rule structure may be replaced with the newly generated rule structure, or the parameter values of the corresponding rule parameters in the rule structure may be updated using the parameter values of the rule parameters indicated by the rule update profile.

[0150] Optionally, a profile of a specific format may be read through the external interface of the first operating system or the second operating system, and considering the level of service that needs to be processed, the second operating system may mainly be responsible for the resource dynamic scheduling of the embedded system, etc. When obtaining the rule update profile, the rule update profile may be obtained through the external interface of the second operating system. For example, the load balancing policy module may have a fixed format, may be arranged by an external interface of the Linux system, and for example, may define a profile (load_balance.config) in the specific format described above, and may change the arrangement by the file reading and writing method.

[0151] Note that the external interface is an external interface of a multi-core processor, and may be a network interface, an SPI (Serial Peripheral Interface) controller interface, a UART serial port, etc., as long as it is a path through which data can be acquired from the outside. The hardware used by the file and the specific file location may be read by various implementation solutions. For example, the profile may be loaded from a Web (World Wide Web) interface via a network interface, the profile may be read from the SPI Flash (flash memory) of a board card by an SPI controller, or the profile may be obtained from a serial port data transmission and reception software tool on another PC (Personal Computer) via a UART serial port.

[0152] According to this embodiment, by obtaining a rule update profile and updating a profile update rule structure using the obtained rule, the flexibility of the arrangement of the resource dynamic allocation rule can be improved. Optionally, a method of allocating the service to be allocated among one group of services, which has a service response speed requirement equal to or higher than the set response speed threshold, to the first operating system, and a method of allocating the service to be allocated among one group of services, which has a service response speed requirement lower than the set response speed threshold, to the second operating system are adopted, and based on the resource dynamic allocation rule, the service to be allocated in one group can be allocated to the corresponding operating system in the embedded system, but it is not limited to these methods.

[0153] When allocating the service to be allocated, the service to be allocated may be allocated to the corresponding operating system based on the service response speed requirement of the service to be allocated. The service response speed is used to evaluate the real-time level of the service. The higher the service response speed requirement, the more sensitive it is to the scheduling time and response speed of the operating system, and the higher the real-time level. It is necessary for the operating system to process the service with a high service response speed requirement at a sufficiently fast speed, and the result of the processing can also control the production process or respond promptly to the processing system within a predetermined time. On the other hand, the service with a low service response speed requirement has a certain tolerance to scheduling delays.

[0154] For services to be assigned where the service response speed requirement is greater than or equal to the set response speed threshold, since they are sensitive to the scheduling time and response speed of the operating system, such services to be assigned may be assigned to the first operating system (for example, real-time services may be assigned to a real-time operating system). For services to be assigned where the service response speed requirement is less than the set response speed threshold, since they are not sensitive to the response speed and scheduling time, such services to be assigned may be assigned to the second operating system (for example, non-real-time services may be assigned to a non-real-time operating system). Here, the service response speed requirement may be indicated by an indication parameter of the service response speed, and the set response speed threshold may be a response speed threshold in the order of milliseconds or seconds, for example, 100 ms, 200 ms, 1 s, etc., and in this embodiment, the set response speed threshold is not limited.

[0155] Optionally, when selectively assigning a group of services to be assigned to the corresponding operating system in an embedded system, a first service list corresponding to the first operating system and a second service list corresponding to the second operating system may be output. The first service list is used to record the services to be assigned to the first operating system, and the second service list is used to record the services to be assigned to the second operating system. That is, the service assignment result includes the first service list and the second service list, and the output first service list and second service list may be used in the dynamic scheduling process of the processing resources of the processor.

[0156] For example, perform a real-time level classification on system services, obtain a list of real-time services and non-real-time services. Assume that there are a total of 20 services. Here, the real-time services are Service 1 and Service 2, and the non-real-time services are Service 3 to Service 20.

[0157] Here, the service management module may classify the services that are about to be executed currently. At the first startup of the BMC system, since all the services that the system is about to execute currently are already known to the system, the service management module classifies these services once based on the output of the load balancing module. After classification, different services are assigned to different operating systems (RTOS system and Linux system) for execution. In the subsequent operation process, if the number of service processes changes (for example, a certain process hangs up or a new process starts), the service management module further continues to perform service classification and classify and manage the existing services in real time according to the load balancing policy. The service management module may be a process resident in the Linux system, which itself runs constantly and manages and classifies the processes that are currently running.

[0158] According to this embodiment, by allocating the services to be allocated to the corresponding operating systems according to the service response speed requirements, the immediacy of the service response of the services sensitive to the scheduling time can be ensured. Optionally, a method of allocating services with a service resource occupancy rate lower than a first occupancy threshold among the services to be allocated to one group to a first operating system, and a method of allocating services with a service resource occupancy rate of the services to be allocated to one group being equal to or higher than the first occupancy threshold to a second operating system are adopted, and according to the dynamic resource allocation rule, the services to be allocated to one group can be allocated to the corresponding operating system in the embedded system, but not limited to these methods.

[0159] When allocating the service to be allocated, the service to be allocated can be allocated to the corresponding operating system based on the service resource occupancy rate of the service to be allocated. The service resource occupancy rate may be the average ratio of the processing resources of the service per unit time (for example, the CPU occupancy rate per minute). Since the height of the service resource occupancy rate affects the response speed of this service and the response speed of subsequent services, the real-time level of the service can be evaluated based on the service resource occupancy rate. The higher the service resource occupancy rate, the greater the impact on the scheduling time and response speed of the operating system, and the lower the real-time level. On the other hand, for services with a low service resource occupancy rate, the impact on the scheduling time and response speed of the operating system is not significant, and the real-time level is high. For a service to be allocated with a service resource occupancy rate lower than the first occupancy threshold, the impact on the scheduling time and response speed of the operating system is not significant, and such a service to be allocated can be allocated to the first operating system. For a service to be allocated with a service resource occupancy rate equal to or higher than the first occupancy threshold, since the impact on the scheduling time and response speed of the operating system is relatively significant, such a service to be allocated can be allocated to the second operating system. Here, the first occupancy threshold may be arranged as needed, and may be 10%, 15%, 20% or other thresholds. At the same time, this first occupancy threshold may also be dynamically adjusted.

[0160] According to this embodiment, by allocating the service to be allocated to the corresponding operating system according to the service resource occupancy rate, the immediacy of responding to a service with a low service resource occupancy rate can be ensured. Optionally, a method of allocating a service to be allocated in a group of services to be allocated to the first operating system, where the service binding degree between the service to be allocated and the service already allocated to the first operating system is equal to or higher than the first binding threshold; at least one of the method of allocating a service to be allocated in a group of services to be allocated to the second operating system, where the service binding degree between the service to be allocated and the service already allocated to the second operating system is equal to or higher than the second binding threshold, can be adopted. According to the dynamic resource allocation rule, a group of services to be allocated can be allocated to the corresponding operating system in the embedded system, but it is not limited to these methods.

[0161] When allocating a service to be allocated, based on the service coupling degree of the service to be allocated, the service to be allocated can be allocated to the corresponding operating system. The service coupling degree can be used to represent the degree of association between the service to be allocated and the services already allocated in each operating system. When the service coupling degree between one service to be allocated and the services already allocated in a certain operating system is relatively high, it is not appropriate to allocate it to another operating system. Therefore, based on the service coupling degree between the service to be allocated and the services already allocated in each operating system, the service to be allocated can be allocated to the corresponding operating system.

[0162] Optionally, based on the relationship between the input and output of the service, the service coupling degree can be evaluated. The service coupling degree may be represented by various coupling degree levels. When there is no relationship between the input and output of the service, the coupling degree level is a low level (or other coupling degree levels indicating no relationship between services). When the execution of one service depends on the output of another application (the service cannot be started without using this output as input), the coupling degree level between services is a high level. When the execution of one service uses the output of another application, but this output does not interfere with the normal execution of the service (it is only necessary to obtain this output when the service executes the corresponding operation, and the corresponding operation is not a core operation), the coupling degree level between services is a middle level. Also, the service coupling degree may be represented by a numerical value, and the service coupling degree may be evaluated according to one or more coupling degree conditions (for example, the relationship between input and output), and the numerical value corresponding to the satisfied coupling degree condition is determined as the numerical value of the service coupling degree.

[0163] For the services to be assigned to one group, if there are services to be assigned whose service coupling degree with the already assigned services of the first operating system is equal to or higher than the first coupling degree threshold, such services to be assigned can be assigned to the first operating system. On the other hand, for the services to be assigned to one group, if there are services to be assigned whose service coupling degree with the already assigned services of the second operating system is equal to or higher than the first coupling degree threshold, such services to be assigned can be assigned to the second operating system.

[0164] For example, in addition to generating a real-time service list and a non-real-time service list, the service management module is further responsible for service decoupling evaluation and management, that is, finding out the services that can be independently passed to the real-time operating system for operation from all real-time services. For the services that cannot be easily reassigned to the processor resources by the hardware resource dynamic allocation module and cannot be independently passed to the real-time operating system for operation, if the service coupling degree with non-real-time services is high, they may be assigned to the non-real-time operating system.

[0165] Here, although some services have real-time requirements, since their interaction with other non-real-time services in the system is very frequent (that is, the service coupling degree is high), in this case, in order to improve the efficiency of the overall data interaction, such services are assigned to the non-real-time operating system. There is another type of real-time service that is relatively independent itself. In this case, it can be classified into the real-time operating system, and this process is the so-called "decoupling" operation. The criterion for determining whether a service is independent is not unique, and it may be the intimacy between the above services, or other indicators that users are interested in.

[0166] The reallocation policy is open. One possible policy is to allocate processor cores based on the proportion of the number of services allocated to the real-time operating system and the non-real-time operating system by the service management module at the first run of the system. In subsequent operation processes, resource allocation is adjusted based on the respective core resource occupancy rates in the dual-system. From this perspective, the reallocation process, the core preemption, and the release process are processes that cooperate with each other.

[0167] According to this embodiment, by allocating the services to be allocated to the corresponding operating system according to the service coupling degree, it is possible to ensure the accuracy of service processing for a plurality of services with relatively high service coupling degrees. Optionally, allocate the service to be allocated that contains sensitive information among one group of services to be allocated to the target operating system, where the target operating system is the operating system with a low interaction frequency with the user among the first operating system and the second operating system. Using this method, according to the dynamic resource allocation rule, one group of services to be allocated can be allocated to the corresponding operating system in the embedded system, but it is not limited to these methods.

[0168] In this embodiment, for a service to be assigned that contains sensitive data (e.g., sensitive information such as a password), which may be an important and sensitive service, for example, a service that is not desirable to be disclosed to users, it may be assigned to a target operating system, and the target operating system performs hard-core level security protection separation for the service to be assigned that contains sensitive information. Here, the target operating system is an operating system with a low interaction frequency with the user among the first operating system and the second operating system, or an operating system with a fast response speed, for example, the first operating system.

[0169] For example, this service processing module further performs hard-core level security protection separation for system services, that is, important and sensitive (services not desirable to be disclosed to users) services are classified as real-time services, and finally, the offloading of these services from the non-real-time operating system to the real-time operating system can be realized to perform the security protection function. Here, when different services classified by this service processing module are realized in software, they can be arranged in the form of a structure. By designing the security space between heterogeneous operating systems, sensitive services are offloaded from the non-real-time operating system to the real-time operating system to achieve the hard-core level security protection purpose. Here, sensitive services refer to services related to security, for example, services related to the privacy of users such as the user's password and identity information.

[0170] Here, the hard core level means that the services are separated at the processor core level. That is, sensitive services are allocated to the real-time operating system (since the cores occupied by the real-time operating system are different from those of the non-real-time operating system, it belongs to the core level separation). The real-time operating system has a relatively weak frequency and degree of interaction with users compared to the non-real-time operating system. Therefore, as a user, it is difficult to "detect" sensitive data generated by the services running on it. For upper-level applications, services such as user authentication management and secure encryption belong to the above-mentioned important and sensitive services. The service management module forcibly classifies the above services as real-time services, and then when dynamically allocating hardware resources, it can be realized that the above services run on the real-time operating system, achieving the effect of secure separation.

[0171] According to this embodiment, by allocating the service to be allocated that contains sensitive information to an operating system with a low interaction frequency with users, it is possible to perform hard core level security protection separation for system services, and improve the security of running services. Optionally, based on the allocation results of one group of services to be allocated, the resource utilization status of the processing resources of the first operating system and the resource utilization status of the processing resources of the second operating system can be combined to generate a resource mapping table of one group of services to be allocated and the processing resources of the processor, and a resource allocation result corresponding to one group of services to be allocated can be determined, but it is not limited to these methods.

[0172] In this embodiment, the allocation result of the services to be allocated in one group is used to indicate the correspondence between the services to be allocated and the operating system. The services to be executed allocated to one operating system are generally executed using the processing resources of this operating system. On the other hand, when the amount of services allocated to a certain operating system is too large and there are unallocated processing resources, unallocated processing resources may be allocated to the services to be allocated that are allocated to a certain operating system. Therefore, based on the allocation result of the services to be allocated in one group, the resource utilization status of the processing resources of the first operating system and the resource utilization status of the processing resources of the second operating system can be combined to generate a resource mapping table of the services to be allocated in one group and the processing resources of the processor, thereby being used to indicate the processing resources allocated to each service to be allocated.

[0173] Here, each service to be allocated has a mapping relationship with only one certain processor core. On the other hand, the same processor core may have a mapping relationship with multiple services to be allocated. Different services may have a mapping relationship with the same processor core by occupying different time slices of the same processor core. At the same time, the same processor core is occupied by only one service, that is, used to execute only one service. Different services allocated to one operating system may determine the time slices for occupying the same processor resource according to the allocation time, service response speed requirements or other methods.

[0174] For example, based on the output result of the service management module, the resource dynamic allocation module dynamically adjusts the processor resources, forms a resource mapping table for different services and actual hardware resources, optimizes the deployment structure of different hardware resources in the heterogeneous operating system, and achieves the purpose of improving the utilization rate of the overall system hardware resources. The above resource dynamic allocation process is managed and arranged by software in the second operating system. Taking an 8-core processor (cores 1 to 8) as an example, the processor cores scheduled in the first operating system include core 1, and the processor cores already scheduled in the second operating system include cores 2, 3, and 4. There are six services to be allocated, and the real-time services are Service 1 and Service 2, and the non-real-time services are Services 3 to 6. Allocate the processor cores corresponding to the six services, allocate core 1 to Service 1, allocate core 5 to Service 2, allocate core 2 to Service 3, allocate core 3 to Service 4, allocate core 4 to Service 5, and allocate core 6 to Service 6.

[0175] According to this embodiment, based on the correspondence between the service and the operating system, the usage status of the processing resources of different operating systems can be combined to perform dynamic allocation of the processing resources, and the rationality of the allocation of the processing resources can be ensured. Optionally, based on the resource allocation result, if it is determined that there is a corresponding service to be allocated among the unallocated processing resources of the processor's processing resources, the unallocated processing resources are allocated to the operating system to which the service to be allocated corresponding to the unallocated processing resources is allocated. Based on the operating system corresponding to each service to be allocated and the resource allocation result, the processing resources of the processor can be allocated to the first operating system and the second operating system, but it is not limited to these methods.

[0176] When allocating processing resources, for the unallocated processing resources among the processing resources of the processor, if there is a corresponding service to be allocated, that is, when unallocated processing resources are allocated to the service to be allocated, the unallocated processing resources can be allocated to the operating system to which the service to be allocated corresponding to the unallocated processing resources is allocated.

[0177] Optionally, the resource adaptive scheduling module can complete the actual scheduling operation of the processing resources of the processor based on the result of the dynamic allocation of the hardware resources. The resource adaptive scheduling module schedules some processor cores to execute the services allocated to the first operating system, for example, schedules M cores in core group 1, and schedules the remaining processor cores to run the services allocated to the second operating system, for example, schedules N cores in core group 2.

[0178] Taking the above-mentioned 8-core processor as an example, based on the service allocation result and the resource allocation result, the unallocated core 4 can be allocated to the first operating system, and the unallocated cores 5 and 6 can be allocated to the Linux system. The entire scheduling process may be mastered by the second operating system. According to this embodiment, based on the resource allocation result, the unallocated processor resources can be scheduled to the corresponding operating system, and the utilization rate of the processor resources can be improved.

[0179] In one exemplary embodiment, in one alternative embodiment, a method for inter-core communication is provided. The method includes the following steps. Step 1: The first operating system transmits target data (which may be service data) to a target virtual channel (which may be a storage space) in the memory of the processor.

[0180] Optionally, the target data is data to be transmitted, the target virtual channel is an idle storage space in the memory, and transmitting the target data by the first operating system to the target virtual channel in the memory of the processor means writing the data to be transmitted to the target virtual channel by the CPU core of the first operating system.

[0181] Step 2: The first operating system transmits an interrupt notification message (which may be the aforementioned inter-core interrupt request) to the second operating system. Optionally, the CPU core of the first operating system transmits an interrupt notification message to the CPU core of the second operating system. The interrupt notification message may include the address of the target virtual channel and is used to notify the second operating system to obtain target data from the target virtual channel. The interrupt notification message may be triggered by software or hardware.

[0182] Step 3: The second operating system responds to the interrupt notification message and obtains target data from the target virtual channel in the memory. Optionally, the CPU core of the second operating system responds to the interrupt notification message, analyzes the address of the target virtual channel from the interrupt notification message, and then locates the target virtual channel in the memory based on the analyzed address to obtain target data from the target virtual channel, thereby realizing data inclusion between the first operating system and the second operating system. When multiple operating systems running on a processor need to transmit data to each other according to the above steps, the first operating system that transmits data sends target data to a target virtual channel in the memory of the processor and sends an interrupt notification message to the second operating system. The second operating system that receives the data responds to the interrupt notification message, acquires the target data from the target virtual channel, solves the problems of high waste of resources and high dependence on the operating system in the inter-core communication process, reduces the waste of resources in the inter-core communication process, and achieves the effect of reducing the dependence on the operating system.

[0183] In one exemplary embodiment, the memory includes a data storage area and a metadata storage area. The data storage area is divided into a plurality of storage units, and each storage unit is used to store service data. The metadata storage area is used to store the size and occupied state of each storage unit in the data storage area. Optionally, the target virtual channel may be composed of one or more storage units in the data storage area. The metadata storage area may be divided into the same number of storage sheets as the number of storage units. Each storage sheet is used to record the size and occupied state of one storage unit. The size of the storage unit may be represented by the start address and end address of the storage unit, or may be represented by the start address and the length of the storage unit. The occupied state includes the occupied state and the unoccupied state, and may be represented by the numerical value of the idle mark.

[0184] In one exemplary embodiment, transmitting target data to a target virtual channel in the memory of a processor by a first operating system includes the first operating system reading a record in a metadata storage area, determining, based on the read record, at least one storage unit that is in an idle state in a data storage area and whose total space is equal to or greater than the length of the target data, obtaining a target virtual channel, setting the state of at least one storage unit corresponding to the target virtual channel in the metadata storage area to an occupied state, and storing the target data in the target virtual channel.

[0185] Note that in order to ensure that target data can be continuously written to the memory, the target virtual channel to be written to needs to be an idle memory space equal to or greater than the length of the target data. Since the memory is divided into a metadata storage area and a data storage area, the occupancy status of each storage unit recorded in the metadata storage area may be read to find a storage unit that is in an idle state and can meet the data storage requirements. For example, if the size of each storage unit is the same and the length of the target data is greater than the length of one memory space, based on the length of the target data, the number of required storage units is determined, and a plurality of consecutive storage units that are in an idle state and whose number can meet the data storage requirements are found therefrom to form a target virtual channel.

[0186] Also, for example, when the sizes of the respective memory units are the same, the data storage area has already pre - combined the memory units to obtain a plurality of virtual channels with different sizes. Each virtual channel is composed of a combination of one or more memory units. By reading the occupancy status of each virtual channel recorded in the metadata storage area, a virtual channel that is in the idle state and has a length greater than the length of the target data, that is, a target virtual channel, may be found. In addition, when the software of the system needs to apply for sharing the memory space, it is necessary to determine whether the data length to be applied for is greater than the maximum length for storing data by the virtual channel. If it is greater than the maximum length for storing data by the virtual channel, the software of the system may transmit the data to be transmitted in multiple parts, ensuring that the length of the data transmitted each time is less than or equal to the maximum length for storing data by the virtual channel, thereby ensuring smooth communication.

[0187] In one exemplary embodiment, for the second operating system to obtain target data from the target virtual channel in the memory by responding to the interrupt notification message, the second operating system reads the records in the metadata storage area and determines the target virtual channel based on the read records, and obtains the target data from at least one memory unit corresponding to the target virtual channel and sets the state of the at least one memory unit to the idle state.

[0188] That is, after the second operating system extracts the target data from the memory unit corresponding to the target virtual channel, in order to prevent other systems or tasks from being affected when using the target virtual channel, the state of the memory unit corresponding to the target virtual channel is set to the idle state. In one exemplary embodiment, for the first operating system to send target data to a target virtual channel in the memory of a processor, the driver layer of the first operating system receives the target data, determines a virtual channel that is in an idle state in the memory, obtains the target virtual channel, sets the state of the target virtual channel to an occupied state, and stores the target data in the target virtual channel.

[0189] Optionally, both a real-time operating system and a non-real-time operating system have a driver layer. After the driver layer receives target data to be sent, it calls an interface to search for a target virtual channel in the memory and, after finding the target virtual channel, sets the state of the target virtual channel to an occupied state and writes the target data to the target virtual channel in order to avoid other systems using the target virtual channel in the process of writing data.

[0190] In one exemplary embodiment, if the first operating system includes an application layer, a human-machine interaction interface is installed in the application layer. Before the driver layer of the first operating system determines a virtual channel that is in an idle state in the memory, the application layer of the first operating system may receive data to be sent input by the user through the human-machine interaction interface, package the data to be sent using a preset format to obtain target data, call a data writing function to transmit the target data to the driver layer through a preset communication interface, where the preset communication interface is installed in the driver layer.

[0191] Optionally, the application layer supplements the data to be sent according to a preset format, obtains the target data, and generates one device file ipidev in the / dev route of the system. When the application layer needs to read and write data from the driver layer, first, it opens the device file / dev / ipidev using the system-owned open function, and then uses the system-owned write function to send the target data from the application layer to the driver layer. The driver layer further stores the data in the target virtual channel in the shared memory and may trigger an interrupt to notify the second operating system to read the data.

[0192] In one exemplary embodiment, for the second operating system to obtain the target data from the target virtual channel in the memory in response to the interrupt notification message includes that the second operating system triggers an interrupt processing function based on the interrupt notification message, the interrupt processing function determines the target virtual channel from the memory, and obtains the target data from the target virtual channel.

[0193] In one exemplary embodiment, for the interrupt processing function to determine the target virtual channel from the memory and obtain the target data from the target virtual channel includes that the interrupt processing function calls the target task, the target task determines the target virtual channel from the memory, and obtains the target data from the target virtual channel. Optionally, the interrupt processing function sends a task notification to wake up the target task responsible for data extraction. The target task first searches for the target virtual channel in the shared memory by calling the interface, and then reads the target data from the target virtual channel for data analysis.

[0194] In one exemplary embodiment, when the application layer is included in the second operating system, storing a function identifier in the memory, where the function identifier indicates a target function, determining a target virtual channel from the memory by an interrupt processing function, and obtaining target data from the target virtual channel is to determine the function identifier and the target virtual channel from the memory by the interrupt processing function and send the address information of the target virtual channel to a target application program that matches the function flag, where the target application program is the target application program in the application layer, and the target application program calls a data reading function and transmits the address information to the driver layer via a preset communication interface, where the driver layer obtains the target data from the target virtual channel and transmits the target data to the target application layer program, where the preset communication interface is installed in the driver layer, and the target application program includes processing the target data based on a processing function that matches the function identifier to execute the target function.

[0195] Optionally, after the second application system receives an interrupt notification message, the application layer calls the corresponding interrupt processing function to search for the target virtual channel from the memory, obtain the address information of the target virtual channel, and generate a device file ipidev in the / dev route of the system. When the application layer needs to read and write data from the driver layer, it first opens the device file / dev / ipidev using the system-owned open function, and then can read the target data in the target virtual channel using the system-owned read function. That is, the driver layer finds the corresponding target data in the shared memory based on the address information of the target virtual channel and returns the target data and the length of the target data to the application layer. In one exemplary embodiment, the state of the target virtual channel is set to idle.

[0196] Note that different application programs in the application layer may use the target data to implement different functions. A function identifier is stored in the memory. The function identifier indicates the target function implemented by the application program using the target data. Optionally, the function identifier may be Net or Cmd. At the initialization of the system, Net, Cmd, and the application program PID are registered with the driver. The driver layer can find the PID of the application program based on the received NetFn and Cmd and send the data to the corresponding application program based on the PID.

[0197] For example, when NetFn = 1 and Cmd = 1, it means that the first operating system and the second operating system send "hello word" to each other. At the start of the system, one array is initialized. The array has a total of three columns. The first column is NetFn, the second column is Cmd, and in the third column, the processing function corresponding to NetFn and Cmd is xxCmdHandler. For example, when the second operating system receives a message sent from the first operating system, it obtains NetFn and Cmd from the message. If it determines that NetFn = 1 and Cmd = 1, it executes the processing function HelloCmdHandler corresponding to "helloword" to complete the corresponding function.

[0198] In one exemplary embodiment, a plurality of memory channels are included in a data storage area. Each memory channel is composed of one or more storage units. A plurality of records are stored in a metadata storage area. Each record is used to record the metadata of one memory channel. The metadata of each memory channel includes at least the channel ID of the memory channel, the size of the memory channel, and the occupied state of the memory channel. Reading a record in the metadata storage area by the first operating system and determining at least one storage unit that is in an idle state in the data storage area and whose total space is greater than or equal to the length of the target data based on the read record to obtain a target virtual channel is to traverse the records stored in the metadata storage area to determine whether there is a first target record indicating that the memory channel is in an idle state and the size of the memory channel is greater than or equal to the length of the target data. If the first target record exists, the memory channel indicated by the channel ID recorded in the first target record is determined as the target virtual channel.

[0199] Note that the data storage area may be divided into n virtual memory channels, and the sizes of the respective memory channels may be different. That is, the sizes of the n virtual memory channels are, in order, 20*m, 21*m, 22*m, 23*m …… 2n-1*m. Here, m is the size of one storage unit, and the following structure is used as metadata to manage the memory channels.

[0200] typedef struct { uint32_t Flag; uint16_t ChannelId; uint8_t SrcId; uint8_t NetFn; uint8_t Cmd; uint32_t Len; uint32_t ChannelSize; uint8_t *pData; uint8_t CheckSum; }IpiHeader_T

[0201] Here, uint32_t Flag represents the state of the memory channel. For example, 0xA5A5A5A5 indicates that this channel is non-empty, otherwise it is empty. uint16_t ChannelId represents the channel ID, uint8_t SrcId represents the source CPU ID, where the source CPU means the CPU that writes data to the memory channel. uint8_t NetFn and uint8_t Cmd are function parameters, uint32_t Len is the length of the data stored in the memory channel, uint32_t ChannelSize represents the size of the memory channel, uint8_t *pData means the starting address of the memory channel, and uint8_t CheckSum means the checksum. When the first operating system needs to send data, the check value of the data to be sent is calculated by the check and algorithm, and the check value is sent to the second operating system. When the second operating system receives the data and the check value, the check value is calculated by the same check and algorithm based on the received data, and the calculated check value is compared with the received check value. If they match, it means the received data is valid; if not, it means the received data is invalid. Each virtual memory channel corresponds to one structure record, and these structure records are sequentially stored at the start position of the shared memory in a way that the channel ID increments. After the system is powered on, these structure records are initialized. An initialization Flag of 0 indicates that this channel is empty. The initialized ChannelId is sequentially 0, 1, 2... n - 1, the initialized ChannelSize is the size of the corresponding virtual memory channel, and the initialized pData points to the starting address of the corresponding virtual memory channel.

[0202] In one exemplary embodiment, when the first operating system determines a target virtual channel, based on the size of the target data to be transmitted, it searches for a virtual channel that satisfies two conditions from all of the memory channels using the interface GetEmptyChannel: that the idle flag Flag in the channel structure IpiHeader is not equal to 0xA5A5A5A5 (i.e., the channel is in an idle state), and that the channel size ChannelSize in the channel structure IpiHeader is greater than or equal to the size of the target data (i.e., the memory size can satisfy the storage requirement of the target data). After finding a target virtual channel that satisfies the above conditions, it sets the state of this channel to non-empty, i.e., sets the idle flag Flag in the channel structure IpiHeader to 0xA5A5A5A5, and then copies the target data to the target virtual channel.

[0203] In one exemplary embodiment, when a memory channel is occupied, the metadata of the memory channel further includes the ID of the source CPU core of the target data and the ID of the destination CPU core of the target data. Determining a target virtual channel by the second operating system by reading the record in the metadata storage area and based on the read record involves traversing the records stored in the metadata storage area to determine whether there is a second target record. Here, the second target record indicates that the memory channel is in an occupied state, the ID of the destination CPU core is the ID of the CPU core of the second operating system, and the ID of the source CPU core is not the ID of the CPU core of the second operating system. When the second target record exists, it includes determining the memory channel indicated by the channel ID recorded in the second target record as the target virtual channel.

[0204] That is, the target virtual channel is a virtual channel that satisfies the following three conditions among all channels. These three conditions are that the idle flag Flag in the channel structure IpiHeader is equal to 0xA5A5A5A5 (i.e., it indicates that the channel is in an occupied state), the TargetId in the channel structure is equal to the current CPU's ID (i.e., it indicates that the destination CPU of the target data is the CPU of the second operating system), and the TargetId in the channel structure is not equal to the SrcId (i.e., it indicates that the target data is not sent by the CPU of the second operating system).

[0205] Note that when representing the idle flag Flag with 1 bit, 0 represents that the channel is empty, 1 represents that the channel is non-empty. If Flag was originally 0 and suddenly mutates to 1, after the system reads Flag, the channel will be considered non-empty, causing communication anomalies. In contrast, in this embodiment, the idle flag Flag is set to a multi-bit special character, for example, 0xA5A5A5A5. The probability that multiple bits mutate to special characters simultaneously is much smaller than the probability of 1-bit mutation, which can prevent the mutation of memory media bits from affecting the value of Flag and improve the security of communication.

[0206] In one exemplary embodiment, a state mapping table is stored in the metadata storage area. There are a plurality of records in the state mapping table, and each record is used to record the occupied state of one storage unit. The first operating system reads the records in the metadata storage area, and based on the read records, determines at least one storage unit that is in an idle state in the data storage area and whose total space is equal to or greater than the length of the target data, and obtaining a target virtual channel includes determining a preset number of storage units that the target data attempts to occupy, sequentially scanning each record from the initial position of the state mapping table, and when a preset number of consecutive target records are scanned, determining consecutive storage units indicated by the preset number of target records, where the target records indicate that the storage unit is in an idle state, and determining the consecutive storage units as the target virtual channel.

[0207] Note that when the operating system transmits service data for easy storage and extraction of data, it is necessary to occupy consecutive storage units in the memory. Therefore, first, it is necessary to determine the number of storage units in the memory application command. Since the memory space of each storage unit is the same, based on the required memory space size, the preset number of consecutive storage units required can be calculated, denoted as numb.

[0208] Optionally, the first operating system traverses the records from the index position in the state mapping table, where the index position may be the starting position of the state mapping table. Starting from the starting position of the state mapping table, each record in the state mapping table is sequentially searched to determine whether there is a record that continuously records that the idle memory pages are equal to or greater than numb. If there is a record that meets the above conditions, based on the correspondence between the record and the memory page, a continuous storage unit in the processor is determined, and this continuous storage unit is determined as the target virtual channel, and data is written to the target virtual channel.

[0209] In one exemplary embodiment, the interrupt notification message includes the starting address of the continuous storage unit and a preset number. Determining the target virtual channel based on the record read by the second operating system from the record in the metadata storage area includes sequentially scanning each record from the initial position of the state mapping table, and when scanning that the starting address of the continuous storage unit is recorded, determining the storage unit indicated by the scanned address and the continuous storage unit obtained by subtracting one from the preset number as the target virtual channel.

[0210] Optionally, the continuous storage unit means a continuous storage unit whose number is equal to numb. Each record in the state mapping table further records the starting address of the corresponding storage unit. When the second operating system scans the record of the starting address of the continuous storage unit whose number is equal to numb in the mapping table, it indicates that the starting address of the target virtual channel has been scanned. The storage unit indicated by the starting address and the numb - 1 continuous storage units after this storage unit constitute the target virtual channel. The second operating system completes data inclusion with the first operating system by acquiring data from the target virtual channel.

[0211] In one exemplary embodiment, in a process of recording target records scanned by a counter and sequentially scanning each record from an initial position of a state mapping table according to the number of memory units, when the current target record is scanned, control is performed to add 1 to the counter, and when the current non-target record is scanned, control is performed to clear the counter.

[0212] Optionally, using the magnitude relationship between the numerical value of the counter and the number of required memory units, determine whether there are a continuous, preset number of target records, that is, determine whether there are a continuous, preset number of memory units. Optionally, let the count value of the counter be cntr. When one scanned memory unit is empty, perform an operation of adding 1 to cntr. When the scanned memory unit is non-empty, clear the accumulated number cntr of consecutive memory units in the idle state, and continue to search for consecutive memory units in the idle state starting from the next address after this memory unit. When cntr is equal to numb, it means that consecutive memory units in the idle state that meet the memory requirement have been found. After scanning the entire state mapping table, if there is no case where cntr is greater than or equal to numb, it means that the current dynamic memory application has failed and there are no consecutive memory units of the preset number.

[0213] In one exemplary embodiment, by a first operating system, records in a metadata storage area are read, and based on the read records, at least one storage unit in an idle state in a data storage area and having a total space equal to or greater than the length of target data is determined. Before obtaining a target virtual channel, the method further includes transmitting a memory application command by the first operating system and performing a locking operation on the memory of the processor, where the memory application command is used to apply for using the memory of the processor, and when the locking of the memory is successful, further includes reading records in a state mapping table.

[0214] Optionally, the memory application command is a command issued by an operating system running on the processor to apply for using the memory of the processor. When multiple operating systems simultaneously apply for using the memory of the processor, in order to prevent application conflicts, when the operating system transmits a memory application command, first, a locking operation is performed on the memory of the processor, and after the locking is successful, the application for using the memory can be made. The locking operation means an exclusive operation for applying for the memory. After the current operating system successfully locks, if the lock has not been released, other servers do not have the right to apply for using the memory of the processor.

[0215] In one exemplary embodiment, performing a lock operation on the memory of a processor involves determining whether the memory is currently in a locked state, where the locked state indicates that the memory has been claimed for use. If the memory is not currently in a locked state, a lock operation is performed on the memory. If the memory is currently in a locked state, it is determined that the lock on the memory has failed, and the lock on the processor's memory is re-claimed after a preset time duration until the lock on the memory is successful or the number of lock requests exceeds a preset number.

[0216] Before running the processor, it is necessary to perform an initialization operation on the metadata storage area and the data storage area in the processor. Optionally, the records stored in the status mapping table in the metadata storage area are initialized, and the memory management information is initialized. Before performing a memory claim operation, the memory management information is arranged as follows. typedef struct { uint32_t MemReady; uint32_t MemLock; }MallocMemInfo_T;

[0217] Here, the member variable MemLock of the structure MallocMemInfo_T indicates whether the shared memory has been initialized. When the variable MemReady is 0xA5A5A5A5, it indicates that the initialization operation has been completed and the memory can be normally claimed and released dynamically. The member variable MemReady of the structure MallocMemInfo_T indicates whether it is locked.

[0218] Optionally, when it reads that the variable MemLock is 0, it means that there is no system or task applying for memory at this time, that is, the memory is not currently locked. When it reads that the variable MemLock is 0xA5A5A5A5, it means that there is a system or task applying for memory, and it needs to apply again after this application is completed, indicating that the current application for lock has failed. In one exemplary embodiment, when there is a situation where a lock operation on the memory fails, after waiting for a preset time period until the lock is successful, the application for locking the memory is made again. For example, the preset time period may be 100 microseconds.

[0219] In one exemplary embodiment, if the application for lock fails and the number of repeated applications exceeds a preset number, it means that the memory in the current time period of the processor is in an unallocatable state, and the application operation is stopped. For example, the preset number may be 3. If the number of applications for lock is greater than 3, the operating system that sends the application may return a message indicating that the current memory is unavailable.

[0220] Optionally, after there is a target virtual channel that can be used by the first operating system in the memory space of the processor, the first operating system stores the target data to be transmitted in the corresponding target virtual channel. In one exemplary embodiment, based on the data writing status of the first operating system, the occupancy status of the memory space of the processor is updated, that is, it is changed from a state where the target continuous memory space is not occupied to a state where it is occupied, and the lock on the memory is released so that other systems or tasks can apply for the memory.

[0221] In one exemplary embodiment, this method further includes releasing the lock on the memory when a continuous preset number of target records have not been scanned. Optionally, after scanning the records in the state mapping table, if a preset number of consecutive idle memory units have not been detected, there is not enough free space memory page in the processor's memory for the first operating system to use, the current memory dynamic application fails, and the lock on the memory is released.

[0222] In one exemplary embodiment, an interrupt notification message is sent to the second operating system in the form of a software interrupt. Optionally, sending an interrupt notification message to the second operating system in the form of a software interrupt writes an interrupt number and the ID of the CPU core of the second operating system to a preset register of the processor, and generates an interrupt notification message based on the interrupt number and the ID of the CPU core of the second operating system.

[0223] Optionally, a software interrupt is an interrupt generated by software, and the software may send an interrupt to the CPU core that executes itself or to another CPU core. The preset register may be the GICD_SGIR register. The software writes an SGI (Software Generated Interrupts) interrupt number and a destination CPU ID to the GICD_SGIR register to generate one software interrupt. The SGI interrupt number is the software interrupt number reserved for inter-core communication. In a multi-core heterogeneous operating system, in order to best support the current resource allocation method, numbers 8 to 15 (a total of 8 interrupts) are used to represent the inter-core interrupt vector table. If the first operating system is a RTOS operating system and the second operating system is a Linux operating system, one possible allocation scheme for the vector table is shown in Table 1.

[0224]

Table 1

[0225] Optionally, a hardware interrupt means an interrupt generated by a hardware device, which may be a private external device interrupt or a shared external device interrupt. Note that a hard interrupt is an interrupt introduced by hardware outside the CPU, which has randomness, and a soft interrupt is an interrupt introduced by executing an interrupt command by software running on the CPU, which is preset. This embodiment does not limit the method of generating an interrupt notification message.

[0226] In one alternative embodiment, a method of sharing memory is provided. This method includes the following steps. Step 1: Receive a memory application command and perform a lock operation on the memory of the processor, where the memory application command is used to apply to use the memory of the processor.

[0227] Optionally, the memory application command is a command issued by an operating system running on the processor to apply to use the memory of the processor, which may be sent by a first operating system. Note that when multiple operating systems simultaneously apply to use the memory of the processor, in order to prevent application conflicts, when the operating system sends a memory application command, first perform a lock operation on the memory of the processor, and after successfully locking, it can apply to use the memory. The lock operation means an exclusive operation for memory application. After successfully locking by the current operating system, if the lock has not been released, other servers do not have the right to apply to use the memory of the processor.

[0228] In the method of sharing memory according to an embodiment of the present application, before performing a lock operation on the memory of a processor, the method is to determine whether the memory is currently in a locked state, where the locked state indicates that the memory is in a state of being claimed for use, and further includes performing a lock operation on the memory if the memory is not currently in a locked state.

[0229] Optionally, when multiple systems or multiple tasks simultaneously claim to use the memory, a conflict in the claims occurs. Since the memory of the processor can be locked by only one system or task within the same time period, if it is detected that the memory is not currently in a locked state, the current operating system can perform a lock operation on the memory.

[0230] Optionally, by determining whether a preset variable stored in the memory is a preset value, it is determined whether the memory is in a locked state. If the preset variable is not a preset parameter, it indicates that the memory is not in a locked state, there is no other system or task claiming the memory space, and the lock is successful; otherwise, if the preset variable is a preset parameter, the memory is in a locked state at the current time, and there is a system or task claiming the memory space other than this operating system, and the lock fails.

[0231] In this method of sharing memory, after determining whether the memory is currently in a locked state, if the memory is currently in a locked state, it is determined that the lock on the memory fails, and if the lock on the memory fails, the lock on the memory of the processor is re-claimed after a preset time period until the lock on the memory is successful or the number of lock claims exceeds a preset number of times. Optionally, when there is a situation where a lock operation on the memory fails, after waiting for a preset time length until the lock is successful, a lock on the memory is applied again. For example, the preset time length may be 100 microseconds.

[0232] In one exemplary embodiment, if the application for the lock fails and the number of repeated applications exceeds a preset number of times, it indicates that the memory in the current time length processor is in an unallocatable state, and the application operation is stopped. For example, the preset number of times may be 3 times. If the number of lock applications is greater than 3 times, the operating system that sends the application may return a message indicating that the current memory is unavailable. Step 2: If the lock on the memory is successful, read the occupied state of the memory, and based on the read occupied state of the memory, determine whether there is a target memory space available in the memory, where the size of the target memory space is greater than or equal to the size of the memory applied by the memory application command.

[0233] After the application for the lock is successful, the operating system applies for the memory in the processor, and optionally, scans for information for recording the occupied state of the memory based on the memory application command issued by the operating system, and determines whether there is a target memory space, that is, determines whether there is a memory space in the processor that is in an unoccupied state and continuous and can satisfy the memory usage requirement. Satisfying the memory usage requirement means that the size of the memory space is greater than or equal to the size of the memory applied by the operating system. In one exemplary embodiment, determine whether the size of the unoccupied and continuous memory space is greater than or equal to the size of the memory applied by the operating system, and obtain the determination result.

[0234] Note that when applying for memory, discontinuous memory spaces may be used. Add one pointer after one non-minimal memory block to point to the smallest memory block obtained by the next application. At the same time, when reading and writing data, reading and writing across data blocks of data are realized by the storage address and the pointer. This embodiment does not limit the form of the target memory space.

[0235] Step 3: If there is a target memory space in the memory, feedback the address information of the target memory space to the sending end of the memory application command, update the occupied state of the memory, and release the lock on the memory. Here, the sending end means the operating system (for example, the first operating system) that sends the memory application command. When the operating system communicates between cores, shared memory is used to send and receive data. Therefore, in the process of sending and receiving data, it is necessary to determine the address information of the already applied memory space in order to access the data by the address returned by the applied memory.

[0236] Optionally, after there is a target memory space available for the operating system in the memory space of the processor (which may be instructed by the foregoing judgment result), send the address information of this target continuous space to this operating system, and the operating system stores the data that needs to be transmitted in the corresponding memory space based on the address information.

[0237] In one exemplary embodiment, based on the writing status of data by the operating system, update the occupied state of the memory space of the processor, that is, change from the state where the target memory space is not occupied to the occupied state, and release the lock operation before dynamically applying for the memory, so that other operating systems can apply to use the memory space of the processor.

[0238] By the above steps, it is possible to solve the problems that the utilization efficiency of the shared memory among multiple cores is low, the flexibility is poor, and it depends too much on the operating system, and achieve the effects of improving the flexibility and utilization rate of the shared memory and reducing the dependence on the operating system. In this method of sharing the memory, the memory includes a metadata storage area for storing a state mapping table for storing the occupied state of the data storage area and a data storage area for storing service data. Reading the occupied state of the memory and determining whether there is a target memory space available in the memory based on the occupied state of the memory includes reading the record in the state mapping table from the metadata storage area and determining whether there is a target memory space in the data storage area based on the record in the state mapping table.

[0239] Search for the occupied state of the memory by searching the records in the state mapping table. Optionally, obtain the metadata storage area stored in the processor, identify the state mapping table in the metadata storage area, and traverse the records in the state mapping table to read the occupied state of the data storage area and determine whether there is a continuous memory space in the data storage area that is in the idle state and meets the memory usage requirements.

[0240] In the method of sharing memory according to an embodiment of the present application, the data storage area is composed of a plurality of memory pages, the state mapping table includes a plurality of records, each record is used to record the occupied state of one memory page, reading a record in the state mapping table from the metadata storage area, and determining whether there is a target memory space in the data storage area based on the read record in the state mapping table includes determining the preset number of memory pages applied by the memory application command, sequentially scanning each record from the initial position of the state mapping table, and when scanning a continuous preset number of target records, determining that there is a target memory space in the memory, where the target record includes indicating that the memory page is in an idle state.

[0241] Note that the data storage area is divided into a plurality of allocation units according to the same memory size, and each allocation unit is regarded as one memory page. For example, if the memory space of the data storage area is A bytes and the allocated unit to be divided is B bytes, this data storage area includes a total of A / B memory pages. The records in the state mapping table are memory page records. Each memory page record is used to record the occupied state of one memory page. The number of memory page records in the state mapping table and the number of memory pages in the data storage area are the same.

[0242] FIG. 9 is a schematic diagram of the relationship between a state mapping table and a memory page in a method for sharing a memory according to an embodiment of the present application. As shown in FIG. 9, a data storage area is a dynamic allocation memory block area, and a metadata storage area includes a dynamic allocation memory mapping table area. Here, the mapping table area divides the same number of records according to the number of memory pages divided by the data storage area, and sets this record as a memory page record. All of the memory page records are combined as a state mapping table. All memory page records in the state mapping table and all memory pages in the data storage area have a one-to-one correspondence. Each memory page record represents the allocation state of the corresponding memory page, that is, whether the memory page is occupied or not.

[0243] Optionally, since service data coordinated by the operating system needs to occupy consecutive memory pages in the processor, first, it is necessary to determine the preset number of memory pages in the memory application command. Since the memory space of each memory page is the same, based on the required memory space size, the preset number of required consecutive memory pages can be calculated and denoted as numb.

[0244] In one exemplary embodiment, after obtaining the state mapping table in the metadata storage area of the processor, traverse the memory page records from the index position in the state mapping table. The index position may be the start position of the state mapping table. Starting from the start position of the state mapping table, sequentially search each memory page record in the state mapping table to determine whether there is a memory page record that continuously records that the idle memory pages are numb or more. If there is a memory page record that meets the above conditions, based on the correspondence between the memory page record and the memory page, it is determined that there is a target memory space in the processor.

[0245] In the method of sharing memory according to an embodiment of the present application, after sequentially scanning each record from the initial position of the state mapping table, the method scans all the records in the state mapping table, and further includes determining that there is no target memory space in the memory if there are no consecutive target records with a preset number.

[0246] Optionally, starting from the start position of the state mapping table, search for the memory page records of the state mapping table to determine whether there is a consecutive space with the number of memory pages being numb or more. After scanning all of the state mapping table, if no consecutive preset number of idle memory pages are found, it indicates that there is no target memory space.

[0247] In the method of sharing memory according to an embodiment of the present application, record the number of target records scanned by a counter. In the process of sequentially scanning each record from the initial position of the state mapping table, when the current target record is scanned, control the counter to add 1, and when the current non-target record is scanned, control the counter to be cleared, where the non-target record indicates that the memory page is in an occupied state.

[0248] Optionally, based on the magnitude relationship between the value of the counter and the required number of memory pages, determine whether there are consecutive target records of a preset number, that is, whether there is a target memory space. Optionally, let the count of the counter be cntr. When one scanned memory page is empty, perform an operation of adding 1 to cntr. When the scanned memory page is non-empty, clear the accumulated number cntr of consecutive memory pages in the idle state, and continue to search for consecutive memory pages in the idle state starting from the address of the next memory page after this memory page. When cntr is equal to numb, it means that consecutive memory pages in the idle state that satisfy the memory demand have been found. In the process of scanning the entire state mapping table, if cntr is smaller than numb, it means that the current dynamic memory application fails, indicating that there is no target memory space.

[0249] In the method of sharing memory according to the embodiment of the present application, when the initial position is the last position in the state mapping table, feeding back the address information of the target memory space to the sending end of the memory application command includes determining the last scanned target record in the consecutive preset number of target records, and feeding back the start address of the memory page indicated by the last scanned target record to the sending end.

[0250] Optionally, when scanning the state mapping table, as a scanning method, it can be selected to scan from the first position of the state mapping table or from the last position of the state mapping table. When the scanning method is to scan from the last position of the state mapping table, if the value cntr displayed on the counter is greater than or equal to the preset number numb, set the start address of the memory page corresponding to the last scanned memory page record as non-empty in the memory page record, and set the start address as the start address of the entire consecutive memory pages of the current memory application command.

[0251] In one exemplary embodiment, this address is fed back to an operating system that issues a memory application command, and the operating system performs a data writing operation on the memory based on the address information. In the method for sharing a memory according to an embodiment of the present application, the initial position is the first position in the state mapping table, and feeding back the address information of the target memory space to the sending end of the memory application command includes determining the first scanned target record in a continuous preset number of target records, and feeding back the start address of the memory page indicated by the first scanned target record to the sending end.

[0252] Optionally, when the scanning method is to scan from the first position of the state mapping table, if the numerical value cntr displayed on the counter is greater than or equal to a preset number numb, the address of the first scanned memory page record is used as the start address, and a memory application command is sent to an operating system that issues the memory application command, and the operating system performs a data writing operation on the memory based on the address information.

[0253] In the method for sharing a memory according to an embodiment of the present application, in the process of sequentially scanning each record from the initial position of the state mapping table, the first target record in the scanned continuous target records is stored by a preset variable. Optionally, the preset variable means a variable for storing the address information of the initial position in the state mapping table, and it is set as offset. Each time a continuous free memory page is scanned, the numerical value cntr displayed on the counter is incremented by 1. When the numerical value cntr displayed on the counter is greater than or equal to a preset number numb, the currently stored address information in offset is set as the address of the first target record.

[0254] In the method of sharing memory according to an embodiment of the present application, after reading the occupied state of the memory and determining whether there is an available target memory space in the memory based on the occupied state of the memory, if this method determines that there is no available target memory space in the memory, it further includes releasing the lock on the memory.

[0255] Optionally, scan the memory page records in the status mapping table. If it is detected that a preset number of consecutive memory pages are not available, that is, no target memory space is included, it means that there is not enough free memory pages used by the operating system in the processor's memory, the current dynamic application for memory fails, and the lock on the memory is released.

[0256] In the method of sharing memory according to an embodiment of the present application, the memory includes a metadata storage area for storing memory management information and a data storage area for storing service data. Determining whether the memory is currently locked is to read the memory management information stored in the metadata storage area and determine whether the preset information is included in the memory management information. Here, the preset information indicates that the memory is in a locked state. When the preset information is included in the memory management information, it is determined that the memory is not currently locked. When the preset information is not included in the memory management information, it is determined that the memory is currently locked.

[0257] When determining whether the memory of the processor is in a locked state, it is necessary to make the determination using the memory management information in the metadata storage area. Optionally, when obtaining the memory management information in the metadata storage area, it is determined whether the memory management information includes preset information. Here, the preset information is used to indicate whether the memory is in a locked state. If the memory management information does not include the preset information, it indicates that the memory is currently not in a locked state; otherwise, it indicates that the memory is in a locked state.

[0258] In the method for sharing memory according to the embodiment of the present application, the memory management information includes first field information and second field information. The first field information is used to describe whether the memory is in a locked state, and the second field is used to describe whether the memory has been initialized. Before receiving the memory application command, this method further includes initializing the first field information and the second field information stored in the data storage area.

[0259] Before running the embedded system, it is necessary to perform an initialization operation on the metadata storage area and the data storage area in the processor. Optionally, initialize the memory page record stored in the state mapping table in the metadata storage area and perform an initialization operation on the memory management information. Optionally, the memory management information consists of first field information and second field information. The first field information indicates whether it is locked, and the second field information indicates whether it has been initialized.

[0260] In the method for sharing memory according to the embodiment of the present application, updating the occupied state of the memory means changing the state of the memory page corresponding to the target memory space recorded in the state mapping table to the occupied state. Optionally, when the operating system needs to occupy the target memory space, by identifying the address information of multiple memory pages in the target memory space, based on the correspondence between the memory pages and the memory page records, update the memory page records in the state mapping table area of the metadata storage area, and change the state from unoccupied to occupied. Further, based on the data writing status by the operating system, update the occupancy status of the memory space of the processor, that is, change the state of the target memory space from unoccupied to occupied, and release the lock operation before dynamically applying for memory.

[0261] Optionally, in response to the storage operation of the first operating system, store the target data in the target memory space, and send the address information of the continuous memory space to the second operating system, receive the acquisition command sent by the second operating system based on the address information, and send the target data stored in the target memory space to the second operating system.

[0262] Here, after successfully applying for memory, the first operating system stores the target data to be transmitted in the applied target memory space, and sends the address information of this target memory space to the second operating system that cooperates with the first operating system, and notifies the second operating system to acquire the data. Optionally, after the second operating system receives the address information of the target memory space, issue a data acquisition command, and the embedded system receives this command and sends the target data stored in the target memory space to the second operating system.

[0263] By the above steps, receive the memory application command of the first operating system, and execute a lock operation on the memory of the processor. Here, the memory application command is used to apply for using the memory of the processor. If the lock on the memory is successful, read the occupied state of the memory, and based on the occupied state of the memory, determine whether there is a target memory space available in the memory. Here, the size of the target memory space is equal to or greater than the size of the memory applied for by the memory application command. If there is a target memory space in the memory, feedback the address information of the target memory space to the sending end of the memory application command, update the occupied state of the memory, release the lock on the memory, in response to the storage operation of the first operating system, store the target data in the target memory space, send the address information of the continuous memory space to the second operating system, receive the acquisition command sent by the second operating system based on the address information, and send the target data stored in the target memory space to the second operating system, solving the problems that the utilization efficiency of the shared memory between multiple cores is low, the flexibility is poor, and it depends too much on the operating system, improving the flexibility and utilization efficiency of the shared memory, and achieving the effect of reducing the dependence on the operating system.

[0264] In one exemplary embodiment, when the first operating system performs read and write operations on data using physical addresses and the second operating system performs read and write operations on data using virtual addresses, the second operating system converts the address information of the target memory space into virtual addresses, accesses the memory using the virtual addresses, and reads the target data from the target memory space.

[0265] When core - to - core communication sends and receives data using shared memory, it uses the address returned by the dynamically allocated memory. However, the address systems used by different systems may be different. For example, a real - time operating system is the first operating system, and a non - real - time operating system is the second operating system. When a real - time operating system directly accesses shared memory using a physical address and a non - real - time operating system cannot directly access shared memory using a physical address, it is necessary to use a mapped virtual address. After the second operating system receives the address information of the target memory space, it is converted by the address information offset and mapped to a virtual address, and operations are performed based on the virtual address. Optionally, in a non - real - time operating system, a memory virtual base address vBase (assuming the true physical address of the shared memory is 0x96000000) is shared, and in a real - time operating system, a memory physical base address pBase (i.e., 0x96000000) is shared.

[0266] In a non-real-time operating system, the address returned by the dynamically allocated memory is also the virtual address vData. In the non-real-time operating system, Offset = vData - vBase, and the data is sent from the non-real-time operating system to the real-time operating system. The real-time operating system uses the address pData to access the dynamically allocated shared memory pData = pBase + Offset. In the real-time operating system, the address returned by the dynamically allocated memory is the physical address pData. In the real-time operating system, Offset = pData - pBase, and the data is sent from the real-time operating system to the non-real-time operating system. The non-real-time operating system uses the address vData to access the dynamically allocated shared memory vData = vBase + Offset.

[0267] In one exemplary embodiment, the memory includes a metadata storage area and a data storage area. Since the metadata storage area and the data storage area are the same as those in the foregoing embodiments, they will not be described further here. Optionally, obtain the metadata storage area stored in the processor, identify the state mapping table in the metadata storage area, traverse each memory page record from the index position in the state mapping table, sequentially search each memory page record in the state mapping table, and determine whether there is a memory page record that continuously records that the number of idle memory pages is greater than or equal to a preset number. If there is a memory page record that meets the above conditions, based on the correspondence between the memory page record and the memory page, determine that there is a target memory space in the processor, and based on the correspondence between the memory page record and the memory page, determine that there is a target memory space in the processor.

[0268] In this embodiment, a method for sharing memory is further provided. Before the operating system issues a memory application command, in order to prevent an application collision caused by multiple operating systems simultaneously applying for the memory space of the processor, it is necessary to apply for a lock operation and determine whether the lock is successful. When the determination result indicates that the lock on the dynamically applied memory is successful, based on the memory size in the issued memory application command, calculate the number of pages of consecutive memory pages that need to be allocated, denoted as nmemb. When the determination result indicates that the application for the lock fails, after waiting for a certain period of time (which may be 100 microseconds), issue the application again until the application is successful. If the number of times of failing to apply for the lock is greater than a preset number of times (the preset number of times may be 3), log out from the memory application.

[0269] In one exemplary embodiment, after successfully applying for a lock, an initialization operation is performed on the metadata storage area of the processor. The last position of the state mapping table is set as offset. Based on the required memory space size in the memory application command, the number of required continuous memory pages is calculated, and the number of memory pages is denoted as nmemb. A counter for recording the number of memory pages is set up and denoted as cmemb. Then, the state mapping table in the metadata storage area of the processor is obtained, and the entire state mapping table is scanned starting from the offset position of the state mapping table. Based on the correspondence between the memory page records stored in the state mapping table and the memory pages in the data storage area, continuous free memory pages are searched for. If the currently scanned memory page is occupied, then offset = offset - cmemb, and the data cmemb of the continuous free memory pages accumulated in the counter is cleared, and continuous free memory pages are searched for again starting from the new offset position. If the scanned memory page is empty, that is, in the idle state, 1 is added to the numerical value cmemb of the counter, and offset = offset - 1, and the next memory page is continuously judged. When cmemb is equal to nmemb, that is, when the counter data is equal to the required memory space size, it indicates that continuous memory pages that meet the requirements have been scanned.

[0270] In one exemplary embodiment, in the corresponding state mapping table, the memory pages that meet the requirements are marked as occupied. The start address of the last found memory page is used as the start address of the entire dynamically allocated continuous memory pages. The lock for dynamically allocating memory is released, and this time the dynamic memory allocation is successful. In the process of scanning the entire state mapping table, if the value of offset is less than 0, it indicates that there are no memory pages that meet the requirements used by the operating system. The lock for dynamically allocating memory is released, and this time the dynamic memory allocation fails.

[0271] Also, if it is found that the space is not sufficient after dynamically applying for the space, the size may be dynamically adjusted, the updated memory application command may be issued again, and a lock operation may be executed on the memory. If the lock is successful, when the memory space to be applied for by the updated memory application command becomes larger, it is necessary to determine whether there is the required memory space after the already applied target continuous memory. If it exists, the application is successful. When the memory space to be applied for by the updated memory application command becomes smaller, some memory space is released.

[0272] In this embodiment, by dividing a plurality of storage areas, using the index position, dynamically applying based on the actually required space size, releasing after use, and dynamically adjusting the size if it is found that the space is not sufficient after dynamically applying for the space, the flexibility and usage efficiency of the shared memory can be improved. From the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments may be implemented by adding a general-purpose hardware platform required for software, and of course, it may also be implemented by hardware. In many cases, the former is a more preferred embodiment. Based on such an understanding, the technical solution of this application may be embodied in the form of a software product in essence or in the part that contributes to the prior art. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a plurality of commands for causing a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods of the embodiments of this application.

[0273] According to another aspect of the embodiments of this application, an embedded system for implementing the startup control method of the above embedded system is further provided. FIG. 10 is a schematic diagram of an alternative embedded system according to the embodiments of this application. The above embedded system includes It may include a chip and at least two operating systems, where the chip includes a processor 1002, a hardware controller 1004, a first bus 1006, and a second bus 1008, where the bandwidth of the second bus 1008 is higher than that of the first bus 1006, and the second bus 1008 is arranged in a multi-master multi-slave mode, and the first bus 1006 is arranged in a one-master multi-slave mode, at least two operating systems operate based on the processor 1002, where the processing resources of the processor are dynamically allocated to at least two operating systems, and the processing resources of the processor include processor cores, at least two operating systems communicate via the first bus 1006, at least two operating systems realize control over the hardware controller via the second bus 1008.

[0274] Here, the above chip may be the aforementioned BMC chip, the above processor may be the aforementioned multi-core processor, the above hardware controller may be used to control external devices connected to the corresponding external interface, the above first bus is arranged in a one-master multi-slave mode and may be a bus used by the processor to control between hardware controllers, such as APB, the above second bus is arranged in a multi-master multi-slave mode and may be a bus used for communication between multiple processor cores of the processor, such as AHB, and the bandwidth of the second bus is higher than that of the first bus.

[0275] The embedded system may include at least two operating systems, the at least two operating systems run based on a processor, the processing resources of the processor are dynamically allocated to the at least two operating systems, the processing resources of the processor include processor cores, the at least two operating systems realize control over a hardware controller via a first bus, and the at least two operating systems communicate via a second bus.

[0276] Optionally, at least two operating systems may be used to implement the startup control method of the above-mentioned embedded system. For example, the first operating system and the second operating system among at least two operating systems may be used to implement the startup control method of the above-mentioned embedded system. Optionally, the hardware controller may include one or more, including but not limited to I2C, USB (Universal Serial Bus), UART, ADC (Analog to Digital Converter), JTAG (Joint Test Action Group), RTC (Real_Time Clock), GPIO (General Purpose Input / Output), WDT (Watch Dog Timer), Virtual UART, Super I / O, Serial General Purpose Input / Output (SGPIO), Pulse Width Modulation (PWM), FanTach (fan rotation speed meter), Timer, PECI (Platform Environment Control Interface), and MailBox. The external interface may include one or more, and may include, but is not limited to, the external interface corresponding to any one of the above controllers.

[0277] For example, one example of a BMC chip is shown in FIG. 11. The hardware of the BMC chip may include, but is not limited to, an SOC sub-module and a BMC out-of-band sub-module. Here, the SOC sub-module mainly includes ARM cores (ARM Core 1, ARM Core 2,..., ARM Core X), which may include, but are not limited to, a DDR (Double Data Rate) 4 controller (memory controller), a MAC (Media Access Control Address) controller (network controller), an SD (Secure Digital) / eMMC (Embedded Multi Media Card) controller (storage controller), a PCIe RC (Root Complex) controller, an SRAM (Static Random-Access Memory), and an SPI controller.

[0278] The above cores and each controller are connected to each other via a second bus to realize the interaction between the cores and each controller. At the same time, the ARM cores are connected to the second bus (for example, they may be connected via an AXI bridge), and the communication between the cores is realized by the second bus. In addition, the connection / communication between the second bus and the first bus in the SOC sub-module is further realized (for example, it is realized by the conversion of an APB bridge). In this way, a physical path is provided for the access of the SOC sub-module to external devices on the first bus.

[0279] The DDR4 controller may be connected to other components or devices via a DDR4 PHY (Physical Layer) interface. The MAC controller may be connected to other components or devices via an RGMII (Reduced Gigabit Media Independent Interface). The SD card / eMMC controller may be connected to other components or devices via an SD interface. The PCIe RC controller may be connected to other components or devices via a PCIe PHY interface.

[0280] The BMC out-of-band sub-module mainly includes controllers for external devices of the chip such as PWM, GPIO, FanTech (fan tachometer), mailbox, etc. Through these controllers, out-of-band management functions such as PECI communication with the BMC (for example, simulating PECI using GPIO) and fan cooperative control can be realized. As can be seen from Figure 11, this BMC out-of-band sub-module may, but is not limited to, realize inclusion with the SOC sub-module via a second bus.

[0281] The BMC chip realizes the interconnection among the on-chip ARM core, memory unit, and controller hardware resources via the first and second buses. The dynamic equalization scheduling of processor resources mainly relates to the ARM core resource scheduling of the BMC chip, and the inter-core communication means the communication conducted between ARM cores. Taking the example of the Linux system preempting the RTOS system core, the Linux system first sends an inter-core interrupt (interrupt number 9) to core 1 via the on-chip second bus on a core with cores 2 to N. At this time, if the RTOS system is in an idle state and allows preemption, core 1 returns an inter-core interrupt (interrupt number 10) via the second bus, releases the external device controller resources (such as PWM / PECI) currently mapped by core 1. When the Linux system receives the inter-core interrupt 10, it issues a preemption flow, adds core 1 to the Linux SMP scheduling, acquires the control right of the PWM / PECI external device, and can control it via the first bus.

[0282] According to one aspect, at least two operating systems include a first operating system and a second operating system. Here, the chip loads a communication value onto the second bus, and the second bus transmits a communication signal including the communication value to a communication register corresponding to the second operating system, thereby realizing communication between the first operating system and the second operating system. Here, the communication value is used to indicate the communication content between the first operating system and the second operating system.

[0283] On the other hand, the chip loads a control value onto the first bus, and the first bus transmits a control signal including the control value to a register corresponding to the hardware controller, thereby realizing the control of the operating system over the hardware controller. Here, the control value is used to indicate the content of the control of the operating system over the hardware controller.

[0284] The operating system controls the hardware controller by accessing (for example, performing read and write operations) the registers of each hardware controller. The way the operating system accesses the registers of the hardware controller may be to read or write the addresses of the registers of each hardware controller, but it is not limited to these methods. The addresses of these registers may be unique and definite at the time of chip design, but are not limited to them. For example, the operating system can realize a specific function (for example, the communication function between the operating systems or the control function of the operating system for the hardware controller) by writing a specific value (that is, the above communication value or control value) to a specific address (that is, the above communication register or the register corresponding to the hardware controller). That is, different functions correspond to different control values, and the correspondence between the functions of the hardware controller and the control values is maintained in the chip. For example, the control value 00 represents accelerating the air conditioner by one stage, and the control value 01 represents decelerating the air conditioner by one stage.

[0285] Among each operating system and between the operating system and the hardware controller, interactions such as communication and control may be performed via a bus, but are not limited to them. The read / write operations of the registers of each hardware controller of the above operating system are finally converted into control signals for this hardware controller on the first bus (or the second bus). These conversion operations and the control process of the first bus (or the second bus) for the hardware controller may be automatically realized by the internal hardware of the chip, but are not limited to them. The realization process follows the bus specification. Here, in the operation process of the first bus (or the second bus), physical signals related to the bus protocol can be transmitted and controlled, and valid data can also be transmitted to each hardware controller through the physical data channel.

[0286] According to another aspect of the embodiment of the present application, there is further provided a startup control device for an embedded system for implementing the startup control method of the embedded system. FIG. 12 is a structural block diagram of a selective embedded system startup control device according to an embodiment of the present application. As shown in FIG. 12, the device includes a first control unit 1202 for controlling the operating state of the target device by controlling the hardware controller of the target device via a first bus by a first operating system running on a first processor core of the processor, where the embedded system includes the first control unit 1202 including the first operating system, and a startup unit 1204 connected to the first control unit 1202 for guiding the startup of a second operating system on a second processor core of the processor, where the embedded system further includes the second operating system, the response speed of the first operating system is higher than that of the second operating system, the first operating system and the second operating system communicate via a second bus, and the bandwidth of the second bus is higher than that of the first bus startup unit 1204, and a first execution unit 1206 connected to the startup unit 1204 for taking over the control right of the target device by taking over the hardware controller via the first bus by the second operating system after the second operating system is started.

[0287] It should be noted that the first control unit 1202 in this embodiment may be used to execute step S202, the startup unit 1204 in this embodiment may be used to execute step S204, and the first execution unit 1206 in this embodiment may be used to execute step S206.

[0288] By the above module, the first operating system running on the first processor core of the processor controls the hardware controller of the target device via the first bus, thereby controlling the operating state of the target device. Here, the embedded system includes the first operating system, guides the start of the second operating system on the second processor core of the processor. Here, the embedded system further includes the second operating system. The response speed of the first operating system is higher than that of the second operating system. The first operating system and the second operating system communicate via the second bus, and the bandwidth of the second bus is higher than that of the first bus. After the second operating system is started, the second operating system takes over the hardware controller via the first bus, thereby taking over the control right of the target device, solving the problem that the cost of the device is high because an additional chip needs to be added in the startup control method of the operating system in the related art, saving the hardware cost, and improving the expandability of the device control.

[0289] In one exemplary embodiment, the first control unit is a first execution module for executing a first control task of the first operating system on the first processor core, where the first control task is a first execution module used to control the hardware controller, and a reading module for reading sensor data of a predetermined sensor corresponding to the target device by the first processor core, and a first transmission module for transmitting a device control command to the hardware controller via the first bus based on the sensor data of the predetermined sensor by the first control task, so that the hardware controller controls the operating state of the target device based on the device control command.

[0290] In one exemplary embodiment, the first transmission module a first determination sub-module for determining a target parameter value of a device operation parameter of a target device based on sensor data of a predetermined sensor by a first control task, where the device operation parameter is a parameter for controlling the operation state of the target device and a transmission sub-module for transmitting a device control command including the target parameter value to a hardware controller via a first bus by a first control task.

[0291] In one exemplary embodiment, the first determination sub-module includes a determination sub-unit for determining a target parameter value of a fan operation parameter of a fan based on sensor data of a predetermined sensor by a first control task when the target device is a fan.

[0292] In one exemplary embodiment, the determination sub-unit is a determination second sub-unit for determining a target rotation speed value of a rotation speed of a fan based on sensor data of a temperature sensor by a first control task when the target device is a fan and the predetermined sensor is a temperature sensor, where the rotation speed of the fan has a positive correlation with the temperature detected by the temperature sensor.

[0293] In one exemplary embodiment, the first execution unit is a second transmission module for transmitting a first inter-core interrupt to a first operating system via a second bus by a second operating system, where the first inter-core interrupt is used to request the second operating system to take over a hardware controller. When receiving a second inter-core interrupt for instructing to agree to take over the hardware controller by a second operating system, which is sent back in response to the first inter-core interrupt by the first operating system, a control module for controlling the hardware controller via a first bus by a second control task of the second operating system, where the second control task includes the control module used to control the hardware controller.

[0294] In one exemplary embodiment, the apparatus is A second control unit for controlling, after sending the first inter-core interrupt to the first operating system via a second bus by the second operating system, and in response to the acquired first inter-core interrupt, to put the third control task of the first operating system to sleep, where the third control task includes the second control unit used to control the hardware controller, and When the third control task has already slept, further includes a first transmission unit for sending a second inter-core interrupt to the second operating system via the second bus by the first operating system.

[0295] In one exemplary embodiment, the apparatus is A second execution unit for pushing the system operation data of the first operating system onto the stack when the third control task has already slept, where the second inter-core interrupt further includes the second execution unit used to instruct the second operating system to take over the first processor core.

[0296] In one exemplary embodiment, the apparatus is Before the first operating system running on the first processor core of the processor controls the hardware controller of the target device via the first bus, after the chip where the processor is located is powered on, a wake-up unit for waking up the first processor core by the processor, and It further includes an operating unit for guiding the first operating system to start on the first processor core by running the bootloader program of the first operating system by the first processor core.

[0297] In one exemplary embodiment, the startup unit A second execution module for waking up the second processor core by the second program loader by running the second program loader by the first processor core, and It includes an operating module for guiding the second operating system to start on the first processor core by running the general-purpose bootloader of the second operating system by the second processor core.

[0298] In one exemplary embodiment, the above device When the second operating system attempts to restart the second operating system after taking over the hardware controller via the first bus, the second operating system wakes up the first operating system via the second bus, and the first operating system takes over the hardware controller via the first bus, so as to take over the control right of the target device. A third execution unit for It further includes a third control unit for controlling the second operating system to restart the system.

[0299] In one exemplary embodiment, the third execution unit When attempting to restart the second operating system, the second operating system includes a transmission module for transmitting a system wake-up interrupt to the first operating system via the second bus to wake up the first operating system.

[0300] In one exemplary embodiment, the apparatus is a first allocation unit for allocating a group of services to be allocated to the corresponding operating system among the first operating system and the second operating system according to a resource dynamic allocation rule, where the resource dynamic allocation rule includes performing resource dynamic allocation based on at least one of service response speed, service resource occupancy rate, service coupling degree, and service importance a first determination unit for determining a resource allocation result corresponding to a group of services to be allocated, where the resource allocation result is used to indicate the processing resources corresponding to each service to be allocated among a group of services to be allocated in the processing resources of the processor, and the processing resources of the processor include processor cores and further includes a second allocation unit for allocating the processing resources of the processor to the first operating system and the second operating system based on the operating system corresponding to each service to be allocated and the resource allocation result.

[0301] In one exemplary embodiment, the first allocation unit is A first allocation module for allocating services to be allocated in a group of services, where the service response speed requirement of the service to be allocated is equal to or higher than a set response speed threshold, to a first operating system, and allocating services to be allocated in a group of services, where the service response speed requirement of the service to be allocated is lower than the set response speed threshold, to a second operating system, A second allocation module for allocating services to be allocated in a group of services, where the service resource occupancy rate of the service to be allocated is lower than a first occupancy threshold, to a first operating system, and allocating services to be allocated in a group of services, where the traffic resource occupancy rate of the service to be allocated is equal to or higher than the first occupancy threshold, to a second operating system, A third allocation module for allocating services to be allocated in a group of services that contain sensitive information to a target operating system, where the target operating system includes at least one of the first operating system and the second operating system, which is the operating system with a lower interaction frequency with the user.

[0302] In one exemplary embodiment, the first allocation unit includes at least one of a fourth allocation module for allocating services to be allocated in a group of services, where the service coupling degree with the services already allocated to the first operating system is equal to or higher than a first coupling threshold, to the first operating system, and a fifth allocation module for allocating services to be allocated in a group of services, where the service coupling degree with the services already allocated to the second operating system is equal to or higher than a second coupling threshold, to the second operating system.

[0303] In one exemplary embodiment, the first determination unit includes a generation module for generating a resource mapping table between a group of services to be assigned and the processing resources of the processor, by associating the resource utilization status of the processing resources of the first operating system and the resource utilization status of the processing resources of the second operating system, based on the assignment results of the group of services to be assigned.

[0304] In one exemplary embodiment, the second assignment unit includes a sixth assignment module for assigning unassigned processing resources among the processing resources of the processor to the operating system to which the corresponding service to be assigned is assigned, when it is determined that there is a corresponding service to be assigned to the unassigned processing resources based on the resource assignment results.

[0305] In one exemplary embodiment, the apparatus further includes a second transmission unit for transmitting target data to a target virtual channel in the memory of the processor by the first operating system, a third transmission unit for transmitting an interrupt notification message to the second operating system, and an acquisition unit for acquiring target data from the target virtual channel in the memory when the second operating system responds to the interrupt notification message.

[0306] In one exemplary embodiment, the memory includes a data storage area and a metadata storage area. The data storage area is divided into a plurality of storage units, each storage unit is used for storing service data, and the metadata storage area is used for storing the size and occupied state of each storage unit in the data storage area.

[0307] In one exemplary embodiment, the second transmission unit reads the records in the metadata storage area by the first operating system, determines at least one storage unit that is in an idle state in the data storage area and whose total space is equal to or greater than the length of the target data based on the read records, and a third execution module for obtaining a target virtual channel, and includes a fourth execution module for setting the state of at least one storage unit corresponding to the target virtual channel in the metadata storage area to an occupied state and storing the target data in the target virtual channel.

[0308] In one exemplary embodiment, the acquisition unit reads the records in the metadata storage area by the second operating system, and a fifth execution module for determining a target virtual channel based on the read records, and includes a sixth execution module for acquiring the target data from at least one storage unit corresponding to the target virtual channel and setting the state of the at least one storage unit to an idle state.

[0309] In one exemplary embodiment, the data storage area includes a plurality of memory channels, each memory channel is composed of one or more storage units, the metadata storage area stores a plurality of records, each record is used to record the metadata of one memory channel, and the metadata of each memory channel includes at least the channel ID of the memory channel, the size of the memory channel, and the occupied state of the memory channel. The third execution module traverses the records stored in the metadata storage area to determine whether there is a first target record indicating that the memory channel is in an idle state and the size of the memory channel is equal to or greater than the length of the target data, and a first traversal sub-module, When there is a first target record, it includes a second determination sub-module for determining, as a target virtual channel, a memory channel indicated by a channel ID recorded in the first target record.

[0310] In one exemplary embodiment, when a memory channel is occupied, the metadata of the memory channel further includes the ID of the source CPU core of the target data and the ID of the destination CPU core of the target data, and the fifth execution module is a second traversal sub-module for traversing records stored in a metadata storage area to determine whether there is a second target record, where the second target record indicates that the memory channel is in an occupied state, and the ID of the destination CPU core is the ID of the CPU core of the second operating system, and the ID of the source CPU core is not the ID of the CPU core of the second operating system. When there is a second target record, it includes a third determination sub-module for determining, as a target virtual channel, a memory channel indicated by a channel ID recorded in the second target record.

[0311] In one exemplary embodiment, the apparatus is a fourth execution unit for receiving a memory application command of a first operating system and performing a locking operation on the memory of the processor, where the memory application command is used to apply to use the memory of the processor. When the lock on the memory is successful, it is a fifth execution unit for reading the occupied state of the memory and determining, based on the occupied state of the memory, whether there is an available target memory space in the memory, where the size of the target memory space is equal to or greater than the size of the memory applied for by the memory application command. If there is a target memory space in the memory, it further includes a feedback unit that feeds back the address information of the target memory space to the first operating system and updates the occupied state of the memory.

[0312] In one exemplary embodiment, the memory includes a metadata storage area in which a state mapping table for storing the occupied state of the data storage area is stored, and a data storage area for storing service data. The fifth execution unit includes a seventh execution module that reads a record in the state mapping table from the metadata storage area and determines whether there is a target memory space in the data storage area based on the record in the state mapping table.

[0313] In one exemplary embodiment, the apparatus includes a determination unit for determining whether the memory is currently in a locked state before performing a lock operation on the memory of the processor. Here, the locked state represents a state in which the memory is claimed to be in use. and, when the memory is not currently in a locked state, further includes a sixth execution unit for performing a lock operation on the memory.

[0314] In one exemplary embodiment, the apparatus reads the occupied state of the memory, and based on the occupied state of the memory, after determining whether there is an empty target memory space in the memory, if there is no empty target memory space in the memory, it further includes a release unit for releasing the lock on the memory.

[0315] Note that each of the above modules may be implemented by software or hardware. When implemented by hardware, each of the above modules may be located in the same processor or may be implemented in such a way that each of the above modules is located in different processors in any combination, but not limited thereto. The embodiments of the present application further provide a chip including at least one of a programmable logic circuit and executable commands. This chip is run on an electronic device to implement the steps in the embodiments of any one of the above methods.

[0316] The embodiments of the present application further provide a BMC chip including a storage unit for storing a program and a processing unit connected to the storage unit for running this program to execute the steps in the embodiments of any one of the above methods. The embodiments of the present application further provide a main board including at least one processor and at least one storage unit for storing at least one program. When the at least one program is executed by the at least one processor, the at least one processor is caused to implement the steps in the embodiments of any one of the above methods.

[0317] The embodiments of the present application further provide a server including a processor, a communication interface, a storage unit, and a communication bus. Here, the processor, the communication interface, and the storage unit realize communication with each other via the communication bus. The storage unit is used for storing a computer program. When the processor executes the program stored in the storage unit, the steps in the embodiments of any one of the above methods are implemented, achieving the same technical effect.

[0318] The communication bus of the above server may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. This communication bus may be divided into an address bus, a data bus, a control bus, etc. The communication interface is used for communication between the above server and other devices.

[0319] The storage unit may include a RAM and may also include an NVM (Non-Volatile Memory), for example, at least one magnetic disk storage unit. Optionally, the storage unit may be at least one storage device located at a position away from the aforementioned processor. The above processor may be a general-purpose processor, including a CPU, an NP (Network Processor), etc., and may be a DSP (Digital Signal Processing), an ASIC, an FPGA or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.

[0320] Embodiments of the present application further provide a computer-readable storage medium storing a computer program configured to execute the steps in the embodiments of any one of the above methods when running. In one exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media capable of storing a computer program, such as a USB memory, a ROM, a RAM, a removable hard disk, a magnetic disk or an optical disk.

[0321] Embodiments of the present application further provide an electronic device including a storage unit and a processor, where a computer program is stored in the storage unit, and the processor is configured to execute the steps in the embodiments of any one of the above methods by running the computer program.

[0322] In one exemplary embodiment, the electronic device may include a transmission device and an input / output device, where the transmission device is connected to the processor, and the input / output device is connected to the processor. Specific examples in this embodiment can refer to the examples described in the above embodiments and exemplary embodiments, and this embodiment will not be further described here.

[0323] As can be clearly understood by those skilled in the art, each module or each step of the present application above may be implemented by a general-purpose computing device. They may be integrated into a single computing device, or distributed across a network consisting of multiple computing devices. They may also be implemented by program code executable by a computing device, and thereby stored in a storage device and executed by a computing device. In some cases, the steps may be performed in an order different from the order shown or described herein, or they may be manufactured into each integrated circuit module, or multiple modules or steps therein may be manufactured into a single integrated circuit module. Thus, the present application is not limited to any specific combination of hardware and software.

[0324] The above are only alternative embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and changes. All modifications, equivalent replacements, improvements, etc. made without departing from the principle of the present application shall be included within the protection scope of the present application.

Claims

1. A method for starting control of an embedded system, comprising: controlling a hardware controller of a target device via a first bus by a first operating system running on a first processor core of a processor, so as to control an operating state of the target device, where the embedded system includes the first operating system; guiding to start a second operating system on a second processor core of the processor, where the embedded system further includes the second operating system, a response speed of the first operating system is higher than that of the second operating system, the first operating system and the second operating system communicate via a second bus, and a bandwidth of the second bus is higher than that of the first bus; after the second operating system is started, the second operating system takes over the hardware controller via the first bus, so as to take over the control right of the target device.

2. The act of controlling a hardware controller of a target device via a first bus by a first operating system running on a first processor core of a processor as described in claim 1 comprises: executing a first control task of the first operating system on the first processor core, where the first control task is used to control the hardware controller; reading sensor data of a predetermined sensor corresponding to the target device by the first processor core; sending a device control command to the hardware controller via the first bus based on the sensor data of the predetermined sensor by the first control task, so that the hardware controller controls the operating state of the target device based on the device control command.

3. The fact that the first control task transmits a device control command to the hardware controller via the first bus based on sensor data of the predetermined sensor is the first control task determines a target parameter value of a device operation parameter of the target device based on sensor data of the predetermined sensor, where the device operation parameter is a parameter for controlling an operation state of the target device, and the first control task includes transmitting the device control command including the target parameter value to the hardware controller via the first bus. The method according to claim 2 is characterized by the above.

4. The fact that the first control task determines a target parameter value of a device operation parameter of the target device based on sensor data of the predetermined sensor is when the target device is a fan, the first control task includes determining a target parameter value of a fan operation parameter of the fan based on sensor data of the predetermined sensor. The method according to claim 3 is characterized by the above.

5. When the target device is a fan, the fact that the first control task determines a target parameter value of a fan operation parameter of the fan based on sensor data of the predetermined sensor is when the target device is a fan and the predetermined sensor is a temperature sensor, the first control task determines a target rotation speed value of the rotation speed of the fan based on sensor data of the temperature sensor, where the rotation speed of the fan has a positive correlation with the temperature detected by the temperature sensor. The method according to claim 4 is characterized by the above.

6. The fact that the second operating system takes over the hardware controller via the first bus is the second operating system transmits a first inter-core interrupt to the first operating system via the second bus, where the first inter-core interrupt is used to request the second operating system to take over the hardware controller. When receiving a second inter-core interrupt for instructing to agree to take over the hardware controller by the second operating system from the first operating system that has been returned in response to the first inter-core interrupt, controlling the hardware controller via the first bus by a second control task of the second operating system, where the second control task is used to control the hardware controller, the method according to claim 1, characterized by including this.

7. After the second operating system transmits a first inter-core interrupt to the first operating system via the second bus, the method is Controlling to put the third control task of the first operating system to sleep in response to the obtained first inter-core interrupt, where the third control task is used to control the hardware controller When the third control task has already slept, further including transmitting the second inter-core interrupt to the second operating system via the second bus by the first operating system, the method according to claim 6, characterized by including this.

8. When the third control task has already slept, pushing the system operation data of the first operating system onto the stack, where the second inter-core interrupt further includes being used to instruct the second operating system to take over the first processor core, the method according to claim 7, characterized by including this.

9. Before the first operating system running on the first processor core of the processor controls the hardware controller of the target device via the first bus, the method is After the chip where the processor is located is powered on, waking up the first processor core by the processor Guiding the first operating system to start on the first processor core by running the bootloader program of the first operating system by the first processor core, further comprising, the method according to claim 1, characterized in that.

10. Guiding the second operating system to start on the second processor core of the processor, this Waking up the second processor core by the second program loader by running the second program loader by the first processor core, and Guiding the second operating system to start on the first processor core by running the general-purpose bootloader of the second operating system by the second processor core, including, the method according to claim 1, characterized in that.

11. After the second operating system takes over the hardware controller via the first bus, the method When attempting to restart the second operating system, the second operating system wakes up the first operating system via the second bus, and the first operating system takes over the hardware controller via the first bus, thereby taking over the control right of the target device, and Controlling the second operating system to restart the system, further comprising, the method according to claim 1, characterized in that.

12. When attempting to restart the second operating system, waking up the first operating system via the second bus by the second operating system, this When attempting to restart the second operating system, sending a system wake-up interrupt to the first operating system via the second bus by the second operating system to wake up the first operating system, including, the method according to claim 11, characterized in that.

13. Allocating the services to be assigned in one group to the corresponding operating system among the first operating system and the second operating system according to the resource dynamic allocation rule, where the resource dynamic allocation rule includes performing resource dynamic allocation based on at least one of service response speed, service resource occupancy rate, service coupling degree, and service importance. Determining a resource allocation result corresponding to the services to be assigned in the one group, where the resource allocation result is used to indicate the processing resources corresponding to each service to be assigned among the services to be assigned in the one group among the processing resources of the processor, and the processing resources of the processor include processor cores. Further including allocating the processing resources of the processor to the first operating system and the second operating system based on the operating system corresponding to each service to be assigned and the resource allocation result. The method according to any one of claims 1 to 12 is characterized by the above.

14. The above-mentioned allocating the services to be assigned in one group to the corresponding operating system in the embedded system according to the resource dynamic allocation rule is Allocating the services to be assigned in the one group whose service response speed requirement is greater than or equal to the set response speed threshold to the first operating system, and allocating the services to be assigned in the one group whose service response speed requirement is less than the set response speed threshold to the second operating system. Allocating the services to be assigned in the one group whose service resource occupancy rate is less than the first occupancy threshold to the first operating system, and allocating the services to be assigned in the one group whose service resource occupancy rate is greater than or equal to the first occupancy threshold to the second operating system. Assigning the service to be assigned in the one group that includes sensitive information among the services to be assigned to the target operating system, where the target operating system includes at least one of the first operating system and the second operating system, which is the operating system with a low interaction frequency with the user. The method according to claim 13, characterized in that.

15. According to the resource dynamic allocation rule, the above-mentioned assigning the services to be assigned in one group to the corresponding operating system in the embedded system is Assigning the service to be assigned in the one group that has a service coupling degree of not less than a first coupling degree threshold with the already assigned services of the first operating system among the services to be assigned in the one group to the first operating system, Assigning the service to be assigned in the one group that has a service coupling degree of not less than a second coupling degree threshold with the already assigned services of the second operating system among the services to be assigned in the one group to the second operating system. The method according to claim 13, characterized in that it includes at least one of the above.

16. The above-mentioned determining the resource allocation result corresponding to the service to be assigned in the one group is Based on the allocation result of the service to be assigned in the one group, combining the resource utilization status of the processing resources of the first operating system and the resource utilization status of the processing resources of the second operating system, and generating a resource mapping table of the service to be assigned in the one group and the processing resources of the processor. The method according to claim 13, characterized in that it includes this.

17. Based on the operating system corresponding to each service to be assigned and the resource allocation result, the above-mentioned allocating the processing resources of the processor to the first operating system and the second operating system is Based on the resource allocation result, when it is determined that there is a corresponding service to be allocated among the unallocated processing resources of the processing resources of the processor, allocating the unallocated processing resources to an operating system to which the service to be allocated corresponding to the unallocated processing resources is allocated, the method according to claim 13, characterized in that.

18. The method is transmitting, by the first operating system, target data to a target virtual channel in the memory of the processor; transmitting an interrupt notification message to the second operating system; and further comprising: obtaining, by the second operating system in response to the interrupt notification message, the target data from the target virtual channel in the memory, the method according to any one of claims 1 to 12, characterized in that.

19. The memory includes a data storage area and a metadata storage area. The data storage area is divided into a plurality of storage units, each storage unit is used to store service data, and the metadata storage area is used to store the size and occupied state of each storage unit in the data storage area, the method according to claim 18, characterized in that.

20. The transmitting, by the first operating system, target data to a target virtual channel in the memory of the processor includes: reading a record in the metadata storage area by the first operating system, determining, based on the read record, at least one storage unit that is in an idle state in the data storage area and whose total space is not less than the length of the target data, and obtaining the target virtual channel; setting the state of at least one storage unit corresponding to the target virtual channel in the metadata storage area to an occupied state, and storing the target data in the target virtual channel, the method according to claim 19, characterized in that.

21. By the second operating system responding to the interrupt notification message, obtaining the target data from the target virtual channel in the memory, the by the second operating system, reading a record in the metadata storage area and determining the target virtual channel based on the read record; obtaining the target data from at least one storage unit corresponding to the target virtual channel and setting the state of the at least one storage unit to an idle state, the method according to claim 20, characterized in that.

22. The data storage area includes a plurality of memory channels, each memory channel is composed of one or more storage units, the metadata storage area stores a plurality of records, each record is used to record the metadata of one memory channel, and the metadata of each memory channel includes at least the channel ID of the memory channel, the size of the memory channel, and the occupied state of the memory channel. By the first operating system reading a record in the metadata storage area and based on the read record, determining at least one storage unit in an idle state in the data storage area and having a total space greater than or equal to the length of the target data, and obtaining the target virtual channel, the traversing the records stored in the metadata storage area to determine whether there is a first target record indicating that the memory channel is in an idle state and the size of the memory channel is greater than or equal to the length of the target data; when the first target record exists, determining the memory channel indicated by the channel ID recorded in the first target record as the target virtual channel, the method according to claim 21, characterized in that.

23. When a memory channel is occupied, the metadata of the memory channel further includes the ID of the original CPU core of the target data and the ID of the destination CPU core of the target data. Reading the record in the metadata storage area by the second operating system and determining the target virtual channel based on the read record is traversing the records stored in the metadata storage area to determine whether a second target record exists, where the second target record indicates that the memory channel is in an occupied state, and the ID of the destination CPU core is the ID of the CPU core of the second operating system, and the ID of the original CPU core is not the ID of the CPU core of the second operating system When the second target record exists, determining the memory channel indicated by the channel ID recorded in the second target record as the target virtual channel. The method according to claim 22, characterized by comprising: **Claim 24** Receiving the memory application command of the first operating system and performing a lock operation on the memory of the processor, where the memory application command is used to apply to use the memory of the processor When the lock on the memory is successful, reading the occupied state of the memory and determining whether there is a target memory space available in the memory based on the occupied state of the memory, where the size of the target memory space is not less than the size of the memory applied for by the memory application command When there is the target memory space in the memory, further comprising feeding back the address information of the target memory space to the first operating system and updating the occupied state of the memory. The method according to any one of claims 1 to 12, characterized by comprising: **Claim 25** The memory includes a metadata storage area in which a state mapping table for storing the occupied state of the data storage area is stored, and a data storage area for storing service data. Reading the occupied state of the memory and determining whether there is a target memory space available in the memory based on the occupied state of the memory, comprises reading a record in the state mapping table from the metadata storage area and determining whether the target memory space exists in the data storage area based on the record in the state mapping table. The method according to claim 24, wherein: **Claim 26** Before performing a lock operation on the memory of the processor, the method further comprises: determining whether the memory is currently in a locked state, where the locked state indicates that the memory is in a state requested to be used; if the memory is not currently in a locked state, performing a lock operation on the memory. The method according to claim 24, wherein: **Claim 27** After reading the occupied state of the memory and determining whether there is a target memory space available in the memory based on the occupied state of the memory, the method further comprises: if there is no available target memory space in the memory, further releasing the lock on the memory. The method according to claim 24, wherein: **Claim 28** comprising a chip and at least two operating systems, wherein the chip includes a processor, a hardware controller, a first bus, and a second bus, where the bandwidth of the second bus is higher than that of the first bus, and the second bus is arranged in a multi-master multi-slave mode, and the first bus is arranged in a one-master multi-slave mode, the at least two operating systems are run based on the processor, where the processing resources of the processor are dynamically allocated to the at least two operating systems, and the processing resources of the processor include processor cores. The at least two operating systems communicate via the second bus, the at least two operating systems realize control over the hardware controller via the first bus, the at least two operating systems are used to realize the steps of the method according to any one of claims 1 to 27, and an embedded system characterized in that.

29. A first control unit for controlling the operating state of a target device by controlling a hardware controller of the target device via a first bus by a first operating system running on a first processor core of a processor, wherein the embedded system includes the first control unit including the first operating system, A startup unit for guiding the startup of a second operating system on a second processor core of the processor, wherein the embedded system further includes the second operating system, the response speed of the first operating system is higher than that of the second operating system, the first operating system and the second operating system communicate via a second bus, and the bandwidth of the second bus is higher than that of the first bus startup unit, After starting the second operating system, a first execution unit for taking over the control right of the target device by taking over the hardware controller via the first bus by the second operating system, and an embedded system startup control device characterized in that.

30. Including at least one of a programmable logic circuit and executable commands, and running on an electronic device to realize the method according to any one of claims 1 to 27, and a chip characterized in that.

31. A storage unit for storing a program, and a processing unit for running the program so as to execute the method according to any one of claims 1 to 27, connected to the storage unit, and a BMC chip characterized in that.

32. including at least one processor; including at least one storage unit for storing at least one program When the at least one program is executed by the at least one processor, the at least one processor realizes the method according to any one of claims 1 to 27. A main board characterized by this.

33. A server including a processor, a communication interface, a storage unit, and a communication bus, where the processor, the communication interface, and the storage unit realize communication with each other via the communication bus. The storage unit is used to store a computer program. When the processor executes the program stored in the storage unit, it is used to realize the method according to any one of claims 1 to 27. A server characterized by this.

34. A computer-readable storage medium, characterized in that when executed by a processor, it stores a computer program that realizes the steps of the method according to any one of claims 1 to 26.

35. Including a storage unit, a processor, and a computer program stored in the storage unit and capable of being run by the processor. When the processor executes the computer program, it realizes the steps of the method according to any one of claims 1 to 27. An electronic device characterized by this.

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