Display substrate and display device

Abstract

A display substrate and a display device are provided. The display substrate includes a display area and a peripheral area. The display substrate includes a plurality of sub-pixels located on a base substrate, and at least a part of the sub-pixels located in the display area includes a light-emitting element and a pixel circuit. The light-emitting element includes a light-emitting functional layer, and a first electrode and a second electrode located on both sides of the light-emitting functional layer in a direction perpendicular to the base substrate. The first electrode is located between the light-emitting functional layer and the base substrate. The pixel circuit includes a driving transistor and a light-emitting control transistor. The first electrode of the light-emitting element is electrically connected to the light-emitting control transistor. The display substrate further includes a bonding area located in the peripheral area and on the first side of the display area. In the same pixel circuit, the channel area of the light-emitting control transistor is located on the side away from the bonding area of the channel area of the driving transistor. In the embodiments of the present disclosure, by designing the pixel circuit located in the display area, it contributes to reducing the lower frame of the display device by fully utilizing the pixel space.

Description

Technical Field

[0001] At least one embodiment of the present disclosure relates to a display substrate and a display device.

Background Art

[0002] Currently, the active matrix organic light emitting diode (AMOLED) flexible screen technology is becoming increasingly mature, with characteristics such as flexibility, high contrast, and low power consumption, and has great development prospects. With the continuous development of display technology, optimization of the display effect is inevitable. In order to improve the uniformity of display devices, a two-layer source and drain metal layer structure is adopted in some display products.

Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a display substrate and a display device.

[0004] An embodiment of the present disclosure provides a display substrate including a display area and a peripheral area located on at least one side of the display area. The display substrate includes a base substrate and a plurality of sub-pixels located on the base substrate. At least a part of the sub-pixels located in the display area includes a light-emitting element and a pixel circuit. The light-emitting element includes a light-emitting functional layer, and a first electrode and a second electrode located on both sides of the light-emitting functional layer in a direction perpendicular to the base substrate. The first electrode is located between the light-emitting functional layer and the base substrate. The pixel circuit includes a driving transistor and a light-emitting control transistor. The first electrode of the light-emitting element is electrically connected to the light-emitting control transistor. The display substrate further includes a plurality of sub-pixels and a bonding area located in the peripheral area and on a first side of the display area. The pixel circuit includes an active semiconductor pattern including a channel region, a source region, and a drain region of each transistor. In the same pixel circuit, the channel region of the light-emitting control transistor is located on a side away from the bonding area of the channel region of the driving transistor.

[0005] For example, according to an embodiment of the present disclosure, in the sub-pixel closest to the binding region, one end of the active semiconductor pattern of the pixel circuit closest to the binding region is the first end, one end of the first electrode of the light-emitting element closest to the binding region is the second end, and the second end is closer to the binding region than the first end.

[0006] For example, according to an embodiment of the present disclosure, in the same sub-pixel of at least one sub-pixel, the channel region of the light-emitting control transistor is located on the side farther from the binding region than the center of the light-emitting region of the light-emitting element.

[0007] For example, according to an embodiment of the present disclosure, the plurality of sub-pixels include a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels. The plurality of first sub-pixels and the plurality of third sub-pixels are alternately arranged along a first direction and a second direction to form a plurality of first pixel rows and a plurality of first pixel columns. The plurality of second sub-pixels are arranged in an array along the first direction and the second direction to form a plurality of second pixel rows and a plurality of second pixel columns. The plurality of first pixel rows and the plurality of second pixel rows are alternately arranged along the second direction and are offset from each other in the first direction. The plurality of first pixel columns and the plurality of second pixel columns are alternately arranged along the first direction and are offset from each other in the second direction. The first direction intersects the second direction. The second pixel row includes a plurality of second sub-pixel pairs arranged along the first direction. The two second sub-pixels in the second sub-pixel pair are a first pixel block and a second pixel block, respectively. The first pixel block and the second pixel block are alternately arranged along the first direction. The first pixel block and the second pixel block of the second pixel column are alternately arranged along the second direction. The plurality of sub-pixels include a plurality of minimum repeating units. The minimum repeating unit includes a first sub-pixel, a first pixel block, a second pixel block, and a third sub-pixel. In the minimum repeating unit, the first pixel block and the first sub-pixel constitute a first pixel unit, and the second pixel block and the third sub-pixel constitute a second pixel unit. In the first pixel unit, the first pixel block is located on a side away from the bonding region of the first sub-pixel. In the second pixel unit, the second pixel block is located on a side away from the bonding region of the third sub-pixel.

[0008] For example, according to an embodiment of the present disclosure, in at least one of the same sub-pixels of the first sub-pixel and the third sub-pixel, the channel region of the light emission control transistor is located on a side away from the bonding region and farther from the center of the light emission region of the light emitting element.

[0009] For example, according to an embodiment of the present disclosure, the first electrode of the light-emitting element includes a main body electrode and a connection electrode that are electrically connected to each other. The main body electrode overlaps with the light-emitting region of the light-emitting element, the connection electrode does not overlap with the light-emitting region, the connection electrode is electrically connected to the light-emitting control transistor, and in at least one of the same sub-pixels of the first sub-pixel and the third sub-pixel, the channel region of the light-emitting control transistor is located on a side farther from the bonding region than the center of the main body electrode.

[0010] For example, according to an embodiment of the present disclosure, in the channel region of the light-emitting control transistor and the light-emitting region of the light-emitting element of the same second sub-pixel, the channel region is farther from the bonding region than the light-emitting region of the light-emitting element.

[0011] For example, according to an embodiment of the present disclosure, the shape of the channel region of the driving transistor includes a U shape, and the opening of the U shape faces a side away from the bonding region.

[0012] For example, according to an embodiment of the present disclosure, the row of sub-pixels closest to the bonding region is the first pixel row.

[0013] For example, according to an embodiment of the present disclosure, in the first pixel unit, the pixel circuit of the first pixel block and the pixel circuit of the first sub-pixel are arranged along the first direction, and in the second pixel unit, the pixel circuit of the second pixel block and the pixel circuit of the third sub-pixel are arranged along the first direction.

[0014] For example, according to an embodiment of the present disclosure, in the first pixel unit, the active semiconductor pattern of the first pixel block and the active semiconductor pattern of the first sub-pixel are symmetrically distributed with respect to a straight line that is located therebetween and extends along the second direction. In the second pixel unit, the active semiconductor pattern of the second pixel block and the active semiconductor pattern of the third sub-pixel are symmetrically distributed with respect to a straight line that is located therebetween and extends along the second direction.

[0015] For example, according to an embodiment of the present disclosure, the display substrate further includes a first conductive layer located between the first electrode of the light-emitting element and the base substrate, and a second conductive layer located between the first conductive layer and the first electrode of the light-emitting element. The first conductive layer includes a first connection structure and a first power signal line. The second conductive layer includes a data cable, a second connection structure, and a second power signal line. The second power signal line is electrically connected to the first power signal line. The first pole of the light-emitting control transistor is electrically connected to the driving transistor. The second pole of the light-emitting control transistor is electrically connected to the first electrode of the light-emitting element through the first connection structure and the second connection structure.

[0016] For example, according to an embodiment of the present disclosure, the second conductive layer further includes a first overlapping portion that overlaps at least one of the light-emitting regions of the first sub-pixel and the third sub-pixel. The ratio of the area of the first overlapping portion to the area of the light-emitting region is 0.6 to 1. The first overlapping portion is substantially symmetrically distributed with respect to a straight line that extends along the second direction.

[0017] For example, according to an embodiment of the present disclosure, the second conductive layer further includes a second overlapping portion that overlaps the light-emitting region of the second sub-pixel. The second overlapping portion is substantially symmetrically distributed with respect to a straight line that extends along the second direction.

[0018] For example, according to an embodiment of the present disclosure, in at least one of the first sub-pixel and the third sub-pixel, the apex angle of the light-emitting region of the light-emitting element includes a first corner portion and a second corner portion that are oppositely arranged, and the distance from the intersection of the extension lines of the two sides constituting the first corner portion to the center of the light-emitting region is greater than the distance from the intersection of the two sides or their extension lines constituting the second corner portion to the center of the light-emitting region. At least one of the first sub-pixel and the third sub-pixel includes a first type of sub-pixel and a second type of sub-pixel. In different types of sub-pixels, the direction from the apex of the first corner portion to the apex of the second corner portion is different. In the first type of sub-pixel and the second type of sub-pixel, the direction from the apex of the first corner portion to the apex of the second corner portion is a first pointing direction and a second pointing direction respectively, and the first pointing direction is opposite to the second pointing direction.

[0019] For example, according to an embodiment of the present disclosure, at least one of the first sub-pixel and the third sub-pixel further includes a third type of sub-pixel and a fourth type of sub-pixel. In the third type of sub-pixel and the fourth type of sub-pixel, the direction from the apex of the first corner to the apex of the second corner is a third pointing direction and a fourth pointing direction respectively, the third pointing direction is opposite to the fourth pointing direction, and the first pointing direction intersects the third pointing direction.

[0020] For example, according to an embodiment of the present disclosure, one of the first sub-pixel and the third sub-pixel is a red sub-pixel configured to emit red light, the other of the first sub-pixel and the third sub-pixel is a blue sub-pixel configured to emit blue light, and the second sub-pixel is a green sub-pixel configured to emit green light.

[0021] Embodiments of the present disclosure provide a display device including any one of the above display substrates.

Brief Description of the Drawings

[0022] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments are briefly introduced below. Obviously, the drawings in the following description are only related to some embodiments of the present disclosure and do not limit the present disclosure.

[0023]

Figure 1

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Figure 8

Figure 9A

Figure 9B

Figure 10A

Figure 10B

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Figure 10D

Figure 10E

Figure 11A

Figure 11B

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Figure 11D

Figure 11E

DETAILED DESCRIPTION OF THE INVENTION

[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, not all of the embodiments. All other embodiments obtained by those skilled in the art based on the described embodiments of the present disclosure without creative efforts are included within the protection scope of the present disclosure.

[0025] Unless otherwise defined, technical or scientific terms used in this disclosure shall have the ordinary meanings as understood by those of ordinary skill in the technical field to which this disclosure pertains. The terms "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similar words such as "comprising" or "containing" mean that the elements or things appearing before such words include the elements or things enumerated after such words and their equivalents without excluding other elements or things.

[0026] The features such as "vertical" and "identical" used in the embodiments of this disclosure include the features of "vertical" and "identical" in a strict sense. "Nearly vertical" and "nearly the same" include some errors and represent being within the acceptable deviation range of a specific value, which is determined by those of ordinary skill in the art considering the errors related to measurement and the measurement of a specific quantity (i.e., limited by the measurement system). The "center" in the embodiments of this disclosure includes not only the position exactly at the geometric center but also the position approximately at the center within a small area around the geometric center. For example, "nearly" can mean within one or more standard deviations, or within 10% or 5% of the said value.

[0027] FIG. 1 is a schematic diagram of a pixel array structure on a display substrate. As shown in FIG. 1, the display substrate includes a display area, and the display area includes a plurality of sub-pixels such as a red sub-pixel 01 configured to emit red light, a blue sub-pixel 02 configured to emit blue light, and a green sub-pixel 03 configured to emit green light. At least a part of the sub-pixels includes a light-emitting element and a pixel circuit for driving the light-emitting element. The light-emitting element includes an anode 06, a light-emitting functional layer, and a cathode stacked in sequence. The pixel circuit includes a plurality of transistors and at least one capacitor. The display substrate includes an active semiconductor pattern 05, and the active semiconductor pattern 05 includes the channel regions, source and drain regions of each transistor.

[0028] As shown in FIG. 1, the plurality of sub-pixels include a plurality of minimum repeating units, and each minimum repeating unit includes one red sub-pixel 01, one blue sub-pixel 02, and two green sub-pixels 03. In each minimum repeating unit, the red sub-pixel 01 and the green sub-pixel 03 form a first pixel unit 010, and the blue sub-pixel 02 and another green sub-pixel 03 constitute a second pixel unit 020. For example, in each minimum repeating unit, the red sub-pixel 01 and the blue sub-pixel 02 are respectively shared by the first pixel unit 010 and the second pixel unit 020.

[0029] As shown in FIG. 1, in the first pixel unit 010, the pixel circuits of the red sub-pixel 01 and the green sub-pixel 03 are arranged along the X direction, and in the second pixel unit 020, the pixel circuits of the blue sub-pixel 02 and the green sub-pixel 03 are arranged along the X direction.

[0030] The arrow in the Y direction in FIG. 1 points upward, and the arrow in the X direction points to the right. In FIG. 1, the green sub-pixel 03 of the first pixel unit 010 is located at the lower right of the red sub-pixel, the green sub-pixel 03 of the second pixel unit 020 is located at the lower right of the blue sub-pixel 02, and the anode 06 of the light-emitting element of each sub-pixel is electrically connected to the position 04 of the active semiconductor pattern 05 (for example, the source or drain of the light-emitting control transistor).

[0031] Due to the pixel borrowing relationship shown in FIG. 1, the anodes 06 of both the red sub-pixel 01 and the blue sub-pixel 02 need to extend downward and be electrically connected to the position 04 of the active semiconductor pattern 05 (for example, the source or drain of the light-emitting control transistor). In this case, the portion of the anode of the sub-pixel for electrically connecting to the position 04 of the active semiconductor pattern 05 is located below the light-emitting region of the sub-pixel.

[0032] FIG. 2 is a schematic diagram of the boundary of the display area and the lower pad area in the display substrate shown in FIG. 1, and FIG. 3 is an enlarged view of the area B shown in FIG. 2. As shown in FIGS. 2 and 3, the display substrate further includes a pad area located on one side of the display area AA, such as a lower pad area located under the display area AA. The lower pad area can include a lower frame. The lower pad area includes a binding area located at a position close to the display area AA of the lower pad area.

[0033] As shown in FIGS. 2 and 3, the row of sub-pixels closest to the binding area is the row of green sub-pixels 03.

[0034] As shown in FIG. 3, the display substrate further includes a conductive layer 07 located between the anode 06 of the light-emitting element and the active semiconductor pattern 05. For example, the conductive layer 07 can include a power signal line for transmitting a VDD signal, and can further include a data cable for transmitting a data signal. A signal transmission line 08 electrically connected to the power signal line is provided in the lower pad area.

[0035] As shown in FIG. 3, due to the pixel borrowing relationship shown in FIG. 1, the portion for electrically connecting the anode of at least some sub-pixels to the active semiconductor pattern 05 extends toward the side closer to the lower pad area, and the active semiconductor pattern 05 electrically connected to the anode of the sub-pixel closest to the lower pad area includes the portion of the boundary B01 of the display area AA on the side closer to the boundary B02 of the signal source 08. In order to meet the design of the pixel circuit of the sub-pixel closest to the lower pad area, it is necessary to set a larger distance between the boundary B01 and the boundary B02. As a result, it is necessary to increase the size of the lower pad area, that is, the size of the lower frame of the display device in the Y direction becomes larger.

[0036] Embodiments of the present disclosure provide a display substrate and a display device. The display substrate includes a display area and a peripheral area located on at least one side of the display area. The display substrate includes a plurality of sub-pixels located on a base substrate. At least a part of the sub-pixels located in the display area includes a light-emitting element and a pixel circuit. The light-emitting element includes a light-emitting functional layer, and a first electrode and a second electrode located on both sides of the light-emitting functional layer in a direction perpendicular to the base substrate. The first electrode is located between the light-emitting functional layer and the base substrate. The pixel circuit includes a driving transistor and a light-emitting control transistor. The first electrode of the light-emitting element is electrically connected to the light-emitting control transistor. The display substrate further includes a bonding area located in the peripheral area and only on one side of the display area. In the pixel circuit, the light-emitting control transistor is located on a side away from the bonding area of the driving transistor. Embodiments of the present disclosure contribute to reducing the lower frame of the display device by fully utilizing the pixel space by designing the pixel circuit located in the display area.

[0037] Hereinafter, with reference to the accompanying drawings, the display substrate and the display device provided by the embodiments of the present disclosure will be described.

[0038] FIG. 4 is a schematic diagram of a partial pixel array structure on the display substrate provided by the embodiment of the present disclosure. FIG. 5 is a schematic diagram of an adjacent portion between the display area and the peripheral area in the display substrate shown in FIG. 4. FIG. 6 is an enlarged view of area C in the display substrate shown in FIG. 5, and FIG. 7 is a schematic diagram of a partial cross-sectional structure along line CC' shown in FIG. 6.

[0039] As shown in FIGS. 4 to 7, the display substrate includes a display area 10 and a peripheral area 20 located on at least one side of the display area 10. For example, the display area 10 is a display area of the display substrate, and the peripheral area 20 is located around the display area 10 and is an area not used for display.

[0040] As shown in FIGS. 4 to 7, the display substrate includes a base substrate 11 and a plurality of sub-pixels 40 located on the base substrate 11. For example, at least a part of the plurality of sub-pixels 40 is located in the display area 10. For example, at least a part of the sub-pixels 40 located in the display area 10 is used to display an image. For example, all of the sub-pixels 40 located in the display area 10 are used to display an image.

[0041] As shown in FIGS. 4 to 7, at least a part of the sub-pixels 40 located in the display area 10 includes a light-emitting element 410 and a pixel circuit 420. The light-emitting element 410 includes a light-emitting functional layer 413, and a first electrode 411 and a second electrode 412 located on both sides of the light-emitting functional layer 413 along a direction perpendicular to the base substrate 11. The first electrode 411 is located between the light-emitting functional layer 413 and the base substrate 11.

[0042] For example, as shown in FIG. 7, the display substrate further includes a pixel defining pattern 50 located on a side of the first electrode 411 of the light-emitting element 410 away from the base substrate 11. The pixel defining pattern 50 includes a plurality of openings 51 and a limiting portion 52 surrounding the plurality of openings 51, and a plurality of light-emitting elements 410 are at least partially located in the plurality of openings 51. FIG. 7 schematically shows that a structural layer 011 is provided on a side of the first electrode 411 of the light-emitting element 410 away from the second electrode 412. The structural layer 011 can include film layers such as a base substrate, a layer where an active semiconductor pattern is located, a film layer where a gate line is located, a film layer where a data cable is located, and a plurality of insulating layers.

[0043] For example, the limiting portion 52 is a structure that limits the opening 51. For example, the material of the limiting portion 52 can include polyimide, acrylic, or polyethylene terephthalate.

[0044] For example, the aperture 51 of the pixel defining pattern 50 is configured to define the light emitting region 401 of the light emitting element 410. For example, the light emitting elements 410 of the plurality of sub-pixels 40 may be arranged in a one-to-one correspondence with the plurality of apertures 51. For example, the light emitting element 410 can include a portion located within the aperture 51 and a portion overlapping the limiting portion 52 in a direction perpendicular to the base substrate 11.

[0045] For example, the aperture 51 of the pixel defining pattern 50 is configured to expose the first electrode 411 of the light emitting element 410, and the exposed first electrode 411 is at least partially in contact with the light emitting functional layer 413 of the light emitting element 410. For example, at least a part of the first electrode 411 is located between the limiting portion 52 and the base substrate 11. For example, when the light emitting functional layer 413 is located within the aperture 51 of the pixel defining pattern 50, the first electrode 411 and the second electrode 220 located on both sides of the light emitting functional layer 413 can drive the light emitting functional layer 413 within the aperture 51 of the pixel defining pattern 50 to emit light. For example, the above-mentioned light emitting region 401 may refer to the effective light emitting region of the light emitting element, and the shape of the light emitting region 401 refers to a two-dimensional shape. For example, it may be the same as the shape of the aperture 51 of the pixel defining pattern 50. For example, the aperture 51 of the pixel defining pattern 50 may have a shape in which the size on the side closer to the base substrate 11 is small and the size on the side farther from the base substrate 11 is large. For example, the shape of the light emitting region 401 may be substantially the same as the size and shape of the aperture 51 of the pixel defining pattern 50 on the side closer to the base substrate 11.

[0046] For example, the first electrode 411 may be an anode, and the second electrode 412 may be a cathode. For example, the cathode may be formed of a material with high conductivity and low work function. For example, it may be formed of a metal material. For example, the anode may be formed of a conductive material having a high work function.

[0047] As shown in FIGS. 4 to 7, the pixel circuit 420 includes a driving transistor T3 and a light emitting control transistor T6 electrically connected to the first electrode 411 of the light emitting element 410.

[0048] As shown in FIGS. 4 to 7, the display substrate further includes a binding region 21 that is located in the peripheral region 20 and on the first side of the display region 10. For example, the binding region 21 is located only on one side of the display region 10. For example, the binding region 21 is located on one side of the display region 10 in the Y direction. For example, the arrow in the Y direction in FIG. 5 points upward, and the binding region 21 is located below the display region 10.

[0049] As shown in FIGS. 4 to 7, in the same pixel circuit 420, the emission control transistor T6 is located on the side away from the binding region 21 of the driving transistor T3. For example, the pixel circuit 420 includes an active semiconductor pattern, the active semiconductor pattern includes the channel region, source, and drain regions of each transistor, and the channel region of the emission control transistor T6 is located on the side away from the binding region 21 of the channel region of the driving transistor T3. For example, the gate electrode of the emission control transistor T6 is located on the side away from the binding region of the gate electrode of the driving transistor T3.

[0050] For example, the driving transistor T3 of each pixel circuit 420 is located between the emission control transistor T6 and the binding region 21. For example, in each pixel circuit 420, the driving transistor T3 is located below the emission control transistor T6. For example, in the same pixel circuit 420, the channel region of the driving transistor T3 is located between the channel region of the emission control transistor T6 and the binding region 21. For example, in each pixel circuit 420, the channel region of the driving transistor T3 is located below the channel region of the emission control transistor T6.

[0051] The embodiments of the present disclosure contribute to maximizing the utilization of pixel space, improving the flatness of the first electrode of the sub-pixel, and reducing the lower frame of the display device by designing a pixel circuit located in the display region and arranging the emission control transistor in the pixel circuit on the side away from the binding region of the driving transistor.

[0052] For example, as shown in FIG. 5, the peripheral region 20 where the binding region 21 is located includes a pad region, and the pad region includes structures such as the binding region 21, CT (Cell Test) 22, COP (IC On Panel) 23, first signal transmission line 24 (for example, transmitting a VSS signal), second signal transmission line 25 (for example, transmitting a VDD signal), and FOP (FPC On Panel) 26.

[0053] For example, the binding region 21 is configured to bind to at least one of a data driving chip and a gate electrode driving chip. For example, the binding region 21 includes a signal input pad and a transmission line electrically connected to the signal input pad. For example, a data cable can be electrically connected to the signal input pad via the transmission line. For example, the binding region 21 can include a bending region, and structures such as the above-mentioned CT (Cell Test) 22, COP (IC On Panel) 23, and FOP (FPC On Panel) 26 can be bent to the non-display back surface of the display substrate. For example, a light-emitting element is located on the first surface (for example, the front surface) of the display substrate, and structures such as the above-mentioned CT (Cell Test) 22, COP (IC On Panel) 23, and FOP (FPC On Panel) 26 can be bent to the second surface (for example, the back surface) of the display substrate.

[0054] FIG. 8 is an equivalent diagram of a pixel circuit provided by an embodiment of the present disclosure. For example, as shown in FIG. 8, the light-emitting control transistor T6 in the pixel circuit 420 may be a first light-emitting control transistor T6, and the pixel circuit 420 further includes a second reset transistor T1, a second light-emitting control transistor T5, a data writing transistor T4, a threshold compensation transistor T2, a first reset control transistor T7, and a storage capacitor C.

[0055] For example, the display substrate further includes a reset power signal line, a scanning signal line, a power signal line, a reset control signal line, a light-emitting control signal line, and a data cable.

[0056] For example, the first pole of the threshold compensation transistor T2 is electrically connected to the first pole of the driving transistor T3, and its second pole is electrically connected to the gate electrode of the driving transistor T3. The first pole of the first reset control transistor T7 is electrically connected to the reset power signal line to receive the reset signal Vinit, and its second pole is electrically connected to the first electrode of the light-emitting element 410 (i.e., the N4 node). The first pole of the data writing transistor T4 is electrically connected to the second pole of the driving transistor T3, and its second pole is electrically connected to the data cable to receive the data signal Data, and its gate electrode is electrically connected to the scanning signal line to receive the scanning signal Gate. The first pole of the storage capacitor C is electrically connected to the power signal line, and its second pole is electrically connected to the gate electrode of the driving transistor T3. The gate electrode of the threshold compensation transistor T2 is electrically connected to the scanning signal line to receive the compensation control signal. The gate electrode of the first reset transistor T7 is electrically connected to the reset control signal line to receive the reset control signal Reset(N + 1). The first pole of the second reset transistor T1 is electrically connected to the reset power signal line to receive the reset signal Vinit, and its second pole is electrically connected to the gate electrode of the driving transistor T3, and its gate electrode is electrically connected to the reset control signal line to receive the reset control signal Reset(N). The gate electrode of the first light-emitting control transistor T6 is electrically connected to the light-emitting control signal line to receive the light-emitting control signal EM, its first pole is electrically connected to the first pole of the driving transistor T3, and its second pole is electrically connected to the first electrode of the light-emitting element 410. The first pole of the second light-emitting control transistor T5 is electrically connected to the power signal line to receive the first power signal VDD, its second pole is electrically connected to the second pole of the driving transistor T3, and its gate electrode is electrically connected to the light-emitting control signal line to receive the light-emitting control signal line EM. The second electrode of the light-emitting element 410 is connected to the voltage terminal VSS. The above-mentioned power signal line refers to a signal line that outputs the voltage signal VDD, and is connected to a voltage source and can output a constant voltage signal such as a positive voltage signal.

[0057] For example, the scanning signal and the compensation control signal may be the same. That is, the gate electrode of the data writing transistor T3 and the gate electrode of the threshold compensation transistor T2 can be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. For example, the gate electrode of the data writing transistor T3 and the gate electrode of the threshold compensation transistor T2 may be electrically connected to different signal lines respectively. That is, the gate electrode of the data writing transistor T3 is electrically connected to the first scanning signal line, and the gate electrode of the threshold compensation transistor T2 is electrically connected to the second scanning signal line. The signals transmitted by the first scanning signal line and the second scanning signal line may be the same or different. Thereby, the gate electrode of the data writing transistor T3 and the threshold compensation transistor T2 can be controlled individually, improving the flexibility of controlling the pixel circuit.

[0058] For example, the light emission control signals input to the first light emission control transistor T6 and the second light emission control transistor T5 may be the same. That is, the gate electrode of the first light emission control transistor T6 and the gate electrode of the second light emission control transistor T5 can be electrically connected to the signal line to receive the same signal, reducing the number of signal lines. For example, the gate electrode of the first light emission control transistor T6 and the gate electrode of the second light emission control transistor T5 can be electrically connected to different light emission control signal lines respectively, and the signals transmitted by the different light emission control signal lines may be the same or different.

[0059] For example, the reset control signals input to the first reset transistor T7 and the second reset transistor T1 may be the same. That is, the gate electrode of the first reset transistor T7 and the gate electrode of the second reset transistor T1 can be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. For example, the gate electrode of the first reset transistor T7 and the gate electrode of the second reset transistor T1 may be electrically connected to different reset control signal lines respectively. In this case, the signals of the different reset control signal lines may be the same or different.

[0060] For example, as shown in FIG. 8, when the display substrate operates, in the first stage of the screen display, the second reset transistor T1 is turned on, and the voltage of the N1 node is initialized. In the second stage of the screen display, the data is stored in the N1 node via the data writing transistor T4, the driving transistor T3, and the threshold compensation transistor T2. In the third light-emitting stage, the second light-emitting control transistor T5, the driving transistor T3, and the first light-emitting control transistor T6 are all turned on, and the light-emitting element 410 conducts in the forward direction and emits light.

[0061] In addition, in the embodiments of the present disclosure, in addition to the 7T1C (i.e., 7 transistors and 1 capacitor) structure shown in FIG. 8, each pixel circuit may, for example, have a structure including other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure. The embodiments of the present disclosure do not limit this. The equivalent diagram of the pixel circuit in the display substrate shown in FIG. 1 may be the same as the equivalent diagram of the pixel circuit shown in FIG. 8.

[0062] FIG. 9A is a schematic partial structure diagram of the active semiconductor pattern in the display substrate shown in FIG. 4. For example, as shown in FIGS. 4 to 7 and FIG. 9A, the pixel circuit 420 includes an active semiconductor pattern 500, and the active semiconductor pattern 500 includes the channel regions 510, the source and drain regions 520 of each transistor. For example, the source and drain regions 520 may include a source electrode region and a drain electrode region.

[0063] For example, FIG. 9A schematically shows that the active semiconductor pattern 500 may be formed by patterning a semiconductor material. The active semiconductor pattern 500 can be used to form the active layers of the drive transistor T3, data write transistor T4, second light emission control transistor T5, first light emission control transistor T6, and first reset control transistor T7 described above in order to form the channel regions of the transistors. The active semiconductor pattern 500 includes the active layer patterns (channel regions) and doping region patterns (source and drain regions) of the transistors of each sub-pixel, and the active layer patterns and doping region patterns of the transistors in the same pixel circuit are provided integrally.

[0064] For example, the active semiconductor pattern 500 can be made of amorphous silicon, polysilicon, an oxide semiconductor material, or the like. Note that the source electrode region and the drain electrode region may be regions doped with an n-type impurity or a p-type impurity.

[0065] For example, on the side of the active semiconductor pattern 500 away from the base substrate, a metal layer such as a gate electrode metal layer is provided. The metal layer includes the gate electrodes of the above-described scanning signal line, reset control signal line, light emission control signal line, driving transistor T3, data writing transistor T4, second light emission control transistor T5, first light emission control transistor T6, and first reset control transistor T7. The dotted rectangular frame in FIG. 9A indicates the overlapping portion of the above metal layer and the active semiconductor pattern 500 as the channel region 510 of each transistor. The active semiconductor pattern 500 on both sides of each channel region 510 becomes conductive through a process such as ion doping and is used as the first and second electrodes (i.e., the aforementioned source and drain regions 520) of each transistor. Since the structures of the source electrode and the drain electrode of the transistor are symmetric, there is no difference in their physical structures. In the embodiments of the present disclosure, to distinguish the transistors, in addition to the gate electrode as the control electrode, one is described as the first electrode directly and the other as the second electrode. Therefore, the first and second electrodes of all or part of the transistors in the embodiments of the present disclosure can be exchanged as needed.

[0066] For example, as shown in FIGS. 5 and 9A, the shape of the channel region of the driving transistor T3 includes a U shape, and the opening of the U shape faces away from the binding region 21. For example, the opening of the U shape faces upward.

[0067] For example, the lower pad region can include sector-shaped wiring electrically connected to the data cable.

[0068] For example, as shown in FIGS. 5 and 9A, in the same pixel circuit, the channel region of the data writing transistor T4 is located closer to the lower pad region than the channel region of the driving transistor T3. For example, in the same pixel circuit, the channel region of the data writing transistor T4 is located closer to the lower pad region of the channel region of the driving transistor T3. For example, in the same pixel circuit, the channel region of the second light emission control transistor T5 is located on the side away from the lower pad region of the channel region of the driving transistor T3. For example, in the same pixel circuit, the channel region of the first reset control transistor T7 is located on the side away from the lower pad region of the channel region of the driving transistor T3.

[0069] For example, the display substrate further includes an imaging region for arranging a camera. For example, the imaging region can be located on the side away from the binding region of the display region (for example, the upper side of the display region), or can be located on the side away from the binding region rather than the center of the display region. For example, the imaging region is located on the side away from the binding region of the display region, and the light emission control transistor in the pixel circuit is located on the side closer to the imaging region of the driving transistor. For example, the imaging region is located on the side away from the binding region rather than the center of the display region, and the light emission control transistor in the pixel circuit between the imaging region and the binding region is located on the side closer to the imaging region of the driving transistor.

[0070] For example, the semiconductor layer forming the channel regions of the second reset transistor T1 and the threshold compensation transistor T2 of the pixel circuit is located on the side away from the base substrate of the active semiconductor pattern, and the semiconductor layer can include an oxide semiconductor material. For example, when an oxide semiconductor is used for the active layers of the second reset transistor T1 and the threshold compensation transistor T2 of the pixel circuit, the transistor using the oxide semiconductor has characteristics of good hysteresis characteristics and low leakage current, and has a low mobility. Therefore, the oxide semiconductor transistor is used instead of the low-temperature polysilicon material in the transistor to form a low-temperature polysilicon oxide (LTPO) pixel circuit, realizing low leakage and improving the stability of the gate electrode voltage of the transistor.

[0071] Naturally, the embodiments of the present disclosure are not limited to the active semiconductor pattern of the pixel circuit shown in FIG. 9A. The semiconductor layer of the channel regions of the second reset transistor T1 and the threshold compensation transistor T2 is located in the same layer as the semiconductor layer of the channel regions of other transistors, that is, the active semiconductor pattern can include the channel regions of the second reset transistor T1, the threshold compensation transistor T2, the driving transistor T3, the data writing transistor T4, the second light emission control transistor T5, the first light emission control transistor T6, and the first reset control transistor T7.

[0072] FIG. 9B is a schematic partial structure diagram of the active semiconductor pattern in the display substrate shown in FIG. 1. For example, as shown in FIG. 9B, the active semiconductor pattern 05 may be formed by patterning a semiconductor material. The active semiconductor pattern 05 can be used to form the active layers of the drive transistor T3, data write transistor T4, second light emission control transistor T5, first light emission control transistor T6, and first reset control transistor T7 described above in order to form the channel regions of the respective transistors. For example, the active semiconductor pattern 05 can be formed of amorphous silicon, polysilicon, an oxide semiconductor material, or the like. Note that the source electrode region and the drain electrode region may be regions doped with an n-type impurity or a p-type impurity.

[0073] For example, a metal layer such as a gate electrode metal layer is provided on the side of the active semiconductor pattern 05 away from the base substrate, and the metal layer includes the gate electrodes of the scanning signal line, reset control signal line, light emission control signal line, drive transistor T3, data write transistor T4, second light emission control transistor T5, first light emission control transistor T6, and first reset control transistor T7 described above. The dotted rectangular frame in FIG. 9B indicates each portion where the conductive layer in which the gate electrodes of the transistors are located as the channel regions of the respective transistors overlaps with the active semiconductor pattern 05. For example, the semiconductor layer that forms the channel regions of the second reset transistor T1 and the threshold compensation transistor T2 in the pixel circuit is located on the side away from the base substrate of the active semiconductor pattern, and the semiconductor layer can include an oxide semiconductor material.

[0074] For example, as shown in FIGS. 1 to 3 and FIG. 9B, in the same pixel circuit among at least one pixel circuit, the channel region of the drive transistor T3 is located on the side away from the lower pad region of the channel region of the light emission control transistor T6.

[0075] For example, as shown in FIGS. 1 to 3 and 9B, in the same pixel circuit among at least one pixel circuit, the channel region of the second light emission control transistor T5 is located closer to the lower pad region of the channel region of the driving transistor T3.

[0076] For example, as shown in FIGS. 1 to 3 and 9B, in the sub-pixel closest to the lower pad region, the pixel circuit is closer to the lower pad region than the first electrode of the light emitting element. For example, the active semiconductor pattern 05 includes a portion between the boundary B01 and the boundary B02.

[0077] For example, as shown in FIGS. 1 to 3 and 9B, the shape of the channel region of the driving transistor T3 includes a U-shape, and the opening of the U-shape faces one side of the peripheral region 20 where the binding region 21 is located. For example, the opening of the U-shape faces downward.

[0078] FIG. 10A is a schematic partial structure diagram of a first conductive layer provided by an embodiment of the present disclosure. FIG. 10B is a schematic partial structure diagram of a second conductive layer provided by an embodiment of the present disclosure. FIG. 10C is a schematic diagram of a stacked structure of an active semiconductor pattern, a first conductive layer, and a second conductive layer provided by an embodiment of the present disclosure. FIG. 10D is a schematic diagram of a stacked structure of an active semiconductor pattern, a second conductive layer, and a first electrode of a light emitting element provided by an embodiment of the present disclosure. FIG. 10E is a schematic structural diagram of a first electrode of a light emitting element provided by an embodiment of the present disclosure. FIGS. 10A to 10E only schematically show a schematic diagram of a stacked structure of some film layers in the display substrate, and other film layers can further include a film layer where a gate line is located, a semiconductor layer in the channel regions of the second reset transistor T1 and the threshold compensation transistor T2, and the like.

[0079] For example, as shown in FIGS. 8, 9A, and 10A to 10D, the display substrate includes a first conductive layer 600 (e.g., SD1 layer) positioned between the first electrode of the light-emitting element and the base substrate. The first conductive layer 600 includes a reset power signal line 610, and the reset power signal line 610 is electrically connected to the first pole of the first reset transistor T7 to provide a reset signal. For example, the above-mentioned reset power signal line 610 may be a first reset power signal line electrically connected to the first pole of the first reset transistor T7. The display substrate further includes a second reset power signal line. The first portion of the second reset power signal line is positioned between the first conductive layer 600 and the film layer where the gate electrode of the first reset transistor T7 is located, and is electrically connected to the first pole of the second reset power signal line to be configured to provide a reset signal.

[0080] For example, as shown in FIGS. 8, 9A, and 10A to 10D, the first conductive layer 600 further includes a connection structure 620. One end of the connection structure 620 is electrically connected to the gate electrode of the driving transistor T1, and the other end is electrically connected to the second pole of the second reset transistor T1 and the second pole of the threshold compensation transistor T2.

[0081] For example, as shown in FIGS. 8, 9A, and 10A to 10D, the first conductive layer 600 further includes a first power signal line 630, and the display substrate further includes a second conductive layer 700 (e.g., SD2 layer) positioned between the first conductive layer 600 and the first electrode of the light-emitting element. The second conductive layer 700 includes a data cable 710 extending along the Y direction and a second power signal line 720. Each first power signal line 630 is electrically connected to two second power signal lines 720 positioned on both sides thereof to form a grid pattern. By the arrangement method of the grid-shaped power signal lines, the second power signal lines of each pixel can be electrically connected, reducing the voltage drop of the second power signal lines and contributing to improving the uniformity of the display device.

[0082] For example, as shown in FIGS. 8, 9A, 10A to 10D, the first conductive layer 600 further includes a second portion 640 that is electrically connected to the first portion of the second reset power signal line.

[0083] For example, as shown in FIGS. 8, 9A, 10A to 10D, the first conductive layer 600 further includes a connection structure 650, and the second pole of the data write transistor T4 is electrically connected to the data cable 710 through the connection structure 650 to receive a data signal.

[0084] For example, as shown in FIGS. 8, 9A, 10A to 10D, the first conductive layer 600 further includes a connection structure 660 (i.e., the first connection structure 660). The second conductive layer 700 further includes a connection structure 730 (i.e., the second connection structure 730). The second pole of the first light emission control transistor T6 is electrically connected to the first electrode 411 of the light emitting element through the first connection structure 660 and the second connection structure 730.

[0085] For example, as shown in FIGS. 4, 10B, and 10D, the second power signal line 720 includes a pad 721, and the plurality of pads 721 included in the plurality of second power signal lines 720 are overlapped with the first electrode in the light emitting region of the light emitting element of some sub-pixels (for example, at least one of the first sub-pixel 100 and the third sub-pixel 100 described later), so as to improve the flatness of the light emitting functional layer in the light emitting region of the sub-pixel, reduce the occurrence probability of defects such as color bleeding during display, and improve the display effect.

[0086] For example, as shown in FIGS. 4, 10B, and 10D, the second power signal line 720 includes a pad 721, and the plurality of pads 721 included in the plurality of second power signal lines 720 are overlapped with the first electrode in the light emitting region of the light emitting element of some sub-pixels (for example, at least one of the first sub-pixel 100 and the third sub-pixel 100 described later), so as to improve the flatness of the light emitting functional layer in the light emitting region of the sub-pixel, reduce the occurrence probability of defects such as color bleeding during display, and improve the display effect.

[0087] For example, as shown in FIGS. 4 and 10A, the first power supply signal line 630 includes a pad 631, and the plurality of pads 631 included in the plurality of first power supply signal lines 630 overlap with the first electrode in the light emitting region of the light emitting element of another part of the sub-pixels (for example, the second sub-pixel 200 described later). Thereby, the flatness of the light emitting functional layer in the light emitting region of the sub-pixel is improved, the occurrence probability of defects such as color bleeding during display is reduced, and the display effect is improved.

[0088] For example, as shown in FIGS. 4 to 6, in the sub-pixel 40 closest to the bonding region 21, one end of the active semiconductor pattern 500 of the pixel circuit 420 closest to the bonding region 21 is the first end 501, and one end of the first electrode 411 of the light emitting element 410 closest to the bonding region 21 is the second end 4110, and the second end 4110 is closer to the bonding region 21 than the first end 501.

[0089] For example, as shown in FIGS. 4 to 6 and 9A, in the sub-pixel 40 closest to the bonding region 21, the first end 501 of the active semiconductor pattern 500 of the pixel circuit 420 closest to the bonding region 21 is the second pole of the data writing transistor T4 and is electrically connected to the data cable 710. For example, the second end 4110 of the first electrode 411 of the light emitting element 410 may be the point closest to the bonding region of the first electrode 411.

[0090] For example, as shown in FIGS. 4 to 6, the boundary of the display region 10 close to the peripheral region 20 where the bonding region 21 is located is the boundary B10. In the sub-pixel 40 closest to the bonding region 21, the distance between the first end 501 of the active semiconductor pattern 500 of the pixel circuit 420 and the boundary B10 is greater than the distance between the second end 4110 of the first electrode 411 of the light emitting element 410 and the boundary B10.

[0091] For example, as shown in FIGS. 4 to 6, in the sub-pixel 40 closest to the bonding region 21, all of the active semiconductor patterns 500 of the pixel circuit 420 are located within the boundary B10 of the display region 10.

[0092] For example, as shown in FIGS. 4 to 6, in the sub-pixel 40 closest to the binding region 21, each transistor of the pixel circuit 420 is located within the display region 10. For example, in the sub-pixel 40 closest to the binding region 21, the channel regions of each transistor of the pixel circuit 420 are all farther from the binding region 21 than the second end portion 4110 of the first electrode 411 of the light-emitting element 410.

[0093] For example, as shown in FIG. 6, the second signal transmission line 25 is electrically connected to the second power supply signal line 720 to transmit a power supply signal such as a VDD signal to the second power supply signal line 720. For example, the second signal transmission line 25 includes a plurality of openings, facilitates deformation of the organic layer between the second signal transmission line 25 and the base substrate and the release of water vapor, and can effectively protect the light-emitting elements in the display region by releasing water vapor from the organic layer.

[0094] For example, the distance between the boundary B20 on the side of the second signal transmission line 25 close to the display region 10 and the boundary B10 of the display region shown in FIG. 6 is 30 to 50 microns smaller than the distance between the boundary B01 and the boundary B02 shown in FIG. 3. For example, the distance between the boundary B20 on the side of the second signal transmission line 25 close to the display region 10 and the boundary B10 of the display region shown in FIG. 6 is 35 to 45 microns smaller than the distance between the boundary B01 and the boundary B02 shown in FIG. 3. The distance between the boundary B20 on the side of the second signal transmission line 25 close to the display region 10 and the boundary B10 of the display region shown in FIG. 6 is 37 to 42 microns smaller than the distance between the boundary B01 and the boundary B02 shown in FIG. 3. The distance between the boundary B20 on the side of the second signal transmission line 25 close to the display region 10 and the boundary B10 of the display region shown in FIG. 6 is 39 to 40 microns smaller than the distance between the boundary B01 and the boundary B02 shown in FIG. 3.

[0095] In the display substrate provided by an embodiment of the present disclosure, by disposing the light emission control transistor of the pixel circuit on the side away from the bonding region of the driving transistor, the first electrode of the pixel circuit closest to the bonding region is made closer to the bonding region than each transistor of the pixel circuit, and the distance between the edge of the display region close to the bonding region and the edge of the second signal transmission line in the pad region where the bonding region is located, close to the display region, can be reduced. As a result, it is not necessary for the pad region to have a large size, which is advantageous for reducing the size of the lower frame of the display device.

[0096] For example, as shown in FIGS. 4, 5, and 9A, in the same sub-pixel among at least one sub-pixel 40, the channel region of the light emission control transistor T6 is located on the side away from the bonding region 21 than the center of the light emission region 401 of the light emitting element 410. For example, in at least one sub-pixel 40, the light emission control transistor T6 is located on the side away from the bonding region 21 of the light emission region 401 of the light emitting element 410. For example, in the same-color sub-pixels in at least one row of sub-pixels 40, the channel region of the light emission control transistor T6 is located on the side away from the bonding region 21 than the center of the light emission region 401 of the light emitting element 410. For example, in the same-color sub-pixels in at least two rows of sub-pixels 40, the channel region of the light emission control transistor T6 is located on the side away from the bonding region 21 than the center of the light emission region 401 of the light emitting element 410. For example, in each of at least one row of sub-pixels 40, the channel region of the light emission control transistor T6 is located on the side away from the bonding region 21 than the center of the light emission region 401 of the light emitting element 410. For example, in each sub-pixel 40, the channel region of the light emission control transistor T6 is located on the side away from the bonding region 21 than the center of the light emission region 401 of the light emitting element 410.

[0097] The center of the light-emitting region is, for example, the geometric center of the light-emitting region of the sub-pixel, or the intersection point of the perpendicular bisectors of the sides of the light-emitting region of the sub-pixel, or a point where the perpendicular distances from the light-emitting region of the sub-pixel to each side are substantially equal. Naturally, a certain amount of error is allowed in the center of the light-emitting region. For example, the center of the light-emitting region can be any point within a radius of 3 μm with the geometric center of the light-emitting region as the center of the circle.

[0098] For example, the plurality of sub-pixels 40 include different-color sub-pixels configured to emit lights of different colors. In a sub-pixel that emits light of one color, the light-emission control transistor T6 is located on the side away from the bonding region 21 of the light-emitting region 401 of the light-emitting element 410. For example, in two-color sub-pixels that emit lights of two different colors, the light-emission control transistor T6 is located on the side away from the bonding region 21 of the light-emitting region 401 of the light-emitting element 410.

[0099] For example, as shown in FIGS. 4 and 10E, the plurality of sub-pixels 40 include a plurality of first sub-pixels 100, a plurality of second sub-pixels 200, and a plurality of third sub-pixels 300. For example, one of the first sub-pixel 100 and the third sub-pixel 300 is a red sub-pixel that emits red light, the other of the first sub-pixel 100 and the third sub-pixel 300 is a blue sub-pixel that emits blue light, and the second sub-pixel 200 is a green sub-pixel that emits green light. For example, the first sub-pixel 100 is a red sub-pixel, the third sub-pixel 300 is a blue sub-pixel, and the area of the light-emitting region of the blue sub-pixel is larger than the area of the light-emitting region of the red sub-pixel. For example, the area of the light-emitting region of the blue sub-pixel is larger than the area of the light-emitting region of the green sub-pixel. Naturally, the embodiments of the present disclosure are not limited thereto, and the names of the first sub-pixel, the second sub-pixel, and the third sub-pixel can be mutually exchanged. For example, the first sub-pixel may be a green sub-pixel, the second sub-pixel may be a blue sub-pixel, the third sub-pixel may be a red sub-pixel, or the first sub-pixel may be a blue sub-pixel, the second sub-pixel may be a red sub-pixel, the third sub-pixel may be a green sub-pixel, etc.

[0100] For example, as shown in FIGS. 4 and 10E, a plurality of first sub-pixels 100 and a plurality of third sub-pixels 300 are alternately arranged along a first direction (the X direction shown in the figures) and a second direction (the Y direction shown in the figures), a plurality of first pixel rows R1 and a plurality of first pixel columns C1 are formed, a plurality of second sub-pixels 200 are arranged in an array along the first direction and the second direction, and a plurality of second pixel rows R2 and a plurality of second pixel columns C2 are formed. The plurality of first pixel rows R1 and the plurality of second pixel rows R2 are alternately arranged along the second direction and are offset from each other in the first direction, the plurality of first pixel columns C1 and the plurality of second pixel columns C2 are alternately arranged along the first direction and are offset from each other along the second direction, and the first direction intersects the second direction. For example, the first direction and the second direction may be perpendicular to each other. For example, the first direction and the second direction are interchangeable with each other.

[0101] For example, taking the centers of the light-emitting regions of adjacent first sub-pixels 100 and third sub-pixels 300 in the first pixel row R1, and the adjacent first sub-pixels 100 and third sub-pixels 300 along the column direction, and the centers of the light-emitting regions of the adjacent first sub-pixels 100 and third sub-pixels 300 respectively as the four vertices of a virtual rectangle, and arranging the center of the light-emitting region of the second sub-pixel 200 within the virtual rectangle.

[0102] For example, as shown in FIGS. 4 and 10E, the second pixel row R2 includes a plurality of second sub-pixel pairs 2120 arranged along the first direction, and the two second sub-pixels 200 in the second sub-pixel pair 2120 are a first pixel block 210 and a second pixel block 220 respectively, and the first pixel block 210 and the second pixel block 220 are alternately arranged along the first direction. For example, the first pixel block 210 and the second pixel block 220 within the second pixel column C2 are alternately arranged along the second direction.

[0103] For example, as shown in FIGS. 4 and 10E, at least two second pixel rows R2 include a plurality of second sub-pixel pairs 2120 arranged along a first direction, and two second sub-pixels 200 in at least two second sub-pixel pairs 2120 are a first pixel block 210 and a second pixel block 220 respectively, and the first pixel block 210 and the second pixel block 220 are alternately arranged along the first direction. For example, the first pixel block 210 and the second pixel block 220 in at least two second pixel columns C2 are alternately arranged along a second direction.

[0104] For example, as shown in FIGS. 4 and 10E, each second pixel row R2 includes a plurality of second sub-pixel pairs 2120 arranged along a first direction, and two second sub-pixels 200 in each second sub-pixel pair 2120 are a first pixel block 210 and a second pixel block 220 respectively, and the first pixel block 210 and the second pixel block 220 are alternately arranged along the first direction. For example, the first pixel block 210 and the second pixel block 220 in each second pixel column C2 are alternately arranged along a second direction.

[0105] For example, as shown in FIGS. 4 and 10E, a plurality of sub-pixels 40 include a plurality of minimum repeating units R, and one minimum repeating unit R includes a first sub-pixel 100, a first pixel block 210, a second pixel block 220, and a third sub-pixel 300. For example, at least two minimum repeating units R include a first sub-pixel 100, a first pixel block 210, a second pixel block 220, and a third sub-pixel 300. For example, each minimum repeating unit R includes a first sub-pixel 100, a first pixel block 210, a second pixel block 220, and a third sub-pixel 300. For example, each minimum repeating unit R includes sub-pixels 40 of two rows and four columns.

[0106] For example, as shown in FIGS. 4 and 10E, in the minimum repeating unit R, the first pixel block 210 and the first sub-pixel 100 constitute the first pixel unit R1, and the second pixel block 220 and the third sub-pixel 300 constitute the second pixel unit R2. For example, in at least two minimum repeating units R, the first pixel block 210 and the first sub-pixel 100 constitute the first pixel unit R1, and the second pixel block 220 and the third sub-pixel 300 constitute the second pixel unit R2. For example, in each minimum repeating unit R, the first pixel block 210 and the first sub-pixel 100 constitute the first pixel unit R1, and the second pixel block 220 and the third sub-pixel 300 constitute the second pixel unit R2.

[0107] The above-mentioned first pixel unit and second pixel unit are not pixels in a strict sense, that is, pixels defined by complete first, second, and third sub-pixels. Here, the minimum repeating unit refers to the minimum repeating unit in which the pixel array structure may include a plurality of repeating arrays.

[0108] For example, the first sub-pixel 100 and the third sub-pixel 300 are shared sub-pixels, and a virtual algorithm can be used to realize the display of two virtual pixel units with four sub-pixels. For example, in the same row of repeating units, the first sub-pixel 100 of the second repeating unit, the third sub-pixel 300 of the first repeating unit, and the second sub-pixel 200 of the first repeating unit close to the second repeating unit form a virtual pixel unit. At the same time, the first sub-pixel 100 of the second repeating unit also forms a virtual pixel unit with the third sub-pixel 300 of the repeating unit and the second sub-pixel 200 of the repeating unit close to the first repeating unit. Furthermore, the third sub-pixel 300 within the second repeating unit forms a virtual pixel unit with another second sub-pixel 200 within the repeating unit and the first sub-pixel 100 of the third repeating unit, thereby effectively improving the resolution of the display substrate.

[0109] For example, as shown in FIGS. 4, 6, and 10E, in the first pixel unit R1, the first pixel block 210 is located on the side of the first sub-pixel 100 away from the binding region 21. In the second pixel unit R2, the second pixel block 220 is located on the side of the third sub-pixel 300 away from the binding region 21.

[0110] For example, the arrow in the Y direction points upward, and the arrow in the X direction points to the right. The first pixel block 210 of the first pixel unit R1 is located in the upper right of the first sub-pixel 100, and the second pixel block 220 of the second pixel unit R2 is located in the upper right of the third sub-pixel 300.

[0111] In the first pixel unit and the second pixel unit of the display substrate provided by the embodiments of the present disclosure, by changing the first sub-pixel and the third sub-pixel and borrowing the second sub-pixels at different positions, the pixel space and the design are optimized, the flatness of the first electrode of the light-emitting element is improved, the pixel space structure is optimized, and the reduction of the lower frame is achieved.

[0112] For example, as shown in FIGS. 4 and 5, in the same sub-pixel of at least one of the first sub-pixel 100 and the third sub-pixel 300, the channel region of the light-emitting control transistor T6 is located on the side away from the binding region 21 than the center of the light-emitting region of the light-emitting element 410. For example, in the same sub-pixel of the first sub-pixel 100 and the third sub-pixel 300, the channel regions of the light-emitting control transistors T6 are both located on the side away from the binding region 21 than the center of the light-emitting region of the light-emitting element 410.

[0113] For example, as shown in FIG. 10E, the first sub-pixel 100 can form a first pixel unit together with the second sub-pixel 200 located at its upper right or the second sub-pixel 100 located at its lower right. Similarly, the third sub-pixel 300 can form a second pixel unit together with the second sub-pixel 200 located at its upper right or the second sub-pixel 100 located at its lower right. In an embodiment of the present disclosure, in the first sub-pixel 100, the light-emitting control transistor T6 is located above the light-emitting region, and the first sub-pixel 100 forms a first pixel unit together with the second sub-pixel 200 located at its upper right. Thereby, the design of the pixel circuit is facilitated, the shape of the flattening pad of the second conductive layer changes, the possibility of affecting the flatness of the pixel is reduced, which contributes to preventing the occurrence of color bleeding, and further, the influence on the image quality of a low gray scale can be prevented. The influence on the capacitance of the node corresponding to the first electrode of the light-emitting element can also be reduced. When the capacitance here is large, in the case of a low gray scale, it is necessary to fully charge the capacitance of the node corresponding to the first electrode of the light-emitting element. As a result, in the low gray scale, the voltage for charging the node decreases, and it takes time (response time) until the pixel lights up, which affects the image quality. Similarly, in the third sub-pixel 300, the light-emitting control transistor T6 is located above the light-emitting region, and the third sub-pixel forms a second pixel unit together with the second sub-pixel 200 located at its upper right, thereby facilitating the design of the pixel circuit.

[0114] For example, as shown in FIGS. 4, 9A, 10A to 10E, in the first pixel unit R1, the pixel circuits of the first pixel block 210 and the first sub-pixel 100 are arranged along the first direction, and in the second pixel unit R2, the pixel circuits of the second pixel block 220 and the third sub-pixel 300 are arranged along the first direction. For example, the pixel circuits of two sub-pixels located in the same pixel unit are arranged along the first direction to facilitate the borrowing of pixels.

[0115] For example, as shown in FIGS. 4, 9A, 10A to 10E, in the first pixel unit R1, the active semiconductor pattern 500 of the first pixel block 210 and the active semiconductor pattern 500 of the first sub-pixel 100 are symmetrically distributed with respect to a straight line located therebetween and extending along the second direction. In the second pixel unit R2, the active semiconductor pattern 500 of the second pixel block 220 and the active semiconductor pattern 500 of the third sub-pixel 300 are symmetrically distributed with respect to a straight line located therebetween and extending along the second direction, which helps to save the distribution space of the active semiconductor pattern.

[0116] For example, as shown in FIGS. 4, 9A, 10A to 10E, the active semiconductor pattern 500 of the first pixel block 210 in the first pixel unit R1 and the active semiconductor pattern 500 of the third sub-pixel 300 located in the second pixel portion R2 and adjacent to the first pixel block 210 are of an integral structure, which not only saves the distribution space of the active semiconductor pattern, but also enables the two data cables to be configured to overlap with the light-emitting region of the second sub-pixel, thereby improving the flatness of the light-emitting functional layer in the light-emitting region of the second sub-pixel. For example, the active semiconductor pattern 500 of the second pixel block 220 in the second pixel unit R2 and the active semiconductor pattern 500 of the first sub-pixel 100 located in the first pixel portion R1 and adjacent to the second pixel block 220 are of an integral structure, which not only saves the distribution space of the active semiconductor pattern, but also enables the two data cables to be configured to overlap with the light-emitting region of the second sub-pixel, thereby improving the flatness of the light-emitting functional layer in the light-emitting region of the second sub-pixel.

[0117] For example, as shown in FIGS. 4, 9A, 10A to 10E, two data cables 710 are respectively provided on both sides in the X direction of the first sub-pixel 100. For example, two data cables 710 are provided between the adjacent first sub-pixel 100 and the third sub-pixel 300 arranged in the X direction.

[0118] For example, as shown in FIGS. 4 and 10E, the first electrode 411 of the light-emitting element 410 includes a main body electrode 4111 and a connection electrode 4112 that are electrically connected to each other. The main body electrode 4111 overlaps with the light-emitting region 401 of the light-emitting element 410, and the connection electrode 4112 does not overlap with the light-emitting region 401 and is electrically connected to the light-emitting control transistor T6. For example, the main body electrode 4111 and the connection electrode 4112 may have an integrated structure.

[0119] For example, as shown in FIGS. 4 and 10A to 10E, the shape of the main body electrode 4111 is substantially the same as the shape of the light-emitting region 401, and is, for example, a quadrilateral. For example, the orthographic projection of the light-emitting region 401 onto the base substrate 11 is located within the orthographic projection of the main body electrode 4111 onto the base substrate 11.

[0120] For example, as shown in FIGS. 4 and 10A to 10E, in the first sub-pixel 100 and the third sub-pixel 300, the orthographic projection of at least a part of the main body electrode 4111 onto the base substrate 11 overlaps with the orthographic projection of the pad 721 onto the base substrate 11. For example, in the first sub-pixel 100 and the third sub-pixel 300, the orthographic projection of the center of the main body electrode 4111 onto the base substrate 11 is located within the orthographic projection of the pad 721 onto the base substrate 11. For example, in the first sub-pixel 100 and the third sub-pixel 300, the orthographic projection of the center of the light-emitting region 401 onto the base substrate 11 is located within the orthographic projection of the pad 721 onto the base substrate 11. For example, in the first sub-pixel 100 and the third sub-pixel 300, the orthographic projection of the light-emitting region 401 onto the base substrate 11 is located within the orthographic projection of the pad 721 onto the base substrate 11.

[0121] For example, as shown in FIGS. 4 and 10A to 10E, in the first sub-pixel 100 and the third sub-pixel 300, the orthographic projection of the main body electrode 4111 onto the base substrate 11 overlaps with the orthographic projections of the reset power signal line 610, the connection structure 620, and the second part 640 of the second reset power signal line onto the base substrate 11. In the first sub-pixel 100 and the third sub-pixel 300, the orthographic projection of each main body electrode 4111 onto the base substrate 11 overlaps with the orthographic projections of the two connection structures 620 onto the base substrate 11.

[0122] For example, as shown in FIGS. 4 and 10A to 10E, the two connection structures 620 overlapping the main electrode 4111 in the first sub-pixel 100 and the third sub-pixel 300 are distributed substantially symmetrically with respect to the center line extending along the Y direction of the main electrode 4111, improving the flatness of the sub-pixel. For example, the reset power signal line 610 overlapping the main electrode 4111 of the first sub-pixel 100 and the third sub-pixel 300 substantially covers the center line extending along the X direction of the main electrode 4111, improving the flatness of the sub-pixel.

[0123] For example, as shown in FIGS. 4 and 10A to 10E, the orthographic projection of the main electrode 4111 of the second sub-pixel 200 onto the base substrate 11 overlaps the orthographic projections of the pad 631, the data cable 710, and the second power signal line 720 onto the base substrate 11.

[0124] For example, as shown in FIGS. 4 and 10A to 10E, the orthographic projection of the main electrode 4111 in the second sub-pixel 200 onto the base substrate 11 overlaps the two data cables 710, and the portions of the two data cables 710 overlapping the main electrode 4111 are distributed symmetrically with respect to the center line extending along the Y direction of the main electrode 4111, improving the flatness of the sub-pixel.

[0125] For example, as shown in FIGS. 4 and 10A to 10E, the second conductive layer 700 further includes a first overlapping portion 701 (for example, a part of the pad 721) overlapping at least one of the light-emitting regions 401 of the first sub-pixel 100 and the third sub-pixel 300, and the ratio of the area of the first overlapping portion 701 to the area of the light-emitting region 401 is 0.6 to 1. For example, the ratio of the area of the first overlapping portion 701 to the area of the light-emitting region 401 is 0.7 to 0.9. For example, the ratio of the area of the first overlapping portion 701 to the area of the light-emitting region 401 is 0.75 to 0.85.

[0126] For example, as shown in FIGS. 4 and 10A to 10E, the first overlapping portion 701 is distributed substantially symmetrically with respect to a straight line extending along the second direction.

[0127] For example, as shown in FIGS. 4 and 10A to 10E, the second conductive layer 700 further includes a second overlapping portion 702 (e.g., a part of the data cable 710) that overlaps with the light-emitting region 401 of the second sub-pixel 200. The second overlapping portion 702 is distributed substantially symmetrically with respect to a straight line extending along the second direction.

[0128] For example, in each sub-pixel 40, the connection electrode 4112 is electrically connected to the light-emitting control transistor T6 via the first connection structure 660 and the second connection structure 730. For example, the second connection structure 730 has two ends, one end overlaps with the connection electrode 4112 and is electrically connected to the connection electrode 4112 via a via hole in the insulating layer, and the other end overlaps with the first connection structure 660 and is electrically connected to the first connection structure 660 via a via hole in another insulating layer.

[0129] For example, as shown in FIGS. 4 and 10A to 10E, in at least one of the first sub-pixel 100 and the third sub-pixel 300, the channel region of the light-emitting control transistor T6 is located on the side away from the binding region 21 than the center of the body electrode 4111. For example, in the same sub-pixel of the first sub-pixel 100 and the third sub-pixel 300, the channel regions of the light-emitting control transistors T6 are both located on the side away from the binding region 21 than the center of the body electrode 4111. In the same sub-pixel in at least one of the first sub-pixel 100 and the third sub-pixel 300, the connection electrode 4112 is located on the side away from the binding region 21 of the body electrode 4111.

[0130] For example, as shown in FIGS. 4 to 6 and 10A to 10E, the row of the sub-pixel 40 closest to the binding region 21 is the first pixel row R1. For example, the row of the sub-pixel 40 closest to the binding region 21 includes the first sub-pixel 100 and the third sub-pixel 300 arranged alternately. For example, the row of the sub-pixel 40 closest to the binding region 21 includes the red sub-pixel 100 and the blue sub-pixel 300 arranged alternately.

[0131] For example, as shown in FIGS. 4 to 6 and FIGS. 10A to 10E, the distances between the center of the channel region of the light emission control transistor T6 of the same second sub-pixel 200 and the light emission region 401 of the light emitting element 410, and the bonding region 210 are the first distance and the second distance respectively, and the first distance is greater than the second distance. For example, in the channel region of the light emission control transistor T6 of the same second sub-pixel 200 and the light emission region 401 of the light emitting element 410, the channel region is farther from the bonding region 21 than the light emission region 401 of the light emitting element 410.

[0132] For example, as shown in FIGS. 4 to 6 and FIGS. 10A to 10E, in at least one of the first sub-pixel 100 and the third sub-pixel 300, the apex angle of the light emission region 401 of the light emitting element 410 includes the first corner portion A1 and the second corner portion A2 arranged opposite to each other, and the distance from the intersection of the extension lines of the two sides constituting the first corner portion A1 to the center of the light emission region 401 is greater than the distance from the intersection of the two sides or their extension lines constituting the second corner portion A2 to the center of the light emission region 401. For example, in the first sub-pixel 100, the apex angle of the light emission region 401 of the light emitting element 410 includes the first corner portion A1 and the second corner portion A2 arranged opposite to each other.

[0133] For example, as shown in FIGS. 4 to 6 and FIGS. 10A to 10E, at least one of the first sub-pixel 100 and the third sub-pixel 300 includes a first type of sub-pixel 40-1 and a second type of sub-pixel 40-2. In different types of sub-pixels, the direction from the vertex of the first corner portion A1 to the vertex of the second corner portion A2 is different. In the first type of sub-pixel 40-1 and the second type of sub-pixel 40-2, the direction from the vertex of the first corner portion A1 to the vertex of the second corner portion A2 is the first pointing direction and the second pointing direction respectively, and the first pointing direction is opposite to the second pointing direction. For example, the first sub-pixel 100 includes the first type of sub-pixel 40-1 and the second type of sub-pixel 40-2.

[0134] For example, the first pointing direction is the direction pointed by the arrow in the U direction shown in the figure, the second pointing direction is the direction opposite to the direction pointed by the arrow in the U direction, and the first pointing direction and the second pointing direction may be interchangeable with each other. For example, the first pointing direction may be the direction pointed by the arrow in the V direction shown in the figure, the second pointing direction may be the direction opposite to the direction pointed by the arrow in the V direction, and the first pointing direction and the second pointing direction are interchangeable with each other.

[0135] For example, as shown in FIGS. 4 to 6 and FIGS. 10A to 10E, the first corner A1 of the light-emitting region of the third sub-pixel 300 may be a rounded chamfer, and the distance between the first corner A1 of the light-emitting region of the third sub-pixel 300 and the apex angle of the light-emitting region of the first sub-pixel 100 facing the first corner A1 is the first corner pitch. The distance between the second corner A2 of the light-emitting region of the third sub-pixel 300 and the apex angle of the light-emitting region of the first sub-pixel 100 facing the second corner A2 is the second corner pitch, and the first corner pitch is larger than the second corner pitch.

[0136] The above-mentioned rounded chamfer can refer to the apex angle formed by a curve, and the curve may be an arc, a curve cut from an ellipse, or an irregular curve such as a wavy line. The embodiments of the present disclosure schematically show that the curve has a shape protruding outward with respect to the center of the sub-pixel, but is not limited thereto, and the curve may have a shape recessed inward with respect to the center of the sub-pixel. For example, when the curve is an arc, the range of the central angle of the arc may be 10° to 150°. For example, the range of the central angle of the arc may be 60° to 120°. For example, the range of the central angle of the arc may be 90°. For example, the length of the curve of the rounded chamfer included in the first corner 111 may be 10 to 60 microns.

[0137] For example, as shown in FIGS. 4 to 6 and FIGS. 10A to 10E, at least one of the first sub-pixel 100 and the third sub-pixel 300 further includes a third type of sub-pixel 40-3 and a fourth type of sub-pixel 40-4. In the third type of sub-pixel 40-3 and the fourth type of sub-pixel 40-4, the directions from the vertex of the first corner A1 to the vertex of the second corner A2 are the third pointing direction and the fourth pointing direction respectively, the third pointing direction is opposite to the fourth pointing direction, and the third pointing direction intersects the first pointing direction. For example, the first sub-pixel 100 includes the third type of sub-pixel 40-3 and the fourth type of sub-pixel 40-4.

[0138] For example, the third pointing direction may be the direction pointed by the arrow in the V direction, and the fourth pointing direction may be the direction opposite to the direction pointed by the arrow in the V direction. The third pointing direction and the fourth pointing direction are interchangeable. For example, the third pointing direction may be the direction pointed by the arrow in the U direction, and the fourth pointing direction may be the direction opposite to the direction pointed by the arrow in the U direction. The third pointing direction and the fourth pointing direction are interchangeable.

[0139] FIGS. 11A to 11E are schematic diagrams of pixel arrays of different examples according to embodiments of the present disclosure.

[0140] For example, the difference between the pixel array shown in FIG. 11A and the pixel array shown in FIG. 10E is that the first sub-pixel 100 can at least include the first type of sub-pixel shown in FIG. 10E, but is not limited thereto. The first sub-pixel 100 may further include at least one of the second type of sub-pixel, the third type of sub-pixel, and the fourth type of sub-pixel shown in FIG. 10E. Embodiments of the present disclosure are not limited to only the first sub-pixel or the third sub-pixel. Any two types of sub-pixels of different colors or three types of sub-pixels of different colors among the first sub-pixel, the second sub-pixel, and the third sub-pixel can all include at least one of the first type of sub-pixel, the second type of sub-pixel, the third type of sub-pixel, and the fourth type of sub-pixel.

[0141] For example, the difference between the pixel array shown in FIG. 11B and the pixel array shown in FIG. 10E is that the third sub-pixel 300 includes only two types of sub-pixels, but is not limited thereto. The third sub-pixel 300 may include only one type of sub-pixel, or only three types of sub-pixels. For example, when the third sub-pixel 300 includes only one type of sub-pixel, the one type of sub-pixel may be any type of sub-pixel shown in FIG. 10E. When the third sub-pixel 300 includes two types of sub-pixels, the two types of sub-pixels may be the first type of sub-pixel and the second type of sub-pixel, or the third type of sub-pixel and the fourth type of sub-pixel shown in FIG. 10E, but is not limited thereto. They may also be the first type of sub-pixel and the third type of sub-pixel, or the second type of sub-pixel and the fourth type of sub-pixel, or the first type of sub-pixel and the fourth type of sub-pixel, or the second type of sub-pixel and the third type of sub-pixel. In the embodiments of the present disclosure, this is not limited.

[0142] For example, the difference between the pixel array shown in FIG. 11C and the pixel array shown in FIG. 10E is that each sub-pixel does not include any of the four types of sub-pixels shown in FIG. 10E. For example, as shown in FIG. 11C, the edges of the light-emitting regions of the first sub-pixel 100 and the third sub-pixel 300 both bend toward the center of the light-emitting region.

[0143] The shape of the light-emitting region of each sub-pixel is not limited to the shape shown in the figure, and can be selected from an elliptical shape, a circular shape, a square shape, an elongated strip shape, a rhombus shape, a trapezoidal shape, or other shapes.

[0144] For example, the sub-pixel arrays shown in FIGS. 11D and 11E are different from the sub-pixel array shown in FIG. 10E. For example, the pixel arrays of the first sub-pixel 100, the second sub-pixel 200, and the third sub-pixel 300 may be a real pixel array, a triangular array, a mosaic pixel array, or the like.

[0145] For example, as shown in FIG. 11D, the first sub-pixel 100, the second sub-pixel 200, and the third sub-pixel 300 may be periodically arranged in order along the X direction or the Y direction. For example, as shown in FIG. 11E, the orthographic projections of the light-emitting regions of the first sub-pixel 100 and the second sub-pixel 200 onto a straight line extending along the X direction overlap.

[0146] The embodiments of the present disclosure do not limit the shapes of the light-emitting regions of the first sub-pixel, the second sub-pixel, and the third sub-pixel and the arrangement of the sub-pixels in the display substrate having the pixel circuit shown in FIGS. 4 to 10C.

[0147] Another embodiment of the present disclosure provides a display device including any one of the above display substrates. The display device provided by the embodiments of the present disclosure contributes to reducing the lower frame of the display device by fully utilizing the pixel space by designing the pixel circuit located in the display area.

[0148] For example, the display device provided by the embodiments of the present disclosure may be an organic light-emitting diode display device.

[0149] For example, the display device may further include a cover located on the display side of the display substrate.

[0150] For example, the display device may be any product or component having a display function, such as a mobile phone, a tablet computer, a notebook computer, a navigator, etc., equipped with an under-screen camera, and the present embodiment is not limited thereto.

[0151] The following points need to be explained. (1) The drawings of the embodiments of the present disclosure include only the structures related to the embodiments of the present disclosure, and common designs can be referred to for other structures. (2) The features in the same and different embodiments of the present disclosure can be combined if there is no contradiction.

[0152] The above description is only an exemplary embodiment of the present disclosure and is not used to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A display substrate including a display area and a peripheral area located on at least one side of the display area, a base substrate, in a plurality of sub-pixels located on the base substrate, at least a part of the sub-pixels located in the display area includes a light-emitting element and a pixel circuit, the light-emitting element includes a light-emitting functional layer, a first electrode and a second electrode located on both sides of the light-emitting functional layer in a direction perpendicular to the base substrate, the first electrode is located between the light-emitting functional layer and the base substrate, the pixel circuit includes a driving transistor and a light-emitting control transistor, and the first electrode of the light-emitting element is electrically connected to the light-emitting control transistor, a plurality of sub-pixels, including a binding area located in the peripheral area and on a first side of the display area, the pixel circuit includes an active semiconductor pattern, and the active semiconductor pattern includes a channel region, a source and a drain region of each transistor, In the same pixel circuit, the channel region of the light-emitting control transistor is located on a side away from the binding area from the channel region of the driving transistor, a display substrate.

2. In the sub-pixel closest to the binding area, one end of the active semiconductor pattern of the pixel circuit closest to the binding area is a first end, one end of the first electrode of the light-emitting element closest to the binding area is a second end, and the second end is closer to the binding area than the first end. The display substrate according to claim 1.

3. In the same sub-pixel among at least one sub-pixel, the channel region of the light-emitting control transistor is located on a side away from the binding area from the center of the light-emitting area of the light-emitting element. The display substrate according to claim 1 or 2.

4. The plurality of sub-pixels includes a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels. The plurality of first sub-pixels and the plurality of third sub-pixels are alternately arranged along a first direction and a second direction such that a plurality of first pixel rows and a plurality of first pixel columns are formed. The plurality of second sub-pixels are arranged in an array along the first direction and the second direction such that a plurality of second pixel rows and a plurality of second pixel columns are formed. The plurality of first pixel rows and the plurality of second pixel rows are alternately arranged along the second direction and are offset from each other in the first direction. The plurality of first pixel columns and the plurality of second pixel columns are alternately arranged along the first direction and are offset from each other in the second direction. The first direction intersects the second direction. The second pixel row includes a plurality of second sub-pixel pairs arranged along the first direction. Two second sub-pixels in a second sub-pixel pair are a first pixel block and a second pixel block, respectively. The first pixel block and the second pixel block are alternately arranged along the first direction. The first pixel block and the second pixel block in the second pixel column are alternately arranged along the second direction. The plurality of sub-pixels includes a plurality of minimum repeating units. One minimum repeating unit includes a first sub-pixel, a first pixel block, a second pixel block, and a third sub-pixel. In the minimum repeating unit, the first pixel block and the first sub-pixel constitute a first pixel unit, and the second pixel block and the third sub-pixel constitute a second pixel unit. In the first pixel unit, the first pixel block is located on a side of the first sub-pixel away from the bonding region. In the second pixel unit, the second pixel block is located on a side of the third sub-pixel away from the bonding region. The display substrate according to any one of claims 1 to 3.

5. In at least one of the same sub-pixels of the first sub-pixel and the third sub-pixel, a channel region of the light emission control transistor is located on a side away from the bonding region than a center of a light emission region of the light emitting element. The display substrate according to claim 4.

6. The first electrode of the light-emitting element includes a main body electrode and a connection electrode that are electrically connected to each other. The main body electrode overlaps with the light-emitting region of the light-emitting element, the connection electrode does not overlap with the light-emitting region, and is electrically connected to the light-emitting control transistor. The display substrate according to claim 4 or 5, wherein in at least one of the same sub-pixels of the first sub-pixel and the third sub-pixel, a channel region of the light-emitting control transistor is located on a side farther from the bonding region than the center of the main body electrode.

7. In a channel region of the light-emitting control transistor and a light-emitting region of the light-emitting element of the same second sub-pixel, the channel region is farther from the bonding region than the light-emitting region of the light-emitting element. The display substrate according to any one of claims 4 to 6.

8. The display substrate according to any one of claims 4 to 7, wherein a shape of a channel region of the driving transistor includes a U-shape, and an opening of the U-shape faces a side away from the bonding region.

9. The display substrate according to any one of claims 4 to 8, wherein a row of sub-pixels closest to the bonding region is the first pixel row.

10. In the first pixel unit, the pixel circuit of the first pixel block and the pixel circuit of the first sub-pixel are arranged along the first direction. In the second pixel unit, the pixel circuit of the second pixel block and the pixel circuit of the third sub-pixel are arranged along the first direction. The display substrate according to any one of claims 4 to 9.

11. In the first pixel unit, an active semiconductor pattern of the first pixel block and an active semiconductor pattern of the first sub-pixel are symmetrically distributed with respect to a straight line that is located therebetween and extends along the second direction. In the second pixel unit, an active semiconductor pattern of the second pixel block and an active semiconductor pattern of the third sub-pixel are symmetrically distributed with respect to a straight line that is located therebetween and extends along the second direction. The display substrate according to any one of claims 4 to 10.

12. A first conductive layer located between the first electrode of the light-emitting element and the base substrate, A second conductive layer located between the first conductive layer and the first electrode of the light-emitting element, The first conductive layer includes a first connection structure and a first power signal line, the second conductive layer includes a data cable, a second connection structure, and a second power signal line, and the second power signal line is electrically connected to the first power signal line. The first pole of the light emission control transistor is electrically connected to the drive transistor, and the second pole of the light emission control transistor is electrically connected to the first electrode of the light emitting element through the first connection structure and the second connection structure. The display substrate according to any one of claims 4 to 11.

13. The second conductive layer further includes a first overlapping portion overlapping at least one of the light emitting regions of the first sub-pixel and the third sub-pixel. The ratio of the area of the first overlapping portion to the area of the light emitting region is 0.6 to 1, and the first overlapping portion is substantially symmetrically distributed with respect to a straight line extending along the second direction. The display substrate according to claim 12.

14. The second conductive layer further includes a second overlapping portion overlapping the light emitting region of the second sub-pixel. The second overlapping portion is substantially symmetrically distributed with respect to a straight line extending along the second direction. The display substrate according to claim 12 or 13.

15. In at least one of the first sub-pixel and the third sub-pixel, the apex angle of the light emitting region of the light emitting element includes a first corner portion and a second corner portion arranged opposite to each other. The distance from the intersection of the extension lines of the two sides constituting the first corner portion to the center of the light emitting region is greater than the distance from the intersection of the two sides or their extension lines constituting the second corner portion to the center of the light emitting region. At least one of the first sub-pixel and the third sub-pixel includes a first type of sub-pixel and a second type of sub-pixel. In different types of sub-pixels, the direction from the apex of the first corner portion to the apex of the second corner portion is different. In the first type of sub-pixel and the second type of sub-pixel, the direction from the apex of the first corner portion to the apex of the second corner portion is the first pointing direction and the second pointing direction respectively, and the first pointing direction is opposite to the second pointing direction. The display substrate according to any one of claims 4 to 14.

16. At least one of the first sub-pixel and the third sub-pixel further includes a third type of sub-pixel and a fourth type of sub-pixel. In the third type of sub-pixel and the fourth type of sub-pixel, the direction from the vertex of the first corner to the vertex of the second corner is a third direction of orientation and a fourth direction of orientation, respectively, the third direction of orientation is opposite to the fourth direction of orientation, and the first direction of orientation intersects the third direction of orientation. The display substrate according to claim 15.

17. One of the first sub-pixel and the third sub-pixel is a red sub-pixel configured to emit red light, and the other of the first sub-pixel and the third sub-pixel is a blue sub-pixel configured to emit blue light. The second sub-pixel is a green sub-pixel configured to emit green light. The display substrate according to any one of claims 4 to 16.

18. A display device including the display substrate according to any one of claims 1 to 17.

Images