Display panel and display device

Abstract

Provided are a display panel and a display device. The display panel includes a display area (AA), a light-emitting unit (OLED) located in the display area (AA), and a pixel driving circuit for driving the light-emitting unit (OLED). The pixel driving circuit is connected to a first electrode of the light-emitting unit (OLED). The display panel further includes a base substrate (90), a first power line (VSS1), a second power line (VSS2), and a common electrode layer. The first power line (VSS1) is located in the display area (AA) of the display panel. The orthographic projection of the first power line (VSS1) onto the base substrate (90) extends along a first direction (X). The second power line (VSS2) is located in the display area (AA) of the display panel. The orthographic projection of the second power line (VSS2) onto the base substrate extends along a second direction (Y). The second direction (Y) intersects with the first direction (X). At least a part of the second power line (VSS2) is connected to at least a part of the first power line (VSS1) through vias. The common electrode layer is located on one side of the base substrate (90). The common electrode layer is used to form a second electrode of the light-emitting unit (OLED). The common electrode layer is connected to the first power line (VSS1) and the second power line (VSS2). The display panel has excellent display uniformity.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and in particular, to a display panel and a display device.

Background Art

[0002] In related technologies, the electrodes of the light-emitting units in a display panel share a common electrode. However, due to the large self-resistance of the common electrode, the electrode voltages of the light-emitting units at different positions on the display panel are different, and furthermore, the display of the display panel becomes uneven.

[0003] It should be noted that the information disclosed in the above background art part is only used to enhance the understanding of the background of the present disclosure, and may include information that does not constitute prior art known to those skilled in the art.

Summary of the Invention

[0004] One aspect of the present disclosure provides a display panel, where the display panel includes a display area, a light-emitting unit located in the display area, and a pixel driving circuit for driving the light-emitting unit. The pixel driving circuit is connected to a first electrode of the light-emitting unit. The display panel further includes a base substrate, a first power line, a second power line, and a common electrode layer. The first power line is located in the display area of the display panel, and the orthographic projection of the first power line on the base substrate extends along a first direction. The second power line is located in the display area of the display panel, and the orthographic projection of the second power line on the base substrate extends along a second direction. The second direction intersects the first direction. At least a part of the second power line is connected to at least a part of the first power line through vias. The common electrode layer is located on one side of the base substrate and is used to form a second electrode of the light-emitting unit. The common electrode layer is connected to the first power line and the second power line.

[0005] In an exemplary embodiment of the present disclosure, both ends of the first power line are respectively connected to the common electrode layer, and both ends of the second power line are respectively connected to the common electrode layer.

[0006] In an exemplary embodiment of the present disclosure, each of the first power lines is connected, via a via, to each of the second power lines that intersect the orthographic projection of the first power line onto the base substrate.

[0007] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes a driving transistor and a seventh transistor. A first pole of the seventh transistor is connected to a second initial signal line, and a second pole is connected to a first electrode of the light-emitting unit. The display panel further includes a first active layer, the first active layer is located between the base substrate and the common electrode layer, the first active layer includes a third active portion and a seventh active portion, the third active portion is used to form a channel region of the driving transistor, the seventh active portion is used to form a channel region of the seventh transistor, the orthographic projection of the second power line onto the base substrate and the orthographic projection of the third active portion onto the base substrate at least partially overlap, and the orthographic projection of the second power line onto the base substrate and the orthographic projection of the seventh active portion onto the base substrate at least partially overlap.

[0008] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes an N-type transistor and a P-type transistor, and the display panel further includes a first active layer, a second active layer, and a third conductive layer. The first active layer is located between the base substrate and the common electrode layer, and a partial structure of the first active layer is used to form a channel region of the P-type transistor. The second active layer is located between the base substrate and the common electrode layer, and a partial structure of the second active layer is used to form a channel region of the N-type transistor. The third conductive layer is located between the second active layer and the common electrode layer, and a partial structure of the third conductive layer is used to form a top gate of the N-type transistor. Here, at least a part of the first power line is located in the third conductive layer.

[0009] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes a driving transistor and a fifth transistor. A first pole of the fifth transistor is connected to a third power line, and a second pole thereof is connected to a first pole of the driving transistor. The display panel further includes a fifth conductive layer. The fifth conductive layer is located between the base substrate and the common electrode layer. The fifth conductive layer includes the third power line, and at least a part of the second power line is located in the fifth conductive layer.

[0010] In an exemplary embodiment of the present disclosure, the display panel further includes a third conductive layer, a fourth conductive layer, and a fifth conductive layer. The third conductive layer is located between the base substrate and the common electrode layer. The first power line is located in the third conductive layer. The fourth conductive layer is located between the third conductive layer and the common electrode layer. The fourth conductive layer includes a seventh bridge portion. The fifth conductive layer is located between the fourth conductive layer and the common electrode layer. The second power line is located in the fifth conductive layer. Here, a positive projection of the seventh bridge portion onto the base substrate and a positive projection of the first power line onto the base substrate at least partially overlap. A positive projection of the seventh bridge portion onto the base substrate and a positive projection of the second power line onto the base substrate at least partially overlap. The seventh bridge portion is connected to the first power line and the second power line via vias respectively.

[0011] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes a driving transistor, a sixth transistor, and a seventh transistor. A first pole of the sixth transistor is connected to a second pole of the driving transistor. A second pole of the sixth transistor is connected to a first electrode of the light emitting unit. A first pole of the seventh transistor is connected to a second initial signal line. A second pole of the seventh transistor is connected to a first electrode of the light emitting unit. The display panel further includes a first active layer. The first active layer is located between the base substrate and the third conductive layer. The first active layer includes a sixth active portion, a seventh active portion, and a tenth active portion. The sixth active portion is used to form a channel region of the sixth transistor. The seventh active portion is used to form a channel region of the seventh transistor. The tenth active portion is connected between the sixth active portion and the seventh active portion. A positive projection of the seventh bridge portion onto the base substrate and a positive projection of the tenth active portion onto the base substrate at least partially overlap.

[0012] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a fourth transistor. A first pole of the fourth transistor is connected to a data line, and a second pole thereof is connected to a first pole of the driving transistor. The fifth conductive layer further includes the data line. Here, a projection of the data line onto the base substrate and a projection of the third power line onto the base substrate extend along the second direction and are located in pixel driving circuits of the same column. A projection of the second power line located in the fifth conductive layer onto the base substrate is located between the projection of the data line onto the base substrate and the projection of the third power line onto the base substrate.

[0013] In an exemplary embodiment of the present disclosure, the first direction is the row direction, the second direction is the column direction, the display panel includes a plurality of repeating units distributed in the matrix direction, each repeating unit includes a first pixel driving circuit and a second pixel driving circuit distributed in the row direction, the first pixel driving circuit and the second pixel driving circuit are arranged in mirror symmetry, the pixel driving circuit includes a driving transistor and a capacitor, a first electrode of the capacitor is connected to a gate of the driving transistor, a second electrode of the capacitor is connected to a third power line, the display panel further includes a second conductive layer and a fifth conductive layer, the second conductive layer is located between the base substrate and the common electrode layer, the second conductive layer includes a first conductive portion, the first conductive portion is used to form the second electrode of the capacitor, the fifth conductive layer is located between the second conductive layer and the common electrode layer, the fifth conductive layer includes the third power line, each column of the pixel driving circuits is provided corresponding to one of the third power lines, the third power line includes a first extension portion, a second extension portion, and a third extension portion, the second extension portion is connected between the first extension portion and the third extension portion, a size of a positive projection of the second extension portion onto the base substrate in the row direction is larger than a size of a positive projection of the first extension portion onto the base substrate in the row direction, the size of the positive projection of the second extension portion onto the base substrate in the row direction is larger than a size of a positive projection of the third extension portion onto the base substrate in the row direction, where, in the same repeating unit, second extension portions in two adjacent third power lines are connected, and two adjacent first conductive portions in repeating units adjacent in the row direction are connected.

[0014] In an exemplary embodiment of the present disclosure, the second conductive layer further includes a first connection portion. In the repeating units adjacent in the row direction, the adjacent first conductive portions are connected via the first connection portion. The pixel driving circuit further includes a fifth transistor. A first pole of the fifth transistor is connected to the third power line. A second pole of the fifth transistor is connected to a first pole of the driving transistor. The display panel further includes a first active layer and a fourth conductive layer. The first active layer is located between the base substrate and the second conductive layer. The first active layer includes a third active portion, a fifth active portion, and a ninth active portion. The third active portion is used to form a channel region of the driving transistor. The fifth active portion is used to form a channel region of the fifth transistor. The ninth active portion is connected to a side where the fifth active portion is away from the third active portion. The ninth active portion is connected between two adjacent fifth active portions among the repeating units adjacent in the row direction. The fourth conductive layer is located between the second conductive layer and the fifth conductive layer. The fourth conductive layer includes a first bridge portion. The first bridge portion is connected to the ninth active portion and the first connection portion via vias respectively. The first bridge portion is connected to the third power line via a via.

[0015] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes a driving transistor, a first transistor, a second transistor, and a capacitor. A first pole of the first transistor is connected to the gate of the driving transistor. A second pole of the first transistor is connected to a first initial signal line. A first pole of the second transistor is connected to the gate of the driving transistor. A second pole of the second transistor is connected to a second pole of the driving transistor. A first pole of the capacitor is connected to the gate of the driving transistor. A second electrode of the capacitor is connected to a third power line. The display panel further includes a first active layer, a first conductive layer, a second active layer, a fourth conductive layer, and a fifth conductive layer. The first active layer is located between the base substrate and the common electrode layer. The first active layer includes a third active portion, which is used to form a channel region of the driving transistor. The first conductive layer is located between the first active layer and the common electrode layer. The first conductive layer includes a second conductive portion, and a positive projection of the second conductive portion onto the base substrate covers a positive projection of the third active portion onto the base substrate. The second conductive portion is used to form a gate of the driving transistor and a first electrode of the capacitor. The second active layer is located between the first conductive layer and the common electrode layer. The second active layer includes a first active portion, a second active portion, and a fifteenth active portion connected between the first active portion and the second active portion. The first active portion is used to form a channel region of the first transistor. The second active portion is used to form a channel region of the second transistor. The fourth conductive layer is located between the second active layer and the common electrode layer. The fourth conductive layer includes a fourth bridge portion, which is connected to the fifteenth active portion and the second conductive portion through vias respectively. The fifth conductive layer is located between the fourth conductive layer and the common electrode layer. The fifth conductive layer includes the third power line, and a positive projection of the third power line onto the base substrate covers positive projections of the first active portion, the second active portion, and the fourth bridge portion onto the base substrate.

[0016] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes a driving transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a capacitor. A first pole of the fourth transistor is connected to a data line, a second pole of the fourth transistor is connected to a first pole of the driving transistor, a first pole of the fifth transistor is connected to a third power line, a second pole of the fifth transistor is connected to a first pole of the driving transistor, a first pole of the sixth transistor is connected to a second pole of the driving transistor, a second pole of the seventh transistor is connected to a second pole of the sixth transistor, a first pole of the seventh transistor is connected to a second initial signal line, a first electrode of the capacitor is connected to a gate of the driving transistor, and a second electrode of the capacitor is connected to the third power line. The display panel further includes a first active layer and a first conductive layer. The first active layer is located between the base substrate and the common electrode layer, and the first active layer includes a third active portion, a fourth active portion, a fifth active portion, a sixth active portion, and a seventh active portion. The third active portion is used to form a channel region of the driving transistor, the fourth active portion is used to form a channel region of the fourth transistor, the fifth active portion is used to form a channel region of the fifth transistor, the sixth active portion is used to form a channel region of the sixth transistor, and the seventh active portion is used to form a channel region of the seventh transistor.The first conductive layer is located between the first active layer and the common electrode layer. The first conductive layer includes a second gate line, an enable signal line, a second reset signal line, and a second conductive portion. The orthographic projection of the second gate line onto the base substrate extends along the first direction and covers the orthographic projection of the fourth active portion onto the base substrate. A partial structure of the second gate line is used to form the gate of the fourth transistor. The orthographic projection of the enable signal line onto the base substrate extends along the first direction and covers the orthographic projection of the fifth active portion onto the base substrate and the orthographic projection of the sixth active portion onto the base substrate. A partial structure of the enable signal line is used to form the gate of the sixth transistor, and another partial structure of the enable signal line is used to form the gate of the fifth transistor. The orthographic projection of the second reset signal line onto the base substrate extends along the first direction and covers the orthographic projection of the seventh active portion onto the base substrate. A partial structure of the second reset signal line is used to form the gate of the seventh transistor. The orthographic projection of the second conductive portion onto the base substrate covers the orthographic projection of the third active portion onto the base substrate. The second conductive portion is used to form the gate of the driving transistor and the first electrode of the capacitor. Here, in the same pixel driving circuit, the orthographic projection of the second conductive portion onto the base substrate is located between the orthographic projection of the second gate line onto the base substrate and the orthographic projection of the enable signal line onto the base substrate, and the orthographic projection of the second reset signal line onto the base substrate is located on the side where the orthographic projection of the enable signal line onto the base substrate is away from the orthographic projection of the second conductive portion onto the base substrate.

[0017] In an exemplary embodiment of the present disclosure, the second gate line in the pixel driving circuit of a row is multiplexed as the second reset signal line in the pixel driving circuit of the previous row.

[0018] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a first transistor and a second transistor. A first pole of the first transistor is connected to the gate of the driving transistor. A second pole of the first transistor is connected to a first initial signal line. A first pole of the second transistor is connected to the gate of the driving transistor. A second pole of the second transistor is connected to a second pole of the driving transistor. The display panel further includes a second active layer and a third conductive layer. The second active layer is located between the first conductive layer and the common electrode layer. The second active layer includes a first active part and a second active part. The first active part is used to form a channel region of the first transistor. The second active part is used to form a channel region of the second transistor. The third conductive layer is located between the second active layer and the common electrode layer. The third conductive layer includes a first reset signal line and a first gate line. A positive projection of the first reset signal line onto the base substrate covers a positive projection of the first active part onto the base substrate. A partial structure of the first reset signal line is used to form a top gate of the first transistor. A positive projection of the first gate line onto the base substrate covers a positive projection of the second active part onto the base substrate. A partial structure of the first gate line is used to form a top gate of the second transistor. In the same pixel driving circuit, a positive projection of the first gate line onto the base substrate is located between a positive projection of the second conductive part onto the base substrate and a positive projection of a second gate line onto the base substrate. A positive projection of the first reset signal line onto the base substrate is located on a side where the positive projection of the second gate line onto the base substrate is away from the positive projection of the second conductive part onto the base substrate.

[0019] In an exemplary embodiment of the present disclosure, the display panel further includes a second conductive layer located between the first conductive layer and the second active layer. The second conductive layer includes a first initial signal line, a third reset signal line, and a third gate line. A positive projection of the first initial signal line onto the base substrate is located on a side where a positive projection of the first reset signal line onto the base substrate is away from a positive projection of the second conductive portion onto the base substrate. The third reset signal line is connected to the first reset signal line via a via, and a positive projection of the third reset signal line onto the base substrate covers a positive projection of the first active portion onto the base substrate. A partial structure of the third reset signal line is used to form a bottom gate of the first transistor. A positive projection of the third gate line onto the base substrate covers a positive projection of the second active portion onto the base substrate. A partial structure of the third gate line is used to form a bottom gate of the second transistor.

[0020] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes a seventh transistor. A first pole of the seventh transistor is connected to a second initial signal line, and a second pole is connected to a first electrode of the light emitting unit. The display panel further includes a fourth conductive layer located between the base substrate and the common electrode layer. The fourth conductive layer includes a fourth bridge portion. The fourth bridge portion is connected to a gate of the driving transistor via a via, and the second initial signal line is located in the fourth conductive layer.

[0021] In an exemplary embodiment of the present disclosure, the display panel further includes a third conductive layer, the third conductive layer is located between the first conductive layer and the common electrode layer, at least a part of the first power line is located in the third conductive layer, and a projection of the first power line located in the third conductive layer onto the base substrate is located between a projection of the second conductive part onto the base substrate and a projection of the second reset signal line onto the base substrate, and the projection of the first power line located in the third conductive layer onto the base substrate and the projection of the enable signal line onto the base substrate at least partially overlap.

[0022] In an exemplary embodiment of the present disclosure, an area of a projection of the first power line located in the third conductive layer onto the base substrate is S1, and an area of an overlap between the projection of the first power line located in the third conductive layer onto the base substrate and the projection of the enable signal line onto the base substrate is S2, where S2 / S1 is 80% or more.

[0023] In an exemplary embodiment of the present disclosure, the first transistor and the second transistor are N-type transistors, and the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are P-type transistors.

[0024] In an exemplary embodiment of the present disclosure, the display area includes a sector-out area and a normal display area. The plurality of first power lines include a first sub-power line, and two first cutouts located in the sector-out area are formed in the first sub-power line. The first sub-power line includes a first sub-power line portion located between the two first cutouts. The plurality of second power lines include a second sub-power line, and a second cutout located in the sector-out area is formed in the second sub-power line. The second sub-power line includes a second sub-power line portion divided by the second cutout. The second sub-power line portion is located in the sector-out area. The display panel further includes a plurality of data lines. The orthographic projection of the data lines onto the base substrate extends along the second direction. The plurality of data lines include a first data line. Here, the first data line is connected to the first sub-power line portion, and the first sub-power line portion is connected to the second sub-power line portion.

[0025] In an exemplary embodiment of the present disclosure, the display panel further includes a third conductive layer, a fourth conductive layer, and a fifth conductive layer. The third conductive layer is located between the base substrate and the common electrode layer. The third conductive layer includes the first sub-power line. The fourth conductive layer is located between the third conductive layer and the common electrode layer. The fourth conductive layer includes a seventh bridge portion and a tenth bridge portion. The fifth conductive layer is located between the fourth conductive layer and the common electrode layer. The fifth conductive layer includes the first data line and the second sub-power line. Here, the first data line is connected to the tenth bridge portion via a via. The tenth bridge portion is connected to the first sub-power line portion via a via. The seventh bridge portion is connected to the first sub-power line portion via a via. The second sub-power line portion is connected to the seventh bridge portion via a via.

[0026] In an exemplary embodiment of the present disclosure, the display panel further includes a first signal line and a second signal line. The first signal line is provided corresponding to a row of the pixel driving circuit, and a positive projection of the first signal line onto the base substrate extends along the first direction. The second signal line is provided corresponding to a column of the pixel driving circuit, and a positive projection of the second signal line onto the base substrate extends along the second direction. The display panel further includes a virtual pixel row and a virtual pixel column located in the display area. Here, the first signal line located in the virtual pixel row is multiplexed as the first power line, and the second signal line located in the virtual pixel column is multiplexed as the second power line.

[0027] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes a driving transistor and a fifth transistor. A first pole of the fifth transistor is connected to a third power line, a second pole is connected to a first pole of the driving transistor, and a gate is connected to an enable signal line. The first signal line includes the enable signal line.

[0028] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes a driving transistor and a fourth transistor. A first pole of the fourth transistor is connected to a data line, a second pole is connected to a first pole of the driving transistor, and the second signal line includes the data line.

[0029] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes a driving transistor and a capacitor. A first electrode of the capacitor is connected to the gate of the driving transistor, and a second electrode of the capacitor is connected to a third power line. The display panel further includes a second conductive layer and a fourth conductive layer. The second conductive layer is located between the base substrate and the common electrode layer. The second conductive layer includes a first conductive portion, and the first conductive portion is used to form the second electrode of the capacitor. The fourth conductive layer is located between the second conductive layer and the common electrode layer. The fourth conductive layer includes a first bridge portion, and the first bridge portion is connected to the first conductive portion via a via. Here, in the virtual pixel row, the first bridge portions are connected to each other, and the first signal line includes a signal line formed by the connected first bridge portions.

[0030] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a fourth transistor. A first pole of the fourth transistor is connected to a data line, a second pole is connected to a first pole of the driving transistor, and a gate is connected to a second gate line. The first signal line includes the second gate line.

[0031] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes a driving transistor. The display panel further includes a fourth conductive layer. The fourth conductive layer is located between the base substrate and the common electrode layer. The fourth conductive layer includes a fourth bridge portion, and the fourth bridge portion is connected to the gate of the driving transistor via a via. At least a part of the first power line is located in the fourth conductive layer.

[0032] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes a driving transistor, and the display panel further includes a first active layer and a light-shielding layer. The first active layer is located between the base substrate and the common electrode layer. The first active layer includes a third active portion, and the third active portion is used to form a channel region of the driving transistor. The light-shielding layer is located between the base substrate and the first active layer. The light-shielding layer includes a light-shielding portion, and a positive projection of the light-shielding portion onto the base substrate covers a positive projection of the third active portion onto the base substrate. At least a part of the second power line is located in the light-shielding layer.

[0033] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes a driving transistor and a capacitor. A first electrode of the capacitor is connected to a gate of the driving transistor, and a second electrode is connected to a third power line. The display panel further includes a second conductive layer. The second conductive layer is located between the base substrate and the common electrode layer. The second conductive layer includes a first conductive portion, and the first conductive portion is used to form the second electrode of the capacitor. At least a part of the first power line is located in the second conductive layer.

[0034] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes a driving transistor, a fourth transistor, and a capacitor. A first pole of the fourth transistor is connected to a data line, a second pole is connected to a first pole of the driving transistor, a first electrode of the capacitor is connected to a gate of the driving transistor, and a second electrode is connected to a third power line. The display panel further includes a first active layer and a second conductive layer. The first active layer is located between the base substrate and the common electrode layer. The first active layer includes a third active portion, a fourth active portion, and a nineteenth active portion. The third active portion is used to form a channel region of the driving transistor. The fourth active portion is used to form a channel region of the fourth transistor. The nineteenth active portion is connected between the third active portion and the fourth active portion. A size of a positive projection of the nineteenth active portion on the base substrate in a first direction is larger than a size of a positive projection of the fourth active portion on the base substrate in the first direction. The second conductive layer is located between the first active layer and the common electrode layer. The second conductive layer includes a first conductive portion and a fourth conductive portion. The first conductive portion is used to form a second electrode of the capacitor. The fourth conductive portion is connected to the first conductive portion. A positive projection of the fourth conductive portion on the base substrate and a positive projection of the nineteenth active portion on the base substrate at least partially overlap.

[0035] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes a P-type transistor, and the display panel further includes a first active layer, a first conductive layer, and a fourth conductive layer. The first active layer is located between the base substrate and the common electrode layer, and a partial structure of the first active layer is used to form a channel region of the P-type transistor. The first conductive layer is located between the first active layer and the common electrode layer, and the first conductive layer includes a first gate driving signal line. The first gate driving signal line includes a plurality of first gate driving signal line segments, and a positive projection of the first gate driving signal line segment onto the base substrate is distributed at intervals along the first direction, extends along the first direction, and a partial structure of the first gate driving signal line segment is used to form a gate of the P-type transistor. The fourth conductive layer is located between the first conductive layer and the common electrode layer, and the fourth conductive layer includes a first connection line. A positive projection of the first connection line onto the base substrate extends along the first direction and is connected to the first gate driving signal line segment in the same first gate driving signal line through vias respectively. Here, a sheet resistance of the fourth conductive layer is smaller than a sheet resistance of the first conductive layer.

[0036] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes an N-type transistor, and the display panel further includes a second active layer, a third conductive layer, and a fourth conductive layer. The second active layer is located between the first conductive layer and the common electrode layer. A partial structure of the second active layer is used to form a channel region of the N-type transistor. The third conductive layer is located between the second active layer and the common electrode layer. The third conductive layer includes a second gate driving signal line. The second gate driving signal line includes a plurality of segments of the second gate driving signal line. The orthographic projection of the segment of the second gate driving signal line onto the base substrate is distributed at intervals along the first direction, extends along the first direction, and a partial structure of the segment of the second gate driving signal line is used to form a gate of the N-type transistor. The fourth conductive layer is located between the third conductive layer and the common electrode layer. The fourth conductive layer includes a second connection line. The orthographic projection of the second connection line onto the base substrate extends along the first direction and is connected to the segment of the second gate driving signal line in the same second gate driving signal line through vias respectively. Here, the sheet resistance of the fourth conductive layer is smaller than that of the third conductive layer.

[0037] One aspect of the present disclosure provides a display device including the above-described display panel.

[0038] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory and do not limit the present disclosure.

Brief Description of the Drawings

[0039] Here, the drawings are incorporated into the specification, show embodiments that conform to the present disclosure, and are used to explain the principles of the present disclosure together with the specification. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and those skilled in the art can also obtain other drawings based on these drawings without creative labor.

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Embodiments for Carrying out the Invention

[0040] Next, with reference to the drawings, exemplary embodiments will be described in more detail. However, it should be understood that the exemplary embodiments can be implemented in various forms and are not limited to the examples described herein. In contrast, these embodiments are provided to make the present disclosure more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. Since the same reference numerals in the figures represent the same or similar structures, detailed descriptions are omitted.

[0041] The terms "one", "a", "the" are used to indicate the presence of one or more elements / components / etc., and the terms "comprising" and "having" are used to mean open inclusion, meaning elements / components / etc. that can exist in addition to the listed elements / components / etc.

[0042] As shown in FIG. 1, it is a circuit configuration diagram of a pixel driving circuit in the display panel of the present disclosure. The pixel driving circuit can include a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. Here, the first pole of the fourth transistor T4 is connected to the data signal terminal Da, the second pole of the fourth transistor T4 is connected to the first pole of the driving transistor T3, the gate of the fourth transistor T4 is connected to the second gate driving signal terminal G2, the first pole of the fifth transistor T5 is connected to the first power supply terminal VDD, the second pole of the fifth transistor T5 is connected to the first pole of the driving transistor T3, the gate of the fifth transistor T5 is connected to the enable signal line EM, the gate of the driving transistor T3 is connected to the node N, the first pole of the second transistor T2 is connected to the node N, the second pole of the second transistor T2 is connected to the second pole of the driving transistor T3, the gate of the second transistor T2 is connected to the first gate driving signal terminal G1, the first pole of the sixth transistor T6 is connected to the second pole of the driving transistor T3, the second pole of the sixth transistor T6 is connected to the second pole of the seventh transistor T7, the gate of the sixth transistor T6 is connected to the enable signal line EM, the first pole of the seventh transistor T7 is connected to the second initial signal line Vinit2, the gate of the seventh transistor T7 is connected to the second reset signal line Re2, the second pole of the first transistor T1 is connected to the node N, the first pole of the first transistor T1 is connected to the first initial signal line Vinit1, the gate of the first transistor T1 is connected to the first reset signal line Re1, the first electrode of the capacitor C is connected to the node N, and the second electrode of the capacitor C is connected to the first power supply terminal VDD. This pixel driving circuit is connected to one light-emitting unit OLED and is used to drive the light emission of the light-emitting unit. The light-emitting unit OLED can be connected between the second pole of the sixth transistor T6 and the second power supply terminal VSS. The first electrode of the light-emitting unit may be the anode of the light-emitting unit, and the second electrode of the light-emitting unit may be the cathode of the light-emitting unit.Here, the first transistor T1 and the second transistor T2 may be N-type transistors. For example, the first transistor T1 and the second transistor T2 may be N-type metal oxide transistors. N-type transistors have a small leakage current, and it is possible to avoid the node N leaking through the first transistor T1 and the second transistor T2 during the light-emitting stage. At the same time, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type transistors. For example, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type low-temperature polycrystalline silicon transistors. P-type transistors have a high carrier mobility and are advantageous for a display panel for realizing high resolution, high response speed, high pixel density, and high aperture ratio. The first initial signal line and the second initial signal line can output the same or different voltage signals according to the actual situation.

[0043] As shown in FIG. 2, it is a timing chart of each node in the driving method of the pixel driving circuit of FIG. 1. Here, G1 indicates the timing of the first gate driving signal terminal G1, G2 indicates the timing of the second gate driving signal terminal G2, Re1 indicates the timing of the first reset signal line Re1, Re2 indicates the timing of the second reset signal line Re2, EM represents the timing of the enable signal line EM, and Da indicates the timing of the data signal terminal Da. The driving method of this pixel driving circuit can include a first reset stage t1, a data writing stage t2, a second reset stage t3, and a light emitting stage t4. First reset stage t1: The first reset signal line Re1 outputs a high-level signal, the first transistor T1 is turned on, and the first initial signal line Vinit1 inputs an initial signal to the node N. Data writing stage t2: The first gate driving signal terminal G1 outputs a high-level signal, the second gate driving signal terminal G2 outputs a low-level signal, the fourth transistor T4 and the second transistor T2 are turned on, and at the same time the data signal terminal Da outputs a data signal to write the compensation voltage Vdata + Vth to the node N. Here, Vdata is the voltage of the data signal, and Vth is the threshold voltage of the driving transistor T3. In the second reset stage t3, the second reset signal line Re2 outputs a low-level signal, the seventh transistor T7 is turned on, and the second initial signal line Vinit2 inputs an initial signal to the second pole of the sixth transistor T6. Light emitting stage t4: The enable signal line EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light emitting unit to emit light by the compensation voltage Vdata + Vth stored in the capacitor C.

[0044] The formula for the output current of the driving transistor is as follows I=(μWCox / 2L)(Vgs-Vth) 2 Here, I is the output current of the driving transistor, μ is the carrier mobility, Cox is the gate capacitance per unit area, W is the channel width of the driving transistor, L is the length of the channel of the driving transistor, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor. The output current I of the driving transistor in the pixel driving circuit of the present disclosure is I = (μWCox / 2L)(Vdata + Vth - Vdd - Vth) 2 That is. This pixel driving circuit can avoid the influence of the threshold value of the driving transistor on its output current.

[0045] In this embodiment, the second electrode of the light-emitting unit OLED in the display panel shares a common electrode layer. However, since this common electrode layer has a large self-resistance, the voltage of the second electrode of the light-emitting cell varies depending on the position of the display panel, and finally the display of the display panel becomes uneven.

[0046] Based on this, in this embodiment, first, as shown in FIG. 3, a display panel is provided that schematically shows the structure of the display panel of the present disclosure. As shown in FIG. 3, this display panel includes a display area AA, an electrode ring VSS0, a first power line VSS1, a second power line VSS2, and a base substrate. The electrode ring VSS0 is located in the edge area around the display area AA. The orthographic projection of the first power line VSS1 onto the base substrate extends along the first direction X, and the orthographic projection of the second power line VSS2 onto the base substrate extends along the second direction. The first direction X and the second direction Y intersect. For example, the first direction X is the row direction and the second direction Y is the column direction. The first power line VSS1 and the second power line VSS2 can be located in different conductive layers. The first power line VSS1 and the second power line VSS2 whose orthographic projections onto the base substrate intersect can be connected via vias H to form a mesh structure. Here, the plurality of first power lines VSS1 may be respectively located in different conductive layers in the display panel, and the plurality of second power lines VSS2 may be respectively located in different conductive layers in the display panel. The first power line VSS1 can be connected to the electrode ring VSS0, the second power line VSS2 can be connected to the electrode ring VSS0, and the electrode ring VSS0 can be connected to the common electrode layer. Therefore, the first power line VSS1 and the second power line VSS2 that form the mesh structure can reduce the voltage difference between different positions on the common electrode layer. In addition, when the first power line VSS1 and the electrode ring VSS0 are located in different conductive layers, the first power line VSS1 and the electrode ring VSS0 can be connected via vias. When the first power line VSS1 and the electrode ring VSS0 are located in the same conductive layer, the first power line VSS1 and the electrode ring VSS0 can be directly connected. Similarly, when the second power line VSS2 and the electrode ring VSS0 are located in different conductive layers, the second power line VSS2 and the electrode ring VSS0 can be connected via vias. When the second power line VSS2 and the electrode ring VSS0 are located in the same conductive layer, the second power line VSS2 and the electrode ring VSS0 can be directly connected.

[0047] The display panel provided by this embodiment can include the pixel driving circuit shown in FIG. 1. In other embodiments, the pixel driving circuit in this display panel may have other structures.

[0048] In this embodiment example, the first power line VSS1 and the second power line VSS2 can be located in different conductive layers within the display panel. For example, in an exemplary embodiment, the display panel can include a base substrate, a light-shielding layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer that are sequentially stacked, where an insulating layer may be provided between the adjacent layers described above. As shown in FIGS. 4-18, FIG. 4 is a structural layout diagram of an embodiment example of the display panel of the present disclosure, FIG. 5 is a structural layout diagram of the light-shielding layer in FIG. 4, FIG. 6 is a structural layout diagram of the first active layer in FIG. 4, FIG. 7 is a structural layout diagram of the first conductive layer in FIG. 4, FIG. 8 is a structural layout diagram of the second conductive layer in FIG. 4, FIG. 9 is a structural layout diagram of the second active layer in FIG. 4, FIG. 10 is a structural layout diagram of the third conductive layer in FIG. 4, FIG. 11 is a structural layout diagram of the fourth conductive layer in FIG. 4, FIG. 12 is a structural layout diagram of the fifth conductive layer in FIG. 4, FIG. 13 is a structural layout diagram of the light-shielding layer and the first active layer in FIG. 4, FIG. 14 is a structural layout diagram of the light-shielding layer, the first active layer, and the first conductive layer in FIG. 4, FIG. 15 is a structural layout diagram of the light-shielding layer, the first active layer, the first conductive layer, and the second conductive layer in FIG. 4, FIG. 16 is a structural layout diagram of the light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer in FIG. 4, FIG. 17 is a structural layout diagram of the light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in FIG. 4, and FIG. 18 is a structural layout diagram of the light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in FIG. 4. The display panel can include a plurality of pixel driving circuits shown in FIG. 1. As shown in FIG. 4, among the plurality of pixel driving circuits, a first pixel driving circuit P1 and a second pixel driving circuit P2 that are distributed adjacent to each other in a first direction X in which a mirror symmetry plane BB can be arranged symmetrically can be included. Here, the mirror symmetry plane BB may be perpendicular to the base substrate. Also, the orthographic projection of the first pixel driving circuit P1 onto the base substrate and the orthographic projection of the second pixel driving circuit P2 onto the base substrate can be provided symmetrically with the intersection line of the mirror symmetry plane BB and the base substrate as the axis of symmetry.Here, the first pixel driving circuit P1 and the second pixel driving circuit P2 can form a repeating unit, and this display panel can include a plurality of repeating units arranged and distributed in the first direction X and the second direction Y.

[0049] As shown in FIGS. 4, 5, and 13, the light-shielding layer can include a plurality of light-shielding portions 61, and can be interconnected between adjacent light-shielding portions 61. It should be understood that in other exemplary embodiments, the display panel may not include a light-shielding layer. Also, the light-shielding portions 61 may be provided independently, that is, the light-shielding portions 61 may not be connected to each other.

[0050] As shown in FIGS. 4, 6, and 14, the first active layer can include a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, and a seventh active portion 77. Here, the third active portion 73 is used to form the channel region of the driving transistor T3, the fourth active portion 74 is used to form the channel region of the fourth transistor T4, the fifth active portion 75 is used to form the channel region of the fifth transistor T5, the sixth active portion 76 is used to form the channel region of the sixth transistor T6, and the seventh active portion 77 is used to form the channel region of the seventh transistor T7. The first active layer further includes a ninth active portion 79, a tenth active portion 710, an eleventh active portion 711, a twelfth active portion 712, and a thirteenth active portion 713. Here, the ninth active portion 79 is connected to the side where the fifth active portion 75 is away from the third active portion 73, and the ninth active portion 79 is connected between two adjacent fifth active portions 75 in the repeating unit adjacent in the first direction X. The tenth active portion 710 is connected between the sixth active portion 76 and the seventh active portion 77, the eleventh active portion 711 is connected between the sixth active portion 76 and the third active portion 73, the twelfth active portion 712 is connected to the end where the fourth active portion 74 is away from the third active portion 73, and the thirteenth active portion 713 is connected to the end where the seventh active portion 77 is away from the sixth active portion 76. Here, the orthographic projection of the light-shielding portion 61 onto the base substrate can cover the orthographic projection of the third active portion 73 onto the base substrate, and the light-shielding portion 61 can reduce the influence on the driving characteristics of the driving transistor T3 by light irradiation. The first active layer can be formed of a polycrystalline silicon material, and accordingly, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type low-temperature polycrystalline silicon thin-film transistors.

[0051] As shown in FIGS. 4, 7, and 14, the first conductive layer may include a second conductive portion 12, a second gate line G2, an enable signal line EM, and a second reset signal line Re2. The second gate line G2 can be used to provide the second gate drive signal terminal in FIG. 1, the enable signal line EM can be used to provide the enable signal terminal in FIG. 1, and the second reset signal line Re2 can be used to provide the second reset signal terminal in FIG. 1. The orthographic projection of the second gate line G2 onto the base substrate, the orthographic projection of the enable signal line EM onto the base substrate, and the orthographic projection of the second reset signal line Re2 onto the base substrate can all extend in the first direction X. In this embodiment example, that the orthographic projection of a certain structure onto the base substrate extends along one direction is understood to mean that the orthographic projection of the structure onto the base substrate extends linearly or is bent and extended. The orthographic projection of the second gate line G2 onto the base substrate covers the orthographic projection of the fourth active portion 74 onto the base substrate, and a partial structure of the second gate line G2 is used to form the gate of the fourth transistor. The orthographic projection of the enable signal line EM onto the base substrate covers the orthographic projection of the fifth active portion 75 onto the base substrate and the orthographic projection of the sixth active portion 76 onto the base substrate, and a partial structure of the enable signal line EM can be respectively used to form the gates of the fifth transistor T5 and the sixth transistor T6. The orthographic projection of the second reset signal line Re2 onto the base substrate can cover the orthographic projection of the seventh active portion 77 onto the base substrate, and a partial structure of the second reset signal line Re2 can be used to form the gate of the seventh transistor T7. The orthographic projection of the second conductive portion 12 onto the base substrate covers the orthographic projection of the third active portion 73 onto the base substrate, and the second conductive portion 12 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C. As shown in FIG. 14, the second gate line G2 in the pixel driving circuit of this row may be multiplexed as the second reset signal line Re2 in the pixel driving circuit of the previous row. With this configuration, the integration degree of the pixel driving circuit can be increased, and the layout area of the pixel driving circuit can be reduced.The light-shielding layer may also be connected to a stable voltage source. For example, it is connected to the first power supply terminal, the first initial signal line, and the second initial signal line in FIG. 1. The light-shielding portion 61 can exert a constant voltage effect on the second conductive portion 12, thereby reducing voltage fluctuations at the gate of the driving transistor T3 during the light-emitting stage, and the light-shielding layer can also shield interference from other signals to the driving transistor T3. Also, this display panel can use the first conductive layer as a mask to conductify the first active layer. That is, the region of the first active layer covered by the first conductive layer can form the channel region of the transistor, and the region of the first active layer not covered by the first conductive layer can form a conductor structure. Also, the light-shielding layer does not need to be connected to a voltage, that is, the light-shielding layer is in a floating state.

[0052] As shown in FIGS. 4, 8, and 15, the second conductive layer can include the first initial signal line Vinit1, the third reset signal line 2Re1, the third gate line 2G1, and a plurality of first conductive portions 21. Here, the first initial signal line Vinit1 is used to provide the first initial signal terminal in FIG. 1, the third reset signal line 2Re1 is used to provide the first reset signal terminal in FIG. 1, and the third gate line 2G1 can be used to provide the first gate driving signal terminal in FIG. 1. The orthographic projection of the first initial signal line Vinit1 onto the base substrate, the orthographic projection of the third reset signal line 2Re1 onto the base substrate, and the orthographic projection of the third gate line 2G1 onto the base substrate can all extend along the first direction X. As shown in FIG. 8, the second conductive layer can also include a plurality of first connection portions 22. In the repeating unit adjacent in the first direction X, the first connection portion 22 is connected between two first conductive portions 21 adjacent in the first direction X. Also, in other embodiments, in the same repeating unit, adjacent first conductive portions 21 may be connected.

[0053] As shown in FIGS. 4, 9, and 16, the second active layer can include a first active portion 81, a second active portion 82, a fourteenth active portion 814, a fifteenth active portion 815, and a sixteenth active portion 816. The first active portion 81 is used to form the channel region of the first transistor T1, and the second active portion 82 is used to form the channel region of the second transistor T2. The fifteenth active portion 815 is connected between the first active portion 81 and the second active portion 82. The fourteenth active portion 814 is connected to the end of the first active portion 81 away from the second active portion 82, and the sixteenth active portion 816 is connected to the end of the second active portion 82 away from the first active portion 81. Here, the second active layer can be formed from indium gallium zinc oxide, and accordingly, the first transistor T1 and the second transistor T2 may be N-type metal oxide thin film transistors. The orthographic projection of the third gate line 2G1 onto the base substrate can cover the orthographic projection of the second active portion 82 onto the base substrate, and the partial structure of the third gate line 2G1 can be used to form the bottom gate of the second transistor T2. The orthographic projection of the third reset signal line 2Re1 onto the base substrate can cover the orthographic projection of the first active portion 81 onto the base substrate, and the partial structure of the third reset signal line 2Re1 can be used to form the bottom gate of the first transistor T1.

[0054] As shown in FIGS. 4, 10, and 17, the third conductive layer may include a first reset signal line 3Re1, a first gate line 3G1, and a first power supply line VSS1. The orthographic projection of the first reset signal line 3Re1 onto the base substrate, the orthographic projection of the first gate line 3G1 onto the base substrate, and the orthographic projection of the first power supply line VSS1 onto the base substrate may all extend along the first direction X. The first reset signal line 3Re1 can be used to provide the first reset signal terminal in FIG. 1. The orthographic projection of the first reset signal line 3Re1 onto the base substrate can cover the orthographic projection of the first active portion 81 onto the base substrate. A partial structure of the first reset signal line 3Re1 can be used to form the top gate of the first transistor T1. At the same time, the first reset signal line 3Re1 can be connected to the third reset signal line 2Re1 via vias located in the edge region of the display panel. The first gate line 3G1 can be used to provide the first gate driving signal terminal in FIG. 1. The orthographic projection of the first gate line 3G1 onto the base substrate can cover the orthographic projection of the second active portion 82 onto the base substrate. A partial structure of the first gate line 3G1 can be used to form the top gate of the second transistor T2. At the same time, the first gate line 3G1 can be connected to the third gate line 2G1 via vias located in the edge region of the display panel. The first power supply line VSS1 can be used to provide the second power supply terminal in FIG. 1. The first power supply line VSS1 is provided corresponding to the rows of the pixel driving circuit. The orthographic projection of the first power supply line VSS1 onto the base substrate in the pixel driving circuit of this row can be located between the orthographic projection of the first initial signal line Vinit1 onto the base substrate in the pixel driving circuit of the adjacent next row and the orthographic projection of the second conductive portion 12 onto the base substrate in the pixel driving circuit of this row. The orthographic projection of the first power supply line VSS1 onto the base substrate in the pixel driving circuit of this row and the orthographic projection of the enable signal line EM onto the base substrate in the pixel driving circuit of this row may at least partially overlap.In this embodiment, the area of the orthographic projection of the first power line VSS1 onto the base substrate is S1, and the area of the orthographic projection of the first power line VSS1 onto the base substrate overlapping with the orthographic projection of the enable signal line EM onto the base substrate is S2. Here, S2 / S1 may be 80% or more. For example, S2 / S1 may be 80%, 90%, 100%, etc. With this configuration, the integration degree of the pixel driving circuit can be improved, the size of the pixel driving circuit in the second direction Y can be reduced, and the transmittance of the display panel can be improved. As shown in FIGS. 10 and 17, in the same pixel driving circuit, the orthographic projection of the second conductive portion 12 onto the base substrate can be located between the orthographic projection of the first gate line 3G1 onto the base substrate and the orthographic projection of the enable signal line EM onto the base substrate. The orthographic projection of the first reset signal line 3Re1 onto the base substrate can be located on the side where the orthographic projection of the first gate line 3G1 onto the base substrate is away from the orthographic projection of the second conductive portion 12 onto the base substrate. The orthographic projection of the second gate line G2 onto the base substrate can be located between the orthographic projection of the first gate line 3G1 onto the base substrate and the orthographic projection of the first reset signal line 3Re1 onto the base substrate. The orthographic projection of the second reset signal line Re2 onto the base substrate can be located on the side where the orthographic projection of the enable signal line EM onto the base substrate is away from the orthographic projection of the second conductive portion 12 onto the base substrate. Further, in this display panel, the second active layer can be made conductive by using the third conductive layer as a mask. That is, the region of the second active layer covered by the third conductive layer can form the channel region of the transistor, and the region of the second active layer not covered by the third conductive layer can form a conductor structure.

[0055] As shown in FIGS. 4, 11, and 18, the fourth conductive layer can include a first bridge portion 41, a second bridge portion 42, a third bridge portion 43, a fourth bridge portion 44, a fifth bridge portion 45, a sixth bridge portion 46, a seventh bridge portion 47, and a second initial signal line Vinit2. Here, the first bridge portion 41 is connected to the first connection portion 22 via a via H and can be connected to the first electrode of the fifth transistor and the second electrode of the capacitor C via a via to the ninth active portion 79. Note that the black blocks in this embodiment represent the positions of vias. Also, adjacent pixel driving circuits in adjacent repeating units in the first direction X can share the same first bridge portion 41. The second bridge portion 42 can be connected to the tenth active portion 710 via a via in order to connect the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. The third bridge portion 43 is connected to the eleventh active portion 711 and the first six active portion 816 via vias respectively and can be connected to the second electrode of the second transistor T2, the first electrode of the sixth transistor T6, and the second electrode of the driving transistor T3. The fourth bridge portion 44 can be connected to the fifteenth active portion 815 and the second conductive portion 12 via vias respectively in order to be connected to the first electrode of the second transistor T2 and the gate of the driving transistor. As shown in FIG. 8, an opening 211 is formed in the first conductive portion 21, and the orthographic projection of the via connected between the second conductive portion 12 and the fourth bridge portion 44 onto the base substrate is located within the orthographic projection of the opening 211 onto the base substrate so that the via and the first conductive portion 21 are insulated from each other. The fifth bridge portion 45 can be connected to the first four active portion 814 and the first initial signal line Vinit1 via vias respectively in order to be connected to the first electrode of the first transistor and the first initial signal line. Note that in the same repeating unit, two adjacent pixel driving circuits can share the same fifth bridge portion 45. The sixth bridge portion 46 can be connected to the twelfth active portion 712 via a via in order to be connected to the first electrode of the fourth transistor.The second initial signal line Vinit2 can be used to provide the second initial signal terminal in FIG. 1. The orthographic projection of the second initial signal line Vinit2 onto the base substrate can extend in the first direction X. The second initial signal line Vinit2 can be connected to the 13th active part 713 via a via for connection to the first pole of the seventh transistor and the second initial signal line. The seventh bridge part 47 can be connected to the first power supply line VSS1 via a via.

[0056] As shown in FIGS. 4 and 12, the fifth conductive layer may include a plurality of third power lines VDD, a plurality of data lines Da, a second power line VSS2, and an eighth bridge portion 58. Here, the orthographic projection of the third power line VDD onto the base substrate, the orthographic projection of the data line Da onto the base substrate, and the orthographic projection of the second power line VSS2 onto the base substrate can all extend along the second direction Y. The third power line VDD can be used to provide the first power terminal in FIG. 1, the data line Da can be used to provide the data signal terminal in FIG. 1, and the second power line VSS2 can be used to provide the second power terminal in FIG. 1. As shown in FIG. 4, for each column of pixel driving circuits, a third power line VDD may be correspondingly provided to be connected to the first pole of the fifth transistor and the first power terminal, and the third power line VDD may be connected to the first bridge portion 41 via a via. The data line Da can be connected to the sixth bridge portion 46 via a via and then connected to the first pole of the fourth transistor and the data signal terminal. The eighth bridge portion 58 can be connected to the second bridge portion 42 via a via to be connected to the second pole of the seventh transistor. As shown in FIG. 12, the third power line VDD includes a first extending portion VDD1, a second extending portion VDD2 connected between the first extending portion VDD1 and the third extending portion VDD3, and the third extending portion VDD3. The size of the orthographic projection of the second extending portion VDD2 onto the base substrate in the first direction X is larger than the size of the orthographic projection of the first extending portion VDD1 onto the base substrate in the first direction, and the size of the orthographic projection of the second extending portion VDD2 onto the base substrate in the first direction X is larger than the size of the orthographic projection of the third extending portion VDD3 onto the base substrate in the first direction X. The orthographic projection of the second extending portion VDD2 onto the base substrate can cover the orthographic projection of the first active portion 81 onto the base substrate and the orthographic projection of the second active portion 82 onto the base substrate. The second extending portion VDD2 can reduce the influence on the characteristics of the first transistor T1 and the second transistor T2 by light irradiation.Also, the orthographic projection of the third power line VDD onto the base substrate can cover the orthographic projection of the fourth bridge portion 44 onto the base substrate. The third power line VDD can be used to shield the fourth bridge portion 44 from noise interference by other signals, and can enhance the stability of the gate voltage of the driving transistor T3. Also, in the same repeating unit, the second extending portions VDD2 in two adjacent pixel driving circuits can be connected to each other. Therefore, the third power line VDD and the first conductive portion 21 can form a mesh structure, and the power lines of this mesh structure can reduce the voltage drop of the power signal.

[0057] The second power line VSS2 can be connected to the first power line VSS1 through vias to the seventh bridge portion 47. Here, the pixel driving circuits in each column can be correspondingly provided with the second power line VSS2, the pixel driving circuits in each row can be correspondingly provided with the first power line VSS1, and each pixel driving circuit can be correspondingly provided with the seventh bridge portion 47. Therefore, the first power line VSS1 and the second power line VSS2 can be connected through vias to form a mesh structure. The first power line VSS1 and the second power line VSS2 forming the mesh structure can reduce the voltage difference between different positions on the common electrode layer. In other exemplary embodiments, the pixel driving circuits in a plurality of columns can be correspondingly provided with the second power line VSS2, the pixel driving circuits in a plurality of rows can be correspondingly provided with the first power line VSS1, and the first power line VSS1 and the second power line VSS2 whose orthographic projections onto the base substrate intersect can be connected through vias. Therefore, the first power line VSS1 and the second power line VSS2 can also form a mesh structure.

[0058] In this embodiment, as shown in FIGS. 4 and 12, the orthographic projection of the second power line VSS2 onto the base substrate and the orthographic projection of the third active portion 73 onto the base substrate at least partially overlap, and the orthographic projection of the second power line VSS2 onto the base substrate and the orthographic projection of the seventh active portion 77 onto the base substrate at least partially overlap. With this configuration, the transmittance of the display panel can be increased.

[0059] In this embodiment example, as shown in FIGS. 4 and 12, the orthographic projection of the seventh bridge portion 47 onto the base substrate and the orthographic projection of the tenth active portion 710 onto the base substrate at least partially overlap. With this configuration, the transmittance of the display panel can be increased in the same manner.

[0060] In this embodiment, in the pixel driving circuits of the same column, the orthographic projection of the second power line VSS2 onto the base substrate is located between the orthographic projection of the third power line VDD onto the base substrate and the orthographic projection of the data line Da onto the base substrate, and the second power line VSS2 can shield the signal crosstalk between the data line Da and the third power line VDD. At the same time, in the pixel driving circuits of the same column, the orthographic projection of the second power line VSS2 onto the base substrate is located between the orthographic projection of the fourth bridge portion 44 onto the base substrate and the orthographic projection of the data line Da onto the base substrate, and the second power line VSS2 can shield the noise interference of the data line Da to the fourth bridge portion 44, and can improve the stability of the driving transistor gate voltage.

[0061] Note that, as shown in FIGS. 4 and 18, the black blocks drawn on the side where the fourth conductive layer is away from the base substrate indicate vias connected to other layers facing the base substrate side of the fourth conductive layer, and the black blocks drawn on the side where the fifth conductive layer is away from the base substrate indicate vias connected to other layers facing the base substrate side of the fifth conductive layer. This black block only indicates the position of the via, and different vias indicated by black blocks at different positions can penetrate different insulating layers.

[0062] As shown in FIG. 19, it is a partial cross-sectional view taken along the broken line CC of the display panel shown in FIG. 4. This display panel further includes a first insulating layer 91, a second insulating layer 92, a third insulating layer 93, a fourth insulating layer 94, a fifth insulating layer 95, a first dielectric layer 96, and a first planarizing layer 97. Here, a base substrate 90, a light-shielding layer, the first insulating layer 91, the first active layer, the second insulating layer 92, the first conductive layer, the third insulating layer 93, the second conductive layer, the fourth insulating layer 94, the second active layer, the fifth insulating layer 95, the third conductive layer, the first dielectric layer 96, the fourth conductive layer, the first planarizing layer 97, and the fifth conductive layer are sequentially stacked. The first insulating layer 91, the second insulating layer 92, the third insulating layer 93, the fourth insulating layer 94, and the fifth insulating layer 95 can be a single-layer structure or a multilayer structure, and the materials of the first insulating layer 91, the second insulating layer 92, the third insulating layer 93, the fourth insulating layer 94, and the fifth insulating layer 95 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride. The first dielectric layer 96 may be a silicon nitride layer, and the material of the first planarizing layer 97 may be an organic material such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or a silicon-glass bonded structure (SoG). The base substrate 90 includes a glass base substrate, a barrier layer, and a polyimide layer that are sequentially stacked, and the barrier layer may be an inorganic material. The materials of the first conductive layer, the second conductive layer, and the third conductive layer may be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy, or a molybdenum / titanium alloy, or a laminate, etc. The materials of the fourth conductive layer and the fifth conductive layer can include a metal material. For example, it can be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy, or a molybdenum / titanium alloy or laminate, etc., or a titanium / aluminum / titanium laminate.

[0063] Note that the ratios of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited thereto. For example, the aspect ratio of the channel, the thickness and pitch of each film layer, and the width and pitch of each signal line can be adjusted according to actual needs. The number of pixels in the display base substrate and the number of sub-pixels per pixel are also not limited to the numbers shown in the figures, and the figures described in the present disclosure are only structural schematic diagrams. In addition, limiting terms such as first, second, etc. are only used to limit different structural names and have no meaning of a specific order.

[0064] As shown in FIG. 20, it is a configuration diagram of another exemplary embodiment of the display panel of the present disclosure. The display panel can include a display area AA and a frame area 10 located around the display area. Note that the configuration of the display area AA of this display panel may be the same as the configuration of the display panel shown in FIG. 4. In this exemplary embodiment, both the first power supply line VSS1 and the second power supply line VSS2 can be arranged in the display area AA of the display panel. This display panel can further include an electrode ring VSS0 located in a fifth conductive layer that can be connected to the common electrode via a via. As shown in FIG. 20, this display panel can be connected to the electrode ring VSS0 and the first power supply line VSS1 via vias using the ninth bridge portion 59 located in the fourth conductive layer, respectively, and the second power supply line VSS2 can be directly connected to the electrode ring VSS0 located in the same conductive layer.

[0065] As shown in FIG. 21, it is a configuration diagram of another exemplary embodiment of the display panel of the present disclosure. The display panel includes a display area AA including a first sector-out area B1, a second sector-out area B2, and a normal display area C other than the first sector-out area B1 and the second sector-out area B2. Here, the data line Da can extend in the first direction X in the first sector-out B1 and the second sector-out B2 in order to be drawn out at local areas C1 and C2 at the edge of the display area AA. This display panel can similarly include a first power supply line VSS1 and a second power supply line VSS2. In the normal display area C, the setting method of the data line Da, the first power supply line VSS1, and the second power supply line VSS2 can be as shown in FIG. 4. Also, in the normal display area C, other configurations of this display panel may be as shown in FIG. 4. As shown in FIGS. 22 to 26, FIG. 22 shows a structural layout diagram of the first fan-out area of the display panel shown in FIG. 21, FIG. 23 shows a structural layout diagram of the third conductive layer of FIG. 22, FIG. 24 shows a structural layout diagram of the fourth conductive layer of FIG. 22, FIG. 25 shows a structural layout diagram of the fifth conductive layer of FIG. 22, and FIG. 26 shows a structural layout diagram of the third conductive layer and the fourth conductive layer of FIG. 22.

[0066] As shown in FIGS. 22, 23, and 26, different from the third conductive layer in the normal display area C, in the first sector-out area B1, a plurality of first power supply lines include a first sub-power supply line VSS11 in which two first cutouts D1 located in the first sector-out area are formed. The first sub-power supply line VSS11 is cut at the position of the first cutout D1 and can be separated from the first sub-power supply line VSS111 located between the two first cutouts D1 of the first sub-power supply line VSS11.

[0067] As shown in FIGS. 22, 24, and 26, different from the fourth conductive layer in the normal display area C, the fourth conductive layer in the first sector-out area B1 can further include a tenth bridge portion 410. The tenth bridge portion 410 is connected to the first sub-power supply line segment VSS111 via a via.

[0068] As shown in FIGS. 22, 24, and 26, unlike the fourth conductive layer in the normal display region C, in the first sector-out region B1, a plurality of second power lines include the second sub-power line VSS22, a second port D2 is formed in the second sub-power line VSS22, the second sub-power line VSS22 is cut at the position of the second port D2 to separate the second sub-power line VSS22 from the second sub-power line VSS222, and the second sub-power line VSS222 is located in the first sector-out region B1. The second sub-power line segment VSS222 can be connected to the seventh bridge portion 47 via a via, and the seventh bridge portion 47 can be connected to the first sub-power line segment VSS111 via a via. The plurality of data lines include the first data line Da1 connected to the tenth bridge portion 410 via a via. Also, the first sub-power line segment VSS111 is not connected to other second power lines VSS2. With this configuration, a data signal transmission path can be formed using the first sub-power line segment VSS111 and the second sub-power line segment VSS222, and a data signal transmission path as indicated by the dotted arrow in FIG. 22 can be formed. In this exemplary embodiment, the data lines can be sector-out as shown in FIG. 21. Note that FIG. 22 shows only a partial sector-out structure of the data lines, and in this embodiment, the other data lines in the first sector-out B1 can be sector-out in the same manner. Also, the structure in the second sector-out region B2 and the structure in the first sector-out region B1 may be mirror-symmetrical.

[0069] As shown in FIG. 27, it is a configuration diagram in another exemplary embodiment of the display panel of the present disclosure. The display panel can include a display area AA that can include a normal display area D. The gate drive circuit and the sector-out in this display panel can be located in the display area AA other than the normal display area D. For example, as shown in FIG. 27, the gate drive circuit can be integrated in the regions E on both sides in the first direction X of the normal display area D, and the sector-out region can be located in the region F on one side in the second direction Y of the normal display area D.

[0070] This display panel needs to create space for compressing the pixel driving circuit in region E to form a gate driving circuit. Similarly, this display panel needs to compress the pixel driving circuit with respect to region F to create a sector out region. Therefore, in order to make the sizes of the pixel driving circuits in each region of the display panel consistent, it is necessary to insert virtual pixel rows and virtual pixel columns into the normal display region D. Virtual pixel rows can be inserted at intervals of a plurality of normal pixel rows, and virtual pixel columns can be inserted at intervals of a plurality of normal pixel columns, where the pixel driving circuits of the virtual pixel rows and virtual pixel columns do not need to output a driving current.

[0071] The display panel can include a base substrate, a light-shielding layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer that are sequentially stacked. Here, an insulating layer may be provided between the adjacent layers. As shown in FIGS. 28 to 42, FIG. 28 is a structural layout diagram of an embodiment of the display panel of the present disclosure, FIG. 29 is a structural layout diagram of the light-shielding layer in FIG. 28, FIG. 30 is a structural layout diagram of the first active layer in FIG. 28, FIG. 31 is a structural layout diagram of the first conductive layer in FIG. 28, FIG. 32 is a structural layout diagram of the second conductive layer in FIG. 28, FIG. 33 is a structural layout diagram of the second active layer in FIG. 28, FIG. 34 is a structural layout diagram of the third conductive layer in FIG. 28, FIG. 35 is a structural layout diagram of the fourth conductive layer in FIG. 28, and FIG. 36 is a structural layout diagram of the fifth conductive layer in FIG. 28. FIG. 37 is a structural layout diagram of the light-shielding layer and the first active layer in FIG. 28, FIG. 38 is a structural layout diagram of the light-shielding layer, the first active layer, and the first conductive layer in FIG. 28, FIG. 39 is a structural layout diagram of the light-shielding layer, the first active layer, the first conductive layer, and the second conductive layer in FIG. 28, FIG. 40 is a structural layout diagram of the light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer in FIG. 28, FIG. 41 is a structural layout diagram of the light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in FIG. 28, and FIG. 42 is a structural layout diagram of the light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in FIG. 28. The display panel can include a plurality of pixel driving circuits shown in FIG. 1. As shown in FIG. 28, the display panel includes a normal pixel row RPn, a virtual pixel row RPd, a normal pixel column LPn, and a virtual pixel column LPd. Here, the display panel can include a plurality of pixel unit groups distributed along a first direction X and a second direction Y array that can include two pixel driving circuits having mirror symmetry. Among the plurality of pixel unit groups located in the normal pixel row RPn and the normal pixel column LPn, there can be included a first pixel unit group Pc1 located in the row immediately adjacent to the virtual pixel row RPd and a fifth pixel unit group Pc5 located at another position.The plurality of pixel unit groups are located in the normal pixel column LPn, and may also include a second pixel unit group Pc2 located in the virtual pixel column LPd, a third pixel unit group Pc3 located in the virtual pixel row RPd and in the normal pixel column LPn, and a fourth pixel unit group Pc4 located in the virtual pixel row RPd and in the virtual pixel column LPd.

[0072] As shown in FIGS. 28, 29, and 37, the light shielding layer includes a plurality of light shielding portions 61, and the spaces between adjacent light shielding portions 61 can be interconnected.

[0073] As shown in FIGS. 28, 30, and 38, the first active layer may include a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, and a seventh active portion 77 located in the fifth pixel unit group Pc5. Here, the third active portion 73 can be used to form the channel region of the driving transistor T3, the fourth active portion 74 can be used to form the channel region of the fourth transistor T4, the fifth active portion 75 can be used to form the channel region of the fifth transistor T5, the sixth active portion 76 can be used to form the channel region of the sixth transistor T6, and the seventh active portion 77 can be used to form the channel region of the seventh transistor T7. The first active layer further includes a ninth active portion 79, a tenth active portion 710, an eleventh active portion 711, a twelfth active portion 712, and a thirteenth active portion 713 located in the fifth pixel unit group Pc5. Here, the ninth active portion 79 is connected to the side of the fifth active portion 75 away from the third active portion 73, and the ninth active portion 79 is connected between two adjacent fifth active portions 75 among the pixel unit groups adjacent in the row direction X. The tenth active portion 710 is connected between the sixth active portion 76 and the seventh active portion 77, the eleventh active portion 711 is connected between the sixth active portion 76 and the third active portion 73, the twelfth active portion 712 is connected to the end of the fourth active portion 74 away from the third active portion 73, and the thirteenth active portion 713 is connected to the end of the seventh active portion 77 away from the sixth active portion 76. Here, the orthographic projection of the light-shielding portion 61 onto the base substrate can cover the orthographic projection of the third active portion 73 onto the base substrate, and the light-shielding portion 61 can reduce the influence on the driving characteristics of the driving transistor T3 due to light irradiation.

[0074] As shown in FIGS. 28, 30, and 38, in the first pixel unit group Pc1, a cutout is formed at the position of the seventh active portion 77 compared to the fifth pixel unit group Pc5, that is, the first pixel unit group Pc1 is not provided with the seventh active portion 77.

[0075] As shown in FIGS. 28, 30, and 38, in the second pixel unit group Pc2 and the fourth pixel unit group Pc4, cutouts may be formed at the positions where the third active portion 73, the fourth active portion 74, the fifth active portion 75, the sixth active portion 76, and the seventh active portion 77 are located, that is, the third active portion 73, the fourth active portion 74, the fifth active portion 75, the sixth active portion 76, and the seventh active portion 77 may not be provided in the second pixel unit group Pc2 and the fourth pixel unit group Pc4.

[0076] As shown in FIGS. 28, 30, and 38, in the third pixel unit group Pc3 compared with the fifth pixel unit group Pc5, cutouts are formed at the positions of the third active portion 73, the fourth active portion 74, the fifth active portion 75, and the sixth active portion 76, that is, the third active portion 73, the fourth active portion 74, the fifth active portion 75, and the sixth active portion 76 are not provided in the second pixel unit group Pc2. The seventh active portion 77 in the pixel unit group Pc5 can be used as the channel region of the seventh transistor in the first pixel unit group Pc1. Accordingly, the seventh active portion 77 in the fifth pixel unit group Pc5 needs to be connected to the tenth active portion 710 in the first pixel unit group Pc1. Here, the seventh active portion 77 in the fifth pixel unit group Pc5 and the tenth active portion 710 in the first pixel unit group Pc1 may be connected by any conductive layer.

[0077] Also, the first active layer can be formed of a polycrystalline silicon material. Accordingly, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type low-temperature polycrystalline silicon thin-film transistors.

[0078] As shown in FIGS. 28, 31, and 38, the first conductive layer may include a second conductive portion 12, a second gate line G2, an enable signal line EM, and a second reset signal line Re2. The second gate line G2 can be used to provide the second gate drive signal terminal in FIG. 1, the enable signal line EM can be used to provide the enable signal terminal in FIG. 1, and the second reset signal line Re2 can be used to provide the second reset signal terminal in FIG. 1. The orthographic projection of the second gate line G2 onto the base substrate, the orthographic projection of the enable signal line EM onto the base substrate, and the orthographic projection of the second reset signal line Re2 onto the base substrate can all extend in the first direction X. The orthographic projection of the second gate line G2 onto the base substrate covers the orthographic projection of the fourth active portion 74 onto the base substrate, and a partial structure of the second gate line G2 is used to form the gate of the fourth transistor. The orthographic projection of the enable signal line EM onto the base substrate covers the orthographic projection of the fifth active portion 75 onto the base substrate and the orthographic projection of the sixth active portion 76 onto the base substrate, and a partial structure of the enable signal line EM can be used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively. The orthographic projection of the second reset signal line Re2 onto the base substrate can cover the orthographic projection of the seventh active portion 77 onto the base substrate, and a partial structure of the second reset signal line Re2 can be used to form the gate of the seventh transistor T7. The orthographic projection of the second conductive portion 12 onto the base substrate covers the orthographic projection of the third active portion 73 onto the base substrate, and the second conductive portion 12 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C. Among the pixel unit groups adjacent in the first direction X, two adjacent second conductive portions 21 can be connected to each other. As shown in FIGS. 28 and 38, the second gate line G2 in the pixel driving circuit of this row can be multiplexed as the second reset signal line Re2 in the pixel driving circuit of the previous row.The light-shielding layer is connected to a stable power supply terminal, and can be connected to, for example, the first power supply terminal, the first initial signal line, and the second initial signal line in FIG. 1. The light-shielding portion 61 can stabilize the voltage with respect to the second conductive portion 12, thereby reducing the voltage fluctuation at the gate of the driving transistor T3 during the light-emitting stage. Further, this display panel can use the first conductive layer as a mask to conductify the first active layer. That is, the region of the first active layer covered by the first conductive layer can form the channel region of the transistor, and the region of the first active layer not covered by the first conductive layer can form a conductor structure.

[0079] As shown in FIGS. 28, 32, and 39, the second conductive layer can include the first initial signal line Vinit1, the third reset signal line 2Re1, the third gate line 2G1, and a plurality of first conductive portions 21. Here, the first initial signal line Vinit1 is used to provide the first initial signal terminal in FIG. 1, the third reset signal line 2Re1 is used to provide the first reset signal terminal in FIG. 1, and the third gate line 2G1 can be used to provide the first gate driving signal terminal in FIG. 1. The orthographic projection of the first initial signal line Vinit1 onto the base substrate, the orthographic projection of the third reset signal line 2Re1 onto the base substrate, and the orthographic projection of the third gate line 2G1 onto the base substrate can all extend along the first direction X. As shown in FIG. 32, the second conductive layer can further include a plurality of first connection portions 22, and among the pixel unit groups adjacent in the first direction X, the first connection portion 22 is connected between two first conductive portions 21 adjacent in the first direction X.

[0080] As shown in FIGS. 28, 33, and 40, the second active layer can include a first active portion 81, a second active portion 82, a fourteenth active portion 814, a fifteenth active portion 815, and a sixteenth active portion 816 located in the first pixel unit group Pc1. The first active portion 81 is used to form the channel region of the first transistor T1, and the second active portion 82 is used to form the channel region of the second transistor T2. The fifteenth active portion 815 is connected between the first active portion 81 and the second active portion 82. The fourteenth active portion 814 is connected to one end of the first active portion 81 away from the fifteenth active portion 815, and the sixteenth active portion 816 is connected to one end of the second active portion 82 away from the first active portion 81.

[0081] As shown in FIGS. 28, 33, and 40, the configuration of the second active layer in the fifth pixel unit group Pc5 is the same as the configuration of the second active layer in the first pixel unit group Pc1.

[0082] As shown in FIGS. 28, 33, and 40, compared with the first pixel unit group Pc1, in the second pixel unit group Pc2 and the third pixel unit group Pc3, cutouts are formed at the positions of the first active portion and the second active portion, that is, the second pixel unit group Pc2 and the third pixel unit group Pc3 are not provided with the first active portion and the second active portion.

[0083] As shown in FIGS. 28, 33, and 40, compared with the first pixel unit group Pc1, in the fourth pixel unit group, cutouts are formed at the positions of the first active portion 81, the second active portion 82, and the fifteenth active portion 815, that is, the fourth pixel unit group includes only the fourteenth active portion 814 and the sixteenth active portion 816.

[0084] Further, the second active layer can be formed from indium gallium zinc oxide, and thus, the first transistor T1 and the second transistor T2 can be N-type metal oxide thin film transistors. The orthographic projection of the third gate line 2G1 onto the base substrate can cover the orthographic projection of the second active portion 82 onto the base substrate, and the partial structure of the third gate line 2G1 can be used to form the bottom gate of the second transistor T2. The orthographic projection of the third reset signal line 2Re1 onto the base substrate can cover the orthographic projection of the first active portion 81 onto the base substrate, and the partial structure of the third reset signal line 2Re1 can be used to form the bottom gate of the first transistor T1.

[0085] As shown in FIGS. 28, 34, and 41, the third conductive layer may include a first reset signal line 3Re1 and a first gate line 3G1. The orthographic projection of the first reset signal line 3Re1 onto the base substrate and the orthographic projection of the first gate line 3G1 onto the base substrate may both extend in the first direction X. The first reset signal line 3Re1 can be used to provide the first reset signal terminal in FIG. 1. The orthographic projection of the first reset signal line 3Re1 onto the base substrate can cover the orthographic projection of the first active portion 81 onto the base substrate. A partial structure of the first reset signal line 3Re1 can be used to form the top gate of the first transistor T1. At the same time, the first reset signal line 3Re1 can be connected to the third reset signal line 2Re1 through vias located in the edge region of the display panel. The first gate line 3G1 can be used to provide the first gate driving signal terminal in FIG. 1. The orthographic projection of the first gate line 3G1 onto the base substrate can cover the orthographic projection of the second active portion 82 onto the base substrate. A partial structure of the first gate line 3G1 can be used to form the top gate of the second transistor T2. At the same time, the first gate line 3G1 can be connected to the third gate line 2G1 through vias located in the frame region of the display panel. This display panel can conductify the second active layer using the third conductive layer as a mask, that is, the region of the second active layer covered by the third conductive layer can form the channel region of the transistor, and the region of the second active layer not covered by the third conductive layer can form a conductor structure.

[0086] As shown in FIGS. 28, 35, and 42, the fourth conductive layer can include a first bridge portion 41, a second bridge portion 42, a third bridge portion 43, a fourth bridge portion 44, a fifth bridge portion 45, a sixth bridge portion 46, and a second initial signal line Vinit2. Here, the first bridge portion 41 is connected to the first connection portion 22 via a via and to the ninth active portion 79 via a via, and can be connected to the first electrode of the fifth transistor and the second electrode of the capacitor C. Here, adjacent pixel driving circuits in a pixel unit group adjacent in the first direction X can share the same first bridge portion 41. The second bridge portion 42 can be connected to the tenth active portion 710 via a via in order to connect to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. The third bridge portion 43 is connected to the eleventh active portion 711 and the first six active portion 816 via vias, respectively, and can be connected to the second electrode of the second transistor T2, the first electrode of the sixth transistor T6, and the second electrode of the driving transistor T3. The fourth bridge portion 44 can be connected to the fifteenth active portion 815 and the second conductive portion 12 via vias, respectively, in order to connect to the first electrode of the second transistor T2 and the gate of the driving transistor. As shown in FIG. 32, an opening 211 is formed in the first conductive portion 21, and the orthographic projection of the via connected between the second conductive portion 12 and the fourth bridge portion 44 onto the base substrate is located within the orthographic projection of the opening 211 onto the base substrate, and the via and the first conductive portion 21 are insulated from each other. The fifth bridge portion 45 can be connected to the fourteenth active portion 814 and the first initial signal line Vinit1 via vias, respectively, in order to connect to the first electrode of the first transistor and the first initial signal line. Here, in the same pixel unit group, two adjacent pixel driving circuits can share the same fifth bridge portion 45. The sixth bridge portion 46 can be connected to the twelfth active portion 712 via a via in order to connect to the first electrode of the fourth transistor.The second initial signal line Vinit2 can be used to provide the second initial signal terminal in FIG. 1. The orthographic projection of the second initial signal line Vinit2 onto the base substrate can extend in the first direction X. The second initial signal line Vinit2 can be connected to the 13th active part 713 through a via for connection to the first pole of the seventh transistor and the second initial signal line.

[0087] As shown in FIGS. 28, 35, and 42, the fourth conductive layer can also include an 11th bridge part 411 corresponding to a pixel unit group provided in a virtual pixel row. In the virtual pixel row, the 11th bridge part 411 is connected between two 4th bridge parts 44 in the same pixel unit group. Two 2nd bridge parts 42 in this pixel unit group are connected to the 11th bridge part 411. Also, in this pixel unit group, the 1st bridge part 41 in the same pixel driving circuit is connected to the 4th bridge part 44. As shown in FIG. 42, in the fourth pixel unit group Pc4, the 4th bridge part 44 can be connected to the second gate line G2 through a via.

[0088] As shown in FIGS. 28 and 36, the fifth conductive layer may include a plurality of third power lines VDD, a plurality of data lines Da, and an eighth bridge portion 58. Since the eighth bridge portion 58 is connected to the second pole of the seventh transistor, it can be connected to the second bridge portion 42 via a via, and the eighth bridge portion 58 can also be used to connect the first electrode of the light-emitting unit. The orthographic projection of the third power line VDD onto the base substrate and the orthographic projection of the data line Da onto the base substrate can extend along the second direction Y. The third power line VDD can be used to provide the first power supply terminal in FIG. 1, and the data line Da can be used to provide the data signal terminal in FIG. 1. As shown in FIG. 28, each column of pixel driving circuits can correspondingly be provided with a third power line VDD and a data line Da. In the first pixel unit group Pc1, the second pixel unit group Pc2, the fourth pixel unit group Pc4, and the fifth pixel unit group Pc5, since the third power line VDD is connected to the first pole of the fifth transistor T5 and the first power supply terminal, it can be connected to the first bridge portion 41 via a via. The data line Da is connected to the sixth bridge portion 46 via a via, and can connect the first pole of the fourth transistor and the data signal terminal. As shown in FIG. 36, the third power line VDD includes a first extending portion VDD1, a second extending portion VDD2 connected between the first extending portion VDD1 and the third extending portion VDD3, and the third extending portion VDD3. The size of the orthographic projection of the second extending portion VDD2 onto the base substrate in the row direction X is larger than the size of the orthographic projection of the first extending portion VDD1 onto the base substrate in the row direction X, and the size of the orthographic projection of the second extending portion VDD2 onto the base substrate in the row direction X is larger than the size of the orthographic projection of the third extending portion VDD2 onto the base substrate in the row direction X. The orthographic projection of the second extending portion VDD2 onto the base substrate can cover the orthographic projection of the first active portion 81 onto the base substrate and the orthographic projection of the second active portion 82 onto the base substrate, and the second extending portion VDD2 can reduce the influence of characteristics on the first transistor T1 and the second transistor T2 due to light irradiation.Also, the orthographic projection of the third power line VDD onto the base substrate can cover the orthographic projection of the fourth bridge portion 44 onto the base substrate. The third power line VDD can be used to shield the fourth bridge portion 44 from noise interference by other signals, and can enhance the stability of the gate voltage of the driving transistor T3. Also, in the same pixel unit group, the second extending portions VDD2 in two adjacent pixel driving circuits can be connected to each other. Therefore, the third power line VDD and the first conductive portion 21 can form a mesh structure, and the power lines of this mesh structure reduce the voltage drop of the power signal.

[0089] As shown in FIGS. 28 and 36, in the virtual pixel column, the second extending portion VDD2 in the fourth pixel unit group Pc4 and the second extending portion VDD2 in the second pixel unit group Pc2 are disconnected. The data line Da in the virtual pixel column is connected to the second extending portion VDD2 in the fourth pixel unit group Pc4, and the second extending portion VDD2 in the fourth pixel unit group Pc4 is connected to the first bridge portion 41 corresponding to the fourth pixel unit group Pc4 via a via. Also, as shown in FIG. 28, the first bridge portion 41 in the third pixel unit group Pc3 is not connected to the third power line VDD corresponding to the third pixel unit group Pc3.

[0090] As shown in FIG. 28, the data line Da in the virtual pixel column can form the second power supply terminal described above, and the second gate line G2 in the virtual pixel row can form the first power supply terminal described above. The data line Da in the virtual pixel column and the second gate line G2 in the virtual pixel row form a mesh structure. Since this mesh structure is connected to the common electrode layer, this mesh structure can reduce the voltage difference at different positions on the common electrode layer. In this embodiment, the first bridge portion 41 connected in the row direction X among the virtual pixel rows may form the first power supply terminal described above. The first bridge portion 41 connected in the row direction X among the virtual pixel rows is connected in parallel with the second gate line G2, can reduce the self-resistance of the first power supply line, and can further reduce the voltage difference at different positions on the common electrode layer. Also, as shown in FIGS. 28, 31, and 38, in the virtual pixel row, in the pixel unit groups adjacent in the row direction, the adjacent second conductive portions 12 are connected. With this configuration, the self-resistance of the first power supply line can also be further reduced.

[0091] In other exemplary embodiments, the second extension VDD2 in the fourth pixel unit group Pc4 and the second extension VDD2 in the second pixel unit group Pc2 may not be cut, that is, the second extension VDD2 in the fourth pixel unit group Pc4 and the second extension VDD2 in the second pixel unit group Pc2 may be connected. Therefore, the data line Da in the virtual pixel column is not connected to the second extension VDD2 in the fourth pixel unit group Pc4, and the data line Da in the virtual pixel column can be connected to the first bridge portion in the virtual pixel row in another way. For example, the data line Da in the virtual pixel column can be directly connected to the first bridge portion in the virtual pixel row via a via.

[0092] In other exemplary embodiments, the fourth bridge portion 44 of the fourth pixel unit group Pc4 may not be connected to the second gate line of the virtual pixel row. Therefore, the first power supply terminal described above can be formed using only the first bridge portion connected in the row direction X among the virtual pixel rows. Further, in other embodiments, the fourth bridge portion 44 of the fourth pixel unit group Pc4 may be connected to the enable signal line EM of the virtual pixel row via a via, so that the enable signal line of the virtual pixel row forms the above-described first power supply terminal. Therefore, the first pixel power group can include the seventh active portion, and the first pixel unit group does not need to share the seventh active portion of the third pixel unit group.

[0093] In other exemplary embodiments, the above-described first power supply terminal can also be formed using other signal lines extending along the first direction X of the virtual pixel row. The second power supply terminal may be formed using other signal lines extending along the second direction Y in the virtual pixel column.

[0094] In this embodiment, a partial cross-sectional view along the broken line CC of the display panel shown in FIG. 28 may be shown as in FIG. 19. The display panel includes an electrode layer located on the side away from the base substrate of the fifth conductive layer, and the electrode layer can be used to form the first electrode of the light-emitting unit, and there is an insulating layer between the electrode layer and the fifth conductive layer.

[0095] As shown in FIGS. 28 and 42, the black blocks drawn on the side away from the base substrate of the fourth conductive layer indicate vias connected to other layers facing the base substrate side of the fourth conductive layer, and the black blocks drawn on the side away from the base substrate of the fifth conductive layer indicate vias connected to other layers facing the base substrate side of the fifth conductive layer. This black block only indicates the position of the via, and different vias indicated by black blocks at different positions can penetrate different insulating layers.

[0096] In the display panel shown in FIG. 4, the first power line VSS1 is located in the third conductive layer, and the second power line VSS2 is located in the fifth conductive layer. In other exemplary embodiments, the first power line VSS1 and the second power line VSS2 may be disposed in other conductive layers. For example, the first power line VSS1 may be disposed in one or more of the light-shielding layer, the second conductive layer, the fourth conductive layer, and the electrode layer, and the second power line VSS2 may be disposed in one or more of the light-shielding layer, the fourth conductive layer, and the electrode layer.

[0097] As shown in FIG. 43, it is a schematic diagram of the configuration of another exemplary embodiment of the display panel of the present disclosure. The pixel driving circuit can include a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a capacitor C. Here, the first pole of the fourth transistor T4 is connected to the data signal terminal Da, the second pole is connected to the first pole of the driving transistor T3, the gate is connected to the second gate driving signal terminal G2, the first pole of the fifth transistor T5 is connected to the first power supply terminal VDD, the second pole is connected to the first pole of the driving transistor T3, the gate is connected to the enable signal line EM, the gate of the driving transistor T3 is connected to the node N, the first pole of the second transistor T2 is connected to the node N, the second pole is connected to the second pole of the driving transistor T3, the gate is connected to the first gate driving signal terminal G1, the first pole of the sixth transistor T6 is connected to the second pole of the driving transistor T3, the second pole is connected to the second pole of the seventh transistor T7, the gate is connected to the enable signal line EM, the first pole of the seventh transistor T7 is connected to the second initial signal line Vinit2, the gate is connected to the second reset signal line Re2, the second pole of the first transistor T1 is connected to the node N, the first pole is connected to the first initial signal line Vinit1, the gate is connected to the first reset signal line Re1, the first electrode of the capacitor C is connected to the node N, the second electrode is connected to the first power supply terminal VDD, the first pole of the eighth transistor T8 is connected to the third initial signal line Vinit3, the second pole is connected to the first pole of the driving transistor, and the gate is connected to the second reset signal line Re2. The pixel driving circuit may be connected to one light-emitting unit OLED to drive the light emission of the light-emitting unit OLED, and the light-emitting unit OLED may be connected between the second pole of the sixth transistor T6 and the second power supply terminal VSS.Here, the first transistor T1 and the second transistor T2 may be N-type transistors, and the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be P-type transistors.

[0098] The driving method of the pixel driving circuit may include a reset stage, a data writing stage, and a light emitting stage. In the reset stage, the first reset signal line Re1 outputs a high-level signal, the second reset signal line Re2 outputs a low-level signal, the first transistor T1 and the eighth transistor T8 are turned on, the first initial signal line Vinit1 inputs a first initial signal to the node N, and the third initial signal line Vinit3 inputs a third initial signal to the first pole of the driving transistor T3. In the data writing stage, the first gate driving signal terminal G1 outputs a high-level signal, the second gate driving signal terminal G2 outputs a low-level signal, the second transistor T2 and the fourth transistor T4 are turned on, and at the same time, the data signal terminal Da outputs a data signal to write a compensation voltage Vdata + Vth to the node N, where Vdata is the voltage of the data signal and Vth is the threshold voltage of the driving transistor T3. In the light emitting stage t4, the enable signal line EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light emitting unit to emit light according to the compensation voltage Vdata + Vth stored in the capacitor C. The output current I of the driving transistor in the pixel driving circuit of the present disclosure is I=(μWCox / 2L)(Vdata + Vth - Vdd - Vth) 2 This pixel driving circuit can avoid the influence of the threshold value of the driving transistor on its output current. Here, I is the output current of the driving transistor, μ is the carrier mobility, Cox is the gate capacitance per unit area, W is the channel width of the driving transistor, L is the length of the channel of the driving transistor, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor.

[0099] This embodiment also provides a display panel, which includes a base substrate, a light-shielding layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer that are sequentially stacked. Here, an insulating layer may be provided between the adjacent layers. As shown in FIGS. 44 to 58, FIG. 44 is a structural layout diagram of an embodiment of the display panel of the present disclosure, FIG. 45 is a structural layout diagram of the light-shielding layer of FIG. 44, FIG. 46 is a structural layout diagram of the first active layer of FIG. 44, FIG. 47 is a structural layout diagram of the first conductive layer of FIG. 44, FIG. 48 is a structural layout diagram of the second conductive layer of FIG. 44, FIG. 49 is a structural layout diagram of the second active layer of FIG. 44, FIG. 50 is a structural layout diagram of the third conductive layer of FIG. 44, FIG. 51 is a structural layout diagram of the fourth conductive layer of FIG. 44, FIG. 52 is a structural layout diagram of the fifth conductive layer of FIG. 44, FIG. 53 is a structural layout diagram of the light-shielding layer and the first active layer in FIG. 44, FIG. 54 is a structural layout diagram of the light-shielding layer, the first active layer, and the first conductive layer in FIG. 44, FIG. 55 is a structural layout diagram of the light-shielding layer, the first active layer, the first conductive layer, and the second conductive layer in FIG. 44, FIG. 56 is a structural layout diagram of the light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer in FIG. 44, FIG. 57 is a structural layout diagram of the light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in FIG. 44, and FIG. 58 is a structural layout diagram of the light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in FIG. 44. The display panel can include a plurality of pixel driving circuits shown in FIG. 43.

[0100] As shown in FIGS. 44, 45, and 53, the light-shielding layer includes a plurality of light-shielding portions 61, and can be interconnected between adjacent light-shielding portions 61.

[0101] As shown in FIGS. 44, 46, and 54, the first active layer can include a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, a seventh active portion 77, and an eighth active portion 78. Here, the third active portion 73 can be used to form the channel region of the driving transistor T3, the fourth active portion 74 can be used to form the channel region of the fourth transistor T4, the fifth active portion 75 can be used to form the channel region of the fifth transistor T5, the sixth active portion 76 can be used to form the channel region of the sixth transistor T6, the seventh active portion 77 can be used to form the channel region of the seventh transistor T7, and the eighth active portion 78 can be used to form the channel region of the eighth transistor T8. The first active layer can further include a ninth active portion 79, a tenth active portion 710, an eleventh active portion 711, a twelfth active portion 712, a thirteenth active portion 713, a seventeenth active portion 717, an eighteenth active portion 718, a nineteenth active portion 719, and a twentieth active portion 720. Here, the ninth active portion 79 is connected to the end of the fifth active portion 75 that is away from the third active portion 73. The tenth active portion 710 is connected between the sixth active portion 76 and the seventh active portion 77, the eleventh active portion 711 is connected between the sixth active portion 76 and the third active portion 73, the twelfth active portion 712 is connected to the end of the fourth active portion 74 that is away from the third active portion 73, the thirteenth active portion 713 is connected to the end of the seventh active portion 77 that is away from the sixth active portion 76, the seventeenth active portion 717 and the eighteenth active portion 718 are respectively connected to both ends of the eighth active portion 78, and the nineteenth active portion 719 is connected between the fourth active portion 74 and the fifth active portion 75. The size of the projection of the nineteenth active portion 719 onto the base substrate in the first direction X is larger than the size of the projection of the fourth active portion 74 onto the base substrate in the first direction X. The twentieth active portion 720 is connected between the nineteenth active portion 719 and the third active portion 73. Here, the projection of the light-shielding portion 61 onto the base substrate can cover the projection of the third active portion 73 onto the base substrate, and the light-shielding portion 61 can reduce the influence on the driving characteristics of the driving transistor T3 due to light irradiation.The first active layer can be formed of a polycrystalline silicon material, and accordingly, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be P-type low-temperature polycrystalline silicon thin-film transistors. As shown in FIGS. 44, 47, and 54, the first conductive layer may include a second conductive portion 12, a second gate line G2, an enable signal line EM, a second reset signal line Re2, and a third conductive portion 13. The second gate line G2 can be used to provide the second gate drive signal terminal in FIG. 1, the enable signal line EM can be used to provide the enable signal terminal in FIG. 1, and the second reset signal line Re2 can be used to provide the second reset signal terminal in FIG. 1. The orthographic projection of the enable signal line EM onto the base substrate and the orthographic projection of the second reset signal line Re2 onto the base substrate can both extend along the row direction X. The second gate line G2 may include a plurality of second gate lines G22 spaced apart in the first direction X. The orthographic projection of the second gate line G22 onto the base substrate extends along the first direction X and covers the orthographic projection of the fourth active portion 74 onto the base substrate. A partial structure of the second gate line G22 is used to form the gate of the fourth transistor T4. The orthographic projection of the enable signal line EM onto the base substrate covers the orthographic projection of the fifth active portion 75 onto the base substrate and the orthographic projection of the sixth active portion 76 onto the base substrate. A partial structure of the enable signal line EM can be respectively used to form the gates of the fifth transistor T5 and the sixth transistor T6. The orthographic projection of the second reset signal line Re2 onto the base substrate can cover the orthographic projection of the seventh active portion 77 onto the base substrate and the orthographic projection of the eighth active portion 78 onto the base substrate. A partial structure of the second reset signal line Re2 can be used to form the gate of the seventh transistor T7, and another partial structure of the second reset signal line Re2 can be used to form the gate of the eighth transistor T8. The orthographic projection of the second conductive portion 12 onto the base substrate covers the orthographic projection of the third active portion 73 onto the base substrate. The second conductive portion 12 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C.The light-shielding layer is also connected to a stable power supply terminal, and can be connected to, for example, the first power supply terminal, the first initial signal line, the second initial signal line, and the third initial signal line Vinit3 in FIG. 1. The light-shielding portion 61 can exert a constant voltage effect on the second conductive portion 12, thereby reducing voltage fluctuations at the gate of the driving transistor T3 during the light-emitting stage. Further, this display panel can use the first conductive layer as a mask to conductify the first active layer, that is, the region of the first active layer covered by the first conductive layer can form the channel region of the transistor, and the region of the first active layer not covered by the first conductive layer can form a conductor structure.

[0102] As shown in FIGS. 44, 48, and 55, the second conductive layer may include a third reset signal line 2Re1, a third gate line 2G1, a plurality of first conductive portions 21, and a fourth conductive portion 24. Here, the third reset signal line 2Re1 can provide the first reset signal terminal in FIG. 1, and the third gate line 2G1 can provide the first gate driving signal terminal in FIG. 1. The orthographic projection of the third reset signal line 2Re1 onto the base substrate can all extend in the first direction X. The third gate line 2G1 includes a plurality of third gate line segments 2G11 arranged at intervals in the first direction X, and the orthographic projection of the third gate line segment 2G11 onto the base substrate can extend along the first direction X. The orthographic projection of the first conductive portion 21 onto the base substrate and the orthographic projection of the second conductive portion 12 onto the base substrate at least partially overlap, and the first conductive portion 21 is used to form the second electrode of the capacitor C. As shown in FIG. 48, in the first direction X, the first conductive portions 21 are connected to each other. The fourth conductive portion 24 is connected to the first conductive portion 21, and the orthographic projection of the fourth conductive portion 24 onto the base substrate and the orthographic projection of the first 9 active portion 719 onto the base substrate can at least partially overlap, and the orthographic projection of the fourth conductive portion 24 onto the base substrate can be located between the orthographic projections of the third gate line segments 2G11 adjacent to each other in the first direction X. The fourth conductive portion 24 and the first 9 active portion 719 can form a parasitic capacitance. In the data writing stage, the data signal input to the second pole of the fourth transistor T4 can be stored in the parasitic capacitance. When the data writing stage ends, the data signal stored in the parasitic capacitance can also continue to input a compensation voltage to the node N through the driving transistor T3. With this configuration, a sufficient compensation voltage can be written to the node N in a short data writing stage, and a high refresh rate of the display panel can be realized.

[0103] As shown in FIGS. 44, 49, and 56, the second active layer can include a first active portion 81, a second active portion 82, a fourteenth active portion 814, a fifteenth active portion 815, and a sixteenth active portion 816. The first active portion 81 is used to form the channel region of the first transistor T1, and the second active portion 82 is used to form the channel region of the second transistor T2. The fifteenth active portion 815 is connected between the first active portion 81 and the second active portion 82. The fourteenth active portion 814 is connected to the end of the first active portion 81 that is away from the fifteenth active portion 815, and the sixteenth active portion 816 is connected to one end of the second active portion 82 that is away from the first active portion 81. Here, the second active layer can be formed from indium gallium zinc oxide, and accordingly, the first transistor T1 and the second transistor T2 can be N-type metal oxide thin film transistors. The orthographic projection of the third gate line 2G1 onto the base substrate can cover the orthographic projection of the second active portion 82 onto the base substrate, and the partial structure of the third gate line 2G1 can be used to form the bottom gate of the second transistor. The orthographic projection of the third reset signal line 2Re1 onto the base substrate can cover the orthographic projection of the first active portion 81 onto the base substrate, and the partial structure of the third reset signal line 2Re1 can be used to form the bottom gate of the first transistor T1.

[0104] As shown in FIGS. 44, 50, and 57, the third conductive layer may include a first reset signal line 3Re1 and a first gate line 3G1. The first reset signal line 3Re1 includes a plurality of first reset signal lines 3Re11 spaced apart in the first direction X, and the orthographic projection of the first reset signal line 3Re11 onto the base substrate extends along the first direction X. The first gate line 3G1 includes a plurality of first gate lines 3G11 spaced apart in the first direction X, and the orthographic projection of the first gate line 3G11 onto the base substrate extends along the first direction X. The first reset signal line 3Re1 can be used to provide the first reset signal terminal in FIG. 1, the orthographic projection of the first reset signal line 3Re1 onto the base substrate can cover the orthographic projection of the first active portion 81 onto the base substrate, and a partial structure of the first reset signal line 3Re1 can be used to form the top gate of the first transistor T1. The first gate line 3G1 can be used to provide the first gate drive signal terminal in FIG. 1, the orthographic projection of the first gate line 3G1 onto the base substrate can cover the orthographic projection of the second active portion 82 onto the base substrate, and a partial structure of the first gate line 3G1 can be used to form the top gate of the second transistor T2. Further, this display panel can use the third conductive layer as a mask to conductify the second active layer, that is, a region of the second active layer covered by the third conductive layer can form a channel region of a transistor, and a region of the second active layer not covered by the third conductive layer can form a conductor structure.

[0105] As shown in FIGS. 44, 51, and 58, the fourth conductive layer can include a first bridge portion 41, a second bridge portion 42, a third bridge portion 43, a fourth bridge portion 44, a sixth bridge portion 46, a seventh bridge portion 47, an eighth bridge portion 48, a first initial signal line Vinit1, a second initial signal line Vinit2, a third initial signal line Vinit3, a first power supply line VSS1, a first gate connection line 4G1, a second gate connection line 4G2, a first reset connection line 4Re1, and a second reset connection line 4Re2. The orthographic projection of the first initial signal line Vinit1 onto the base substrate, the orthographic projection of the second initial signal line Vinit2 onto the base substrate, the orthographic projection of the third initial signal line Vinit3 onto the base substrate, the orthographic projection of the first power supply line VSS1 onto the base substrate, the orthographic projection of the first gate connection line 4G1 onto the base substrate, the orthographic projection of the second gate connection line 4G2 onto the base substrate, the orthographic projection of the first reset connection line 4Re1 onto the base substrate, and the orthographic projection of the second reset connection line 4Re2 onto the base substrate can all extend in the first direction X. The first initial signal line Vinit1 is used to provide a first initial signal terminal, the second initial signal line Vinit2 is used to provide a second initial signal terminal, and the third initial signal line Vinit3 is used to provide a third initial signal terminal. Here, the first bridge portion 41 is connected to the first conductive portion 21 via a via and is connected to the ninth active portion 79 via a via, thereby connecting the first pole of the fifth transistor to the second electrode of the capacitor C. The second bridge portion 42 is connected to the tenth active portion 710 via a via and is connected to the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7. The third bridge portion 43 is connected to the eleventh active portion 711 and the sixteenth active portion 816 via vias, respectively, and is connected to the second pole of the second transistor T2, the first pole of the sixth transistor T6, and the second pole of the driving transistor T3. The fourth bridge portion 44 is connected to the third conductive portion 13 and the second conductive portion 12 via vias, respectively, and the seventh bridge portion 47 is connected to the third conductive portion 13 and the fifteenth active portion 815 via vias, respectively, and is connected to the first pole of the second transistor T2 and the gate of the driving transistor.

[0106] As shown in FIG. 48, an opening 211 is formed in the first conductive portion 21, and the orthographic projection of the via connected between the second conductive portion 12 and the fourth bridge portion 44 onto the base substrate is such that the opening 211 is located within the orthographic projection on the base substrate so that the conductive structure in the via and the first conductive portion 21 are insulated from each other. The eighth bridge portion 48 is connected to the seventh active portion 717 and the second 0 active portion 720 via vias respectively, and can be connected to the second pole of the eighth transistor and the first pole of the driving transistor. The first initial signal line Vinit1 can be connected to the first 4 active portion 814 via a via in order to be connected to the first initial signal line and the first pole of the first transistor T1. The second initial signal line Vinit2 can be connected to the first 3 active portion 713 via a via in order to be connected to the second initial signal line and the first pole of the seventh transistor. The third initial signal line Vinit3 is connected to the first 8 active portion 718 via a via in order to be connected to the first pole of the eighth transistor and the third initial signal line. The first gate connection line 4G1 is connected to the second gate line segment 2G11 located on the same third gate line 2G1 via a via, and can be connected to the first gate line segment 3G11 located on the same first gate line 3G1 via a via. The second gate connection line 4G2 can be connected to the second gate line segment G22 located on the same second gate line G2 via vias respectively. The first reset connection line 4Re1 is connected to the first reset signal line segment 3Re11 located on the same first reset signal line 3Re1 via a via, and can be connected to the third reset signal line 2Re1 via a plurality of vias. The second reset connection line 4Re2 can be connected to the second reset signal line Re2 via a plurality of vias. In this embodiment example, the sheet resistance of the fourth conductive layer may be smaller than the square resistance of the first conductive layer, the second conductive layer, and the third conductive layer. The first gate connection line 4G1 can reduce the self-resistance of the first gate line 3G1 and the third gate line 2G1, and increase the response speed of the second transistor. The second gate connection line 4G2 can reduce the self-resistance of the second gate line G2, and improve the response speed of the fourth transistor T4.The first reset connection line 4Re1 can reduce the self-resistance of the first reset signal line 3Re1 and the third reset signal line 2Re1, and improve the response speed of the first transistor T1. The second reset connection line 4Re2 can reduce the self-resistance of the second reset signal line Re2, and improve the response speed of the seventh transistor and the eighth transistor.

[0107] As shown in FIGS. 44 and 52, the fifth conductive layer may include a plurality of third power supply lines VDD, a plurality of data lines Da, a second power supply line VSS2, a fourth initial line 5Vinit1, a fifth initial line 5Vinit2, and a ninth bridge portion 59. Here, the orthographic projection of the third power supply line VDD onto the base substrate, the orthographic projection of the data line Da onto the base substrate, the orthographic projection of the second power supply line VSS2 onto the base substrate, the orthographic projection of the fourth initial line 5Vinit1 onto the base substrate, and the orthographic projection of the fifth initial line 5Vinit2 onto the base substrate can all extend along the second direction Y. The third power supply line VDD can be used to provide a first power supply terminal, the data line Da can be used to provide a data signal terminal, and the second power supply line VSS2 can be used to provide a second power supply terminal. As shown in FIG. 44, a third power supply line VDD may be correspondingly provided for each column of pixel driving circuits, and the third power supply line VDD may be connected via a first bridge portion 41 and a via so as to connect the first pole of the fifth transistor to the first power supply terminal. The data line Da can be connected via a via to a sixth bridge portion 46 to connect the first pole of the fourth transistor to the data signal terminal. The ninth bridge portion 59 can be connected via a via to a second bridge portion 42 to connect the second pole of the seventh transistor. The second power supply line VSS2 can be connected via a via to an intersecting first power supply line VSS1, and the first power supply line VSS1 and the second power supply line VSS2 can be connected to a common electrode layer. The first power supply line VSS1 and the second power supply line VSS2 forming a mesh structure can reduce the voltage difference between different positions on the common electrode layer. The fourth initial line 5Vinit1 can be connected via a via to an intersecting first initial signal line Vinit1, and the fourth initial line 5Vinit1 and the first initial signal line Vinit1 form a mesh structure to reduce the voltage difference between the first initial signal lines in pixel driving circuits at different positions of the display panel.The fifth initial line 5Vinit2 can be connected to the intersecting second initial signal line Vinit2 via vias. The fifth initial line 5Vinit2 and the second initial signal line Vinit2 form a mesh structure, which can reduce the voltage difference between the second initial signal lines in pixel driving circuits at different positions of the display panel. In this exemplary embodiment, as shown in FIG. 44, each three columns of pixel driving circuits can correspondingly be provided with the second power line VSS2, the fourth initial line 5Vinit1, and the fifth initial line 5Vinit2.

[0108] In other exemplary embodiments, it should be understood that the fifth conductive layer can also include a third initial connection line connected to the intersecting third initial signal lines via vias to reduce the voltage difference between the third initial signal lines in pixel driving circuits at different positions of the display panel.

[0109] As shown in FIGS. 44 and 58, the black blocks drawn on the side where the fourth conductive layer is away from the base substrate side indicate the vias connected to other layers facing the base substrate side of the fourth conductive layer, and the black blocks drawn on the side where the fifth conductive layer is away from the base substrate indicate the vias connected to other layers facing the base substrate side of the fifth conductive layer. This black block only indicates the position of the via, and the different holes indicated by the black blocks at different positions can penetrate different insulating layers.

[0110] As shown in FIG. 59, it is a partial cross-sectional view taken along the broken line CC of the display panel shown in FIG. 44. This display panel further includes a first insulating layer 91, a second insulating layer 92, a third insulating layer 93, a fourth insulating layer 94, a fifth insulating layer 95, a first dielectric layer 96, and a first planarizing layer 97. Here, a base substrate 90, a light-shielding layer, the first insulating layer 91, the first active layer, the second insulating layer 92, the first conductive layer, the third insulating layer 93, the second conductive layer, the fourth insulating layer 94, the second active layer, the fifth insulating layer 95, the third conductive layer, the first dielectric layer 96, the fourth conductive layer, the first planarizing layer 97, and the fifth conductive layer are sequentially laminated. The first insulating layer 91, the second insulating layer 92, the third insulating layer 93, the fourth insulating layer 94, and the fifth insulating layer 95 can be a single-layer structure or a multilayer structure, and the materials of the first insulating layer 91, the second insulating layer 92, the third insulating layer 93, the fourth insulating layer 94, and the fifth insulating layer 95 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride. The first dielectric layer 96 may be a silicon nitride layer, and the material of the first planarizing layer 97 may be an organic material such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or a silicon-on-glass structure (SOG). The base substrate 90 includes a glass base substrate, a barrier layer, and a polyimide layer laminated in sequence, and the barrier layer may be an inorganic material. The materials of the first conductive layer, the second conductive layer, and the third conductive layer may be one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum / titanium alloy, or a laminate, etc. The materials of the fourth conductive layer and the fifth conductive layer can include a metal material. For example, it can be one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum / titanium alloy or a laminate, etc., or a titanium / aluminum / titanium laminate. The light-shielding layer may be a conductive layer. For example, the light-shielding layer may be a molybdenum layer.

[0111] In other exemplary embodiments, it should be understood that the second power line may be disposed on the light-shielding layer. As shown in FIGS. 60 to 63, FIG. 60 is a structural layout diagram of another exemplary embodiment of the display panel of the present disclosure, FIG. 61 is a structural layout diagram of the light-shielding layer of FIG. 60, FIG. 62 is a structural layout diagram of the fourth conductive layer of FIG. 60, and FIG. 63 is a structural layout diagram of the light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer of FIG. 60.

[0112] As shown in FIGS. 60, 61, and 63, the display panel shown in FIG. 60 is different from the display panel shown in FIG. 44 in that the light-shielding layer of the display panel shown in FIG. 60 can also include a sixth initial line 6Vinit1, a seventh initial line 6Vinit2, and a second power line 6VSS2. The orthographic projection of the sixth initial line 6Vinit1 onto the base substrate, the orthographic projection of the seventh initial line 6Vinit2 onto the base substrate, and the orthographic projection of the second power line 6VSS2 onto the base substrate can extend in the second direction Y. As shown in FIGS. 60, 61, 62, and 63, the first initial line Vinit1 can be via-connected to the intersecting sixth initial line 6Vinit1, the second initial line Vinit2 can be via-connected to the intersecting seventh initial line 6Vinit2, and the first power line VSS1 can be via-connected to the intersecting second power line 6VSS2. Here, the sixth initial line 6Vinit1, the first initial line Vinit1, and the fourth initial line 5Vinit1 can form a mesh structure, and the sixth initial line 6Vinit1 can further display the voltage difference of the first initial signal line in the pixel driving circuits at different positions of the panel. The seventh initial line 6Vinit2, the second initial line Vinit2, and the fifth initial line 5Vinit2 can form a mesh structure. The seventh initial line 6Vinit2 can further display the voltage difference of the second initial signal line in the pixel driving circuits at different positions of the panel. The second power line 6VSS2, the first power line VSS1, and the second power line VSS2 can form a mesh structure. The second power line 6VSS2 can further reduce the voltage difference between different positions of the common electrode layer.

[0113] The other configurations of the display panel shown in FIG. 60 may be the same as those of the display panel shown in FIG. 44.

[0114] In other exemplary embodiments, it should be understood that the third initial signal line Vinit3 can also form a mesh structure. As shown in FIGS. 64 to 68, FIG. 64 is a structural layout diagram of another exemplary embodiment of the display panel of the present disclosure, FIG. 65 is a structural layout diagram of the light-shielding layer of FIG. 64, FIG. 66 is a structural layout diagram of the fourth conductive layer of FIG. 64, FIG. 67 is a structural layout diagram of the fifth conductive layer of FIG. 64, and FIG. 68 is a structural layout diagram of the light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer of FIG. 64.

[0115] As shown in FIGS. 64, 65, and 68, the display panel shown in FIG. 64 is different from the display panel shown in FIG. 44 in that the light-shielding layer of the display panel shown in FIG. 64 can also include a sixth initial line 6Vinit1, a seventh initial line 6Vinit2, and an eighth initial line 6Vinit3. As shown in FIGS. 64, 65, 66, and 68, the first initial line Vinit1 can be connected to the intersecting sixth initial line 6Vinit1 via a via, the second initial line Vinit2 can be connected to the intersecting seventh initial line 6Vinit2 via a via, and the third initial line Vinit3 can be connected to the intersecting eighth initial line 6Vinit3 via a via. Here, the sixth initial line 6Vinit1 and the first initial line Vinit1 can form a mesh structure, and the initial signal line of this mesh structure can reduce the voltage difference of the first initial signal line in the pixel driving circuits at different positions of the display panel. The seventh initial line 6Vinit2 and the second initial line Vinit2 can form a mesh structure. The initial signal line of this mesh structure can reduce the voltage difference of the second initial signal line in the pixel driving circuits at different positions of the display panel. The eighth initial line 6Vinit3 and the third initial line Vinit3 can form a mesh structure. The initial signal line of this mesh structure can reduce the voltage difference of the third initial signal line in the pixel driving circuits at different positions of the display panel.

[0116] As shown in FIGS. 64 and 67, the fifth conductive layer of the display panel shown in FIG. 64 does not provide the fourth initial line 5Vinit1 and the fifth initial line 5Vinit2 compared to the display panel shown in FIG. 44. A second power line VSS2 is provided for each column of pixel driving circuits, and each second power line VSS2 is via-connected to a first power line VSS1 that intersects it.

[0117] Other configurations of the display panel shown in FIG. 64 may be the same as those of the display panel shown in FIG. 44.

[0118] FIG. 69 is a structural layout diagram of another exemplary embodiment of the display panel of the present disclosure, as shown in FIGS. 69 to 71. FIG. 70 is a structural layout diagram of the second conductive layer in FIG. 69, and FIG. 71 is a structural layout diagram of the fifth conductive layer in FIG. 69.

[0119] The display panel shown in FIG. 69 is different from the display panel shown in FIG. 64 in that the second conductive layer of the display panel shown in FIG. 69 can include a first power line 2VSS1, and the orthographic projection of the first power line 2VSS1 onto the base substrate can extend in the first direction X. The display panel shown in FIG. 69 is different from the display panel shown in FIG. 64 in that the second power line VSS2 in the fifth conductive layer can also be connected to the intersecting first power line 2VSS1 via vias, as shown in FIG. 69. Therefore, the first power line 2VSS1, the first power line VSS1, and the second power line VSS2 can form a mesh structure that can reduce the voltage difference at different positions of the common electrode layer.

[0120] Other configurations of the display panel shown in FIG. 69 may be the same as those of the display panel shown in FIG. 64.

[0121] In addition, this embodiment provides a display device including the above-described display panel. This display device may be a display device such as a mobile phone, a tablet, or a television.

[0122] After considering and practicing the specification and the content disclosed herein, those skilled in the art will readily conceive of other embodiments of the present disclosure. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include known common general knowledge or conventional technical means in the art not disclosed in the present disclosure. The specification and embodiments are to be regarded only as examples, and the true scope and spirit of the present disclosure are pointed out by the claims.

[0123] It should be understood that the present disclosure is not limited to the exact structures shown in the above-described drawings, and various modifications and changes can be made without departing from its scope. The scope of the present disclosure is defined only by the appended claims.

Claims

Claim 1 A display panel including a display area, a light-emitting unit located in the display area, and a pixel driving circuit for driving the light-emitting unit, wherein the pixel driving circuit is connected to a first electrode of the light-emitting unit, The display panel further includes a base substrate, a first power line, a second power line, and a common electrode layer, The first power line is located in the display area of the display panel, and a positive projection of the first power line onto the base substrate extends along a first direction, The second power line is located in the display area of the display panel, and a positive projection of the second power line onto the base substrate extends along a second direction, the second direction intersects the first direction, and at least a part of the second power line is connected to at least a part of the first power line via a via, The common electrode layer is located on the side of the base substrate, the common electrode layer is used to form a second electrode of the light-emitting unit, and the common electrode layer is connected to the first power line and the second power line A display panel characterized by the above. Claim 2 Both ends of the first power line are respectively connected to the common electrode layer, and both ends of the second power line are respectively connected to the common electrode layer The display panel according to claim 1, characterized by the above. Claim 3 The pixel driving circuit includes a driving transistor and a seventh transistor. A first pole of the seventh transistor is connected to a second initial signal line, and a second pole is connected to a first electrode of the light-emitting unit, The display panel further includes a first active layer, The first active layer is located between the base substrate and the common electrode layer. The first active layer includes a third active part and a seventh active part. The third active part is used to form a channel region of the driving transistor, and the seventh active part is used to form a channel region of the seventh transistor, A positive projection of the second power line onto the base substrate and a positive projection of the third active part onto the base substrate at least partially overlap, and a positive projection of the second power line onto the base substrate and a positive projection of the seventh active part onto the base substrate at least partially overlap The display panel according to claim 1, characterized by the above. Claim 4 The pixel driving circuit includes an N-type transistor and a P-type transistor, and the display panel further includes a first active layer, a second active layer, and a third conductive layer. The first active layer is located between the base substrate and the common electrode layer, and a partial structure of the first active layer is used to form a channel region of the P-type transistor. The second active layer is located between the base substrate and the common electrode layer, and a partial structure of the second active layer is used to form a channel region of the N-type transistor. The third conductive layer is located between the second active layer and the common electrode layer, and a partial structure of the third conductive layer is used to form a top gate of the N-type transistor. At least a part of the first power line is located in the third conductive layer. The display panel according to claim 1, characterized in that.

5. The pixel driving circuit includes a driving transistor and a fifth transistor. A first pole of the fifth transistor is connected to a third power line, and a second pole is connected to a first pole of the driving transistor. The display panel further includes a fifth conductive layer. The fifth conductive layer is located between the base substrate and the common electrode layer, and the fifth conductive layer includes the third power line. At least a part of the second power line is located in the fifth conductive layer. The display panel according to claim 1, characterized in that.

6. The display panel further includes a third conductive layer, a fourth conductive layer, and a fifth conductive layer. The third conductive layer is located between the base substrate and the common electrode layer, and the first power line is located in the third conductive layer. The fourth conductive layer is located between the third conductive layer and the common electrode layer, and the fourth conductive layer includes a seventh bridge portion. The fifth conductive layer is located between the fourth conductive layer and the common electrode layer, and the second power line is located in the fifth conductive layer. A positive projection of the seventh bridge portion onto the base substrate and a positive projection of the first power line onto the base substrate at least partially overlap, and a positive projection of the seventh bridge portion onto the base substrate and a positive projection of the second power line onto the base substrate at least partially overlap. The seventh bridge portion is connected to the first power line and the second power line through vias respectively. The display panel according to claim 1, characterized in that.

7. The pixel driving circuit includes a driving transistor, a sixth transistor, and a seventh transistor. A first pole of the sixth transistor is connected to a second pole of the driving transistor. A second pole of the sixth transistor is connected to a first electrode of the light emitting unit. A first pole of the seventh transistor is connected to a second initial signal line. A second pole of the seventh transistor is connected to the first electrode of the light emitting unit. The display panel further includes a first active layer. The first active layer is located between the base substrate and the third conductive layer. The first active layer includes a sixth active portion, a seventh active portion, and a tenth active portion. The sixth active portion is used to form a channel region of the sixth transistor. The seventh active portion is used to form a channel region of the seventh transistor. The tenth active portion is connected between the sixth active portion and the seventh active portion. A positive projection of the seventh bridge portion onto the base substrate and a positive projection of the tenth active portion onto the base substrate at least partially overlap. The display panel according to claim 6, characterized in that.

8. The pixel driving circuit further includes a fourth transistor. A first pole of the fourth transistor is connected to a data line. A second pole of the fourth transistor is connected to a first pole of the driving transistor. The fifth conductive layer further includes the data line. A positive projection of the data line onto the base substrate and a positive projection of the third power line onto the base substrate extend along the second direction. In pixel driving circuits in the same column, a positive projection of the third power line located in the fifth conductive layer onto the base substrate is located between the positive projection of the data line onto the base substrate and the positive projection of the third power line onto the base substrate. The display panel according to claim 5, characterized in that.

9. The first direction is the row direction, and the second direction is the column direction. The display panel includes a plurality of repeating units distributed in a matrix direction. Each repeating unit includes a first pixel driving circuit and a second pixel driving circuit distributed in the row direction. The first pixel driving circuit and the second pixel driving circuit are arranged in mirror symmetry. The pixel driving circuit includes a driving transistor and a capacitor. A first electrode of the capacitor is connected to the gate of the driving transistor, and a second electrode of the capacitor is connected to a third power line. The display panel further includes a second conductive layer and a fifth conductive layer. The second conductive layer is located between the base substrate and the common electrode layer. The second conductive layer includes a first conductive portion, and the first conductive portion is used to form the second electrode of the capacitor. The fifth conductive layer is located between the second conductive layer and the common electrode layer. The fifth conductive layer includes the third power line. Each pixel driving circuit in each column is provided corresponding to one third power line. The third power line includes a first extending portion, a second extending portion, and a third extending portion. The second extending portion is connected between the first extending portion and the third extending portion. The size of the positive projection of the second extending portion on the base substrate in the row direction is larger than the size of the positive projection of the first extending portion on the base substrate in the row direction, and the size of the positive projection of the second extending portion on the base substrate in the row direction is larger than the size of the positive projection of the third extending portion on the base substrate in the row direction. In the same repeating unit, the second extending portions of two adjacent third power lines are connected, and the first conductive portions of two adjacent repeating units adjacent in the row direction are connected. The display panel according to claim 1, characterized in that.

10. The pixel driving circuit includes a driving transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a capacitor. A first pole of the fourth transistor is connected to a data line, a second pole of the fourth transistor is connected to a first pole of the driving transistor, a first pole of the fifth transistor is connected to a third power line, a second pole of the fifth transistor is connected to a first pole of the driving transistor, a first pole of the sixth transistor is connected to a second pole of the driving transistor, a second pole of the seventh transistor is connected to a second pole of the sixth transistor, a first pole of the seventh transistor is connected to a second initial signal line, a first electrode of the capacitor is connected to the gate of the driving transistor, and a second electrode of the capacitor is connected to the third power line. The display panel further includes a first active layer and a first conductive layer, wherein the first active layer is located between the base substrate and the common electrode layer, and the first active layer includes a third active portion, a fourth active portion, a fifth active portion, a sixth active portion, and a seventh active portion. The third active portion is used to form the channel region of the driving transistor. The fourth active portion is used to form the channel region of the fourth transistor. The fifth active portion is used to form the channel region of the fifth transistor. The sixth active portion is used to form the channel region of the sixth transistor. The seventh active portion is used to form the channel region of the seventh transistor. The first conductive layer is located between the first active layer and the common electrode layer. The first conductive layer includes a second gate line, an enable signal line, a second reset signal line, and a second conductive portion. The orthographic projection of the second gate line onto the base substrate extends in the first direction and covers the orthographic projection of the fourth active portion onto the base substrate, and a partial structure of the second gate line is used to form the gate of the fourth transistor. The orthographic projection of the enable signal line onto the base substrate extends along the first direction and covers the orthographic projection of the fifth active portion onto the base substrate and the orthographic projection of the sixth active portion onto the base substrate. A partial structure of the enable signal line is used to form the gate of the sixth transistor, and another partial structure of the enable signal line is used to form the gate of the fifth transistor. The orthographic projection of the second reset signal line onto the base substrate extends along the first direction and covers the orthographic projection of the seventh active portion onto the base substrate, and a partial structure of the second reset signal line is used to form the gate of the seventh transistor. The orthographic projection of the second conductive portion onto the base substrate covers the orthographic projection of the third active portion onto the base substrate, and the second conductive portion is used to form the gate of the driving transistor and the first electrode of the capacitor. In the same pixel driving circuit, the orthographic projection of the second conductive portion onto the base substrate is located between the orthographic projection of the second gate line onto the base substrate and the orthographic projection of the enable signal line onto the base substrate. The orthographic projection of the second reset signal line onto the base substrate is located on the side where the orthographic projection of the enable signal line onto the base substrate is away from the orthographic projection of the second conductive portion onto the base substrate. The display panel according to claim 1, characterized in that.

11. The second gate line in the pixel driving circuit of this row is multiplexed as the second reset signal line in the pixel driving circuit of the previous row. The display panel according to claim 10, characterized in that.

12. The pixel driving circuit further includes a first transistor and a second transistor. The first pole of the first transistor is connected to the gate of the driving transistor. The second pole of the first transistor is connected to a first initial signal line. The first pole of the second transistor is connected to the gate of the driving transistor. The second pole of the second transistor is connected to the second pole of the driving transistor. The display panel further includes a second active layer, a third conductive layer, and a fifth conductive layer. The second active layer is located between the first conductive layer and the common electrode layer. The second active layer includes a first active portion and a second active portion. The first active portion is used to form the channel region of the first transistor. The second active portion is used to form the channel region of the second transistor. The third conductive layer is located between the second active layer and the common electrode layer. The third conductive layer includes a first reset signal line and a first gate line. The orthographic projection of the first reset signal line onto the base substrate covers the orthographic projection of the first active portion onto the base substrate. A partial structure of the first reset signal line is used to form the top gate of the first transistor. The orthographic projection of the first gate line onto the base substrate covers the orthographic projection of the second active portion onto the base substrate. A partial structure of the first gate line is used to form the top gate of the second transistor. The fifth conductive layer is located between the third conductive layer and the common electrode layer. The fifth conductive layer includes the third power line, and the orthographic projection of the third power line onto the base substrate covers the orthographic projection of the first active portion onto the base substrate and the orthographic projection of the second active portion onto the base substrate. In the same pixel driving circuit, the orthographic projection of the first gate line onto the base substrate is located between the orthographic projection of the second conductive portion onto the base substrate and the orthographic projection of the second gate line onto the base substrate. The orthographic projection of the first reset signal line onto the base substrate is located on the side where the orthographic projection of the second gate line onto the base substrate is away from the orthographic projection of the second conductive portion onto the base substrate. The display panel according to claim 10, characterized in that.

13. The display panel further includes a second conductive layer located between the first conductive layer and the second active layer. The second conductive layer includes a first initial signal line, a third reset signal line, and a third gate line. The orthographic projection of the first initial signal line onto the base substrate is located on the side where the orthographic projection of the first reset signal line onto the base substrate is away from the orthographic projection of the second conductive portion onto the base substrate. The third reset signal line is connected to the first reset signal line via a via, and its orthographic projection onto the base substrate covers the orthographic projection of the first active portion onto the base substrate. A partial structure of the third reset signal line is used to form the bottom gate of the first transistor. The orthographic projection of the third gate line onto the base substrate covers the orthographic projection of the second active portion onto the base substrate, and a partial structure of the third gate line is used to form the bottom gate of the second transistor. The display panel according to claim 12, characterized in that.

14. The pixel driving circuit includes a driving transistor and a seventh transistor. A first pole of the seventh transistor is connected to a second initial signal line, and a second pole is connected to a first electrode of the light-emitting unit. The display panel further includes a fourth conductive layer. The fourth conductive layer is located between the base substrate and the common electrode layer. The fourth conductive layer includes a fourth bridge portion, and the fourth bridge portion is connected to the gate of the driving transistor via a via. The second initial signal line is located in the fourth conductive layer The display panel according to claim 1, characterized in that

15. The display panel further includes a third conductive layer, The third conductive layer is located between the first conductive layer and the common electrode layer, At least a part of the first power line is located in the third conductive layer, and a positive projection of the first power line located in the third conductive layer onto the base substrate is located between a positive projection of the second conductive portion onto the base substrate and a positive projection of the second reset signal line onto the base substrate. A positive projection of the first power line located in the third conductive layer onto the base substrate and a positive projection of the enable signal line onto the base substrate overlap at least partially The display panel according to claim 10, characterized in that

16. The area of the positive projection of the first power line located in the third conductive layer onto the base substrate is S1, The area of the overlap between the positive projection of the first power line located in the third conductive layer onto the base substrate and the positive projection of the enable signal line onto the base substrate is S2, S2 / S1 is 80% or more The display panel according to claim 15, characterized in that

17. The first transistor and the second transistor are N-type transistors, The driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are P-type transistors The display panel according to claim 12, characterized in that

18. The display area includes a sector-out area and a normal display area, The plurality of first power lines include a first sub-power line, and two first cutouts located in the sector-out area are formed in the first sub-power line. The first sub-power line includes a portion of the first sub-power line located between the two first cutouts, The plurality of second power lines include a second sub-power line, and a second cutout located in the sector-out area is formed in the second sub-power line. The second sub-power line includes portions of the second sub-power line divided by the second cutout, and the portions of the second sub-power line are located in the sector-out area, The display panel further includes a plurality of data lines, a positive projection of the data lines onto the base substrate extends along the second direction, and the plurality of data lines include a first data line The first data line is connected to the first sub-power supply line, and the first sub-power supply line is connected to the second sub-power supply line. The display panel according to claim 1, characterized in that.

19. The display panel further includes a third conductive layer, a fourth conductive layer, and a fifth conductive layer. The third conductive layer is located between the base substrate and the common electrode layer, and the third conductive layer includes the first sub-power supply line. The fourth conductive layer is located between the third conductive layer and the common electrode layer, and the fourth conductive layer includes a seventh bridge portion and a tenth bridge portion. The fifth conductive layer is located between the fourth conductive layer and the common electrode layer, and the fifth conductive layer includes the first data line and the second sub-power supply line. The first data line is connected to the tenth bridge portion via a via, the tenth bridge portion is connected to the first sub-power supply line via a via, the seventh bridge portion is connected to the first sub-power supply line via a via, and the second sub-power supply line is connected to the seventh bridge portion via a via. The display panel according to claim 18, characterized in that.

20. The display panel further includes a first signal line and a second signal line. The first signal line is provided corresponding to a row of the pixel driving circuit, and a positive projection of the first signal line onto the base substrate extends along the first direction. The second signal line is provided corresponding to a column of the pixel driving circuit, and a positive projection of the second signal line onto the base substrate extends along the second direction. The display panel further includes a virtual pixel row and a virtual pixel column located in the display area. The first signal line located in the virtual pixel row is multiplexed as the first power supply line, and the second signal line located in the virtual pixel column is multiplexed as the second power supply line. The display panel according to claim 1, characterized in that.

21. The pixel driving circuit includes a driving transistor and a fifth transistor. A first pole of the fifth transistor is connected to a third power supply line, a second pole is connected to a first pole of the driving transistor, and a gate is connected to an enable signal line. The first signal line includes the enable signal line. The display panel according to claim 20, characterized in that.

22. The pixel driving circuit includes a driving transistor and a fourth transistor. A first pole of the fourth transistor is connected to a data line, and a second pole thereof is connected to a first pole of the driving transistor. The second signal line includes the data line. The display panel according to claim 20, characterized in that.

23. The pixel driving circuit includes a driving transistor and a capacitor. A first electrode of the capacitor is connected to a gate of the driving transistor, and a second electrode of the capacitor is connected to a third power line. The display panel further includes a second conductive layer and a fourth conductive layer. The second conductive layer is located between the base substrate and the common electrode layer. The second conductive layer includes a first conductive portion, and the first conductive portion is used to form the second electrode of the capacitor. The fourth conductive layer is located between the second conductive layer and the common electrode layer. The fourth conductive layer includes a first bridge portion, and the first bridge portion is connected to the first conductive portion via a via. In the virtual pixel row, the first bridge portions are connected to each other, and the first signal line includes a signal line formed by the connected first bridge portions. The display panel according to claim 20, characterized in that.

24. The pixel driving circuit further includes a driving transistor and a fourth transistor. A first pole of the fourth transistor is connected to a data line, a second pole thereof is connected to a first pole of the driving transistor, and a gate is connected to a second gate line. The first signal line includes the second gate line. The display panel according to claim 20, characterized in that.

25. The pixel driving circuit includes a driving transistor. The display panel further includes a fourth conductive layer. The fourth conductive layer is located between the base substrate and the common electrode layer. The fourth conductive layer includes a fourth bridge portion, and the fourth bridge portion is connected to a gate of the driving transistor via a via. At least a part of the first power line is located in the fourth conductive layer. The display panel according to claim 1, characterized in that.

26. The pixel driving circuit includes a driving transistor. The display panel further includes a first active layer and a light-shielding layer. The first active layer is located between the base substrate and the common electrode layer. The first active layer includes a third active portion, and the third active portion is used to form the channel region of the driving transistor. The light-shielding layer is located between the base substrate and the first active layer. The light-shielding layer includes a light-shielding portion, and the orthographic projection of the light-shielding portion onto the base substrate covers the orthographic projection of the third active portion onto the base substrate. At least a part of the second power line is located in the light-shielding layer. The display panel according to claim 1, characterized in that.

27. The pixel driving circuit includes a driving transistor and a capacitor. The first electrode of the capacitor is connected to the gate of the driving transistor, and the second electrode is connected to a third power line. The display panel further includes a second conductive layer. The second conductive layer is located between the base substrate and the common electrode layer. The second conductive layer includes a first conductive portion, and the first conductive portion is used to form the second electrode of the capacitor. At least a part of the first power line is located in the second conductive layer. The display panel according to claim 1, characterized in that.

28. The pixel driving circuit includes a driving transistor, a fourth transistor, and a capacitor. The first electrode of the fourth transistor is connected to a data line, the second electrode is connected to the first electrode of the driving transistor, the first electrode of the capacitor is connected to the gate of the driving transistor, and the second electrode is connected to a third power line. The display panel further includes a first active layer and a second conductive layer. The first active layer is located between the base substrate and the common electrode layer. The first active layer includes a third active portion, a fourth active portion, and a nineteenth active portion. The third active portion is used to form the channel region of the driving transistor, the fourth active portion is used to form the channel region of the fourth transistor, the nineteenth active portion is connected between the third active portion and the fourth active portion, and the size of the orthographic projection of the nineteenth active portion onto the base substrate in the first direction is larger than the size of the orthographic projection of the fourth active portion onto the base substrate in the first direction. The second conductive layer is located between the first active layer and the common electrode layer, and the second conductive layer includes a first conductive portion and a fourth conductive portion. The first conductive portion is used to form the second electrode of the capacitor, the fourth conductive portion is connected to the first conductive portion, and the orthographic projection of the fourth conductive portion onto the base substrate and the orthographic projection of the nineteenth active portion onto the base substrate overlap at least partially. The display panel according to claim 1, characterized in that.

29. Including the display panel according to any one of claims 1 to 28 A display device characterized by that.

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