Display substrate, method for manufacturing the same, and display device

Abstract

A display substrate, a manufacturing method thereof, and a display device. The display substrate includes a plurality of sub-pixels, each sub-pixel includes a first region q1, a gap region q3, and a second region q2, each sub-pixel includes a first transistor T1, a second transistor T2, and a third transistor T3, the first transistor T1 includes a first active layer 1 and a first gate electrode 11, the second transistor T2 includes a second active layer 2 and a second gate electrode 12, the third transistor T3 includes a third active layer 3 and a third gate electrode 13, the first active layer 1 is provided in the first region q1, the second active layer 2 and the third active layer 3 are provided in the second region q2, a via where the first gate electrode 11 and the third gate electrode 13 are connected to a scanning signal line, and a via where the second gate electrode 12 is connected to the first transistor T1 are both provided in the gap region q3.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, but is not limited thereto, and particularly relates to a display substrate, a manufacturing method thereof, and a display device.

Background Art

[0002] A micro organic light-emitting diode (abbreviated as Micro-OLED) is a microdisplay that has been developed in recent years, and a silicon-based OLED is a type thereof. The silicon-based OLED can not only realize active addressing of pixels, but also provide structures such as pixel driving circuits on a silicon-based substrate, which is advantageous for reducing the volume of the system and achieving weight reduction. The silicon-based OLED is manufactured using a mature complementary metal oxide semiconductor (CMOS) integrated circuit process, and has advantages such as a small volume, high resolution (abbreviated as Pixels Per Inch, PPI), and a high refresh rate.

Summary of the Invention

[0003] The following is an overview of the theme to be described in detail in the text. This overview is not intended to limit the scope of protection of the claims.

[0004] In one aspect, an embodiment of the present disclosure provides a display substrate including a display area and a bezel area. The display area includes a plurality of sub-pixels in which a plurality of pixel rows and a plurality of pixel columns are formed. The sub-pixels include a first area, a gap area, and a second area that are sequentially arranged along the pixel row direction. At least one sub-pixel includes a pixel driving circuit, a first scanning signal line, and a second scanning signal line. The pixel driving circuit includes at least a first transistor, a second transistor, and a third transistor. The first scanning signal line is configured to control the on or off of the first transistor. The second scanning signal line is configured to control the on or off of the second transistor. The first transistor includes at least a first gate electrode, a first active layer, a first pole of the first transistor, and a second pole of the first transistor. The second transistor includes at least a second gate electrode and a second active layer. The third transistor includes at least a third gate electrode and a third active layer. The first active layer is provided in the first area. The second active layer and the third active layer are provided in the second area. The second active layer is provided on one side of the third active layer in the pixel column direction. The first scanning signal line is connected to the first gate electrode via a first gate via. The second pole of the first transistor is connected to the second gate electrode via a second gate via. The second scanning signal line is connected to the third gate electrode via a third gate via. The first gate via, the second gate via, and the third gate via are provided in the gap area.

[0005] In an exemplary embodiment, along the pixel row direction, the first area has a first width, the second area has a second width, the gap area has a third width, the third width is less than or equal to 0.5 * the first width, and the third width is less than or equal to 0.5 * the second width.

[0006] In an exemplary embodiment, the first gate electrodes of two adjacent sub-pixels on the pixel row are an integrated structure connected to each other, and the third gate electrodes of two adjacent sub-pixels on the pixel row are an integrated structure connected to each other.

[0007] In an exemplary embodiment, the first gate electrode of the integrated structure is connected to the first scanning signal line via two first gate vias, and the third gate electrode of the integrated structure is connected to the second scanning signal line via two third gate vias.

[0008] In an exemplary embodiment, the first transistor, the second transistor, and the third transistor of two adjacent sub-pixels on the pixel row are mirror-symmetric with respect to the pixel center line, and the pixel center line is located between two adjacent sub-pixels on the pixel row and is a straight line extending along the pixel column direction.

[0009] In an exemplary embodiment, in at least one sub-pixel, the first gate electrode includes a first gate main body portion and a first gate connection portion that are connected to each other, the first gate connection portion is provided in the gap region, and the first scanning signal line is connected to the first gate connection portion via the first gate via.

[0010] In an exemplary embodiment, in at least one sub-pixel, the second gate electrode includes a second gate main body portion and a second gate connection portion that are connected to each other, the second gate connection portion is provided in the gap region, and the second pole of the first transistor is connected to the second gate connection portion via the second gate via.

[0011] In an exemplary embodiment, in at least one sub-pixel, the third gate electrode includes a third gate main body portion and a third gate connection portion that are connected to each other, the third gate connection portion is provided in the gap region, and the second scanning signal line is connected to the third gate connection portion via the third gate via.

[0012] In an exemplary embodiment, in at least one sub-pixel, the first gate electrode includes a first gate main body portion and a first gate connection portion that are connected to each other. The first gate connection portion is disposed on a side of the first gate main body portion close to the third gate electrode. The third gate electrode includes a third gate main body portion and a third gate connection portion that are connected to each other. The third gate connection portion is disposed on a side of the third gate main body portion close to the first gate electrode. The first gate connection portion and the third gate connection portion are disposed offset in the pixel column direction.

[0013] In an exemplary embodiment, edges on a side of the first gate main body portion and the first gate connection portion away from the second transistor are flush, and edges on a side of the third gate main body portion and the third gate connection portion close to the second transistor are flush.

[0014] In an exemplary embodiment, in at least one sub-pixel, the second gate electrode includes a second gate main body portion and a second gate connection portion that are connected to each other. The second gate connection portion is provided in the gap region. Edges on a side of the second gate main body portion and the second gate connection portion close to the third transistor are flush.

[0015] In an exemplary embodiment, the shapes of the first scanning signal line and the second scanning signal line are linear with the main body portions extending along the pixel row direction. A front projection of the first scanning signal line on the plane of the display substrate overlaps at least a part of the front projections of the first gate electrode and the third gate electrode on the plane of the display substrate. A front projection of the second scanning signal line on the plane of the display substrate overlaps at least a part of the front projections of the first gate electrode and the third gate electrode on the plane of the display substrate.

[0016] In an exemplary embodiment, the second transistor further includes a first pole of the second transistor and a second pole of the second transistor, the third transistor further includes a first pole of the third transistor and a second pole of the third transistor, the first source electrode is connected to a data signal line, the first pole of the second transistor is connected to a light emission voltage line, the first pole of the third transistor is connected to a reference signal line, and the second pole of the second transistor and the second pole of the third transistor are in an integrated structure connected to each other.

[0017] In an exemplary embodiment, in at least one sub-pixel, the pixel driving circuit further includes a storage capacitor, the storage capacitor includes a first electrode plate and a second electrode plate, a positive projection of the first electrode plate on the plane of the display substrate overlaps at least a part of a positive projection of the second electrode plate on the plane of the display substrate, the first electrode plate is connected to the second pole of the first transistor through a connection electrode, and the second electrode plate is connected to a first power supply line.

[0018] In an exemplary embodiment, at least one sub-pixel further includes a contact electrode, the contact electrode is provided in the first region, and the contact electrode is provided on one side of the first active layer in the pixel column direction.

[0019] In an exemplary embodiment, at least one sub-pixel further includes a bias voltage line, the bias voltage line is connected to the contact electrode through a via, and a positive projection of the bias voltage line on the plane of the display substrate overlaps at least a part of a positive projection of the second gate electrode on the plane of the display substrate.

[0020] In an exemplary embodiment, in at least one sub-pixel, the shape of the contact electrode is a stripe shape extending along the pixel column direction, the shape of the bias voltage line is a linear shape extending along the pixel column direction, and on one side or both sides of the bias voltage line in the pixel column direction, a bias connection line whose positive projection on the plane of the display substrate overlaps at least a part of the positive projection of the contact electrode on the plane of the display substrate is connected, and the bias connection line is connected to the contact electrode through a via.

[0021] In an exemplary embodiment, the bias voltage line and the bias connection line are of an integral structure connected to each other.

[0022] In an exemplary embodiment, the bezel region includes at least a light emission control transistor. The gate electrode of the light emission control transistor is connected to a light emission control line. The first pole of the light emission control transistor is connected to a bezel power lead wire. The second pole of the light emission control transistor is connected to a light emission voltage line. The light emission voltage line is connected to the first poles of second transistors of a plurality of sub-pixels in one pixel row. The bezel power lead wire is connected to the first power supply line.

[0023] In an exemplary embodiment, in a plane perpendicular to the display substrate, the display substrate includes at least a first conductive layer and a second conductive layer sequentially provided on a silicon base. The silicon base includes at least the first active layer, the second active layer, and the third active layer. The first conductive layer includes at least a first gate electrode, a second gate electrode, and a third gate electrode. The second conductive layer includes at least the first scanning signal line and the second scanning signal line.

[0024] In an exemplary embodiment, the display substrate further includes a third conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a seventh conductive layer, and an eighth conductive layer provided on a side of the second conductive layer away from the silicon base. The third conductive layer includes at least a data signal line and a reference signal line. The fourth conductive layer includes at least a light emission voltage line. The sixth conductive layer includes at least a first electrode plate of a storage capacitor. The seventh conductive layer includes at least a second electrode plate of the storage capacitor. The eighth conductive layer includes at least an anode connection electrode and a first power supply line.

[0025] In another aspect, embodiments of the present disclosure provide a display device including the above-described display substrate.

[0026] In still another aspect, embodiments of the present disclosure provide a method for manufacturing a display substrate, the display substrate including a display area and a bezel area, the display area including a plurality of sub-pixels in which pixel rows and pixel columns are formed, the sub-pixels including a first area, a gap area, and a second area that are sequentially arranged along the pixel row direction, at least one sub-pixel including a pixel driving circuit, a first scanning signal line, and a second scanning signal line, the pixel driving circuit including at least a first transistor, a second transistor, and a third transistor, the first scanning signal line being configured to control on or off of the first transistor, the second scanning signal line being configured to control on or off of the second transistor, the first transistor including at least a first gate electrode, a first active layer, a first pole of the first transistor, and a second pole of the first transistor, the second transistor including at least a second gate electrode and a second active layer, the third transistor including at least a third gate electrode and a third active layer, the manufacturing method including:

[0027] forming a first transistor, a second transistor, a third transistor, a first scanning signal line, and a second scanning signal line, providing the first active layer in the first area, providing the second active layer and the third active layer in the second area, providing the second active layer on one side of the third active layer in the pixel column direction, connecting the first gate electrode to the first scanning signal line via a first gate via, connecting the second gate electrode to the second pole of the first transistor via a second gate via, connecting the third gate electrode to the second scanning signal line via a third gate via, and providing the first gate via, the second gate via, and the third gate via in the gap area.

[0028] After reading and understanding the drawings and the detailed description, other aspects can be understood.

Brief Description of the Drawings

[0029]

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Embodiments for Carrying Out the Invention

[0030] The drawings are provided for understanding the technical solutions of the present disclosure, form a part of the specification, and are for interpreting the technical solutions of the present disclosure together with the embodiments of the present disclosure, rather than for limiting the technical solutions of the present disclosure. The shapes and sizes of each component in the drawings do not reflect the actual proportions and are for schematically explaining the content of the present disclosure.

[0031] To make the objectives, technical solutions, and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the drawings. The embodiments can be implemented in many different forms. As can be easily understood by those skilled in the art, the methods and contents can be converted into various forms without departing from the gist and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited only to the descriptions of the following embodiments. When there is no conflict, the embodiments and features of the embodiments of the present disclosure can be combined with each other. To keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure are only related to the structures related to the embodiments of the present disclosure, and other structures can refer to the general design.

[0032] The ratios of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited thereto. For example, the aspect ratio of the channel, the thickness and pitch of each film layer, and the width and pitch of each signal line can be adjusted according to actual needs. Also, the number of pixels in the display device and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in the present disclosure are merely structural schematic diagrams, and one form of the present disclosure is not limited to the shapes or numerical values shown in the drawings.

[0033] The ordinal numbers such as "first", "second", and "third" in this specification are for avoiding confusion of components and do not limit in terms of quantity.

[0034] In this specification, for convenience, terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positions of components with reference to the drawings. This is for the purpose of explaining this specification and simplifying the explanation, and is not for indicating or suggesting that the described device or element must have a specific orientation and be configured and operated in a specific orientation. Therefore, it is not for restricting the present disclosure. The positional relationship of the components can be appropriately changed according to the direction of explaining the components. Therefore, it can be appropriately changed as the case may be, not limited to the terms described in the specification.

[0035] In this specification, unless otherwise clearly defined and limited, the terms "attach", "connect", and "couple" should be understood in a broad sense. For example, it may be a fixed connection, or a removable connection, or an integrated connection. It may be a mechanical connection or an electrical connection. It may be a direct connection, or an indirect connection via a linker, or an internal communication between two elements. Those skilled in the art can understand the specific meaning of the above terms in the present disclosure according to the specific situation.

[0036] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to the region where current mainly flows.

[0037] In this specification, in order to identify two poles other than the gate electrode of a transistor, one of the poles is directly described as the first pole, and the other pole is the second pole. The first pole may be the drain electrode, and the second pole may be the source electrode, or the first pole may be the source electrode, and the second pole may be the drain electrode. When using transistors with opposite polarities, or when the current direction during operation in a circuit changes, etc., the functions of the "source electrode" and the "drain electrode" may be converted with each other. Therefore, in this specification, the "source electrode" and the "drain electrode" may be converted with each other.

[0038] In this specification, "electrical connection" includes the case where a component is connected via an element having a certain electrical function. The "element having a certain electrical function" is not particularly limited as long as it can transmit and receive electrical signals between the connected components. Examples of the "element having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and elements having various other functions.

[0039] In this specification, "parallel" refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and thus also includes a state where the angle is -5° or more and 5° or less. Also, "perpendicular" refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and thus also includes a state where the angle is 85° or more and 95° or less.

[0040] In this specification, "film" and "layer" are interchangeable. For example, the "conductive layer" may be changed to the "conductive film". Similarly, the "insulating film" may also be changed to the "insulating layer".

[0041] In this specification, the "installed in the same layer" adopted refers to a structure formed by patterning two types (or more than two types) of structures by the same patterning process, and their materials may be the same or different. For example, the materials of the precursors for forming a plurality of structures installed in the same layer may be the same, and the finally formed materials may be the same or different.

[0042] Triangles, rectangles, trapezoids, pentagons, hexagons, etc. in this specification do not have a strict meaning, and may be approximate triangles, rectangles, trapezoids, pentagons, hexagons, etc., and there may be some small deformations due to tolerances, and there may be chamfers, arc edges, and deformations, etc.

[0043] In the present disclosure, "about" does not strictly limit the limit and allows numerical values within the process or measurement error range.

[0044] FIG. 1 is a schematic structural diagram of a silicon-based OLED display device. As shown in FIG. 1, the silicon-based OLED display device may include a timing controller, a data signal driver, a scan signal driver, and a pixel array. The pixel array may include a plurality of scan signal lines (S1 to Sm), a plurality of data signal lines (D1 to Dn), and a plurality of sub-pixels Pxij. In an exemplary embodiment, the timing controller can supply a gradation value and a control signal that conform to the specifications of the data signal driver to the data signal driver, and can supply a clock signal, a scan start signal, etc. that conform to the specifications of the scan signal driver to the scan signal driver. The data signal driver can generate data voltages to be supplied to the data signal lines D1, D2, D3, …, Dn by using the gradation value and the control signal received from the timing controller. For example, the data signal driver may sample the gradation value using a clock signal and apply data voltages corresponding to the gradation value to the data signal lines D1 to Dn in units of sub-pixel rows, and n may be a natural number. The scan signal driver can generate scan signals to be supplied to the scan signal lines S1, S2, S3, …, Sm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan signal driver can sequentially supply scan signals having turn-on level pulses to the scan signal lines S1 to Sm. For example, the scan signal driver is configured as a shift register, and can generate scan signals by transferring a scan start signal sequentially supplied in the form of turn-on level pulses under the control of a clock signal to the next-stage circuit, and m may be a natural number. The sub-pixel array can include a plurality of sub-pixels Pxij. Each sub-pixel Pxij may be connected to a corresponding data signal line and a corresponding scan signal line, and i and j may be natural numbers. The sub-pixel Pxij can refer to a sub-pixel in which a transistor is connected to the i-th scan signal line and the j-th data signal line.

[0045] FIG. 2 is a schematic plan view of a silicon-based OLED display device. As shown in FIG. 2, the display device may include a plurality of pixel units P arranged in a matrix form, and at least one of the plurality of pixel units P includes a first sub-pixel P1 that emits a first color light ray, a second sub-pixel P2 that emits a second color light ray, and a third sub-pixel P3 that emits a third color light ray. All three sub-pixels include a pixel driving circuit and a light-emitting element. The pixel driving circuit in the sub-pixel is respectively connected to a scanning signal line and a data signal line. The pixel driving circuit is configured to receive a data voltage transmitted from the data signal line under the control of the scanning signal line and output a corresponding current to the display light-emitting element. The display light-emitting elements in the sub-pixels are respectively connected to the pixel driving circuits of the corresponding sub-pixels, and the display light-emitting elements are configured to emit light with a corresponding luminance in response to the current output by the pixel driving circuits of the corresponding sub-pixels.

[0046] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel that emits a red (R) light ray, the second sub-pixel P2 may be a blue sub-pixel that emits a blue (B) light ray, and the third sub-pixel P3 may be a green sub-pixel that emits a green (G) light ray.

[0047] In an exemplary embodiment, the shape of the sub-pixel may be any one or more of a triangle, a square, a rectangle, a rhombus, a trapezoid, a parallelogram, a pentagon, a hexagon, and other polygons. The three sub-pixels may be arranged in a horizontal parallel, vertical parallel, or L-shaped manner, but the present disclosure is not limited thereto here. In other possible embodiments, the pixel unit may include four sub-pixels, and the present disclosure is not limited thereto here.

[0048] FIG. 3 is a schematic cross-sectional view of a silicon-based OLED display device, showing a structure for realizing full color by adopting a white light + color film method. As shown in FIG. 3, the silicon-based OLED display device includes a silicon base 101, a driving circuit layer 102 installed on the silicon base 101, a light-emitting structure layer 103 installed on the side of the driving circuit layer 102 away from the silicon base 101, a first package layer 104 installed on the side of the light-emitting structure layer 103 away from the silicon base 101, a color film structure layer 105 installed on the side of the first package layer 104 away from the silicon base 101, a second package layer 106 installed on the side of the color film structure layer 105 away from the silicon base 101, and a cover plate layer 107 installed on the side of the second package layer 106 away from the silicon base 101. In some possible embodiments, the silicon-based OLED display device may include other film layers, and the present disclosure is not limited here.

[0049] In an exemplary embodiment, the silicon base 101 may be a bulk silicon base or a silicon-on-insulator (SOI) base. The driving circuit layer 102 may be provided on the silicon base 101 by a silicon semiconductor process (e.g., a CMOS process). The driving circuit layer 102 may include a plurality of circuit units, and the circuit units may at least include a pixel driving circuit. The pixel driving circuit is respectively connected to a scanning signal line and a data signal line, and the pixel driving circuit may include a plurality of transistors and a storage capacitor. FIG. 3 takes only one transistor as an example. The transistor may include a gate electrode G, a first electrode S, and a second electrode D. The gate electrode G, the first electrode S, and the second electrode D are respectively connected to corresponding connection electrodes through vias filled with tungsten metal (i.e., tungsten vias, W-vias), and can be connected to other electrical structures (e.g., wirings, etc.) through the connection electrodes.

[0050] In an exemplary embodiment, the light-emitting structure layer 103 may include a plurality of light-emitting elements. The light-emitting element may include at least an anode, an organic light-emitting layer, and a cathode. The anode may be connected to the second pole D of the transistor via a connection electrode. The organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, the anode is connected to the second power line, and the organic light-emitting layer emits light rays under the drive of the anode and the cathode. In an exemplary embodiment, the organic light-emitting layer may include a light-emitting layer (abbreviated as EML) and any one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, in the case of a light-emitting element that emits white light, the organic light-emitting layers of all sub-pixels may be a common layer connected together.

[0051] In an exemplary embodiment, the first package layer 104 and the second package layer 106 may adopt a thin film encapsulation (TFE) method, which can ensure that water vapor from the outside does not penetrate into the light-emitting structure layer. The cover plate layer 107 may adopt glass, or a flexible plastic-based colorless polyimide, etc.

[0052] In an exemplary embodiment, the color filter structure layer 105 may include a black matrix (BM) and a color filter (CF). The color filter is respectively installed in the red sub-pixel, the green sub-pixel, and the blue sub-pixel, filtering the white light emitted from the light-emitting element into red (R) light, green (G) light, and blue (B) light, and the black matrix can be located between adjacent color filters.

[0053] At present, silicon-based OLED display devices are gradually applied to the near-eye display area of virtual reality (abbreviated as VR) or augmented reality (abbreviated as AR). Users can experience real sensitivity in the virtual reality world, and with a super-powerful simulation system, man-machine interaction is realized. According to research, when the resolution of the screen is large enough, the human eye's retina cannot distinguish pixel points. Resolution (Pixels Per Inch, abbreviated as PPI) is the number of pixels per unit area and can be called pixel density. The higher the PPI value, the higher the density at which the display substrate can display the screen, indicating that the details of the screen become richer. Therefore, in order to improve the display quality, significantly improving the PPI has become the focus of research for each manufacturer.

[0054] Exemplary embodiments of the present disclosure provide a display substrate, which includes a display area and a bezel area. The display area includes a plurality of sub-pixels in which a plurality of pixel rows and a plurality of pixel columns are formed. The sub-pixels include a first area, a gap area, and a second area that are sequentially arranged along the pixel row direction. At least one sub-pixel includes a pixel driving circuit, a first scanning signal line, and a second scanning signal line. The pixel driving circuit includes at least a first transistor, a second transistor, and a third transistor. The first scanning signal line is configured to control the on or off of the first transistor. The second scanning signal line is configured to control the on or off of the second transistor. The first transistor includes at least a first gate electrode, a first active layer, a first pole of the first transistor, and a second pole of the first transistor. The second transistor includes at least a second gate electrode and a second active layer. The third transistor includes at least a third gate electrode and a third active layer. The first active layer is provided in the first area. The second active layer and the third active layer are provided in the second area. The second active layer is provided on one side of the third active layer in the pixel column direction. The first scanning signal line is connected to the first gate electrode through a first gate via. The second pole of the first transistor is connected to the second gate electrode through a second gate via. The second scanning signal line is connected to the third gate electrode through a third gate via. The first gate via, the second gate via, and the third gate via are provided in the gap area.

[0055] In an exemplary embodiment, along the pixel row direction, the first area has a first width, the second area has a second width, the gap area has a third width, the third width is less than or equal to 0.5 * the first width, and the third width is less than or equal to 0.5 * the second width.

[0056] In an exemplary embodiment, the first gate electrodes of two adjacent sub-pixels on the pixel row are an integrated structure connected to each other, and the third gate electrodes of two adjacent sub-pixels on the pixel row are an integrated structure connected to each other.

[0057] In an exemplary embodiment, the first gate electrode of the integrated structure is connected to the first scanning signal line via two first gate vias, and the third gate electrode of the integrated structure is connected to the second scanning signal line via two third gate vias.

[0058] In an exemplary embodiment, the first transistor, the second transistor, and the third transistor of two adjacent sub-pixels on the pixel row are mirror-symmetrical with respect to the pixel center line, and the pixel center line is located between two adjacent sub-pixels on the pixel row and is a straight line extending along the pixel column direction.

[0059] In an exemplary embodiment, the second transistor further includes a first pole and a second pole of the second transistor, the third transistor further includes a first pole and a second pole of the third transistor, the first source electrode is connected to the data signal line, the first pole of the second transistor is connected to the emission voltage line, the first pole of the third transistor is connected to the reference signal line, and the second pole of the second transistor and the second pole of the third transistor are an integrated structure connected to each other.

[0060] The exemplary embodiments of the present disclosure provide an ultra-high PPI display substrate. By installing the lap positions of the gate electrodes at the same interval and adopting minimization designs such as gate electrode sharing, drain electrode sharing, and sub-pixel inversion, the PPI of the display substrate is maximally improved, and the highest PPI design of Real RGB silicon-based OLEDs in the industry is realized.

[0061] Hereinafter, the technical solution of the display substrate of the present disclosure will be described using exemplary embodiments.

[0062] FIG. 4 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the pixel driving circuit can be configured as 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, etc. As shown in FIG. 4, the pixel driving circuit according to an exemplary embodiment of the present disclosure may have a 3T1C structure including three transistors (a first transistor T1, a second transistor T2, and a third transistor T3) and one storage capacitor C. The pixel driving circuit is connected to seven signal lines (a first scan signal line S1, a second scan signal line S1, a data signal line D, a reference signal line VE, a first power supply line VDD, and a light emission voltage line VF). The first node N1 and the second node N2 are junctions indicating relevant electrical connections in the circuit diagram.

[0063] In an exemplary embodiment, the first end of the storage capacitor C may be connected to the first node N1, and the second end of the storage capacitor C may be connected to the first power supply line VDD.

[0064] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the first scan signal line S1, the first pole of the first transistor T1 is connected to the data signal line D, and the second pole of the first transistor T1 is connected to the first node N1.

[0065] In an exemplary embodiment, the gate electrode of the second transistor T2 is connected to the first node N1, the first pole of the second transistor T2 is connected to the light emission voltage line VF, and the second pole of the second transistor T2 is connected to the second node N2.

[0066] In an exemplary embodiment, the gate electrode of the third transistor T3 is connected to the second scan signal line S2, the first pole of the third transistor T3 is connected to the reference signal line VE, and the second pole of the third transistor T3 is connected to the second node N2.

[0067] In an exemplary embodiment, the first pole of the light emitting element XL is connected to the second node N2, and the second pole of the light emitting element XL is connected to the second power supply line VSS.

[0068] In an exemplary embodiment, the first transistor T1 is configured to receive a data voltage transmitted from the data signal line D under the control of a signal on the first scanning signal line S1, store the data voltage in the storage capacitor C, and supply the data voltage to the gate electrode of the second transistor T2. The second transistor T2 is configured to generate a corresponding current at the second terminal so as to drive the light emission of the display light-emitting element XL under the control of the data signal received by its gate electrode. The third transistor T3 is configured to receive a reference voltage transmitted from the reference signal line VE under the control of a signal on the second scanning signal line S2 and supply the reference voltage to the second node N2. The storage capacitor C is configured to store the potential of the gate electrode of the second transistor T2, and the light-emitting element XL is configured to emit light with a corresponding luminance in response to the current at the second terminal of the second transistor T2.

[0069] In an exemplary embodiment, the signal on the first power supply line VDD may be a high-level signal that continues to be provided, the signal on the light-emitting voltage line VF may be a voltage signal output by the light-emitting control transistor, and the signal on the second power supply line VSS may be a low-level signal that continues to be provided.

[0070] In an exemplary embodiment, the first transistor T1, the second transistor T2, and the third transistor T3 may be P-type transistors. In another exemplary embodiment, the first transistor T1, the second transistor T2, and the third transistor T3 may be N-type transistors. By adopting the same type of transistors in the pixel driving circuit, the process flow is simplified, the process difficulty of the display panel is reduced, and the product yield is improved. In still another exemplary embodiment, the first transistor T1, the second transistor T2, and the third transistor T3 may include P-type transistors and N-type transistors. For example, the first transistor T1 and the third transistor T3 may be P-type metal-oxide semiconductor transistors (PMOS), and the second transistor T2 may be an N-type metal-oxide semiconductor transistor (NMOS).

[0071] In an exemplary embodiment, the light-emitting element XL may be an organic light-emitting diode (OLED) including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode).

[0072] FIG. 5 is a plan view of a display substrate in an exemplary embodiment of the present disclosure, showing the structure of three sub-pixels in one pixel unit. In an exemplary embodiment, in a plane perpendicular to the display substrate, the display substrate may include at least a silicon base, a driving circuit layer disposed on the silicon base, a light-emitting structure layer disposed on a side of the driving circuit layer away from the silicon base, and a package layer disposed on a side of the light-emitting structure layer away from the silicon base. In a plane parallel to the display substrate, the driving circuit layer of the display substrate may include a plurality of sub-pixels in which a plurality of pixel rows and a plurality of pixel columns are formed. Along the first direction D1, a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3 are sequentially disposed to form one pixel unit. The first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 all include a pixel driving circuit, a first scanning signal line 26, and a second scanning signal line 27. The pixel driving circuit may include at least a first transistor T1, a second transistor T2, and a third transistor T3. The first scanning signal line 26 is configured to control the on or off of the first transistor T1, and the second scanning signal line 27 is configured to control the on or off of the second transistor T2.

[0073] As shown in FIG. 5, in an exemplary embodiment, the first transistor T1 may include a first active layer 1, a first gate electrode 11, a first electrode (a 21st connection electrode) 21 of the first transistor T1, and a second electrode (a 22nd connection electrode) 22 of the first transistor T1. The second transistor T2 may include a second active layer 2, a second gate electrode 12, a first electrode (a 23rd connection electrode) 23 of the second transistor T2, and a second electrode (a 24th connection electrode) 24 of the second transistor T2. The third transistor T3 may include a third active layer 3, a third gate electrode 13, a first electrode (a 25th connection electrode) 25 of the third transistor T3, and a second electrode (the 24th connection electrode) 24 of the third transistor T3.

[0074] In an exemplary embodiment, the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 may all include a first region q1, a gap region q3, and a second region q2 that are sequentially arranged along the pixel row direction. The gap region q3 may be disposed between the first region q1 and the second region q2. For example, the first sub-pixel P1 and the third sub-pixel P3 may include a first region q1, a gap region q3, and a second region q2 that are sequentially arranged along the first direction D1. The second sub-pixel P2 may include a first region q1, a gap region q3, and a second region q2 that are sequentially arranged along the reverse direction of the first direction D1. The installation positions of the three regions in the first sub-pixel P1 and the second sub-pixel P2 are mirror-symmetric with respect to the pixel center line A. The installation positions of the three regions in the second sub-pixel P2 and the third sub-pixel P3 are mirror-symmetric with respect to the pixel center line A. The pixel center line A is located between two adjacent sub-pixels in the first direction D1 and is a straight line extending along the second direction D2.

[0075] In an exemplary embodiment, along the first direction D1, the first region q1 may have a first width, the second region q2 may have a second width, the gap region q3 may have a third width, the third width may be equal to or less than 0.5 * the first width, and the third width may be equal to or less than 0.5 * the second width.

[0076] In an exemplary embodiment, in at least one sub-pixel, the first active layer 1 may be provided in the first region q1, the second active layer 2 and the third active layer 3 may be provided in the second region q2, the second active layer 2 may be provided on the second direction D2 side of the third active layer 3, and no active layer is provided in the gap region q3. The gap region q3 is a gap region between the active layer in the first region q1 and the active layer in the second region q2. In this way, the first transistor T1, the second transistor T2, and the third transistor T3 arranged in an "L" shape are formed, and the first transistor T1 and the third transistor T3 can be sequentially arranged along the first direction D1, and the second transistor T2 and the third transistor T3 can be sequentially arranged along the second direction D2.

[0077] In an exemplary embodiment, in at least one sub-pixel, the first scanning signal line 26 is connected to the first gate electrode 11 of the first transistor T1 via the first gate via K1, the second pole 22 of the first transistor is connected to the second gate electrode 12 of the second transistor T2 via the second gate via K2, the second scanning signal line 27 is connected to the third gate electrode of the third transistor T3 via the third gate via K3, and all of the first gate via K1, the second gate via K2, and the third gate via K3 can be disposed in the gap region q3, thereby forming a structure in which the lap positions of the gate electrodes in the sub-pixel are all located in the same gap region.

[0078] In an exemplary embodiment, the first pole 21 of the first transistor T1 may be connected to the data signal line, the first pole 23 of the second transistor T2 may be connected to the light-emitting voltage line, the first pole 25 of the third transistor T3 may be connected to the reference signal line, the second poles 24 of the second transistor T2 and the third transistor T3 are disposed in the same layer and are interconnected by the same patterning process to form an integrated structure, thereby forming a drain electrode sharing structure in the sub-pixel.

[0079] In an exemplary embodiment, the first transistors T1, the second transistors T2, and the third transistors T3 of two adjacent sub-pixels in the first direction D1 are mirror-symmetric with respect to the pixel center line A, thereby forming a structure in which the sub-pixel is horizontally inverted with respect to the pixel center line A.

[0080] In an exemplary embodiment, the first gate electrodes 11 of two adjacent sub-pixels in the first direction D1 are disposed in the same layer and are interconnected by the same patterning process to form an integrated structure, the third gate electrodes 13 of two adjacent sub-pixels in the first direction D1 are disposed in the same layer and are interconnected by the same patterning process to form an integrated structure, and a gate electrode sharing structure of adjacent sub-pixels may be formed. For example, the third gate electrode 13 of the first sub-pixel P1 and the third gate electrode 13 of the second sub-pixel P2 are an integrated structure connected to each other, and the first gate electrode 11 of the second sub-pixel P2 and the first gate electrode 11 of the third sub-pixel P3 are an integrated structure connected to each other.

[0081] In an exemplary embodiment, in at least one sub-pixel, the first gate electrode 11 of the first transistor T1 may include a first gate main body portion 11-1 and a first gate connection portion 11-2. The first gate connection portion 11-2 may be disposed on the side closer to the third transistor T3 of the first gate main body portion 11-1 and may be connected to the first gate main body portion 11-1. Thus, the first gate connection portion 11-2 is located in the gap region q3, and the first scanning signal line 26 may be connected to the first gate connection portion 11-2 via the first gate via K1.

[0082] In an exemplary embodiment, in at least one sub-pixel, the second gate electrode 12 of the second transistor T2 may include a second gate main body portion 12-1 and a second gate connection portion 12-2. The second gate connection portion 12-2 may be disposed on the side closer to the first transistor T1 of the second gate main body portion 12-1 and may be connected to the second gate main body portion 12-1. Thus, the second gate connection portion 12-2 is located in the gap region q3, and the 12th pole 22 of the first transistor may be connected to the second gate connection portion 12-2 via the second gate via K2.

[0083] In an exemplary embodiment, in at least one sub-pixel, the third gate electrode 13 of the third transistor T3 may include a third gate main body portion 13-1 and a third gate connection portion 13-2. The third gate connection portion 13-2 may be disposed on the side closer to the first transistor T1 of the third gate main body portion 13-1 and may be connected to the third gate main body portion 13-1. Thus, the third gate connection portion 13-2 is located in the gap region q3, and the second scanning signal line 27 may be connected to the third gate connection portion 13-2 via the third gate via K3.

[0084] In an exemplary embodiment, in at least one sub-pixel, the first gate connection portion 11-2 and the third gate connection portion 13-2 are arranged with a shift at an interval in the second direction D2.

[0085] In an exemplary embodiment, the edges of the first gate main body portion 11-1 and the first gate connection portion 11-2 on the side away from the second transistor T2 may be flush.

[0086] In an exemplary embodiment, the edges of the third gate main body portion 13-1 and the third gate connection portion 13-2 on the side close to the second transistor T2 may be flush.

[0087] In an exemplary embodiment, the shapes of the first scanning signal line 26 and the second scanning signal line 27 may be linear with the main body portion extending along the first direction D1, and the orthographic projection of the first scanning signal line 26 on the plane of the display substrate overlaps at least partially with the orthographic projections of the first gate electrode 11 and the third gate electrode 13 on the plane of the display substrate, and the orthographic projection of the second scanning signal line 27 on the plane of the display substrate overlaps at least partially with the orthographic projections of the first gate electrode 11 and the third gate electrode 13 on the plane of the display substrate.

[0088] In an exemplary embodiment, at least one sub-pixel may further include a contact electrode 4, the contact electrode 4 may be disposed in the first region q1, the contact electrode 4 may be disposed on one side of the first active layer 1 in the second direction D2, the contact electrode 4 is configured to bias the silicon base to a low voltage, thereby avoiding fluctuations in the threshold voltage due to parasitic effects such as the silicon base bias effect and improving the stability of the circuit.

[0089] In an exemplary embodiment, at least one sub-pixel may further include a bias voltage line 28, and the orthographic projection of the bias voltage line 28 on the plane of the display substrate overlaps at least partially with the orthographic projection of the second gate electrode 12 of the second transistor T2 on the plane of the display substrate. The bias voltage line 28 is connected to the contact electrode 4 via a via, and it can be realized that the bias voltage line 28 supplies a low voltage to the contact electrode 4.

[0090] In an exemplary embodiment, in at least one sub-pixel, the shape of the contact electrode 4 may be linear with the main body extending along the second direction D2, the shape of the bias voltage line 28 may be linear with the main body extending along the first direction D1, the bias connection line 29 may be connected to one or both sides of the bias voltage line 28 in the second direction D2, the shape of the bias connection line 29 may be stripe-shaped with the main body extending along the second direction D2, the orthographic projection of the bias connection line 29 on the plane of the display substrate overlaps at least partially with the orthographic projection of the contact electrode 4 on the plane of the display substrate, and the bias connection line 29 is connected to the contact electrode 4 via a plurality of vias.

[0091] In an exemplary embodiment, the bias voltage line 28 and the bias connection line 29 may be provided in the same layer and form an integrated structure interconnected by the same patterning process.

[0092] In an exemplary embodiment, in a plane perpendicular to the display substrate, the drive circuit layer of the display substrate may include a first conductive layer and a second conductive layer sequentially provided on a silicon base. The silicon base may include at least a first active layer 1, a second active layer 2, a third active layer 3, and a contact electrode 4. The first conductive layer may include at least a first gate electrode 11, a second gate electrode 12, and a third gate electrode 13. The second conductive layer may include at least a first pole 21 of the first transistor T1, a second pole 22 of the first transistor T1, a second pole 23 of the second transistor T2, a second pole (which is also the second pole of the third transistor T3) 24 of the second transistor T2, a first pole 25 of the third transistor T3, a first scanning signal line 26, a second scanning signal line 27, a bias voltage line 28, and a bias connection line 29.

[0093] In an exemplary embodiment, the driving circuit layer may further include a third conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a seventh conductive layer, and an eighth conductive layer disposed on a side away from the silicon base of the second conductive layer. The third conductive layer may include at least a data signal line and a reference signal line. The fourth conductive layer may include at least a light-emitting voltage line. The fifth conductive layer may include at least a plurality of connection electrodes. The sixth conductive layer may include at least a first electrode plate of a memory capacitor. The seventh conductive layer may include at least a second electrode plate of the memory capacitor. The eighth conductive layer may include at least an anode connection electrode and a first power supply line.

[0094] Hereinafter, the manufacturing process of the display device will be described by way of example. The "patterning process" as referred to in the present disclosure includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as organic material coating, mask exposure, and development for organic materials. Deposition may be any one or more of sputtering, evaporation, and chemical vapor deposition. Coating may be any one or more of spraying, spin coating, and inkjet printing. Etching may be any one or more of dry etching and wet etching, and the present disclosure is not limited thereto. The "thin film" refers to a thin film formed by depositing, coating, or other methods of a certain material on a substrate. If the "thin film" does not require a patterning process throughout the manufacturing process, the "thin film" can also be called a "layer". If a patterning process is required for the "thin film" throughout the manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern". The statement "A and B are disposed in the same layer" in the present disclosure means that A and B are simultaneously formed by the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display device. In an exemplary embodiment of the present disclosure, the statement "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B is within the range of the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0095] In an exemplary embodiment, taking three sub-pixels per pixel as an example, the manufacturing process of the display device may include the following steps.

[0096] (1) Form a silicon base. In an exemplary embodiment, forming a silicon base may include providing a silicon base of a P-type silicon material such as P-type single-crystalline silicon that can be used as the channel region of an N-type transistor.

[0097] In an exemplary embodiment, an N-type silicon material can be adopted as the channel region of the P-type transistor for the silicon base, and the present disclosure is not limited herein.

[0098] (2) Form a first conductive layer pattern. In an exemplary embodiment, as shown in FIG. 6, forming a first conductive layer pattern may include sequentially depositing a first insulating thin film and a polysilicon thin film on the silicon base, first patterning the polysilicon thin film by a patterning process to form a first insulating layer covering the silicon base and a polysilicon layer pattern disposed on the first insulating layer, and then performing a doping process using the polysilicon layer pattern as an occlusion to form a first conductive layer and an active layer pattern.

[0099] In an exemplary embodiment, the doping process may adopt an N-type doping process, the doping element may be a boron element or the like, the formed active layer pattern may include at least a first active layer 1 of the first transistor T1, a second active layer 2 of the second transistor T2, a third active layer 3 of the third transistor T3, and a contact electrode 4, and the formed first conductive layer pattern may include at least a first gate electrode 11 of the first transistor T1, a second gate electrode 12 of the second transistor T2, and a third gate electrode 13 of the third transistor T3.

[0100] In an exemplary embodiment, the doping process can employ an ion implantation process. Since the polysilicon layer is a semiconductor material, on the one hand, the polysilicon layer can be used as an occlusion to implant ions on both sides of the polysilicon layer to form the first region and the second region of a plurality of transistors, achieving self-alignment. On the other hand, the polysilicon layer can be simultaneously doped so that the high-resistance polysilicon layer becomes the low-resistance first conductive layer, thereby forming the gate electrodes of a plurality of transistors. By adopting the polysilicon material as the first conductive layer, the present disclosure can save the process cost and reduce the process difficulty.

[0101] In an exemplary embodiment, the first active layer 1 and the contact electrode 4 in each sub-pixel may be provided in the first region q1, the second active layer 2 and the third active layer 3 may be provided in the second region q2, and no active layer is provided in the gap region q3. The gap region q3 is a gap region between the active layer in the first region q1 and the active layer in the second region q2.

[0102] In an exemplary embodiment, the first active layer 1, the second active layer 2, the third active layer 3, and the contact electrode 4 may be strip-shaped and extend along the second direction D2. The contact electrode 4 may be provided on one side of the first active layer 1 in the second direction D2, and the second active layer 2 may be provided on one side of the third active layer 3 in the second direction D2. Accordingly, the third active layer 3 may be provided on one side or the opposite side of the first active layer 1 in the first direction D1, the second active layer 2 may be provided on one side or the opposite side of the contact electrode 4 in the first direction D1, the first active layer 1 and the third active layer 3 may be provided on one side of the sub-pixel in the second direction D2, the contact electrode 4 and the second active layer 2 may be provided on the other side of the sub-pixel in the second direction D2, and the first active layer 1, the second active layer 2, and the third active layer 3 in each sub-pixel form an "L"-shaped layout. The present disclosure can facilitate the connection between the second region of the second active layer 2 and the second region of the third active layer 3, simplify the structure, reduce the occupied area of the pixel driving circuit, and realize the resolution of the display product by arranging the second active layer 2 and the third active layer 3 on the same side of the sub-pixel in the first direction D1.

[0103] In an exemplary embodiment, the active layer patterns of two adjacent sub-pixels adjacent to the first direction D1 may be mirror-symmetrical with respect to the pixel center line A, the active layer patterns of two adjacent sub-pixels adjacent to the second direction D2 may be basically the same, the pixel center line A is located between two adjacent sub-pixels adjacent to the first direction D1, and is a straight line extending along the second direction D2. For example, the active layer patterns of the first sub-pixel P1 and the second sub-pixel P2 may be mirror-symmetrical with respect to the pixel center line A. Also, the active layer patterns of the second sub-pixel P2 and the third sub-pixel P3 may be mirror-symmetrical with respect to the pixel center line A.

[0104] In an exemplary embodiment, the first gate electrode 11 and the third gate electrode 13 in each sub-pixel may be sequentially provided along the first direction D1, the second gate electrode 12 and the third gate electrode 13 may be sequentially provided along the second direction D2, and an "L"-shaped layout may be formed in the sub-pixel.

[0105] In an exemplary embodiment, the first conductive layer patterns of two sub-pixels adjacent to the first direction D1 may be mirror-symmetric with respect to the pixel center line A, and the first conductive layer patterns of two sub-pixels adjacent to the second direction D2 may be basically the same. For example, the first conductive layer patterns of the first sub-pixel P1 and the second sub-pixel P2 may be mirror-symmetric with respect to the pixel center line A. Also, the first conductive layer patterns of the second sub-pixel P2 and the third sub-pixel P3 may be mirror-symmetric with respect to the pixel center line A.

[0106] In an exemplary embodiment, due to the symmetry of the first conductive layer pattern, the first gate electrodes 11 of two sub-pixels adjacent to the first direction D1 may be an integrated structure connected to each other, and the third gate electrodes 13 of two sub-pixels adjacent to the first direction D1 may be an integrated structure connected to each other. For example, the third gate electrodes 13 of the first sub-pixel P1 and the second sub-pixel P2 may be an integrated structure connected to each other. Also, the first gate electrodes 11 of the second sub-pixel P2 and the third sub-pixel P3 may be an integrated structure connected to each other. The present disclosure makes the first gate electrodes of two adjacent sub-pixels an integrated structure connected to each other, and makes the third gate electrodes of two adjacent sub-pixels an integrated structure connected to each other. By doing so, on the premise of meeting the design rules, the layout of the pixel driving circuit can be made more compact, and the resolution of the display device can be improved.

[0107] In an exemplary embodiment, the first gate electrode 11 of the first transistor T1 may include a first gate main body portion 11-1 and a first gate connection portion 11-2. The shape of the first gate main body portion 11-1 may be rectangular, and the region where the first gate main body portion 11-1 overlaps with the first active layer 1 may be used as the first channel region of the first active layer 1. The first region 1-1 of the first active layer 1 may be located on one side (the side away from the contact electrode 4) in the second direction D2 of the first channel region, and the second region 1-2 of the first active layer 1 may be located on one side (the side close to the contact electrode 4) in the opposite direction of the second direction D2 of the first channel region. The shape of the first gate connection portion 11-2 may be rectangular, and it may be provided on the side of the first gate main body portion 11-1 close to the third transistor T3 and connected to the first gate main body portion 11-1. Thus, the first gate connection portion 11-2 is located in the gap region q3, and the first gate connection portion 11-2 is configured to be connected to a first scanning signal line formed subsequently via a first gate via.

[0108] In an exemplary embodiment, the second gate electrode 12 of the second transistor T2 may include a second gate main body portion 12-1 and a second gate connection portion 12-2. The shape of the second gate main body portion 12-1 may be rectangular, and the region where the second gate main body portion 12-1 overlaps with the second active layer 2 may be used as the second channel region of the second active layer 2. The first region 2-1 of the second active layer 2 may be located on the opposite side (the side away from the third active layer 3) in the second direction D2 of the second channel region, and the second region 2-2 of the second active layer 2 may be located on one side (the side close to the third active layer 3) in the second direction D2 of the second channel region. The second gate connection portion 12-2 may be rectangular, and it may be provided on the side of the second gate main body portion 12-1 close to the contact electrode 4 and connected to the second gate main body portion 12-1. Thus, the second gate connection portion 12-2 is located in the gap region q3, and the second gate connection portion 12-2 is configured to be connected to the second pole of the first transistor formed subsequently via a second gate via.

[0109] In an exemplary embodiment, the third gate electrode 13 of the third transistor T3 may include a third gate main body portion 13-1 and a third gate connection portion 13-2. The shape of the third gate main body portion 13-1 may be rectangular, and the region where the third gate main body portion 13-1 overlaps with the third active layer 3 may be defined as the third channel region of the third active layer 3. The first region 3-1 of the third active layer 3 may be located on one side in the second direction D2 of the third channel region (the side away from the second active layer 2), and the second region 3-2 of the third active layer 3 may be located on one side in the opposite direction of the second direction D2 of the third channel region (the side close to the second active layer 2). The shape of the third gate connection portion 13-2 may be rectangular, and it may be provided on the side of the third gate main body portion 13-1 close to the first transistor T1 and connected to the third gate main body portion 13-1. As a result, the third gate connection portion 13-2 is located in the gap region q3, and the third gate connection portion 13-2 is configured to be connected to a third scanning signal line formed subsequently via a third gate via.

[0110] In an exemplary embodiment, since the first gate connection portion 11-2, the second gate connection portion 12-2, and the third gate connection portion 13-2 are all located in the gap region q3 and are respectively configured to be connected to the first scanning signal line, the second pole of the first transistor, and the second scanning signal line, the lap positions of the three gate electrodes are all located within the same interval. On the premise of meeting the design rules, the layout of the pixel driving circuit can be made more compact, which can not only contribute to the improvement of the resolution of the display device, but also improve the operation reliability of the pixel driving circuit by ensuring that the gate via does not affect the electrical performance of the transistor.

[0111] In an exemplary embodiment, the first gate connection portion 11-2 and the third gate connection portion 13-2 located in the gap region q3 may be installed with a shift in the second direction D2 and may have a gap between the first gate connection portion 11-2 and the third gate connection portion 13-2.

[0112] In an exemplary embodiment, the first gate connection portion 11-2 may be located at one end of the gap region q3 in the second direction D2, the third gate connection portion 13-2 may be located at one end of the gap region q3 in the direction opposite to the second direction D2, the edges of the first gate main body portion 11-1 and the first gate connection portion 11-2 on the side away from the second transistor T2 may be flush, and the edges of the third gate main body portion 13-1 and the third gate connection portion 13-2 on the side close to the second transistor T2 may be flush. In some possible embodiments, the first gate connection portion 11-2 may be located at one end of the gap region q3 in the direction opposite to the second direction D2, the third gate connection portion 13-2 may be located at one end of the gap region q3 in the second direction D2, the edges of the first gate main body portion 11-1 and the first gate connection portion 11-2 on the side close to the second transistor T2 may be flush, and the edges of the third gate main body portion 13-1 and the third gate connection portion 13-2 on the side away from the second transistor T2 may be flush.

[0113] In an exemplary embodiment, the contact electrode 4 may be an N-type doping region (N+), and the contact electrode 4 is configured to bias the silicon base at a low voltage, thereby avoiding fluctuations in the threshold voltage due to parasitic effects such as the silicon base bias effect and improving the stability of the circuit. The present disclosure can electrically isolate the devices between sub-pixels by setting that the contact electrode 4 biases the silicon base at a low voltage, reduce the parasitic effects between the devices, and improve the stability of the circuit.

[0114] (3) Form a second insulating layer pattern. In an exemplary embodiment, as shown in FIG. 7, forming the second insulating layer pattern may include depositing a second insulating thin film on the silicon base on which the above pattern is formed, patterning the second insulating thin film by a patterning process to form a second insulating layer covering the first conductive layer pattern, and a plurality of vias may be provided in the second insulating layer.

[0115] In an exemplary embodiment, the plurality of vias in each sub-pixel may include at least a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, and a tenth via V10.

[0116] In an exemplary embodiment, the orthographic projection of the first via V1 on the silicon base may be located within the range of the orthographic projection of the first region of the first active layer 1 on the silicon base. The first insulating layer and the second insulating layer in the first via V1 are etched and removed to expose the surface of the first region of the first active layer 1. The first via V1 is configured to connect a subsequently formed 21st connection electrode to the first region of the first active layer 1 through the via.

[0117] In an exemplary embodiment, the orthographic projection of the second via V2 on the silicon base may be located within the range of the orthographic projection of the second region of the first active layer 1 on the silicon base. The first insulating layer and the second insulating layer in the second via V2 are etched and removed to expose the surface of the second region of the first active layer 1. The second via V2 is configured to connect a subsequently formed 22nd connection electrode to the second region of the first active layer 1 through the via.

[0118] In an exemplary embodiment, the orthographic projection of the third via V3 on the silicon base may be located within the range of the orthographic projection of the first region of the second active layer 2 on the silicon base. The first insulating layer and the second insulating layer in the third via V3 are etched and removed to expose the surface of the first region of the second active layer 2. The third via V3 is configured to connect a subsequently formed 23rd connection electrode to the first region of the second active layer 1 through the via.

[0119] In an exemplary embodiment, the orthographic projection of the fourth via V4 on the silicon base may be located within the range of the orthographic projection on the second region of the second active layer 2. The first insulating layer and the second insulating layer in the fourth via V4 are etched and removed to expose the surface of the second region of the second active layer 2. The fourth via V4 is configured to connect a subsequently formed 24th connection electrode to the first region of the second active layer 1 through the via.

[0120] In an exemplary embodiment, the orthographic projection on the silicon base of the fifth via V5 may be located within the range of the orthographic projection on the silicon base of the first region of the third active layer 3. The first insulating layer and the second insulating layer in the third via V3 are etched and removed to expose the surface of the first region of the third active layer 3. The third via V3 is configured to connect a subsequently formed 25th connection electrode to the first region of the second active layer 1 through the via.

[0121] In an exemplary embodiment, the orthographic projection on the silicon base of the sixth via V6 may be located within the range of the orthographic projection on the silicon base of the second region of the third active layer 3. The first insulating layer and the second insulating layer in the sixth via V6 are etched and removed to expose the surface of the second region of the third active layer 3. The sixth via V6 is configured to connect a subsequently formed 24th connection electrode to the second region of the third active layer 3 through the via.

[0122] In an exemplary embodiment, the orthographic projection on the silicon base of the seventh via V7 may be located within the range of the orthographic projection on the silicon base of the first gate connection portion 11-2 of the first gate electrode 11. The second insulating layer in the seventh via V7 is etched and removed to expose the surface of the first gate connection portion 11-2. The seventh via V7 is configured to connect a subsequently formed first scanning signal line to the first gate connection portion 11-2 through the via, and the seventh via V7 may be used as the first gate via of the present disclosure.

[0123] In an exemplary embodiment, since the first gate electrodes 11 of two adjacent sub-pixels in the first direction D1 are connected to each other in an integrated structure, two seventh vias V7 (first gate vias) are provided in the region where the integrated first gate electrode 11 is located. The two seventh vias V7 are respectively located at both ends of the first gate electrode 11 of the integrated structure in the first direction D1. Thus, the first gate electrode 11 of the same integrated structure may be connected to a subsequently formed first scanning signal line through the two seventh vias V7.

[0124] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the silicon base may be located within the range of the orthographic projection of the second gate connection portion 12-2 of the second gate electrode 12 on the silicon base. The second insulating layer within the eighth via V8 is etched and removed to expose the surface of the second gate connection portion 12-2. The eighth via V8 is configured to connect a subsequently formed second connection electrode to the second gate connection portion 12-2 through this via. The eighth via V8 may be used as the second gate via of the present disclosure.

[0125] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the silicon base may be located within the range of the orthographic projection of the third gate connection portion 11-2 of the third gate electrode 13 on the silicon base. The second insulating layer within the ninth via V9 is etched and removed to expose the surface of the third gate connection portion 13-2. The ninth via V9 is configured to connect a subsequently formed second scanning signal line to the third gate connection portion 13-2 through this via. The ninth via V9 may be used as the third gate via of the present disclosure.

[0126] In an exemplary embodiment, since the third gate electrodes 13 of two adjacent sub-pixels in the first direction D1 are connected to each other in an integrated structure, two ninth vias V9 (third gate vias) are provided in the region where the integrated third gate electrode 13 is located. The two ninth vias V9 are respectively located at both ends of the integrated third gate electrode 13 in the first direction D1. Thereby, the third gate electrode 13 of the same integrated structure may be connected to a subsequently formed second scanning signal line through the two ninth vias V9.

[0127] In an exemplary embodiment, the orthographic projection of the tenth via V10 on the silicon base may be located within the range of the orthographic projection of the contact electrode 4 on the silicon base. The first insulating layer and the second insulating layer within the tenth via V10 are etched and removed to expose the surface of the contact electrode 4. The tenth via V10 is configured to connect a subsequently formed reference signal line to the contact electrode 4 through this via.

[0128] In an exemplary embodiment, there may be a plurality of the eighth vias V8 and the tenth vias V10, thereby reducing contact resistance and improving connection reliability.

[0129] (4) Form a second conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 8A and 8B, FIG. 8B is a schematic diagram of the second conductive layer in FIG. 8A. Forming the second conductive layer pattern may include depositing a second conductive thin film on the silicon base on which the above pattern is formed and patterning the second conductive thin film by a patterning process to form a second conductive layer pattern on the second insulating layer. In an exemplary embodiment, the second conductive layer may be referred to as a first metal (Metal1) layer.

[0130] In an exemplary embodiment, the second conductive layer pattern in each sub-pixel may at least include at least a 21st connection electrode 21, a 22nd connection electrode 22, a 23rd connection electrode 23, a 24th connection electrode 24, a first scanning signal line 26, a second scanning signal line 27, a bias voltage line 28, and a bias connection line 29.

[0131] In an exemplary embodiment, the shape of the 21st connection electrode 21 may be rectangular, the 21st connection electrode 21 may be connected to the first region of the first active layer via the first via V1, the 21st connection electrode 21 may be the first pole of the first transistor T1, and the 21st connection electrode 21 is configured to be connected to a subsequent formed data signal line.

[0132] In an exemplary embodiment, the shape of the 22nd connection electrode 22 may be an "L" shape. The first end of the 22nd connection electrode 22 may be connected to the second region of the first active layer via the second via V2. After the second end of the 22nd connection electrode 22 bends and extends in the direction of the second gate electrode 12, it is connected to the second gate electrode 12-2 of the second gate electrode 12 via the eighth via V8. The 22nd connection electrode 22 may be the second pole of the first transistor T1, realizing the connection between the second pole of the first transistor T1 and the second gate electrode 12 of the second transistor T2.

[0133] In an exemplary embodiment, the shape of the 23rd connection electrode 23 may be stripe-shaped with the main body portion extending along the second direction D2. The first end of the 23rd connection electrode 23 is connected to the first region of the second active layer via the third via V3. The second end of the 23rd connection electrode 23 extends along the second direction D2 to the middle position of the second gate electrode 12. The 23rd connection electrode 23 may also serve as the first pole of the second transistor T2, and the 23rd connection electrode 23 is configured to be connected to a 32nd connection electrode to be formed subsequently.

[0134] In an exemplary embodiment, the shape of the 24th connection electrode 24 may be rectangular. The first end of the 24th connection electrode 24 may be connected to the second region of the second active layer 2 via the fourth via V4. The second end of the 24th connection electrode 24 may be connected to the second region of the third active layer 3 via the sixth via V6. The 24th connection electrode 24 may simultaneously serve as the second pole of the second transistor T2 and the second pole of the third transistor T3. That is, the second poles of the second transistor T2 and the third transistor T3 are an integrated structure connected to each other, and the 24th connection electrode 24 is configured to be connected to a 33rd connection electrode to be formed subsequently.

[0135] In an exemplary embodiment, the shape of the 25th connection electrode 25 may be rectangular. The 25th connection electrode 25 may be connected to the first region of the third active layer 3 via the fifth via V5. The 25th connection electrode 25 may also serve as the first pole of the third transistor T3, and the 25th connection electrode 25 is configured to be connected to a reference signal line to be formed subsequently.

[0136] In an exemplary embodiment, the shape of the first scanning signal line 26 may be linear with the main body portion extending along the first direction D1. Since the first scanning signal line 26 may be connected to the first gate connection portion 11-2 of each sub-pixel via the seventh via V7, the connection between the first scanning signal line 26 and the first gate electrode 11 of each sub-pixel is realized, and the first scanning signal line 26 can supply the first scanning signal for controlling the on / off of the first transistor T1 to the first transistor T1 of each sub-pixel.

[0137] In an exemplary embodiment, since the first gate electrodes 11 of two sub-pixels adjacent to the first direction D1 are connected to each other in an integrated structure, two seventh vias V7 (first gate vias) are provided in the region where the integrated first gate electrode 11 is located, and the first scanning signal line 26 is connected to the first gate electrode 11 of the same integrated structure via the two seventh vias V7.

[0138] In an exemplary embodiment, the shape of the second scanning signal line 27 may be linear with the main body extending along the first direction D1, and the second scanning signal line 27 may be connected to the third gate connection portion 13-2 of each sub-pixel via the ninth via V9. Thus, the connection between the second scanning signal line 27 and the third gate electrode 13 of each sub-pixel is realized, and the second scanning signal line 27 can supply the second scanning signal for controlling the on / off of the third transistor T3 to the third transistor T3 of each sub-pixel.

[0139] In an exemplary embodiment, since the third gate electrodes 13 of two sub-pixels adjacent to the first direction D1 are connected to each other in an integrated structure, two ninth vias V9 (third gate vias) are provided in the region where the integrated third gate electrode 13 is located, and the second scanning signal line 27 is connected to the third gate electrode 13 of the same integrated structure via the two ninth vias V9.

[0140] In an exemplary embodiment, the orthographic projection of the first scanning signal line 26 on the silicon base overlaps at least partially with the orthographic projections of the first gate electrode 11 and the third gate electrode 13 on the silicon base, and the orthographic projection of the second scanning signal line 27 on the silicon base overlaps at least partially with the orthographic projections of the first gate electrode 11 and the third gate electrode 13 on the silicon base. The present disclosure contributes to reducing the occupied area of the first scanning signal line and the second scanning signal line and the occupied area of the pixel driving circuit by arranging both the first scanning signal line and the second scanning signal line to overlap the first gate electrode and the third gate electrode, thereby realizing the resolution of the display product.

[0141] In an exemplary embodiment, the shape of the bias voltage line 28 of each sub-pixel may be linear with the main body extending along the first direction D1, and the bias voltage line 28 may be connected to the contact electrode 4 of each sub-pixel via the tenth via V10, so as to supply a low voltage to the contact electrode 4, bias the silicon base at a low voltage, electrically isolate the devices, reduce the parasitic effect between the devices, and improve the stability of the pixel driving circuit.

[0142] In an exemplary embodiment, the shape of the bias connection line 29 of each sub-pixel may be stripe-shaped with the main body extending along the second direction D2, and it may be installed on one or both sides of the bias voltage line 28 in the second direction D2 and connected to the bias voltage line 28. The bias connection line 29 of each sub-pixel may be connected to the contact electrode 4 via a plurality of tenth vias V10, thereby reducing the contact resistance and improving the connection reliability.

[0143] In an exemplary embodiment, the first scanning signal line 26 may be located on the side closer to the twenty-first connection electrode 21, and the second scanning signal line 27 may be located on the side away from the twenty-first connection electrode 21 of the first scanning signal line 26.

[0144] In an exemplary embodiment, the bias voltage line 28 may be located between the twenty-second connection electrode 22 and the twenty-third connection electrode 23, and at least a part of the orthographic projection of the bias voltage line 28 on the silicon base overlaps with the orthographic projection of the second gate electrode 12 on the silicon base.

[0145] In an exemplary embodiment, the width of the bias voltage line 28 may be made larger than the width of the first scanning signal line 26, and the width of the bias voltage line 28 may be made larger than the width of the second scanning signal line 27, thereby reducing the resistance of the bias voltage line 28 and improving the uniformity of the power supply voltage.

[0146] In an exemplary embodiment, the second conductive layer patterns of two sub-pixels adjacent to the first direction D1 may be mirror-symmetrical with respect to the pixel center line A, and the second conductive layer patterns of two sub-pixels adjacent to the second direction D2 may be basically the same. For example, the second conductive layer patterns of the first sub-pixel P1 and the second sub-pixel P2 may be mirror-symmetrical with respect to the pixel center line A. Also for example, the second conductive layer patterns of the second sub-pixel P2 and the third sub-pixel P3 may be mirror-symmetrical with respect to the pixel center line A.

[0147] (5) Form a third insulating layer pattern. In an exemplary embodiment, as shown in FIG. 9, forming the third insulating layer pattern may include depositing a third insulating thin film on the silicon base on which the above patterns are formed, patterning the third insulating thin film by a patterning process to form a third insulating layer covering the second conductive layer pattern, and a plurality of vias may be provided in the third insulating layer.

[0148] In an exemplary embodiment, the plurality of vias in each sub-pixel may include a 11th via V11, a 12th via V12, a 13th via V13, a 14th via V14, and a 15th via V15.

[0149] In an exemplary embodiment, the orthographic projection of the 11th via V11 on the silicon base may be located within the range of the orthographic projection of the 21st connection electrode 21 on the silicon base. The third insulating layer within the 11th via V11 is etched and removed to expose the surface of the 21st connection electrode 21. The 11th via V11 is configured to connect a subsequently formed data signal line to the 21st connection electrode 21 through the via.

[0150] In an exemplary embodiment, the orthographic projection of the 12th via V12 on the silicon base may be located within the range of the orthographic projection of the 22nd connection electrode 22 on the silicon base. The third insulating layer within the 12th via V12 is etched and removed to expose the surface of the 22nd connection electrode 22. The 12th via V12 is configured to connect a subsequently formed 31st connection electrode to the 22nd connection electrode 22 through the via.

[0151] In an exemplary embodiment, the orthographic projection of the 13th via V13 on the silicon base may be located within the range of the orthographic projection of the 23rd connection electrode 23 on the silicon base. The third insulating layer within the 13th via V13 is etched and removed to expose the surface of the 23rd connection electrode 23. The 13th via V13 is configured to connect a subsequently formed 32nd connection electrode to the 23rd connection electrode 23 through this via.

[0152] In an exemplary embodiment, the orthographic projection of the 14th via V14 on the silicon base may be located within the range of the orthographic projection of the 24th connection electrode 24 on the silicon base. The third insulating layer within the 14th via V14 is etched and removed to expose the surface of the 24th connection electrode 24. The 14th via V14 is configured to connect a subsequently formed 33rd connection electrode to the 24th connection electrode 24 through this via.

[0153] In an exemplary embodiment, the orthographic projection of the 15th via V15 on the silicon base may be located within the range of the orthographic projection of the 25th connection electrode 25 on the silicon base. The third insulating layer within the 15th via V15 is etched and removed to expose the surface of the 25th connection electrode 25. The 15th via V15 is configured to connect a subsequently formed reference signal line to the 25th connection electrode 25 through this via.

[0154] In an exemplary embodiment, there may be a plurality of the 11th via V11 to the 15th via V15, thereby reducing contact resistance and improving connection reliability.

[0155] (6) Form a third conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 10A and 10B, FIG. 10B is a schematic diagram of the second conductive layer in FIG. 10A. Forming the third conductive layer pattern may include depositing a third conductive thin film on the silicon base on which the above pattern is formed and patterning the third conductive thin film by a patterning process to form a third conductive layer pattern on the third insulating layer. In an exemplary embodiment, the third conductive layer may be referred to as a second metal (Metal2) layer.

[0156] In an exemplary embodiment, the third conductive layer pattern in each sub-pixel may include at least a 31st connection electrode 31, a 32nd connection electrode 32, a 33rd connection electrode 33, a data signal line 34, and a reference signal line 35.

[0157] In an exemplary embodiment, the shape of the 31st connection electrode 31 may be stripe-shaped extending along the second direction D2, and the end portion of the 31st connection electrode 31 in the direction opposite to the second direction D2 (the end portion close to the second transistor T2) may be connected to the 22nd connection electrode 22 via a 12th via V12, and the 31st connection electrode 31 is configured to be connected to a 41st connection electrode to be formed subsequently.

[0158] In an exemplary embodiment, the shape of the 32nd connection electrode 32 may be rectangular, the 32nd connection electrode 32 may be connected to the 23rd connection electrode 23 via a 13th via V13, and the 32nd connection electrode 32 is configured to be connected to a light-emitting voltage line to be formed subsequently.

[0159] In an exemplary embodiment, the shape of the 33rd connection electrode 33 may be a broken line shape extending along the second direction D2, and the end portion of the 33rd connection electrode 33 in the second direction D2 (the end portion close to the third transistor T3) is connected to the 24th connection electrode 24 via a 14th via V14, and the 33rd connection electrode 33 is configured to be connected to a 42nd connection electrode to be formed subsequently.

[0160] In an exemplary embodiment, the shape of the data signal line 34 may be linear extending along the second direction D2, and the data signal line 34 may be connected to the 21st connection electrode 21 via a 11th via V11. Since the 21st connection electrode 21 is connected to the first region of the first active layer, it realizes that the data signal line 34 writes a data signal to the first pole of the first transistor T1.

[0161] In an exemplary embodiment, the shape of the reference signal line 35 may be linear extending along the second direction D2, and the reference signal line 35 may be connected to the 25th connection electrode 25 via the 15th via V15. Since the 25th connection electrode 25 is connected to the first region of the third active layer, it is realized that the data signal line 34 writes a reference signal to the first pole of the third transistor T3.

[0162] In an exemplary embodiment, the third conductive layer patterns of two adjacent sub-pixels adjacent to the first direction D1 may be mirror-symmetrical with respect to the pixel center line A, and the third conductive layer patterns of two adjacent sub-pixels adjacent to the second direction D2 may be basically the same. For example, the third conductive layer patterns of the first sub-pixel P1 and the second sub-pixel P2 may be mirror-symmetrical with respect to the pixel center line A. Also for example, the third conductive layer patterns of the second sub-pixel P2 and the third sub-pixel P3 may be mirror-symmetrical with respect to the pixel center line A.

[0163] (7) Form a fourth insulating layer pattern. In an exemplary embodiment, as shown in FIG. 11, forming the fourth insulating layer pattern may include depositing a fourth insulating thin film on the silicon base on which the above pattern is formed, patterning the fourth insulating thin film by a patterning process to form a fourth insulating layer covering the third conductive layer pattern, and a plurality of vias may be provided in the fourth insulating layer.

[0164] In an exemplary embodiment, the plurality of vias in each sub-pixel may include the 21st via V21, the 22nd via V22, and the 23rd via V23.

[0165] In an exemplary embodiment, the orthographic projection of the 21st via V21 on the silicon base may be located within the range of the orthographic projection onto the silicon base at the end of the 31st connection electrode 31 in the second direction D2. The fourth insulating layer in the 21st via V21 is etched and removed to expose the surface of the 31st connection electrode 31. The 21st via V21 is configured to connect the subsequently formed 41st connection electrode to the 31st connection electrode 31 through the via.

[0166] In an exemplary embodiment, the orthographic projection of the second via V22 on the silicon base may be located within the range of the orthographic projection of the third connection electrode 32 on the silicon base. The fourth insulating layer within the second via V22 may be etched and removed to expose the surface of the third connection electrode 32. The second via V22 is configured to connect a subsequently formed light-emitting voltage line to the third connection electrode 32 through the via.

[0167] In an exemplary embodiment, the orthographic projection of the second via V23 on the silicon base may be located within the range of the orthographic projection of the end portion of the third connection electrode 33 in the direction opposite to the second direction D2 on the silicon base. The fourth insulating layer within the second via V23 is etched and removed to expose the surface of the third connection electrode 33. The second via V23 is configured to connect a subsequently formed forty-second connection electrode to the third connection electrode 33 through the via.

[0168] (8) Form a fourth conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 12A and 12B, FIG. 12B is a schematic diagram of the fourth conductive layer in FIG. 12A. Forming the fourth conductive layer pattern may include depositing a fourth conductive thin film on the silicon base on which the above pattern is formed and patterning the fourth conductive thin film by a patterning process to form a fourth conductive layer pattern on the fourth insulating layer. In an exemplary embodiment, the fourth conductive layer may be referred to as a third metal (Metal3) layer.

[0169] In an exemplary embodiment, the fourth conductive layer pattern in each sub-pixel may include at least a forty-first connection electrode 41, a forty-second connection electrode 42, and a light-emitting voltage line 43.

[0170] In an exemplary embodiment, the shape of the forty-first connection electrode 41 may be a "T" shape. The forty-first connection electrode 41 may be connected to the thirty-first connection electrode 31 through the twenty-first via V21. The forty-first connection electrode 41 is configured to be connected to a subsequently formed fifty-first connection electrode.

[0171] In an exemplary embodiment, the shape of the 42nd connection electrode 42 may be a "T" shape, the 42nd connection electrode 42 may be connected to the 33rd connection electrode 33 via the 23rd via V23, and the 42nd connection electrode 42 is configured to be connected to a 52nd connection electrode formed subsequently.

[0172] In an exemplary embodiment, the shape of the light emission voltage line 43 may be linear with the main body portion extending along the first direction D1, and the light emission voltage line 43 may be connected to the 32nd connection electrode 32 via the 22nd via V22. The light emission voltage line 43 is connected to the second pole of a light emission control transistor located in the bezel region and is configured to output a light emission voltage signal. The 32nd connection electrode 32 is connected to the 23rd connection electrode 23 via a via, and the 23rd connection electrode 23 is connected to the first region of the second active layer via a via. Thus, it is realized that the light emission voltage line 43 writes a light emission voltage signal to the first pole of the second transistor T2.

[0173] In an exemplary embodiment, the fourth conductive layer patterns of two adjacent sub-pixels adjacent to the first direction D1 may be mirror-symmetric with respect to the pixel center line A, and the fourth conductive layer patterns of two adjacent sub-pixels adjacent to the second direction D2 may be basically the same. For example, the fourth conductive layer patterns of the first sub-pixel P1 and the second sub-pixel P2 may be mirror-symmetric with respect to the pixel center line A. Also, for example, the fourth conductive layer patterns of the second sub-pixel P2 and the third sub-pixel P3 may be mirror-symmetric with respect to the pixel center line A.

[0174] (9) Form a fifth insulating layer pattern. In an exemplary embodiment, as shown in FIG. 13, forming the fifth insulating layer pattern may include depositing a fifth insulating thin film on the silicon base on which the above patterns are formed, patterning the fifth insulating thin film by a patterning process to form a fifth insulating layer covering the fourth conductive layer pattern, and a plurality of vias may be provided in the fifth insulating layer.

[0175] In an exemplary embodiment, the plurality of vias in each sub-pixel may include a 31st via V31 and a 32nd via V32.

[0176] In an exemplary embodiment, the orthographic projection on the silicon base of the 31st via V31 may be located within the range of the orthographic projection on the silicon base of the 41st connection electrode 41. The 5th insulating layer within the 31st via V31 is etched and removed to expose the surface of the 41st connection electrode 41. The 31st via V31 is configured to connect a subsequently formed 51st connection electrode to the 41st connection electrode 41 through this via.

[0177] In an exemplary embodiment, the orthographic projection on the silicon base of the 32nd via V32 may be located within the range of the orthographic projection on the silicon base of the 42nd connection electrode 42. The 5th insulating layer within the 32nd via V32 is etched and removed to expose the surface of the 42nd connection electrode 42. The 32nd via V32 is configured to connect a subsequently formed 52nd connection electrode to the 42nd connection electrode 41 through this via.

[0178] In an exemplary embodiment, a plurality of 31st vias V31 and a plurality of 32nd vias V32 are sequentially installed along the first direction D1, thereby reducing contact resistance and improving connection reliability.

[0179] (10) Form a 5th conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 14A and 14B, FIG. 14B is a schematic diagram of the 5th conductive layer in FIG. 14A. Forming the 5th conductive layer pattern may include depositing a 5th conductive thin film on the silicon base on which the above pattern is formed and patterning the 5th conductive thin film by a patterning process to form a 5th conductive layer pattern on the 5th insulating layer. In an exemplary embodiment, the 5th conductive layer can be called a 4th metal (Metal4) layer.

[0180] In an exemplary embodiment, the 5th conductive layer pattern in each sub-pixel may include at least a 51st connection electrode 51 and a 52nd connection electrode 52.

[0181] In an exemplary embodiment, the shape of the 51st connection electrode 51 may be stripe-shaped extending along the first direction D1, the 51st connection electrode 51 may be connected to the 41st connection electrode 41 via a plurality of 31st vias V31, and the 51st connection electrode 51 is configured to be connected to a first electrode plate formed subsequently.

[0182] In an exemplary embodiment, the shape of the 52nd connection electrode 52 may be stripe-shaped extending along the first direction D1, the 52nd connection electrode 52 may be connected to the 42nd connection electrode 42 via a plurality of 32nd vias V32, and the 52nd connection electrode 52 is configured to be connected to a 61st connection electrode formed subsequently.

[0183] In an exemplary embodiment, the 5th conductive layer patterns of two adjacent sub-pixels adjacent to the first direction D1 may be mirror-symmetric with respect to the pixel center line A, and the 5th conductive layer patterns of two adjacent sub-pixels adjacent to the second direction D2 may be basically the same. For example, the 5th conductive layer patterns of the first sub-pixel P1 and the second sub-pixel P2 may be mirror-symmetric with respect to the pixel center line A. Also for example, the 5th conductive layer patterns of the second sub-pixel P2 and the third sub-pixel P3 may be mirror-symmetric with respect to the pixel center line A.

[0184] (11) Form a 6th insulating layer pattern. In an exemplary embodiment, as shown in FIG. 15, forming the 6th insulating layer pattern includes depositing a 6th insulating thin film on the silicon base on which the above patterns are formed, patterning the 6th insulating thin film by a patterning process to form a 6th insulating layer covering the 5th conductive layer pattern, and a plurality of vias may be provided in the 6th insulating layer.

[0185] In an exemplary embodiment, the plurality of vias in each sub-pixel may include 41st vias V41 and 42nd vias V42.

[0186] In an exemplary embodiment, the orthographic projection of the 41st via V41 on the silicon base may be located within the range of the orthographic projection of the 51st connection electrode 51 on the silicon base. The 6th insulating layer within the 41st via V41 is etched and removed to expose the surface of the 51st connection electrode 51. The 41st via V41 is configured to connect a first electrode plate formed subsequently to the 51st connection electrode 51 through the via.

[0187] In an exemplary embodiment, the orthographic projection of the 42nd via V42 on the silicon base may be located within the range of the orthographic projection of the 52nd connection electrode 52 on the silicon base. The 6th insulating layer within the 42nd via V42 is etched and removed to expose the surface of the 52nd connection electrode 52. The 42nd via V42 is configured to connect a 61st connection electrode formed subsequently to the 52nd connection electrode 52 through the via.

[0188] In an exemplary embodiment, a plurality of the 41st vias V41 and a plurality of the 42nd vias V42 are sequentially installed along the first direction D1, thereby reducing contact resistance and improving connection reliability.

[0189] (12) Form a 6th conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 16A and 16B, FIG. 16B is a schematic diagram of the 6th conductive layer in FIG. 16A. Forming the 6th conductive layer pattern may include depositing a 6th conductive thin film on the silicon base on which the above pattern is formed and patterning the 6th conductive thin film by a patterning process to form the 6th conductive layer pattern on the 6th insulating layer. In an exemplary embodiment, the 6th conductive layer can be called a 5th metal (Metal5) layer.

[0190] In an exemplary embodiment, the 6th conductive layer pattern in each sub-pixel may include at least a 61st connection electrode 61 and a first electrode plate 91 of the storage capacitor.

[0191] In an exemplary embodiment, the shape of the 61st connection electrode 61 may be rectangular, the 61st connection electrode 61 may be connected to the 52nd connection electrode 52 via a plurality of 42nd vias V42, and the 61st connection electrode 61 is configured to be connected to an anode connection electrode formed subsequently.

[0192] In an exemplary embodiment, the shape of the first electrode plate 91 of the memory capacitor may be rectangular, the first electrode plate 91 may be connected to the 51st connection electrode 51 via a plurality of 41st vias V41, and the first electrode plate 91 is configured as one of the electrode plates of the memory capacitor. The 51st connection electrode 51 is connected to the 41st connection electrode 41 via a via, the 41st connection electrode 41 is connected to the 31st connection electrode 31 via a via, the 31st connection electrode 31 is connected to the 22nd connection electrode 22 via a via, and the 22nd connection electrode 22 is connected to the second region of the first active layer and the gate electrode of the second transistor T2 via a via. Therefore, the first electrode plate 91, the second electrode of the first transistor T1, and the gate electrode of the second transistor T2 have the same potential.

[0193] In an exemplary embodiment, the 6th conductive layer patterns of two adjacent sub-pixels in the first direction D1 may be mirror-symmetric with respect to the pixel center line A, and the 6th conductive layer patterns of two adjacent sub-pixels in the second direction D2 may be basically the same. For example, the 6th conductive layer patterns of the first sub-pixel P1 and the second sub-pixel P2 may be mirror-symmetric with respect to the pixel center line A. Also, for example, the 6th conductive layer patterns of the second sub-pixel P2 and the third sub-pixel P3 may be mirror-symmetric with respect to the pixel center line A.

[0194] (13) A seventh conductive layer pattern is formed. In an exemplary embodiment, as shown in FIGS. 17A and 17B, FIG. 17B is a schematic diagram of the seventh conductive layer in FIG. 17A. Forming the seventh conductive layer pattern may include sequentially depositing a seventh insulating thin film and a seventh conductive thin film on the silicon base on which the pattern is formed, and patterning the seventh conductive thin film by a patterning process to form a seventh insulating layer covering the sixth conductive layer pattern and a seventh conductive layer pattern disposed on the seventh insulating layer. In an exemplary embodiment, the seventh conductive layer can be referred to as a Metal-Insulator-Metal (abbreviated as MIM) layer.

[0195] In an exemplary embodiment, the seventh conductive layer in each sub-pixel may include at least the second electrode plate 92 of the memory capacitor.

[0196] In an exemplary embodiment, the shape of the second electrode plate 92 may be rectangular, and the orthographic projection of the second electrode plate 92 on the silicon base overlaps at least partially with the orthographic projection of the first electrode plate 91 on the silicon base. The second electrode plate 92 is configured as the other electrode plate of the memory capacitor, and the first electrode plate 91 and the second electrode plate 92 constitute the memory capacitor of the pixel driving circuit.

[0197] In an exemplary embodiment, the area of the second electrode plate 92 may be smaller than the area of the first electrode plate 91, and the orthographic projection of the second electrode plate 92 on the silicon base may be located within the range of the orthographic projection of the first electrode plate 91 on the silicon base.

[0198] In an exemplary embodiment, the seventh conductive layer patterns of two adjacent sub-pixels in the first direction D1 may be mirror-symmetric with respect to the pixel center line A, and the seventh conductive layer patterns of two adjacent sub-pixels in the second direction D2 may be basically the same. For example, the seventh conductive layer patterns of the first sub-pixel P1 and the second sub-pixel P2 may be mirror-symmetric with respect to the pixel center line A. Also for example, the seventh conductive layer patterns of the second sub-pixel P2 and the third sub-pixel P3 may be mirror-symmetric with respect to the pixel center line A.

[0199] (14) Form the eighth insulating layer pattern. In an exemplary embodiment, as shown in FIG. 18, forming the eighth insulating layer pattern includes depositing an eighth insulating layer thin film on the silicon base on which the pattern is formed, patterning the eighth insulating layer by a patterning process to form an eighth insulating layer covering the seventh conductive layer pattern, and a plurality of vias may be provided in the eighth insulating layer.

[0200] In an exemplary embodiment, the plurality of vias in each sub-pixel may include at least the 51st via V51 and the 52nd via V52.

[0201] In an exemplary embodiment, the orthographic projection of the 51st via V51 on the silicon base is located within the range of the orthographic projection of the 61st connection electrode 61 on the silicon base. The seventh insulating layer and the eighth insulating layer in the 51st via V51 are etched and removed to expose the surface of the 61st connection electrode 61. The 51st via V51 is configured to connect a subsequently formed anode connection electrode to the 61st connection electrode 61 through the via.

[0202] In an exemplary embodiment, the orthographic projection of the 52nd via V52 on the silicon base is located within the range of the orthographic projection of the second electrode plate 92 on the silicon base. The eighth insulating layer in the 52nd via V52 is etched and removed to expose the surface of the second electrode plate 92. The 52nd via V52 is configured to connect a subsequently formed first power line to the second electrode plate 92 through the via.

[0203] (15) Form the eighth conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 19A and 19B, FIG. 19B is a schematic diagram of the eighth conductive layer in FIG. 19A. To form the eighth conductive layer pattern, forming the eighth conductive layer pattern includes depositing an eighth conductive thin film on the silicon base on which the pattern is formed, patterning the eighth conductive thin film by a patterning process to form an eighth conductive layer pattern on the eighth insulating layer. In an exemplary embodiment, the eighth conductive layer can be called the sixth metal (Metal6) layer or the second metal connection (TM2) layer.

[0204] In an exemplary embodiment, the eighth conductive layer in each sub-pixel may include at least an anode connection electrode 71, a power supply electrode 72, and a first power supply line 73.

[0205] In an exemplary embodiment, the shape of the anode connection electrode 71 may be rectangular, the anode connection electrode 71 may be connected to the 61st connection electrode 61 via the 51st via V51, and the anode connection electrode 71 is configured to be connected to an anode formed subsequently. The 61st connection electrode 61 is connected to the 52nd connection electrode 52 via a via, the 52nd connection electrode 52 is connected to the 42nd connection electrode 42 via a via, the 42nd connection electrode 42 is connected to the 33rd connection electrode 33, the 33rd connection electrode 33 is connected to the 24th connection electrode 24 via a via, and the 24th connection electrode 24 is connected to the second region of the second active layer and the second region of the third active layer via a via. Therefore, the connection between the anode formed subsequently and the second pole of the second transistor T2 and the second pole of the third transistor T3 (the second node N2 of the pixel driving circuit) can be realized, and the current output by the pixel driving circuit can be supplied to the anode.

[0206] In an exemplary embodiment, the shape of the power supply electrode 72 may be rectangular, and the power supply electrode 72 may be connected to the second electrode plate 92 via the 52nd via V52. The shape of the first power supply line 73 may be linear extending along the first direction D1, and the first power supply line 73 is connected to the power supply electrode 72 of each sub-pixel. Thereby, the second electrode plate 92 has the potential of the first power supply line 73.

[0207] In an exemplary embodiment, the power supply electrode 72 and the first power supply line 73 may be an integral structure connected to each other.

[0208] In an exemplary embodiment, since the second electrode plate 92 has the potential of the first power supply line 73 and the first electrode plate 91 has the potential of the first node N1 of the pixel driving circuit, the first electrode plate 91 and the second electrode plate 92 constitute a storage capacitor having a MIM capacitor structure. By adopting the MIM capacitor structure in the present disclosure, the capacitance value per unit area is high, the capacitor capacitance required for high PPI can be satisfied, and the driving ability of the pixel driving circuit can be improved.

[0209] In an exemplary embodiment, subsequent manufacturing processes may include processes such as forming an anode, a pixel definition layer, an organic light-emitting layer, a cathode, a first package layer, a color film structure layer, and a second package layer, which will not be described here.

[0210] In the exemplary embodiments of the present disclosure, the structure of the display device and its manufacturing process are merely exemplary descriptions, and according to the actual situation, the corresponding structure can be changed, or the patterning process can be added or reduced, and the present disclosure is not limited here.

[0211] In an exemplary embodiment, the first insulating layer to the eighth insulating layer may be silicon oxide SiOx, silicon nitride SiNx, silicon oxynitride SiON, etc., and may have a single-layer structure or a multilayer composite structure. The first metal layer to the sixth metal layer may use a metal material such as silver (Ag), copper (Cu), aluminum (Al), or molybdenum (Mo), or an alloy material made of a metal such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). The alloy material may have a single-layer structure or a multilayer composite structure composed of a Mo layer, a Cu layer, and a Mo layer. In an exemplary embodiment, the planar shape of the via may be rectangular, circular, or elliptical, etc., and the sizes of a plurality of vias may be the same or different, and the present disclosure is not limited here.

[0212] FIG. 20 is an equivalent circuit diagram of a display substrate according to an exemplary embodiment of the present disclosure. As shown in FIG. 20, the display substrate may include a display area AA and a bezel area BK, and the bezel area BK may be provided on one side of the display area AA.

[0213] In an exemplary embodiment, the display area AA may include a plurality of sub-pixels formed by a plurality of pixel rows and a plurality of pixel columns. At least one sub-pixel may include a pixel driving circuit. The pixel driving circuit may include a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor C. The pixel driving circuit is respectively connected to a first scanning signal line 26, a second scanning signal line 27, a data signal line 34, a reference signal line 35, a light-emitting voltage line 43, a first power supply line 73, and a first pole of a light-emitting element XL. The second pole of the light-emitting element XL is connected to a second power supply line VSS. The first scanning signal line 26, the second scanning signal line 27, the light-emitting voltage line 43, and the first power supply line 73 extend along the pixel row direction and may be connected to the pixel driving circuits of a plurality of sub-pixels in one pixel row. The data signal line 34 and the reference signal line 35 extend along the pixel column direction and may be connected to the pixel driving circuits of a plurality of sub-pixels in one pixel column.

[0214] In an exemplary embodiment, the bezel area BK may include a gate driving circuit, a light-emitting control circuit, and a bezel power lead wire.

[0215] In an exemplary embodiment, the gate driving circuit may include a plurality of cascaded gate driving units (shift registers). The gate driving circuit is connected to the first scanning signal line 26 and the second scanning signal line 27 of each pixel row, and can output a first scanning signal and a second scanning signal to the first scanning signal line 26 and the second scanning signal line 27 respectively.

[0216] In an exemplary embodiment, the light-emitting control circuit may include at least a light-emitting control transistor T4. The gate electrode of the light-emitting control transistor T4 is connected to a light-emitting control line E. The first pole of the light-emitting control transistor T4 is connected to a bezel power lead wire F. The second pole of the light-emitting control transistor T4 is connected to the light-emitting voltage line 43 of each pixel row. The light-emitting control transistor T4 is configured to output a light-emitting voltage to the light-emitting voltage line 43 under the control of the light-emitting control line E.

[0217] In an exemplary embodiment, the bezel power lead wire F is connected to the first power supply line 73 and continuously outputs a high-level signal to the first power supply line 73.

[0218] In an exemplary embodiment, the gate drive circuit, the light emission control circuit, and the bezel power lead in the bezel region may be formed in synchronization with the pixel drive circuit in the display region, which will not be described herein.

[0219] As can be seen from the structure of the display device of the exemplary embodiments of the present disclosure and its manufacturing process, the present disclosure installs the wrap positions of the gate electrodes at the same interval, and adopts minimization designs such as gate electrode sharing, drain electrode sharing, and sub-pixel inversion, thereby maximizing the PPI of the display substrate and realizing the highest PPI design of Real RGB silicon-based OLEDs in the industry. The present disclosure provides vias connecting the first scanning signal line and the gate electrode of the first transistor T1, vias connecting the second scanning signal line and the gate electrode of the third transistor T3, and vias connecting the second pole of the first transistor T1 and the gate electrode of the second transistor T2 in the gap region of the sub-pixel, thereby forming a structure in which the wrap positions of the gate electrodes in the sub-pixel are all located in the same gap region. The present disclosure makes the first transistor T1, the second transistor T2, and the third transistor T3 of two adjacent sub-pixels in the first direction mirror-symmetric with respect to the pixel center line, and forms a structure in which the sub-pixels are inverted horizontally with respect to the pixel center line, thereby making the first gate electrodes of two adjacent sub-pixels an integrated structure connected to each other, making the third gate electrodes of two adjacent sub-pixels an integrated structure connected to each other, and forming a gate electrode sharing structure of adjacent sub-pixels. The present disclosure arranges the second transistor T2 and the third transistor T3 along the second direction, thereby making the second pole of the second transistor T2 and the second pole of the third transistor T3 an integrated structure connected to each other, and forming a drain electrode sharing structure in the sub-pixel. The present disclosure adopts the MIM capacitor structure, which not only increases the capacitance value of the memory capacitor, but also ensures the stability of the output current of the pixel driving circuit and the stability of the luminance of the OLED. Through the above structural design, the present disclosure optimizes the layout of the pixel driving circuit, optimizes the layout space, reduces the occupied area of the pixel driving circuit, maximizes the PPI of the display substrate, realizes the highest PPI design of Real RGB silicon-based OLEDs in the industry, can reach a resolution of 4k*4k, and can achieve higher display quality and display effect.

[0220] Exemplary embodiments of the present disclosure further provide a method for manufacturing a display substrate. In an exemplary embodiment, the display substrate includes a display area and a bezel area. The display area includes a plurality of sub-pixels in which pixel rows and pixel columns are formed. The sub-pixels include a first area, a gap area, and a second area that are sequentially arranged along the pixel row direction. At least one sub-pixel includes a pixel driving circuit, a first scanning signal line, and a second scanning signal line. The pixel driving circuit includes at least a first transistor, a second transistor, and a third transistor. The first scanning signal line is configured to control the on or off of the first transistor. The second scanning signal line is configured to control the on or off of the second transistor. The first transistor includes at least a first gate electrode, a first active layer, a first pole of the first transistor, and a second pole of the first transistor. The second transistor includes at least a second gate electrode and a second active layer. The third transistor includes at least a third gate electrode and a third active layer. The manufacturing method includes,

[0221] forming a first transistor, a second transistor, a third transistor, a first scanning signal line, and a second scanning signal line, wherein the first active layer is provided in the first area, the second active layer and the third active layer are provided in the second area, the second active layer is provided on one side of the third active layer in the pixel column direction, the first gate electrode is connected to the first scanning signal line through a first gate via, the second gate electrode is connected to the second pole of the first transistor through a second gate via, the third gate electrode is connected to the second scanning signal line through a third gate via, and the first gate via, the second gate via, and the third gate via are provided in the gap area.

[0222] Exemplary embodiments of the present disclosure further provide a display device including the display substrate. The display device of the present disclosure can be used in a virtual reality device or an augmented display device, etc. The display device includes, but is not limited to, a mobile phone, a tablet, a television, a display, a notebook computer, a digital frame, a navigator, or any product or component having a display function.

[0223] Although the embodiments disclosed in the present disclosure are as described above, the above content is only the embodiments adopted for facilitating the understanding of the present disclosure and does not limit the present disclosure. Those skilled in the art can make all modifications and changes in the embodiments and details without departing from the spirit and scope disclosed by the present disclosure. However, the scope of patent protection of the present disclosure shall be in accordance with the scope defined by the appended patent claims.

Description of Reference Numerals

[0224] 1 First active layer 2 Second active layer 3 Third active layer 4 Contact electrode 11 First gate electrode 11-1 First gate main body 11-2 First gate connection part 12 Second gate electrode 12-1 Second gate main body 12-2 Second gate connection part 13 Third gate electrode 13-1 Third gate main body 13-2 Third gate connection part 21 21st connection electrode 22 22nd connection electrode 23 23rd connection electrode 24 24th connection electrode 26 First scanning signal line 27 Second scanning signal line 28 Bias voltage line 29 Bias connection line 31 31st connection electrode 32 32nd connection electrode 33 33rd connection electrode 34 Data signal line 35 Reference signal line 41 41st connection electrode 42 42nd connection electrode 43 Light-emitting voltage line 51 51st connection electrode 52 52nd connection electrode 61 61st connection electrode 71 Anode connection electrode, 72 Power supply electrode 73 First power line 91 First electrode plate 92 Second electrode plate 101 Silicon base 102 Driving circuit layer 103 Light-emitting structure layer 104 First package layer 105 Color filter structure layer 106 Second package layer 107 Cover plate layer

Claims

1. A display substrate, comprising: a display area and a bezel area, the display area including a plurality of sub-pixels formed by a plurality of pixel rows and a plurality of pixel columns, the sub-pixels including a first area, a gap area, and a second area arranged in sequence along the pixel row direction, at least one sub-pixel including a pixel driving circuit, a first scanning signal line, and a second scanning signal line, the pixel driving circuit including at least a first transistor, a second transistor, and a third transistor, the first scanning signal line being configured to control on or off of the first transistor, the second scanning signal line being configured to control on or off of the second transistor, the first transistor including at least a first gate electrode, a first active layer, a first pole of the first transistor, and a second pole of the first transistor, the second transistor including at least a second gate electrode and a second active layer, the third transistor including at least a third gate electrode and a third active layer, the first active layer being provided in the first area, the second active layer and the third active layer being provided in the second area, the second active layer being provided on one side of the third active layer in the pixel column direction, the first scanning signal line being connected to the first gate electrode through a first gate via, the second pole of the first transistor being connected to the second gate electrode through a second gate via, the second scanning signal line being connected to the third gate electrode through a third gate via, and the first gate via, the second gate via, and the third gate via being provided in the gap area of the display substrate.

2. The display substrate according to claim 1, wherein along the pixel row direction, the first area has a first width, the second area has a second width, the gap area has a third width, the third width is not more than 0.5 * the first width, and the third width is not more than 0.5 * the second width.

3. The first gate electrodes of two adjacent sub-pixels on the pixel row are in an integrated structure connected to each other, and the third gate electrodes of two adjacent sub-pixels on the pixel row are in an integrated structure connected to each other. The display substrate according to claim 1, wherein the integrated first gate electrode is connected to the first scanning signal line through two first gate vias, and the integrated third gate electrode is connected to the second scanning signal line through two third gate vias.

4. In the display substrate according to claim 1, the first transistor, the second transistor, and the third transistor of two adjacent sub-pixels on the pixel row are mirror-symmetric with respect to the pixel center line, and the pixel center line is located between two adjacent sub-pixels on the pixel row and is a straight line extending along the pixel column direction.

5. In at least one sub-pixel, the first gate electrode includes a first gate main body portion and a first gate connection portion that are connected to each other. The first gate connection portion is provided in the gap region, and the first scanning signal line is connected to the first gate connection portion through the first gate via. Or In at least one sub-pixel, the second gate electrode includes a second gate main body portion and a second gate connection portion that are connected to each other. The second gate connection portion is provided in the gap region, and the second electrode of the first transistor is connected to the second gate connection portion through the second gate via. Or In at least one sub-pixel, the third gate electrode includes a third gate main body portion and a third gate connection portion that are connected to each other. The third gate connection portion is provided in the gap region, and the second scanning signal line is connected to the third gate connection portion through the third gate via.

6. In at least one sub-pixel, the first gate electrode includes a first gate main body portion and a first gate connection portion that are connected to each other. The first gate connection portion is installed on the side of the first gate main body portion close to the third gate electrode. The third gate electrode includes a third gate main body portion and a third gate connection portion that are connected to each other. The third gate connection portion is installed on the side of the third gate main body portion close to the first gate electrode. The first gate connection portion and the third gate connection portion are installed with a shift in the pixel column direction.

7. For the first gate main body portion and the first gate connection portion, the edges on the side away from the second transistor are flush. For the third gate main body portion and the third gate connection portion, the edges on the side close to the second transistor are flush.

8. In at least one sub-pixel, the second gate electrode includes a second gate main body portion and a second gate connection portion that are connected to each other, the second gate connection portion is provided in the gap region, and an edge on a side closer to the third transistor of the second gate main body portion and the second gate connection portion is flush. The display substrate according to claim 1.

9. The shapes of the first scanning signal line and the second scanning signal line are linear with the main body portion extending along the pixel row direction, and a front projection of the first scanning signal line on the plane of the display substrate overlaps at least a part of front projections of the first gate electrode and the third gate electrode on the plane of the display substrate, and a front projection of the second scanning signal line on the plane of the display substrate overlaps at least a part of front projections of the first gate electrode and the third gate electrode on the plane of the display substrate. The display substrate according to claim 1.

10. In at least one sub-pixel, the pixel driving circuit further includes a storage capacitor, the storage capacitor includes a first electrode plate and a second electrode plate, a front projection of the first electrode plate on the plane of the display substrate overlaps at least a part of a front projection of the second electrode plate on the plane of the display substrate, the first electrode plate is connected to a second pole of the first transistor through a connection electrode, and the second electrode plate is connected to a first power supply line. The display substrate according to claim 1.

11. At least one sub-pixel further includes a contact electrode, the contact electrode is provided in the first region, and the contact electrode is provided on one side in the pixel column direction of the first active layer. The display substrate according to claim 1.

12. At least one sub-pixel further includes a bias voltage line, the bias voltage line is connected to the contact electrode through a via, and a front projection of the bias voltage line on the plane of the display substrate overlaps at least a part of a front projection of the second gate electrode on the plane of the display substrate. The display substrate according to claim 11.

13. In at least one sub-pixel, the shape of the contact electrode is stripe-shaped extending along the pixel column direction, the shape of the bias voltage line is linear extending along the pixel row direction, the bias voltage line has bias connection lines connected to one side or both sides in the pixel column direction, the orthographic projection of the bias connection line on the plane of the display substrate overlaps at least partially with the orthographic projection of the contact electrode on the plane of the display substrate, and the bias connection line is connected to the contact electrode via the via. The display substrate according to claim 12.

14. A display device including the display substrate according to any one of claims 1 to 13.

15. A method for manufacturing a display substrate, wherein the display substrate includes a display area and a bezel area, the display area includes a plurality of sub-pixels in which pixel rows and pixel columns are formed, the sub-pixels include a first area, a gap area, and a second area arranged in order along the pixel row direction, at least one sub-pixel includes a pixel driving circuit, a first scanning signal line, and a second scanning signal line, the pixel driving circuit includes at least a first transistor, a second transistor, and a third transistor, the first scanning signal line is configured to control on or off of the first transistor, the second scanning signal line is configured to control on or off of the second transistor, the first transistor includes at least a first gate electrode, a first active layer, a first pole of the first transistor, and a second pole of the first transistor, the second transistor includes at least a second gate electrode and a second active layer, the third transistor includes at least a third gate electrode and a third active layer, and the manufacturing method includes forming a first transistor, a second transistor, a third transistor, a first scanning signal line, and a second scanning signal line, providing the first active layer in the first area, providing the second active layer and the third active layer in the second area, providing the second active layer on one side in the pixel column direction of the third active layer, connecting the first gate electrode to the first scanning signal line via a first gate via, connecting the second gate electrode to the second pole of the first transistor via a second gate via, connecting the third gate electrode to the second scanning signal line via a third gate via, and providing the first gate via, the second gate via, and the third gate via in the gap area. A method for manufacturing a display substrate.

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