Small array of color-adjustable pixels having two P-N junctions

Abstract

A monolithically integrated red, green, and blue (RGB) light-emitting diode (LED) array with a reduced mesa etching step and number of contact terminals is manufactured. The LED array can have two or three p-n junctions grown continuously on a wafer. One of the p-n junctions has a reverse deposition order of the n-layer and the p-layer. A light-emitting active region is embedded between each n-layer and p-layer of each p-n junction. Each active region emits light of a different wavelength. The wafer is etched into multiple levels of mesas, two separate voltage terminals and a ground contact are formed, and the bias between specific semiconductor layers is controlled. All of the p-n junctions share a common ground contact.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to an array of light-emitting diode (LED) devices and a method of manufacturing the same. More particularly, the embodiments relate to a monolithic integrated red, green, blue (RGB) emitter array with reduced mesa etching steps and number of contact terminals.

Background Art

[0002] Visualization systems such as virtual reality systems and augmented reality systems are becoming increasingly common in fields such as entertainment, education, medicine, business, and the like. Efforts to improve visualization systems such as virtual reality systems and augmented reality systems continue.

[0003] Micro light-emitting diodes (μLEDs) are small-sized LEDs (typically with a diameter of ~50 μm or less), and by using them, when μLEDs of red, green, and blue wavelengths are arranged in close proximity, a very high-resolution color display can be generated. The manufacture of μLED displays typically involves a step of picking up μLEDs isolated from separate blue, green, and red WL wafers and a step of arranging them alternately in close proximity on the display.

[0004] There is interest in high-resolution color LED displays that require a fine pixel pitch. When the size of the LED is in the range of several tens of microns or less, assembling red, green, and blue LEDs grown on separate wafers is difficult. Monolithic RGB integration is an approach that avoids the problem of manipulating fine LEDs in the correct positions on the display, but it itself involves a series of problems. Current monolithic RGB arrays require at least three bias terminals and a ground connection. In high-resolution displays, the space available for configuring all of these mesa etchings and terminals is limited, and it is actually difficult to implement the design.

Summary of the Invention

Problems to be Solved by the Invention

[0005] Another approach to monolithic RGB is to use one p-n junction containing three-color quantum wells. Depending on the applied bias, relatively more or less light is generated in a particular well, which allows for some control over the color point. Such an approach is attractive in that it operates with only two terminals per pixel, but an excessive voltage across the active region cannot be avoided and a filter is required to obtain display-acceptable color characteristics. Therefore, this approach simplifies the manufacture of the die but is not very suitable for manufacturing an efficient display with low power consumption.

[0006] Accordingly, there is a need for improved μLED devices and improved manufacturing methods.

Means for Solving the Problems

[0007] Embodiments of the present disclosure relate to a light-emitting diode (LED) array and a method of manufacturing the LED array. In one or more embodiments, the light-emitting diode (LED) array has a first light-emitting stack on a second light-emitting stack on a reflective p-contact electrode bonded to a backplane, the first light-emitting stack having a first electrical contact on a first n-type layer, the first n-type layer being on a first tunnel junction, the first tunnel junction being on a first p-type layer, the first p-type layer being on a first color active region, the second light-emitting stack having a second electrical contact on a second n-type layer in contact with the first color active region and on a second color active region, the second color active region being on a second p-type layer, the LED array further having a dielectric layer surrounding the first light-emitting stack and the second light-emitting stack, and a conformal reflective metal layer on the dielectric layer.

[0008] Another embodiment of the present disclosure relates to a method of manufacturing a light emitting diode (LED) array. In certain embodiments, a method of manufacturing an LED array includes sequentially forming two p-n junctions on an epitaxial wafer to form an epitaxial stack, the epitaxial stack having at least one n-type layer and at least one p-type layer, and having a color active region buried between the at least one n-type layer and the at least one p-type layer; depositing a reflective p-contact electrode on the epitaxial stack; bonding the reflective p-contact electrode to a backplane wafer; dry etching the epitaxial stack to access the at least one n-type layer and form an electrical contact and a mesa; conformally depositing a dielectric layer on the mesa; removing a portion of the dielectric layer to form a dielectric opening in an upper surface of the mesa, the dielectric opening exposing the at least one n-type layer; depositing an ohmic metal contact in the dielectric opening to form an electrical contact; depositing a conformal metal layer over a portion of the mesa to form a gap crossing a center of the mesa to enable light to exit to the outside; and depositing an electrode grid over an upper portion of the LED array.

[0009] Additional embodiments of the present disclosure relate to visualization systems or display systems. In one or more embodiments, a visualization system includes a battery, a wireless device, a sensor, a video generation process, a light source including an LED array according to the foregoing embodiments, a modulator, a modulation processor, a beam combiner, projection optics, a screen, and a lens.

[0010] To better understand the foregoing features of the present disclosure, a more specific description of the present disclosure, briefly summarized above, can be obtained by referring to the embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings are merely illustrative of typical embodiments of the present disclosure, and thus the present disclosure should not be considered as limiting its scope, as it may admit other equally effective embodiments. The embodiments described in this application are shown by way of example and are not limited to the figures in the accompanying drawings. In the figures, like reference numerals represent like elements.

Brief Description of the Drawings

[0011]

Figure 1

Figure 2A

Figure 2B

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

DETAILED DESCRIPTION OF THE INVENTION

[0012] For ease of understanding, whenever possible, the same reference numerals are used to denote common and equal elements in the drawings. The drawings are not drawn to scale. For example, no scale is shown for the height and width of the mesa.

[0013] Before describing some exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of the structures or process steps described in the following description. The present disclosure can be in other embodiments and can be implemented or realized in various ways.

[0014] The term "substrate" as used in the present application according to one or more embodiments represents a structure, intermediate, or final product having a surface or a portion of a surface on which a process acts. Also, the reference to a substrate in some embodiments represents only a portion of the substrate unless the context clearly indicates otherwise. Further, the reference to deposition on a substrate according to some embodiments includes deposition on a bare substrate or on a substrate on which one or more layers, films, features, or materials have been deposited or formed.

[0015] In one or more embodiments, "substrate" means any substrate or the surface of a material formed on a substrate on which film processing is performed during the manufacturing process. In an exemplary embodiment, the substrate surface on which the processing is performed is a material such as silicon, silicon oxide, silicon on insulator (SOI), strained silicon, amorphous silicon, doped silicon, carbon-doped silicon oxide, germanium, gallium arsenide, glass, sapphire, and any other suitable material, for example, depending on the application, including metals, metal nitrides, group III-nitrides (e.g., GaN, AlN, InN, and other alloys), metal alloys, and other conductive materials. The substrate includes, but is not limited to, light-emitting diode (LED) devices. In some embodiments, the substrate is subjected to a pretreatment process in which the substrate surface is polished, etched, reduced, oxidized, hydroxylated, annealed, UV cured, electron beam cured, and / or baked. Also, in addition to performing the film processing directly on the surface of the substrate itself, in some embodiments, any of the disclosed film processing steps are also performed on an underlying layer formed on the substrate, and the term "substrate surface" is intended to include such an underlying layer as the context indicates. Thus, for example, when a film / layer or a partial film / layer is deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0016] The terms "wafer" and "substrate" are used interchangeably in this disclosure. Thus, as used in this application, a wafer functions as a substrate for forming the LED devices described in this application.

[0017] Hereinafter, with reference to the accompanying drawings, examples of different light irradiation systems and / or light-emitting diodes (LEDs) will be described in more detail. These examples are not mutually exclusive, and features found in one example may be combined with features found in one or more other examples to achieve additional embodiments. Accordingly, it is understood that the examples shown in the accompanying drawings are provided for illustrative purposes only and are not intended to limit the disclosure in any way. Like reference numerals represent like elements throughout.

[0018] Semiconductor light-emitting devices, or optical power emitting devices such as, for example, devices that emit ultraviolet (UV) or infrared (IR) optical power, are one of the most efficient light sources currently available. These devices can include light-emitting diodes, resonant cavity light-emitting diodes, vertical cavity laser diodes, edge-emitting lasers, etc. (hereinafter referred to as "LEDs"). Due to their compact size and low power requirements, LEDs, for example, can be an attractive candidate for many different applications. For example, these may be used as light sources (e.g., flashlights, camera flashes) for portable battery-powered devices such as cameras and mobile phones. They may also be used, for example, for automotive lighting, head-up display (HUD) lighting, horticultural lighting, street lighting, video torches, general lighting (e.g., home, store, office and studio lighting, theater / stage lighting and architectural lighting), augmented reality (AR) lighting, virtual reality (VR) lighting, as backlights for displays, and for IR spectroscopy. A single LED may provide light with lower brightness than an incandescent light source, and thus, for applications where higher brightness is desired or required, a multi-connected device or an array of LEDs (such as a monolithic LED array, a micro-LED array, etc.) may be used.

[0019] The present invention generally relates to the manufacture of micro-light-emitting diode (μLED) displays and multi-wavelength light emitters having a wide bandwidth for free-space visible light communication. Multiple emission wavelengths may be combined within a single LED device using an epitaxial tunnel junction.

[0020] When two or more active regions emitting different wavelengths are integrated within a single wafer, the manufacturing of μLEDs can be simplified. Such an approach may be possible in the AlInGaN material system. This is because it has been demonstrated that blue, green, and red LEDs can all be fabricated in this system. However, for using multi-color chips in μLED displays, not only is it necessary to stack multiple layers capable of emitting different wavelengths in a single epitaxial growth run, but also a function to vary the respective emission intensity ratios between emitters of different wavelengths is required.

[0021] In one or more embodiments, LED color bias system control is used to reduce the number of terminals to a more manageable number than current technologies. However, independent control of some of the separate junctions is used to avoid the problems of low color purity and high voltage inherent in other approaches. Also, in one or more embodiments, an improved method of controlling the LED wavelength via voltage is provided.

[0022] In one or more embodiments, "reverse polarity" LEDs are significantly used for display applications. As used herein, the term "reverse polarity" refers to growing the p-GaN layer of the LED in front of the quantum well rather than behind it. It is widely recognized that high-efficiency p-side-down LEDs are difficult to realize because acceptor dopants unintentionally mix into the quantum well. However, in one or more embodiments, it has been recognized that, significantly, the above problems can be mitigated by using special growth conditions. Reverse polarity LEDs are so named because the direction of the p-n junction and InGaN polarization fields is reversed from conventional means.

[0023] As used herein, the term "p-n junction" refers to the boundary between two semiconductor layers of opposite conductivity types, a p-type and an n-type. The "p" side contains an excess of holes, and the "n" side contains an excess of electrons. The excess of holes and electrons can be obtained, respectively, by intentionally doping acceptor or donor impurities, and / or may be due to the presence of natural crystal defects. The boundary need not necessarily be abrupt, flat, or smooth. The boundary may include a gradient of impurity concentration and / or an intrinsic (neutral) conductivity type layer between the p-type layer and the n-type layer. The boundary may be characterized by a protrusion of the p-type semiconductor into the n-type semiconductor, or vice versa.

[0024] Embodiments of the present disclosure are illustrated by the drawings. The figures show an apparatus according to one or more embodiments of the present disclosure and a process for forming the apparatus. The processes shown are merely examples that may be used with respect to the disclosed processes, and one of ordinary skill in the art will appreciate that the disclosed processes are not limited to the applications shown.

[0025] In one or more embodiments, the reversed orientation of the polarity facilitates the control of the net electric field across the quantum well in a manner that is advantageous for wavelength control. The advantages of this concept are conceptually illustrated in FIGS. 2A, 2B, and 3, and the measured spectra of the color-shifted LEDs are shown in FIG. 4.

[0026] FIGS. 2A and 2B are schematic diagrams showing how the control of the emission wavelength by an applied voltage is facilitated by reversing the order of the p-layer and the n-layer. The larger the magnitude of the electric field across the indium gallium nitride (InGaN) quantum well, the higher the wavelength due to the quantum confinement Stark effect. The graph shown in FIG. 3 shows the measured data for LEDs of opposite polarities and the same quantum well design.

[0027] FIG. 4 is a graph showing the measurement spectra of a red-green switchable color LED having p-GaN grown in front of a quantum well. The spectra are characterized by distinct peaks that vary with voltage, rather than multiple peaks with voltage-dependent heights, such as those of existing LEDs that use multiple quantum wells of different colors in the same active region. The quantum wells of FIG. 4 are wider than the quantum wells shown in FIGS. 2A and 2B, allowing for a large wavelength shift with voltage.

[0028] The μLED array of one or more embodiments is significant in that it requires fewer contact terminals and mesa etching compared to conventional μLED arrays. The μLED array of one or more embodiments requires only two independent bias terminals and a common ground electrode. Also, in the μLED array of one or more embodiments, better control of the emission color is possible compared to conventional single-junction RGB technology. Without intending to be bound by theory, it is believed that the μLED array of one or more embodiments can achieve lower display power consumption than the published single-junction RGB technology.

[0029] In one or more embodiments, two or three p-n junctions are grown continuously on the same epitaxial wafer. One of these junctions has the order of deposition of the n and p layers reversed compared to the other junctions. In one or more embodiments, an emission active region is embedded between the n and p layers of each junction. Each active region emits light of a different wavelength than the other active regions. At least one junction has the property that as the bias across the junction increases, its emission shifts from one of the primary colors to a different (shorter) primary color. For example, the emission may shift from red to green or from green to blue.

[0030] In one or more embodiments, the epitaxial growth includes at least one tunnel junction, avoiding the need for contact to the etched p-GaN layer. The wafer is etched into a multi-level mesa that forms two separate voltage terminals and a ground contact, and the bias between specific semiconductor layers is controlled. All junctions share a common ground contact.

[0031] In one or more other embodiments, two junction devices are provided, and by changing the voltage of one terminal, the color emitted by one of the junctions is controlled. For example, by increasing the voltage, the color may change from red to green. When the bias voltage is increased, the red and green emission luminance can be made to match by decreasing the pulse width modulation cycle. Blue emission is controlled by an independent contact terminal for the third (blue) active region. The voltage-dependent color change function is facilitated by an orientation that is inverted from the normal orientation of the p-n junction field with respect to the InGaN quantum well polarization field.

[0032] In the example shown in the figures and described in detail below, blue light is generated by an independent drive voltage (applied to terminal A in FIGS. 6 and 10). However, another embodiment is possible where the red active region is exchanged with the blue active region. In these embodiments, red light is emitted by the bias to terminal A, and the magnitude of the bias to terminal B can be used to adjust the emission of other colors from green to blue.

[0033] FIG. 1 shows a process flow diagram of a method 50 for manufacturing a micro light emitting diode (μLED) array according to one or more embodiments of the present invention. Referring to FIG. 1, in one or more embodiments, the method begins in operation 52 by sequentially forming two or three p-n junctions on the same epitaxial wafer to form an epitaxial stack that includes at least one n-type layer and at least one p-type layer, with a color active region embedded between the at least one n-type layer and the at least one p-type layer. In operation 54, a reflective p-contact electrode is deposited on the epitaxial stack. In operation 56, the epitaxial stack with the reflective p-contact is bonded to a backplane wafer. In operation 58, the epitaxial stack is dry etched to provide access to the n-type layer and form electrical contacts and mesas. In operation 60, a dielectric layer is conformally deposited across the epitaxial wafer on the mesa. In operation 62, a portion of the dielectric layer is removed to form a dielectric opening on the top surface of the mesa, exposing at least one n-type layer through the dielectric opening. In operation 64, an ohmic contact is deposited within the dielectric opening to form an electrical contact. In operation 66, a conformal reflective metal layer is deposited over a portion of the mesa to form a gap across the center of the mesa for emitting light externally. In operation 68, an electrode grid is deposited over the top of the LED array.

[0034] Referring to FIG. 5, the epitaxial growth steps of Modification A, which is the first modification example 100, are described. FIG. 5 shows a cross-sectional view of the μLED array 100 according to one or more embodiments. One aspect of the present disclosure relates to a method of manufacturing a μLED array. Referring to FIG. 5, the first modification example 100, Modification "A", is a three-junction device having first and second (opposite p-n deposition orders) p-n junctions sharing a common n-type layer connected to one of the electrical terminals. These two junctions are driven in parallel (not independently), but the collective color of their emissions can be controlled by voltage. For example, when red and green active regions are connected in parallel, current flows only through the red region at a low voltage. The red active region can be designed such that its emission shifts to green at a high voltage and is added to the light emitted by the green active region. Blue emission is controlled by an independent contact terminal for the third (blue) active region.

[0035] Referring to FIG. 5, the μLED array 100 is manufactured by forming a plurality of group-III nitride layers on a substrate 102 and forming a three-junction LED on the substrate including color active regions. The color active regions include a first color active region 106a, a second color active region 106b, and a third color active region 106c. Any order of stacking different color active regions is within the scope of the present disclosure.

[0036] In certain embodiments, the LED array 100 includes three or more p-n junctions. In one or more embodiments, the first light-emitting stack 105a has a first n-type layer 104a formed on the substrate 102, a first color active region 106a formed on the first n-type layer 104a, a first p-type layer 108a formed on the first color active region 106a, and a first tunnel junction 110a formed on the first p-type layer 108a. The first p-n junction includes the first n-type layer 104a and the first p-type layer 108a separated by the first color active region 106a.

[0037] In one or more embodiments, the first color active region 106a is a blue color active region. In the illustrated embodiment, a first tunnel junction 110a is present on the first emission stack, particularly on the first p-type layer 108a. A tunnel junction is a structure in which electrons can tunnel in reverse bias from the valence band of the p-type layer to the conduction band of the n-type layer. When electrons tunnel, holes are left in the p-type layer and carriers are generated in both regions. Thus, in an electronic device such as a diode, a large current can flow in reverse bias through the tunnel junction because the leakage current flowing in reverse bias is small. A tunnel junction has a specific arrangement of the conduction band and valence band in a p-n tunnel junction. This can be achieved by using extremely high doping (e.g., p++ / n++ junction). Also, group-III nitride materials have an inherent polarization that forms an electric field at the heterointerface between different alloy compositions. In certain situations, this polarization field can also be utilized in achieving the band arrangement for tunneling.

[0038] Referring further to FIG. 5, the μLED array 100 further has a second emission stack 105b on the first emission stack 105a. The second emission stack 105b has a second n-type layer 104b on the first tunnel junction 110a, a second tunnel junction 110b on the second n-type layer 104b, a second p-type layer 108b on the second tunnel junction 110b, and a second color active region 106b on the second p-type layer 108b. In one or more embodiments, the second color active region 106b is a red color active region. In the illustrated embodiment, a second tunnel junction 110b is present on the second junction 110a, particularly on the second n-type layer 104b. When the second n-type layer 104b is biased in the forward direction with respect to the second p-type layer 108b, a hole current flows through the second tunnel junction 110b to the second p-type layer 108b. The second tunnel junction 110b itself is a (second) p-n junction and is composed of an n-type layer and a p-type layer, although not shown separately in the figure. The second p-type layer 108b serves to inject the holes necessary to excite the luminescence from the second color active region 106b.

[0039] The third light-emitting stack 105c is formed on the second light-emitting stack 105b and has a third n-type layer 104c on the second color active region 106b, a third color active region 106c on the third n-type layer 104c, and a third p-type layer 108c on the third color active region 106c. The third n-type layer 104c functions to inject electrons into both the second color active region 106b of the second light-emitting stack and the third color active region 106c of the third light-emitting stack. The third p-n junction has the third n-type layer 104c and the third p-type layer 108c separated by the third color active region 106c.

[0040] In one or more embodiments, the first n-type layer 104a is formed on the substrate 102. The substrate 102 may be any substrate known to those skilled in the art configured for use in the formation of an LED device. In one or more embodiments, the substrate 102 includes one or more of sapphire, silicon carbide, silicon (Si), quartz, magnesium oxide (MgO), zinc oxide (ZnO), and spinel. In one or more embodiments, the substrate 102 is a transparent substrate. In a particular embodiment, the substrate 102 includes sapphire. In one or more embodiments, the substrate 102 is not patterned prior to the formation of the LED. Thus, in some embodiments, the substrate 102 can be considered unpatterned and flat or substantially flat. In other embodiments, the substrate 102 is a patterned substrate.

[0041] In one or more embodiments, the first n-type layer 104a, the second n-type layer 104b, and the third n-type layer 104c may include any III-V semiconductor including binary alloys, ternary alloys, and quaternary alloys of gallium (Ga), aluminum (Al), indium (In), and nitrogen (N). This is also referred to as group-III nitride materials. Thus, in some embodiments, the first n-type layer 104a, the second n-type layer 104b, and the third n-type layer 104c may each independently include one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), etc. In certain embodiments, the first n-type layer 104a, the second n-type layer 104b, and the third n-type layer 104c include gallium nitride (GaN). In one or more embodiments, the first n-type layer 104a, the second n-type layer 104b, and the third n-type layer 104c are independently doped with an n-type dopant such as silicon (Si) or germanium (Ge). In one or more embodiments, the dopant concentration ranges from 1×10 17 to 2×10 19 cm 3 .

[0042] In one or more embodiments, the layer of group-III nitride material may be formed by one or more of sputtering, atomic layer deposition (ALD), metalorganic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), plasma-enhanced atomic layer deposition (PEALD), and plasma-enhanced chemical vapor deposition (PECVD).

[0043] As used herein, "sputter deposition" refers to a physical vapor deposition (PVD) method for depositing a thin film by sputtering. In the sputter deposition method, a material, such as a group III-nitride, is released from a target, which is the source, onto a substrate. This technique is based on ion bombardment of the target, which is the source material. The ion bombardment results in vaporization by a purely physical process, namely sputtering of the target material.

[0044] When used in some embodiments of the present application, "atomic layer deposition" (ALD) or "cyclic deposition" refers to a vapor phase technique used to deposit a thin film on a substrate surface. The process of ALD involves exposing the substrate surface or a part of the substrate to alternating precursors, i.e., two or more reactive compounds, to form a layer of material on the substrate surface. When the substrate is exposed to the alternating precursors, the precursors are introduced continuously or simultaneously. The precursors are introduced into the reaction zone of the processing chamber, and the substrate or a part of the substrate is exposed to the precursors separately.

[0045] When used in an embodiment, "chemical vapor deposition" refers to a process in which a film of a material is deposited on a substrate surface from the vapor phase by decomposition of a chemical substance. In CVD, the substrate surface is exposed to a precursor and / or a co-reactant simultaneously or substantially simultaneously. In a particular subset of CVD processes commonly used in LED manufacturing, metal-organic precursor chemicals are used and it is called MOCVD or metal-organic vapor phase epitaxy (MOVPE). As used herein, "substantially simultaneously" refers to either a parallel flow or a case where there is an overlap in the majority of the exposure of the plurality of precursors.

[0046] "Plasma-enhanced atomic layer deposition (PEALD)" as used in some embodiments represents a technique for depositing a thin film on a substrate. In some examples of PEALD processes related to thermal ALD processes, the materials may be formed from the same chemical precursors, but are carried out at a higher film deposition rate and a lower temperature. In the PEALD process, generally, a reactive gas and a reactive plasma are sequentially introduced into a processing chamber containing the substrate. The first reactive gas is pulsed in the processing chamber and adsorbed on the substrate surface. Thereafter, the reactive plasma is pulsed in the processing chamber and reacts with the first reactant gas to form a film-forming material, e.g., a thin film, on the substrate. Similar to the thermal ALD process, a purge step may be carried out between the supply of each reactant.

[0047] When used in one or more embodiments, "plasma-enhanced chemical vapor deposition (PECVD)" represents a technique for forming a thin film on a substrate. In the PECVD process, a source material in a gaseous or liquid phase is introduced into a PECVD chamber, which is, for example, a gaseous group-III nitride material or a liquid phase group-III nitride material entrained in a carrier gas. A plasma initiation gas is also introduced into the chamber. When a plasma is generated in the chamber, excited radicals are generated. The excited radicals chemically bond to the surface of the substrate disposed in the chamber, and a desired film is formed thereon.

[0048] In one or more embodiments, the μLED array 100 is manufactured by placing the substrate 102 in a metalorganic vapor phase epitaxy (MOVPE) reactor such that the μLED array layer grows epitaxially.

[0049] In one or more embodiments, the first p-type layer 108a, the second p-type layer 108b, and the third p-type layer 108c may each independently comprise any III-V semiconductor including binary alloys, ternary alloys, and quaternary alloys of gallium (Ga), aluminum (Al), indium (In), and nitrogen (N). These are also referred to as group-III nitride materials. Thus, in some embodiments, the first p-type layer 108a, the second p-type layer 108b, and the third p-type layer 108c may each independently comprise one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), etc.

[0050] In some embodiments, the first p-type layer 108a, the second p-type layer 108b, and the third p-type layer 108c each independently comprise a series of doped p-type layers. In one or more embodiments, the first p-type layer 108a, the second p-type layer 108b, and the third p-type layer 108c each independently comprise a gallium nitride (GaN) layer. The first p-type layer 108a, the second p-type layer 108b, and the third p-type layer 108c may each independently be doped with any suitable p-type dopant known to those skilled in the art. In one or more embodiments, the first p-type layer 108a, the second p-type layer 108b, and the third p-type layer 108c may each independently be doped with magnesium (Mg). In one or more embodiments, the first p-type layer 108a, the second p-type layer 108b, and the third p-type layer 108c each independently comprise a first magnesium-doped p-type aluminum gallium nitride layer, a magnesium-doped p-type gallium nitride layer, and a second magnesium-doped p-type aluminum gallium nitride layer.

[0051] In one or more embodiments, the main differentiating factor of the epitaxy used between this μLED array and a conventional μLED array is the aforementioned reverse polarity orientation and the use of wells that are wider than typical quantum wells in applications where a large color shift is intentionally desired. For example, the well width for optimizing the internal quantum efficiency (IQE) may be 3 nm, but in one or more embodiments, it may be preferable to increase the width up to 5 nm. In one or more embodiments, the well width may range from 2 nm to 8 nm.

[0052] FIG. 6 shows a schematic cross-sectional view after processing the first modification 100 into a micro-LED array. Arrows 126, 128, 130 having different line patterns represent recombination paths where red, green, and blue emissions occur. In one or more embodiments, when terminal A122 has a voltage of about 3 volts and terminal B124 has a voltage of about 0 volts, blue light 130 is generated. In one or more embodiments, when terminal A122 has a voltage of about 0 volts and terminal B124 has a voltage greater than 3 volts, red light 128 is generated. In one or more embodiments, when terminal A122 has a voltage of about 0 volts and terminal B has a voltage of about 5 volts or more, green light 126 (or red-green light) is generated. Using a color-shifted red active region similar to that shown in FIG. 4, red emission with a small bias on terminal B124 and additional green emission with a large bias on terminal B124 may be generated. As will be understood by those skilled in the art, the first modification 100 shown in FIG. 6 is rotated 180 degrees with respect to the depiction in FIG. 5.

[0053] Referring to FIG. 6, the micro-LED wafer 150 is fabricated in the first step of acceptor activation annealing. A reflective p-contact electrode (p-mirror) 118 is deposited. The reflective p-contact electrode (p-mirror) 118 may include any suitable material known to those skilled in the art. In one or more embodiments, the reflective p-contact electrode (p-mirror) 118 includes one or more of aluminum (Al), platinum (Pt), silver (Ag), etc. In other embodiments, the reflective p-contact electrode (p-mirror) 118 may include a bilayer of a reflective material (i.e., one or more of aluminum (Al), platinum (Pt), silver (Ag), etc.) and indium tin oxide (ITO), and the ITO is part of the bilayer that is in direct contact with the third p-type layer 108c.

[0054] In one or more embodiments, the reflective p-contact electrode (p-mirror) 118 is then bonded to the backplane wafer 120, which may be pre-coated with a similar metal to facilitate wafer bonding. In one or more embodiments, the backplane wafer 120 includes vias 122 and 124 between the bonding surface and the circuit inside or on the opposite surface of the backplane wafer 120.

[0055] Still referring to FIG. 6, in one or more embodiments, the first n-type layer 104a, the second n-type layer 104b, and the third n-type layer 104c are etched, for example, by dry etching to form openings for electrical contacts 114, separate the pixels, and access the via 124 to the backplane terminal B. In one or more embodiments, there are a total of three etching levels 152, 154, and 156, which is a number that is easier to manage than a conventional μLED array.

[0056] In one or more embodiments, a dielectric layer 112 is conformally deposited over the entire wafer 150. As used herein, the term "dielectric" refers to an electrically insulating material that can be polarized by an applied electric field. In one or more embodiments, the dielectric layer includes, but is not limited to, oxides such as silicon dioxide (SiO2), aluminum oxide (Al2O3), nitrides such as silicon nitride (Si3N4), and the like. In one or more embodiments, the dielectric layer includes silicon nitride (Si3N4), silicon dioxide (SiO2), or a multi-layer of silicon dioxide (SiO2) and silicon nitride (Si3N4). In some embodiments, the composition of the dielectric layer is non-stoichiometric with respect to the ideal molecular formula. For example, in some embodiments, the dielectric layer includes, but is not limited to, oxides (e.g., silicon oxide, aluminum oxide), nitrides (e.g., silicon nitride (SiN)), oxycarbides (e.g., silicon oxycarbide (SiOC)), and oxynitrocarbides (e.g., silicon oxynitride carbonate (SiNCO)).

[0057] In one or more embodiments, the dielectric layer 112 is removed from the electrical contact points using dry etching. An ohmic contact metal layer 114 is formed over the dielectric opening. Each of the ohmic contact metal layers 114 is in contact with the n-type layers 104a, 104b, 104c and may be the same metal. The ohmic contact metal layer 114 may include any suitable metal known to those skilled in the art. In one or more embodiments, the ohmic contact metal layer 114 includes aluminum (Al).

[0058] Referring further to FIG. 6, a thick, partially conformal metal layer 116 is deposited over most of the mesa region. As shown in FIGS. 6 and 7, a gap 132 is left that traverses the center of the mesa, allowing light to be radiated out and the terminal B124 to be electrically insulated from ground. The partially conformal metal layer 116 may include any suitable material known to those skilled in the art. In one or more embodiments, the partially conformal metal layer 116 has high reflectivity and stability. In one or more embodiments, the partially conformal metal layer 116 includes aluminum (Al) or platinum (Pt). The layer 116 may be composed of a stack of multiple different metal thin films, for example, a first metal such as Al or silver (Ag) having high reflectivity characteristics and a second metal such as titanium (Ti), chromium (Cr), tungsten (W), gold (Au) or Pt having better chemical stability. The partially conformal metal layer 116 connects the second n-type layer 104b to the via 124 to the backplane terminal B.

[0059] FIG. 7 shows a schematic top view of the array 150 shown in cross-section in FIG. 6. The cross-section shown in FIG. 7 corresponds to the northwest corner of a larger display. In one or more embodiments, the ground line electrode grid 172 is deposited over the top of the reflective, partially conformal metal layer 116 on one side of each pixel, as shown in FIG. 7. The electrode grid 172 connects to the ground line around the display 150. In one or more embodiments, the electrode grid 172 connects the ground terminal (left side in FIG. 6) to the ground electrodes around the display.

[0060] Referring to FIGS. 6 and 7, in one or more embodiments, blue light 130 is emitted when terminal A174 is biased above ground potential (i.e., +3V) and terminal B176 is at ground (i.e., 0V). In one or more embodiments, when terminal A174 is at ground (i.e., 0V), either red light 128 or green light 126 can be generated by applying a bias to terminal B176 depending on the magnitude of the bias. For example, when the bias to terminal B is in the range of about 3V to less than 5V, red light 128 is generated, and when the bias to terminal B176 exceeds 5V, green light 126 can be generated. The first color active region 106a and the second color active region 106b are connected in parallel, but for small biases, it can be designed such that current flows only through the second color (red) active region 106b. Thus, only red light 128 is generated. For a larger bias to terminal B176, the current flows through both the red and green active regions, but due to the higher IQE of the green active region relative to red and the natural tendency of red emission to shift towards shorter wavelengths at higher current densities, the generated color can be predominantly green. The green color purity may be further enhanced using a "red" active region as in FIG. 4, which itself emits green (not red) light at high current densities. The pulse width modulation duty cycle is reduced for the green operating mode, and can produce a similar emission luminance as the red mode with a higher duty cycle.

[0061] FIG. 8 shows the top placement of conformal dielectric layers 182, 184, 186 formed over the entire surface following the last mesa etching step. In one or more embodiments, conformal dielectric layers 182, 184, 186 are below the electrode grid 172 shown in FIG. 7. Referring to FIGS. 6 - 8, regions 188, 194 indicate locations where the dielectric layers 182, 184, 186 are removed by later etching to access the ohmic contact metal layer 114 on the pixels. Also, the conformal dielectric layers 182, 184, 186 may be used to access via 190 connected to terminal B in the backplane, or via 190 connected to terminal A.

[0062] Referring to FIG. 9, the epitaxial growth step of variant B, which is the second variant 200, is shown. FIG. 9 shows a cross - sectional view of a μLED array 200 according to one or more embodiments. One aspect of the present disclosure relates to a method of manufacturing a μLED array. Referring to FIG. 9, the second variant 200, variant “b”, is a two - junction device where the first and second p - n junctions (with opposite p - n deposition orders) share a common n - type layer connected to one of the electrical terminals. In one or more embodiments, variant B200 has a simpler epitaxial structure and a simpler mesa surface topography than variant A100. The manufacture of the micro - LEDs is achieved with one less mesa etching level in variant B200. In variant B200, the first active region itself supplies both red and green light to terminal B according to the mechanism shown in FIG. 4 in response to bias.

[0063] Referring to FIG. 9, the μLED array 200 is manufactured by forming a plurality of group - III nitride layers on a substrate 202 to form a two - junction LED on the substrate including color active regions. The color active regions include a first color active region 206a and a second color active region 206b. Any order of stacking different color active regions is within the scope of the present disclosure.

[0064] In certain embodiments, the LED array 200 has a first light-emitting stack 205a, which includes a first n-type layer 204a formed on a substrate 202, a first tunnel junction 210a formed on the first n-type layer 204a, a first p-type layer 208a formed on the first tunnel junction 210a, a first color active region 206a formed on the first p-type layer 208a, and a second n-type layer 204b on the first color active region 206a.

[0065] In one or more embodiments, the first color active region 206a is a red / green color active region. In the illustrated embodiment, there is a tunnel junction 210a between the first n-type layer 204a and the first p-type layer 208a. This arrangement enables holes to be injected into the first color active region 206a without directly contacting metal with the surface of the p-type layer 208a. Electrons are injected into the first color active region 206a from the second n-type layer 204b.

[0066] Referring further to FIG. 9, the μLED array 200 further has a second light-emitting stack 205b on the first light-emitting stack 205a. The second light-emitting stack 205b includes a second n-type layer 204b, a second color active region 206b on the second n-type layer 204b, and a second p-type layer 208b on the second color active region 206b. It should be noted that the second n-type layer 204b is "shared" between both the first and second light-emitting stacks 205a and 205b. In other words, the second n-type layer 204b can be used to inject electrons into both the first active region 206a and the second active region 206b. The second n-type layer 204b may be composed of a plurality of layers with different n-type doping concentrations. In one or more embodiments, the second color active region 206b is a blue color active region. Optionally, a second tunnel junction 210b and a third n-type layer 204c may be formed on the second p-type layer 208b. These optional layers enable the wafer to be subjected to high-temperature processing (e.g., high-temperature annealing to activate the buried p-type layer) without damaging the p-type layer 208b.

[0067] In one or more embodiments, a first n-type layer 204a is formed on a substrate 202. The substrate 202 may be any substrate known to those skilled in the art configured for use in the formation of an LED device. In one or more embodiments, the substrate 202 includes one or more of sapphire, silicon carbide, silica (Si), quartz, magnesium oxide (MgO), zinc oxide (ZnO), spinel, etc. In one or more embodiments, the substrate 202 is a transparent substrate. In certain embodiments, the substrate 202 includes sapphire. In one or more embodiments, the substrate 202 is not patterned prior to the formation of the LED. Thus, in some embodiments, the substrate 202 can be considered unpatterned and flat or substantially flat. In other embodiments, the substrate 202 is a patterned substrate.

[0068] In one or more embodiments, the first n-type layer 204a, the second n-type layer 204b, and any third n-type layer 204c may include any III-V semiconductor including binary alloys, ternary alloys, and quaternary alloys of gallium (Ga), aluminum (Al), indium (In), and nitrogen (N), also referred to as group-III nitride materials. Thus, in some embodiments, the first n-type layer 204a, the second n-type layer 204b, and the third n-type layer 204c each independently include one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), etc. In a specific embodiment, the first n-type layer 204a, the second n-type layer 204b, and the third n-type layer 204c include gallium nitride (GaN). In one or more embodiments, the first n-type layer 204a, the second n-type layer 204b, and the third n-type layer 204c are each independently doped with an n-type dopant such as silicon (Si) or germanium (Ge).

[0069] In one or more embodiments, the group-III nitride material layer may be formed by one or more of sputter chemical vapor deposition, atomic layer chemical vapor deposition (ALD), metalorganic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), plasma-enhanced atomic layer chemical vapor deposition (PEALD), and plasma-enhanced chemical vapor deposition (PECVD) as described above.

[0070] In one or more embodiments, the μLED array 200 is manufactured by disposing the substrate 202 in a metalorganic vapor phase epitaxy (MOVPE) reactor such that the μLED array layer grows epitaxially.

[0071] In one or more embodiments, the first p-type layer 208a and the second p-type layer 208b may each independently include any III-V semiconductor including binary alloys, ternary alloys, and quaternary alloys of gallium (Ga), aluminum (Al), indium (In), and nitrogen (N), also referred to as group-III nitride materials. Thus, in some embodiments, the first p-type layer 208a and the second p-type layer 208b each independently include one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), etc.

[0072] In some embodiments, the first p-type layer 208a and the second p-type layer 208b each independently include a series of doped p-type layers. In one or more embodiments, the first p-type layer 208a and the second p-type layer 208b each independently include a gallium nitride (GaN) layer. The first p-type layer 208a and the second p-type layer 208b may each independently be doped with any suitable p-type dopant known to those skilled in the art. In one or more embodiments, the first p-type layer 208a and the second p-type layer 208b may each independently be doped with magnesium (Mg). In one or more embodiments, the first p-type layer 208a and the second p-type layer 208b each independently include a first magnesium-doped p-type aluminum gallium nitride layer, a magnesium-doped p-type gallium nitride layer, and a second magnesium-doped p-type aluminum gallium nitride layer.

[0073] In one or more embodiments, the main differentiating factor of the epitaxy used between the present μLED array 200 and an existing μLED array is the reverse polarization orientation described above, and in applications where a large color shift is intentionally desired, using wells that are wider than typical quantum wells. For example, the well width for optimizing the internal quantum efficiency (IQE) at a high current density is 3 nm, but in one or more embodiments, it may be preferable to increase the width to 5 nm. In one or more embodiments, the well width may range from 2 nm to 8 nm.

[0074] FIG. 10 shows a schematic cross-sectional view after processing the second variant 200 into a micro LED array 250. Arrows 226, 228 having different line patterns represent recombination paths where red, green, and blue emissions occur. Using a color shift red active region similar to FIG. 4, red emission with a small bias at terminal B and green emission with a large bias at terminal B may be generated. As will be understood by those skilled in the art, the second variant 200 of FIG. 9 is rotated 180 degrees to form the micro LED array 250.

[0075] Referring to FIG. 10, the micro LED wafer 250 is manufactured by first performing an acceptor activation anneal. A reflective p-contact electrode (p-mirror) 218 is formed. The reflective p-contact electrode (p-mirror) 218 may include any suitable material known to those skilled in the art. In one or more embodiments, the reflective p-contact electrode (p-mirror) 218 includes one or more of aluminum (Al), platinum (Pt), silver (Ag). In other embodiments, the reflective p-contact electrode (p-mirror) 218 may include a bilayer of a reflective material (i.e., one or more of aluminum (Al), platinum (Pt), silver (Ag), etc.) and indium-tin oxide (ITO), and the ITO is part of the layer in direct contact with the second p-type layer 208b.

[0076] In one or more embodiments, the reflective p-contact electrode (p-mirror) 218 is then bonded to the backplane wafer 220. This wafer may be pre-coated with a similar metal to facilitate wafer bonding. In one or more embodiments, the backplane wafer 220 has vias 222 and 224 between the bonding surface and the circuits on or in the opposite side of the backplane wafer 220.

[0077] Still referring to FIG. 10, in one or more embodiments, the first n-type layer 204a and the second n-type layer 204b are etched, for example, by dry etching, to form openings for the electrical contacts 214, separate the pixels, and access the via 224 to the backplane terminal B. In one or more embodiments, there are a total of two etching levels 252 and 254, which is a number that is easier to manage than a conventional RGB μLED array.

[0078] In one or more embodiments, the dielectric layer 212 is conformally deposited over the entire wafer 250. In one or more embodiments, the dielectric layer 212 includes, but is not limited to, oxides such as silicon oxide (SiO2), aluminum oxide (Al2O3), nitrides such as silicon nitride (Si3N4). In one or more embodiments, the dielectric layer 212 includes silicon nitride (Si3N4), silicon oxide (SiO2), or a multi-layer of silicon dioxide (SiO2) and silicon nitride (Si3N4). In some embodiments, the composition of the dielectric layer 212 is non-stoichiometric with respect to the ideal molecular formula. For example, in some embodiments, but not limited to, the dielectric layer 212 includes oxides (such as silicon oxide, aluminum oxide), nitrides (such as silicon nitride (SiN)), oxynitrides (such as silicon oxynitride (SiOC)) and oxynitrocarbides (such as silicon oxynitrocarbide (SiNCO)).

[0079] In one or more embodiments, the dielectric layer 212 is removed from the electrical contact points using dry etching. An ohmic contact metal 214 is deposited and formed within the dielectric opening. Each of the ohmic contact metals 214 may be the same metal with respect to the n-type layers 204a, 204b, respectively. The ohmic contact metal 214 may include any suitable metal known to those skilled in the art. In one or more embodiments, the ohmic contact metal 214 includes aluminum (Al).

[0080] Referring further to FIG. 10, a thick, partially conformal metal layer 216 is deposited over most of the mesa region. A gap 232 is left traversing the center of the mesa, enabling light to be emitted externally and electrically insulating terminal B224 from ground. The partially conformal metal layer 216 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the partially conformal metal layer 116 has high reflectivity and stability. In one or more embodiments, the partially conformal metal layer 216 comprises aluminum (Al) or platinum (Pt). The partially conformal metal layer 216 connects the second n-type layer 204b to the backplane terminal B via via 224. Layer 216 may be composed of a stack of multiple different metal thin films, for example, a first metal such as Al or silver (Ag) having high reflectivity characteristics and a second metal having better chemical stability such as titanium (Ti), chromium (Cr), tungsten (W), gold (Au) or Pt. The partially conformal metal layer 216 connects the second n-type layer 204b to the backplane terminal B via via 224.

[0081] In other non-shown embodiments, different embodiments of Variant B can be formed. This configuration has a red color active region that operates with a fixed current supplied by terminal A and a green / blue voltage-controlled color switching active region connected to terminal B.

[0082] Variant A100 of FIGS. 5 and 6 is more complex compared to Variant B200 of FIGS. 9 and 10, but enables higher system efficiency. In one or more embodiments, the green color active region (Variant A) designed to emit green at a higher current is optimized to obtain a higher internal quantum efficiency than the red color active region that switches to green emission at a high bias voltage. In an InGaN red active region, the quantum efficiency tends to peak at a very low current density. A similar argument applies to the relative IQE of the green / blue switching active region with respect to an active region specially designed to emit blue at a high current density.

[0083] Visualization systems such as virtual reality systems and augmented reality systems are becoming increasingly common in fields such as entertainment, education, healthcare, and business.

[0084] In a virtual reality system, the display can provide the user with a view of a scene such as a three-dimensional scene. The user can move within the scene by repositioning the user's head or by walking. The virtual reality system can detect the user's movement and change the view of the scene to match that movement. For example, when the user rotates the user's head, the system can present a view of the scene in which the viewing direction changes to match the user's line of sight. In this way, a virtual reality system can simulate the user's presence in a three-dimensional scene. Additionally, a virtual reality system can receive tactile sensing input from a wearable position sensor or the like and provide tactile feedback to the user as needed.

[0085] In an augmented reality system, the display can incorporate elements from the user's surroundings into the view of the scene. For example, an augmented reality system can add text captions and / or visual elements to the view of the user's surroundings. For example, a retailer can use an augmented reality system to show the user how furniture pieces would look in a room of the user's house by incorporating the visual of the furniture piece onto a captured image of the user's surroundings. As the user moves around the user's room, the visualization takes the user's movement into account and changes the visualization of the furniture in a way that matches the movement. For example, an augmented reality system can place a virtual chair within the room. The user can stand in front of the virtual chair position and view the front side of the chair. The user can move into the room to the area behind the virtual chair position to view the back side of the chair. In this way, an augmented reality system can add elements to the dynamic view of the user's surroundings.

[0086] FIG. 11 shows a block diagram of an example of a visualization system 10 using a μLED array of one or more embodiments. The visualization system 10 can include a wearable housing 12 such as a headset or goggles. The housing 12 can mechanically support and house the elements shown below. In some examples, one or more of the elements shown below can be included in one or more additional housings, which are separated from the wearable housing 12 and can be coupled to the wearable housing 12 via a wireless connection and / or a wired connection. For example, a separate housing can reduce the weight of the wearable goggles by housing a battery, a wireless device, and other elements, etc. The housing 12 includes one or more batteries 14 and can supply power to any or all of the elements shown below. The housing 12 has a circuit and can be electrically coupled to an external power source such as a wall outlet to recharge the battery 14. The housing 12 includes one or more wireless devices 16 and can wirelessly communicate with a server or network via a suitable protocol such as WiFi (registered trademark).

[0087] The visualization system 10 can include one or more sensors 18 such as an optical sensor, an audio sensor, a tactile sensor, a thermal sensor, a gyro sensor, a time-of-flight sensor, a triangulation-based sensor, etc. In some examples, one or more of the sensors can sense the position, arrangement, and / or orientation of the user. In some examples, one or more of the sensors 18 can generate a sensor signal in response to the sensed arrangement, position, and / or orientation. The sensor signal can have sensor data corresponding to the sensed arrangement, position, and / or orientation. For example, the sensor data can include a surrounding depth map. In some examples such as an augmented reality system, one or more of the sensors 18 can capture a real-time video image of the surroundings near the user.

[0088] The visualization system 10 can include one or more video generation processors 20. The one or more video generation processors 20 can receive scene data representing a three-dimensional scene, such as a set of position coordinates of objects in a scene or a depth map of the scene, from a server and / or a storage medium. The one or more video generation processors 20 can receive one or more sensor signals from one or more sensors 18. In response to the scene data representing the surroundings and at least one sensor signal representing the position and / or orientation of the user relative to the surroundings, the one or more video generation processors 20 can generate at least one video signal corresponding to a view of the scene. In some examples, the one or more video generation processors 20 can generate two video signals, one for each eye of the user, which respectively represent views of the scene from the viewpoints of the user's left and right eyes. In some examples, the one or more video generation processors 20 can generate three or more video signals and combine these video signals to provide one video signal for both eyes, two video signals for both eyes, or other combinations.

[0089] The visualization system 10 has one or more light sources 22 and can provide light to the display of the visualization system 10. Suitable light sources 22 can include light-emitting diodes, monolithic light-emitting diodes, multiple light-emitting diodes, arrays of light-emitting diodes, arrays of light-emitting diodes arranged on a common substrate, segmented light-emitting diodes having light-emitting diode elements arranged on a single substrate and individually addressable and controllable (and / or controllable in groups and / or subsets), arrays of micro light-emitting diodes (micro LEDs), etc.

[0090] The light-emitting diode may be a white light-emitting diode. For example, the white light-emitting diode can emit excitation light such as blue light or violet light. The white light-emitting diode includes one or more phosphors, which can absorb some or all of the excitation light and, in response, emit fluorescence such as yellow light having a wavelength longer than that of the excitation light.

[0091] One or more light sources 22 can include light generating elements having different colors or wavelengths. For example, the light source can include a red light emitting diode capable of emitting red light, a green light emitting diode capable of emitting green light, and a blue light emitting diode capable of emitting blue light. The red, green, and blue lights are combined in a specific ratio to produce any suitable color visually perceptible in the visible portion of the electromagnetic spectrum.

[0092] The visualization system 10 can include one or more modulators 24. The modulator 24 can be used in at least one of two configurations.

[0093] In a first configuration, the modulator 24 can include a circuit that can directly modulate the light source 22. For example, the light source 22 has an array of light emitting diodes, and the modulator 24 can directly modulate the power, voltage, and / or current induced in each light emitting diode in the array to form modulated light. The modulation can be implemented in an analog and / or digital manner. In some examples, the light source 22 has an array of red light emitting diodes, an array of green light emitting diodes, and an array of blue light emitting diodes, and the modulator 24 can directly modulate the red light emitting diode, the green light emitting diode, and the blue light emitting diode to form modulated light and generate a specified image.

[0094] In the second configuration, the modulator 24 can have a modulation panel such as a liquid crystal panel. The light source 22 can generate uniform illumination, or substantially uniform illumination, that irradiates the modulation panel. The modulation panel can include pixels. Each pixel can selectively attenuate respective portions of the modulation panel area in response to an electrical modulation signal to form modulated light. In some examples, the modulator 24 can include a plurality of modulation panels that can modulate light of different colors. For example, the modulator 24 can include a red modulation panel that can attenuate red light from a red light source such as a red light emitting diode, a green modulation panel that can attenuate green light from a green light source such as a green light emitting diode, and a blue modulation panel that can attenuate blue light from a blue light source such as a blue light emitting diode.

[0095] In some examples of the second configuration, the modulator 24 can receive uniform white light or substantially uniform white light from a white light source such as a white light emitting diode. The modulation panel can include a wavelength selection filter on each pixel of the modulation panel. The panel pixels can be arranged in groups (e.g., three or four groups), and each group can form a pixel of a color image. For example, each group can include panel pixels having a red color filter, panel pixels having a green color filter, and panel pixels having a blue color filter. Other suitable configurations can also be used.

[0096] The visualization system 10 has one or more modulation processors 26, which can receive a video signal from one or more video generation processors 20, etc., and can generate an electrical modulation signal in response thereto. In the case of a configuration where the modulator 24 directly modulates the light source 22, the electrical modulation signal can drive the light source 24. In the case of a configuration where the modulator 24 includes a modulation panel, the electrical modulation signal can drive the modulation panel.

[0097] The visualization system 10 can include one or more beam combiners 28 (also known as beam splitters 28), which can combine light beams of different colors to form a single multi-color beam. In a configuration where the light source 22 can have a plurality of light-emitting diodes of different colors, the visualization system 10 has one or more wavelength-sensitive (e.g., dichroic) beam splitters 28 that can combine light of different colors to form a single multi-color beam.

[0098] In at least one of two configurations, the visualization system 10 can direct the modulated light to the observer's eyes. In the first configuration, the visualization system 10 functions as a projector and has a suitable projection optical system 30 that can project the modulated light onto one or more screens 32. The screen 32 can be placed at a suitable distance from the user's eyes. The visualization system 10 can optionally have one or more lenses 34 and place a virtual image of the screen 32 at a suitable distance from the eyes, such as a short focal distance like 500 mm, 750 mm, or another suitable distance. In some examples, the visualization system 10 has a single screen 32, and the modulated light can be directed towards both of the user's eyes. In some examples, the visualization system 10 has two screens 32, and the modulated light from each screen 32 can be directed towards each of the user's eyes. In some examples, the visualization system 10 can have three or more screens 32. In the second configuration, the visualization system 10 can directly direct the modulated light to one or both of the observer's eyes. For example, the projection optical system 30 can form an image on the retina of the user's eye or on the retina of each of the user's two eyes.

[0099] In some configurations of the augmented reality system, the visualization system 10 has a display that is at least partially transparent, and the user can see the user's surroundings through the display. In such a configuration, the augmented reality system can generate modulated light corresponding to the augmentation of the surroundings rather than the surroundings themselves. For example, in the case of a retailer displaying a chair, the augmented reality system can direct modulated light that corresponds to the chair but not to other parts of the room towards the screen or the user's eyes.

[0100] (Embodiment) Various embodiments are listed below. It is understood that the embodiments listed below can be combined with all aspects and other embodiments in accordance with the scope of the present invention.

[0101] Embodiment (a) A light-emitting diode (LED) array, having a first light-emitting stack on a second light-emitting stack on a reflective p-contact electrode joined to a backplane, wherein the first light-emitting stack has a first electrical contact on a first n-type layer, the first n-type layer is on a first tunnel junction, the first tunnel junction is on a first p-type layer, and the first p-type layer is on a first color active region, the second light-emitting stack has a second electrical contact on a second n-type layer in contact with the first color active region and on a second color active region, and the second color active region is on a second p-type layer, the LED array.

[0102] Embodiment (b) Furthermore, the LED array according to embodiment (a), having a dielectric layer surrounding the first light-emitting stack and the second light-emitting stack.

[0103] Embodiment (c) Furthermore, the LED array according to embodiment (a) or (b), having a reflective metal layer on the dielectric layer.

[0104] Embodiment (d) The color emitted by one of the first light emitting stack or the second light emitting stack is controlled by changing the voltage at one of the first electrical contact or the second electrical contact, the LED array according to any one of Embodiments (a) to (c).

[0105] Embodiment (e) Furthermore, the LED array according to any one of Embodiments (a) to (d), which has an electrode grid.

[0106] Embodiment (f) The first n-type layer and the second n-type layer each independently contain one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), etc., the LED array according to any one of Embodiments (a) to (e).

[0107] Embodiment (g) The first n-type layer and the second n-type layer contain gallium nitride (GaN), the LED array according to Embodiment (f).

[0108] Embodiment (h) The first electrical contact and the second electrical contact contain aluminum, the LED array according to any one of Embodiments (a) to (g).

[0109] Embodiment (i) The reflective p-contact electrode contains one or more of aluminum (Al), platinum (Pt), silver (Ag), the LED array according to any one of Embodiments (a) to (h).

[0110] Embodiment (j) The LED array according to any one of embodiments (a) to (i), wherein the reflective p-contact electrode has a bilayer including indium tin oxide (ITO) and one or more of aluminum (Al), platinum (Pt), and silver (Ag).

[0111] Embodiment (k) A method of manufacturing an LED array, comprising: sequentially forming two p-n junctions on an epitaxial wafer to form an epitaxial stack, the epitaxial stack having at least one n-type layer and at least one p-type layer, and having a color active region embedded between the at least one n-type layer and the at least one p-type layer; depositing a reflective p-contact electrode on the epitaxial stack; bonding the reflective p-contact electrode to a backplane wafer; dry etching the epitaxial stack to access the at least one n-type layer and form an electrical contact and a mesa; conformally depositing a dielectric layer on the mesa; removing a part of the dielectric layer to form a dielectric opening on the upper surface of the mesa, the dielectric opening exposing the at least one n-type layer; depositing an ohmic contact in the dielectric opening to form an electrical contact; depositing a conformal metal layer on a part of the upper portion of the mesa to form a gap crossing the center of the mesa to enable light to exit to the outside; depositing an electrode grid over the upper portion of the LED array; A method having the above steps.

[0112] Embodiment (l) The method according to embodiment (k), further comprising annealing the epitaxial stack before the step of depositing the reflective p-contact electrode.

[0113] Embodiment (m) The epitaxial stack is a first light emitting stack having a first n-type layer, the first n-type layer being on a first tunnel junction, the first tunnel junction being on a first p-type layer, the first p-type layer being on a first color active region, a first light emitting stack; and a second light emitting stack in contact with the first color active region and having a second n-type layer on a second color active region, the second color active region being on a second p-type layer, a second light emitting stack; The method according to any one of Embodiments (k) to (l), comprising

[0114] Embodiment (n) When the first light emitting stack and the second light emitting stack are driven in parallel, the collective color of the light emission is controlled by a voltage, the method according to any one of Embodiments (k) to (m).

[0115] Embodiment (o) The first n-type layer and the second n-type layer each independently include one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), the method according to any one of Embodiments (k) to (n).

[0116] Embodiment (p) The first n-type layer and the second n-type layer include gallium nitride (GaN), the method according to any one of Embodiments (k) to (o).

[0117] Embodiment (q) a The electrical contact includes aluminum, the method according to any one of Embodiments (k) to (p).

[0118] Embodiment (r) The reflective p-contact electrode contains one or more of aluminum (Al), platinum (Pt), and silver (Ag), and is the method according to any one of Embodiments (k) to (q).

[0119] Embodiment (s) The reflective p-contact electrode has a bilayer containing indium tin oxide (ITO) and one or more of aluminum (Al), platinum (Pt), and silver (Ag), and is the method according to any one of Embodiments (k) to (r).

[0120] Embodiment (t) Battery Wireless device Sensor Video generation processing A light source including the LED array according to any one of Embodiments (a) to (j) Modulator Modulation processor Beam combiner Projection optical system Screen, and Lens And has a visualization system

[0121] In the context of the materials and methods discussed in this application (in particular, in the context of the claims), the use of "a", "an", "the", and similar terms should be construed to cover both the singular and the plural, unless otherwise indicated or clearly contradicted by the context. The recitation of a range of values in this application is merely intended to serve as a shorthand way of referring individually to each separate value within that range, and each separate value is incorporated into this application as if it were individually recited herein. All methods described in this application can be performed in any suitable order, unless otherwise indicated or clearly contradicted by the context. The use of any and all examples, or exemplary terms (e.g., "such as") provided in this application is merely intended to better illustrate the materials and methods and does not otherwise purport to limit the scope. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the disclosed materials and methods.

[0122] Throughout this application, references to terms such as "first", "second", "third", etc. are used to describe various elements, and these elements are not limited by these terms. These terms are used to distinguish one element from another.

[0123] Throughout this application, the expressions that a layer, region, or substrate is "on" or "extends on" another element mean that it is directly on or extends directly on another element, or that intervening elements may be present. When an element is referred to as being "directly on" or "extending directly on" another element, intervening elements may not be present. Further, when an element is referred to as being "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element and / or may be connected or coupled to the other element via one or more intervening elements. When an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements between the element and the other element. It is understood that these terms are intended to encompass different orientations of the elements in addition to any orientation shown in the drawings.

[0124] Relative terms such as "lower", "upper", "above", "below", "horizontal", or "vertical" may be used to describe the relationship between one element, layer, or region and another element, layer, or region as shown in the drawings. It is understood that these terms are intended to encompass different orientations of the device in addition to the orientation shown in the drawings.

[0125] Throughout this application, the expressions "one embodiment", "an embodiment", "one or more embodiments", or "embodiments" mean that the particular features, structures, materials, or characteristics described in connection with the embodiment are included in at least one embodiment of the present disclosure. Accordingly, the phrases such as "in one or more embodiments", "in a particular embodiment", "in one embodiment", or "in an embodiment" that appear in various places throughout this application do not necessarily represent the same embodiment of the present disclosure. In one or more embodiments, the particular features, structures, materials, or characteristics are combined in any suitable manner.

[0126] The disclosure of the present application has been described with reference to specific embodiments, but it is understood that these embodiments are merely examples of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatuses of the present disclosure without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure is intended to cover modifications and variations that are within the scope of the appended claims and their equivalents.

Claims

1. A light-emitting diode (LED) array, comprising: a first light-emitting stack over a second light-emitting stack over a reflective p-contact electrode bonded to a backplane, wherein the first light-emitting stack has a first electrical contact over a first n-type layer, the first n-type layer is over a first tunnel junction, the first tunnel junction is over a first p-type layer, and the first p-type layer is over a first color active region, the second light-emitting stack has a second electrical contact over a second n-type layer in contact with the first color active region and over a second color active region, and the second color active region is over a second p-type layer, the LED array.

2. The LED array of claim 1, further comprising a dielectric layer surrounding the first light-emitting stack and the second light-emitting stack.

3. The LED array of claim 2, further comprising a reflective metal layer over the dielectric layer.

4. The color emitted by one of the first light-emitting stack or the second light-emitting stack is controlled by changing a voltage at one of the first electrical contact or the second electrical contact, the LED array of claim 1.

5. The LED array of claim 1, further comprising an electrode grid.

6. The first n-type layer and the second n-type layer independently comprise one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), etc., the LED array of claim 1.

7. The LED array of claim 6, wherein the first n-type layer and the second n-type layer comprise gallium nitride (GaN).

8. The first electrical contact and the second electrical contact comprise aluminum, the LED array of claim 1.

9. The reflective p-contact electrode comprises one or more of aluminum (Al), platinum (Pt), silver (Ag), the LED array of claim 1.

10. The LED array according to claim 1, wherein the reflective p-contact electrode has a bilayer including indium tin oxide (ITO) and one or more of aluminum (Al), platinum (Pt), and silver (Ag).

11. A method of manufacturing an LED array, comprising: sequentially forming two p-n junctions on an epitaxial wafer to form an epitaxial stack, the epitaxial stack having at least one n-type layer and at least one p-type layer, and having a color active region embedded between the at least one n-type layer and the at least one p-type layer; depositing a reflective p-contact electrode on the epitaxial stack; bonding the reflective p-contact electrode to a backplane wafer; dry etching the epitaxial stack to access the at least one n-type layer and form an electrical contact and a mesa; conformally depositing a dielectric layer on the mesa; removing a portion of the dielectric layer to form a dielectric opening on the upper surface of the mesa, the dielectric opening exposing the at least one n-type layer; depositing an ohmic contact in the dielectric opening to form an electrical contact; depositing a conformal metal layer on a portion of the upper part of the mesa to form a gap crossing the center of the mesa to enable light to exit to the outside; depositing an electrode grid over the LED array; A method having the above steps.

12. The method according to claim 11, further comprising annealing the epitaxial stack before the step of depositing the reflective p-contact electrode.

13. The epitaxial stack includes: a first light-emitting stack having a first n-type layer, the first n-type layer being on a first tunnel junction, the first tunnel junction being on a first p-type layer, and the first p-type layer being on a first color active region; a second light-emitting stack in contact with the first color active region and having a second n-type layer on a second color active region, the second color active region being on a second p-type layer; The method according to claim 11, having the above structures.

14. When the first light-emitting stack and the second light-emitting stack are driven in parallel, The method according to claim 13, wherein the collective color of the light emission is controlled by a voltage.

15. The method according to claim 13, wherein the first n-type layer and the second n-type layer independently include one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), and indium aluminum nitride (InAlN).

16. The method according to claim 15, wherein the first n-type layer and the second n-type layer include gallium nitride (GaN).

17. The method according to claim 11, wherein the electrical contact includes aluminum.

18. The method according to claim 11, wherein the reflective p-contact electrode includes one or more of aluminum (Al), platinum (Pt), and silver (Ag).

19. The method according to claim 11, wherein the reflective p-contact electrode has a bilayer including indium tin oxide (ITO) and one or more of aluminum (Al), platinum (Pt), and silver (Ag).

20. Battery, Wireless device, Sensor, Video generation process, A light source including the LED array according to any one of claims 1 to 10, Modulator, Modulation processor, Beam combiner, Projection optical system, Screen, and Lens, A visualization system having.

Images