Voltage Converter and Method for Converting Voltage

Abstract

In the present disclosure, a converter that generates a multiphase output voltage is described using a three-level converter having an upper switch pair (upper and central lower) and a lower switch pair (lower and central upper) arranged between positive and negative DC input voltages and an intermediate DC voltage. The controller uses PWM over a plurality of PWM periods to control the upper and lower switch pairs to generate a multiphase AC output voltage. In each PWM period, the controller controls the upper or lower pair of each switch to simultaneously apply a positive or negative offset voltage to each phase output. Here, the positive and negative offset voltages represent the average peak-to-peak voltage of the phase output voltage offset positively or negatively, respectively, from the central DC voltage. Advantageously, when the central DC voltage is not the same as the average phase voltage, there is a possibility of reducing conduction losses.

Description

Technical Field

[0001] The present invention relates to a converter and a method for generating a multiphase voltage for supplying power to an electromechanical device, for example, for supplying power to a motor or a generator.

Background Art

[0002] There is a general movement away from internal combustion engines towards more electrical and fully electric vehicles. The automotive industry has built its reputation based on reliability and technological innovation, and the rapid movement towards more electrical vehicles has led to a demand to maximize many aspects of the electrical power supply and electrical drive. Power supplies, inverters / rectifiers / converters, switching circuits, control devices, and passive components are important components in an electrical drive, and their reliability is of utmost importance. Minimizing the cost of ownership while maximizing reliability and efficiency over all parts of the transient / model drive cycle is driving innovation.

[0003] A two-level inverter creates an alternating current (AC) output waveform by using pulse width modulation (PWM) applied to semiconductor switches between two voltage levels. For each switching period, a phase spends a time period connected to the +DC voltage and a time connected to the -DC voltage. The ratio of these times determines the voltage output in the AC waveform.

[0004] Two-level inverters have good efficiency when operating under heavy loads, i.e., a significant portion of the available voltage range, but they are inefficient when operating at light loads where switching losses are dominant. Switching can also cause disturbances (ripple) on the DC supply voltage that can affect other devices, and to counter this, a DC capacitance rated for the full voltage range is often used to smooth out the ripple disturbances induced by the switches and provide a local reservoir of energy.

[0005] Three-level inverters are so called because they operate switches using PWM between three voltage levels. The upper and lower voltages are the same as in the case of two-level operation, and the third supply point is the mid / centre voltage between these two boundaries.

[0006] The intermediate voltage level is supplied by a capacitor voltage divider, and since each capacitor only sees a fraction of the full range voltage of a two-level inverter, the capacitors can be of lower specification and smaller cost.

[0007] Three-level inverters can be used over the whole voltage range, but it is beneficial to operate at low load to reduce the centre voltage switch specification and the series capacitor specification. Three-level inverters are usually neutral point clamped (NPC) to protect components of lower specification.

[0008] In the inventors' previous application (GB2203651.1), a converter having a three-level topology was proposed in which the centre level switches have lower voltage ratings and current ratings compared to the upper and lower switches. The result of such an arrangement is that the centre level switches in a three-level topology will have different on-state resistances (since they have different, lower ratings), and thus the conduction losses between the upper or lower switches and the centre level will be unbalanced.

[0009] When the desired phase output voltage is reduced in such a three-level topology, the centre level switches spend more time being on. Thus, the conduction losses increase as the output voltage (and modulation index) is reduced, leading to a decrease in the efficiency of the system.

[0010] Thus, there is a recognized need for a converter having the benefits of three-level converter techniques for use over the whole operating range of a three-level converter.

Prior Art Documents

Patent Document

[0011]

Patent Document 1

Summary of the Invention

[0012] Accordingly, the present invention provides a method for generating a polyphase output voltage and a converter for generating a polyphase output voltage for driving an electromechanical machine in accordance with the independent claims appended hereto.

[0013] Further advantageous embodiments are also provided in accordance with the dependent claims also appended hereto.

[0014] A converter for generating a polyphase voltage for powering an electrical machine, comprising an input for receiving a positive DC input voltage and a negative DC input voltage, a plurality of AC outputs, each for outputting a polyphase AC output voltage for driving the electrical machine, and for each phase, a plurality of switches arranged in a T-configuration between the DC input and the respective AC phase output, the T-configuration comprising an upper switch coupled between the positive DC input and the respective AC phase output, a lower switch coupled between the respective AC phase output and the negative DC input, and a central upper switch and a central lower switch coupled between the AC phase output and an intermediate DC voltage, the switches being arranged in respective upper and lower pairs of switches, the upper pair comprising the upper switch and the central lower switch, the lower pair of switches comprising the lower switch and the central upper switch, the intermediate DC voltage being the voltage between the positive DC input voltage and the negative DC input voltage, a plurality of switches, an input for receiving data representing the required phase voltage demand for the electrical machine, and a controller for controlling each of the switches using pulse width modulation (PWM) over a plurality of PWM periods to generate a polyphase AC output voltage for the electrical machine, the controller being configured to control, for each PWM period, each respective upper or lower pair of switches to simultaneously apply either a positive offset voltage or a negative offset voltage to each of the phase outputs, the positive offset voltage and the negative offset voltage each representing the average peak-to-peak voltage for a phase output voltage offset positively or negatively from the intermediate DC voltage, is described for the converter.

[0015] Advantageously, the conduction losses can be reduced when the intermediate DC voltage is not the same as the average phase output voltage.

[0016] Controlling each upper pair or lower pair of switches to apply a positive offset voltage or a negative offset voltage, respectively, may include determining a positive offset voltage and a negative offset voltage for application to each of the phase output voltages based on one or more of an offset buffer voltage, an output phase voltage demand, a negative DC input voltage, a positive DC input voltage, and an output load power factor, wherein the offset buffer voltage represents the minimum voltage difference between the peak phase output voltage and each of the positive DC input voltage and the negative DC input voltage.

[0017] Controlling each upper pair or lower pair of switches to apply a positive offset voltage or a negative offset voltage, respectively, may include determining a positive intermediate target voltage and a negative intermediate target voltage based on one or more of a positive offset voltage or a negative offset voltage, a negative DC input voltage, a positive DC input voltage, a phase voltage demand, an intermediate target buffer voltage, and a frequency of an intermediate DC voltage, wherein the positive intermediate target voltage and the negative intermediate target voltage represent a target voltage deviation of the intermediate DC voltage.

[0018] In either case, the controller may apply a positive offset voltage or a negative offset voltage when the difference between each positive offset voltage or negative offset voltage and the intermediate DC voltage is greater than a threshold voltage.

[0019] The controller can determine whether to apply a positive offset voltage or a negative offset voltage during the first PWM period based on the voltage difference between the positive offset voltage and the intermediate DC voltage and the voltage difference between the negative offset voltage and the intermediate DC voltage. When the controller applies a positive offset voltage or a negative offset voltage during the first PWM period, the controller can be configured to apply the positive offset voltage when the difference between the positive offset voltage and the intermediate DC voltage is greater than the difference between the negative offset voltage and the intermediate DC voltage, and the controller can be configured to apply the negative offset voltage when the difference between the negative offset voltage and the intermediate DC voltage is greater than the difference between the positive offset voltage and the intermediate DC voltage.

[0020] During subsequent PWM periods, when the controller controls the upper pair of switches to apply a positive offset voltage and when the intermediate DC voltage approaches the positive intermediate target voltage, the controller can be configured to apply a negative offset voltage to the phase output voltage by controlling the lower pair of switches.

[0021] During subsequent PWM periods, when the controller controls the lower pair of switches to apply a negative offset voltage and when the intermediate DC voltage approaches the negative intermediate target voltage, the controller can be configured to apply a positive offset voltage to the phase output voltage by controlling the upper pair of switches.

[0022] When the controller switches between applying a positive offset voltage and applying a negative offset voltage, the controller can control the upper pair and / or the lower pair of switches to apply a slew to the offset voltage between the positive offset voltage and the negative offset voltage.

[0023] The intermediate DC voltage can be provided by a capacitor voltage divider arranged between the positive DC input and the negative DC input. Alternatively, the intermediate DC voltage is provided by a second DC source.

[0024] Also, a method for generating a polyphase voltage for powering an electromechanical machine, the method comprising: receiving a positive DC input voltage and a negative DC input voltage; receiving data representing the required phase voltage demand for the electromechanical machine; controlling a plurality of switches by using pulse width modulation (PWM) over a plurality of PWM periods to generate a polyphase AC output voltage for the electromechanical machine, wherein the plurality of switches are arranged in a plurality of groups, one for each phase, and for each phase, the group of switches is arranged in a T-configuration between the DC input and the respective AC phase output, the T-configuration comprising an upper switch coupled between the positive DC input and the respective AC phase output, a lower switch coupled between the respective AC phase output and the negative DC input, and a center upper switch and a center lower switch coupled between the AC phase output and an intermediate DC voltage, the switches being arranged in respective upper and lower pairs of switches, the upper pair comprising the upper switch and the center lower switch, the lower pair of switches comprising the lower switch and the center upper switch, and the intermediate DC voltage being the voltage between the positive DC input voltage and the negative DC input voltage; and outputting the polyphase AC output voltage to drive the electromechanical machine, wherein for each PWM period, the step of controlling the plurality of switches comprises controlling each respective upper or lower pair of switches to simultaneously apply either a positive offset voltage or a negative offset voltage to each of the phase outputs, the positive offset voltage and the negative offset voltage each representing an average peak-to-peak voltage for a phase output voltage offset positively or negatively from the intermediate DC voltage, is described.

[0025] Advantageously, conduction losses can be reduced when the intermediate DC voltage is not the same as the average phase output voltage.

[0026] The step of controlling each upper pair or lower pair of switches to apply a positive offset voltage or a negative offset voltage, respectively, may include determining a positive offset voltage and a negative offset voltage for each of the phase output voltages based on one or more of an offset buffer voltage, an output phase voltage demand, a negative DC input voltage, a positive DC input voltage, and an output load power factor, wherein the offset buffer voltage represents the minimum voltage difference between the peak phase output voltage and the respective positive and negative DC input voltages.

[0027] The step of controlling each upper pair or lower pair of switches to apply a positive offset voltage or a negative offset voltage, respectively, may include determining a positive intermediate target voltage and a negative intermediate target voltage based on one or more of a positive offset voltage or a negative offset voltage, a negative DC input voltage, a positive DC input voltage, a phase voltage demand, an intermediate target buffer voltage, and a frequency of an intermediate DC voltage, wherein the positive intermediate target voltage and the negative intermediate target voltage represent a target voltage deviation of the intermediate DC voltage.

[0028] The positive offset voltage or the negative offset voltage may be applied when the difference between the respective positive offset voltage or negative offset voltage and the intermediate DC voltage is greater than a threshold voltage.

[0029] Which of the positive offset voltage or the negative offset voltage should be applied during the first PWM period may be based on the voltage difference between the positive offset voltage and the intermediate DC voltage and the voltage difference between the negative offset voltage and the intermediate DC voltage.

[0030] When a positive offset voltage or a negative offset voltage is applied during the first PWM period, the positive offset voltage can be applied when the difference between the positive offset voltage and the intermediate DC voltage is greater than the difference between the negative offset voltage and the intermediate DC voltage, and the negative offset voltage can be applied when the difference between the negative offset voltage and the intermediate DC voltage is greater than the difference between the positive offset voltage and the intermediate DC voltage.

[0031] During subsequent PWM periods, when the upper pair of switches is controlled to apply a positive offset voltage and the intermediate DC voltage approaches the positive intermediate target voltage, the negative offset voltage can be applied to the phase output voltage by controlling the lower pair of switches.

[0032] During subsequent PWM periods, when the lower pair of switches is controlled to apply a negative offset voltage and the intermediate DC voltage approaches the negative intermediate target voltage, the positive offset voltage can be applied to the phase output voltage by controlling the upper pair of switches.

[0033] When the upper pair and / or the lower pair of switches switch between applying a positive offset voltage and applying a negative offset voltage, they can be controlled to apply a slew to the offset voltage between the positive offset voltage and the negative offset voltage.

[0034] The intermediate DC voltage can be provided via a capacitor voltage divider arranged between the positive DC input and the negative DC input. Alternatively, the intermediate DC voltage can be provided by a second DC source.

Brief Description of the Drawings

[0035] Next, the present invention will be described by way of example only with reference to the accompanying drawings.

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

[0036] Briefly, a converter for generating a polyphase output voltage is described that uses a three-level converter having an upper pair of switches (upper and middle lower) and a lower pair of switches (lower and middle upper) arranged between a positive DC input voltage, a negative DC input voltage, and an intermediate DC voltage. A controller uses PWM over a plurality of PWM periods to control the upper and lower pairs of switches to generate a polyphase AC output voltage. For each PWM period, the controller controls each upper or lower pair of switches to simultaneously apply either a positive offset voltage or a negative offset voltage, respectively, to each of the phase outputs, where the positive and negative offset voltages each represent the average peak-to-peak voltage for a phase output voltage offset positively or negatively from the intermediate DC voltage. Advantageously, conduction losses can be reduced when the intermediate DC voltage is not the same as the average phase output voltage.

[0037] As some simple background, power converters are generally known. One example can be found in Patent Document 1, from which FIG. 1 is obtained, showing a three-phase two-level power inverter 100 for converting a DC power supply 101 into an AC output 103 that can then be connected to a load (not shown). The inverter comprises three separate phases 200, 300, 400 (also called phase U, V, W respectively). Each phase includes two switches in series, namely 200a, 200b in phase 200 / U, 300a, 300b in phase 300 / V, and 400a, 400b in phase 400 / W. Switches 200a, 300a and 400a are connected to the positive rail 105 (sometimes called the "upper" switches), and switches 200b, 300b and 400b are connected to the negative rail 107 (sometimes called the "lower" switches). In FIG. 1, each switch can be an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and for each IGBT or MOSFET, an associated anti-parallel diode can be used (not shown). However, any switch with high-speed switching capabilities may be used. A control system (not shown) (such as a processor) often uses pulse width modulation (PWM) or a variant of PWM to control the switching of switches 200a, 200b, 300a, 300b, 400a, 400b to control the AC output of inverter 100. The power inverter also includes a DC bus capacitor 102 that provides a more stable DC voltage, which limits the fluctuations when the inverter demands sporadic large currents. This inverter is a so-called two-level inverter since each of phases 200, 300, and 400 switches between two DC levels. In this case, it is the DC voltage and ground, but it can also be a positive DC level and a negative DC level.

[0038] The sinusoidal output current can be created at the AC output 103 by the combination of the switching states of six switches using a PWM switching pattern. However, the inverter 100 must be controlled so that two switches in the same phase are never switched on at the same time so that the DC supply 101 is not short-circuited. Therefore, if 200a is on, 200b must be off, and vice versa; if 300a is on, 300b must be off, and vice versa; if 400a is on, 400b must be off, and vice versa.

[0039] Figure 2 shows the phase voltage versus the output voltage angle (for a 250V DC bus and 200V peak demand) with symmetric switching (with respect to the 0V line shown in Figure 1, which is half of the dc bus). Figure 3 shows the resulting line voltage as seen from an electromechanical device, for example, a motor.

[0040] A two-level inverter switches the entire DC bus voltage every PWM period, which creates large switching harmonics and conduction losses become dominant at low loads / currents, which can cause an increase in losses in an electrical load, for example, a motor or a generator.

[0041] A known technique to overcome at least some of the drawbacks of a two-level converter is to use a three-level converter.

[0042] Figure 4 shows an example of a simplified layout of one solution for implementing a three-level converter, in this case a series T-configuration. This figure shows only one of the phases, in this case corresponding to phase U200 in Figure 1. In this arrangement, the upper (Q1) 200a and lower (Q4) 200b are connected between the +DC supply and the -DC supply and provide the phase output 103. The central lower (Q3) 200d and central upper (Q2) 200c are connected between the intermediate DC voltage and the phase output 103. The intermediate DC is a DC voltage at a level between the +DC supply and the -DC supply. In this arrangement, it is generated by a series network of capacitors 102a, 102b, but alternatively it may be provided from an external source. The intermediate DC voltage is not necessarily exactly the midpoint voltage between +DC and -DC, but it may be. The intermediate DC voltage may be common to all phases.

[0043] In the illustrated three-level configuration, the switches function in the upper and lower pairs of switches. The upper pair of switches comprises an upper (Q1) 200a switch and a central lower (Q3) 200d switch, and the lower pair of switches comprises a lower (Q4) 200b switch and a central upper (Q2) 200c switch. The upper pair of switches can be connected to the +DC voltage or the central DC voltage, and the lower pair can be connected to the central DC voltage and the -DC voltage. Again, the switches are controlled by the controller and the switches using a PWM switching pattern to generate the required phase output voltage. The upper pair is used when the output phase voltage level is to exceed the central DC voltage level. The lower pair is used when the output phase voltage level is to fall below the central DC voltage level. (When the central voltage is balanced at half the DC bus voltage) each pair of switches switches only half the DC voltage.

[0044] Figure 5 shows another T-configuration for a single phase. This arrangement is a so-called parallel T three-level converter. The parallel T has two separate central voltage connection paths, each of which must have blocking diodes to avoid uncontrolled reverse conduction.

[0045] Figure 6 shows a simplified multiphase (in this case three-phase) converter in which each phase has a three-level series T-type switch arrangement.

[0046] Switching at half of the DC bus significantly reduces harmonics and losses in the load. Some simulations have shown an approximately 80% reduction in WLTP (Worldwide Harmonised Light Vehicle Test Procedure) losses due to PWM harmonics when a three-level inverter is used instead of a two-level inverter. In a standard saloon car, this is an increase of approximately 5% in the range.

[0047] In a preferred implementation of the three-level converter by the inventors, both the central lower switch and the central upper switch are appropriately rated for the required switched output voltage, which may be different from the ratings of the upper and lower switches.

[0048] The result of this arrangement is that the channel resistances of the upper and lower switches can be much lower than those of the central lower and central upper switches. As an example, in a preferred implementation, MOSFETs are used as power switching devices, and the channel resistances of the upper and lower switches (i.e., the higher-rated switches) can be in the region of 1.4 mΩ, and the channel resistances of the central lower and central upper switches (i.e., the lower-rated switches) can be in the region of 10 mΩ. In the exemplary configurations shown in FIGS. 4 and 6, the central lower and central upper are arranged in series. In the exemplary configuration shown in FIG. 5, blocking diodes are present. In all of these arrangements, the conduction losses increase due to the devices being arranged in series.

[0049] For example, the time-averaged power loss due to conduction in a MOSFET depends on the duty cycle, the square of the current conducted by the MOSFET, and the resistance of the MOSFET channel. Thus, it is already known that having a higher channel resistance in a lower-rated switch will affect the conduction power loss in the switch.

[0050] FIG. 7 shows an exemplary conduction loss graph versus output current for different levels of modulation (lower modulation index = lower output voltage). It can be seen that as the modulation index or degree of modulation decreases (i.e., the output voltage becomes lower), the losses increase significantly.

[0051] This is due in part to the variable duty cycle used in the PWM scheme, and the ratio of the duty cycles between pairs of switches (upper and center lower, and lower and center upper) is varied to achieve the desired output voltage for a particular PWM period. That is, as the phase output approaches the center DC voltage, more time is spent with the appropriate center-level switch on (and thus conducting), and less time is spent with each upper or lower switch on. As the phase output voltage becomes more positive or more negative (i.e., moves away from the center DC level), less time is spent with the center-level switches on (i.e., less time that they are conducting current), and more time is spent with each upper switch (for more positive voltages) or lower switch (for more negative voltages) on.

[0052] When there is more demand for the center - level switch (i.e., when the switching requirements for generating the output voltage require the center - level switch to be on more often than each of the upper - side switches or lower - side switches), one solution for reducing losses in the converter is to introduce a voltage offset to the phase output voltage, which moves the average phase output voltage away from the intermediate voltage towards either the +DC bus or the -DC bus. When the same voltage offset is applied to each of the output - phase voltages, the offset voltages on each phase cancel out in the line - to - line (phase - to - phase) voltage, so the electrical load does not see the offset voltage.

[0053] In summary, adding a voltage offset to each of the phase voltages has the result of moving the phase voltages away from the second DC voltage towards either the +DC bus or the -DC bus. Thus, if the offset voltage applied to the output - phase voltage moves the output - phase voltage towards the +DC bus, the upper - side switch will need to spend more time being on compared to the center - lower - side switch. Similarly, if the offset voltage applied to the output - phase voltage moves the output - phase voltage towards the -DC bus, the lower - side switch will need to spend more time being on compared to the center - upper - side switch.

[0054] The result of this method is a reduction in the conduction losses of the three - level converter, because for a given phase output voltage, the upper - side switch or lower - side switch spends more time being on compared to the center - lower - side switch or center - upper - side switch (respectively) being on. This is the case for various levels of the modulation index (i.e., output - phase voltage). However, this method can affect the intermediate DC voltage level.

[0055] The intermediate DC voltage can be created by a capacitor divider arranged between the +DC bus and the -DC bus. Nominally, the intermediate voltage can be DC / 2 which is approximately in the middle between the +DC bus and the -DC bus, but this is not necessary and the intermediate voltage can be at different levels. In this arrangement, the intermediate DC voltage naturally balances over time at the average phase voltage. Thus, spending more time in the state where the upper switch is on (i.e., having an offset voltage that moves the phase output voltage towards the +DC bus) will result in the intermediate DC voltage gradually drifting over time towards the +offset voltage as more charge is added to the capacitor divider. Similarly, spending more time in the state where the lower switch is on (i.e., having an offset voltage that moves the phase output voltage towards the -DC bus) will result in the intermediate DC voltage gradually drifting over time towards the -offset voltage as the charge from the capacitor divider depletes. As described above, the intermediate DC voltage will move towards the average of the phase voltages. The speed of the drift depends on various factors including, but not limited to, the size of the capacitor and the current load effect.

[0056] Figure 8 shows exemplary time plots of the phase output voltage with and without the introduction of a common offset voltage.

[0057] The figure shows the output phase voltage over several output cycles. In this example, a low voltage phase output (i.e., a low modulation index) is required. First, no common offset is applied, and thus the average phase output voltage remains at the intermediate voltage.

[0058] During the period when no offset is introduced, the lower pair of switches (lower and central upper) are used to generate voltage when the desired phase output voltage needs to be lower than the intermediate voltage, and the upper pair of switches (upper and central lower) are used to generate voltage when the desired phase output voltage is higher than the intermediate DC voltage. Since the desired phase voltage output is very low, more time will be spent with the central lower switch and the central upper switch on, respectively, compared to the upper and lower switches.

[0059] Applying a common offset voltage (here shown as + offset since the offset voltage moves the average phase output voltage away from the intermediate voltage towards the + DC bus) by controlling the upper switch and the central lower switch accordingly causes the phase output voltage to be around the + offset level. Since the phase output voltage is located more positively away from the intermediate DC voltage, the switching pattern required to generate the phase output voltage will require the upper switch to be on for a longer period and the central lower switch to be on for a shorter period when compared to the situation where no offset voltage is applied. Thus, conduction losses are reduced compared to when no offset is applied.

[0060] Generally, conduction losses are reduced when the intermediate voltage is not the same as the average phase voltage (i.e., + offset voltage).

[0061] However, as can be seen in the figure, this has the result that the intermediate voltage drifts more positively towards the average of the phase output voltage (i.e., towards the + offset). This increase depends on the capacitance value that generates the intermediate DC voltage, the electrical load current, and the common offset used.

[0062] To prevent the intermediate voltage from drifting too close to the offset average of the phase output voltage (which would nullify the benefits of this scheme), this scheme can apply a negative DC offset, i.e., a negative offset voltage closer to the -DC bus. In this example, the lower switch and the center upper switch are controlled to apply the negative offset of the -offset, which positions the average phase output voltage at the -offset level. Since the phase output voltage is lower than the intermediate voltage, the switching pattern required to generate the phase output voltage will require the lower switch to be on for a longer period and the center upper switch to be on for a shorter period compared to the situation where no offset voltage is applied. Thus, conduction losses are reduced compared to the situation where no offset is applied.

[0063] Generally, conduction losses are reduced when the intermediate voltage is not the same as the average phase voltage.

[0064] Furthermore, it can be seen that the intermediate voltage then drifts more negatively from the previous value (again, it tries to stabilize at the average of the phase output voltage, which is now at the -offset level). Similarly, to prevent the intermediate voltage from drifting too close to the new average (i.e., -offset) of the phase output voltage and reducing or nullifying the benefits of the switching scheme, this scheme can also, in this case, apply a positive DC offset, i.e., an offset voltage greater than the intermediate DC voltage.

[0065] Preferably, the positive intermediate target value and the negative intermediate target value are each selected to prevent the intermediate DC voltage from reaching the closest peak of the output phase voltage. Take the example where a + offset voltage is applied to drift the intermediate DC voltage more positively towards the + offset voltage. When the intermediate DC voltage reaches the + intermediate target voltage, the switching scheme is changed to apply the - offset as described above, which drifts the intermediate DC voltage more negatively towards the - offset voltage. Again, when the intermediate voltage reaches the - intermediate target voltage, the switching scheme is changed to apply the + offset as described above, and the pattern repeats.

[0066] As can be seen, this alternation between the + offset and the - offset creates a wave that approximates a triangular wave with respect to the intermediate voltage, and the approximate triangular wave of the intermediate DC voltage has a frequency. The frequency depends on capacitance, phase voltage, offset voltage, intermediate target voltage, load current, and phase angle.

[0067] FIG. 9 shows a second exemplary time plot of the phase output voltage with and without the introduction of a common offset. In FIG. 9, the values of the + offset voltage and the - offset voltage are each closer to the + DC rail and the - DC rail, respectively. The + intermediate DC target voltage and the - intermediate DC target voltage may or may not be the same.

[0068] Similar to the example shown in FIG. 8, the scheme in FIG. 9 controls the switching pattern of the upper pair of switches (upper and central lower) when the phase output voltage exceeds the intermediate DC voltage, and controls the switching pattern of the lower pair of switches (lower and central upper) when the phase output voltage is below the intermediate DC voltage, thereby applying the repeating + offset voltage and - offset voltage to the phase output voltage. Similar to the case of FIG. 8, the phase output voltage is relatively low (i.e., low modulation index). Also in this case, the intermediate voltage drifts more positively when the + offset voltage is applied to the phase output, and drifts more negatively when the - offset voltage is applied to the phase output voltage.

[0069] As described above with reference to FIG. 8, the conduction loss in the switch is reduced when the intermediate voltage is not the same as the average phase voltage.

[0070] In FIG. 9, the common offset voltage is pushed towards the DC rail to maximize the peak of the intermediate voltage triangular wave and thus maximize the conduction loss reduction. To prevent the peak or valley of the phase output voltage from reaching the DC rail (thus overmodulating the system), the maximum phase output voltage within the DC rail is selected. This is the headroom or offset buffer voltage, which can vary depending on the required phase output voltage (i.e., modulation index).

[0071] FIG. 10 shows a third exemplary time plot of the phase output voltage with and without the introduction of the common offset. In this example, the phase output voltage is increased (i.e., a larger modulation index) compared to those in FIGS. 8 and 9.

[0072] Similar to the cases of the examples shown in FIGS. 8 and 9, the method in FIG. 10 controls the switching pattern of the upper pair of switches (upper and central lower) when the phase output voltage exceeds the intermediate DC voltage, and controls the switching pattern of the lower pair of switches (lower and central upper) when the phase output voltage is below the intermediate DC voltage, thereby applying repetitive + offset voltage and - offset voltage to the phase output voltage. Also in this case, the intermediate voltage drifts more positively when the + offset voltage is applied to the phase output, and drifts more negatively when the - offset voltage is applied to the phase output voltage.

[0073] As described above with reference to FIGS. 8 and 9, the conduction loss in the switch is reduced when the intermediate voltage is not the same as the average phase voltage.

[0074] In FIG. 10, the common offset voltage (+ offset and - offset) is lower (i.e., closer to the midpoint between the + DC rail and the - DC rail) to prevent the phase output voltage from reaching the DC rail.

[0075] Preferably, the phase output voltage should not cross the intermediate voltage; otherwise, the inverter will change to the other pair of switches, thus nullifying the benefits of the method.

[0076] Calculating the common positive offset voltage and negative offset voltage can be based on one or more of several parameters, including the offset buffer voltage, the output phase voltage requirement, the negative DC input voltage, the positive DC input voltage, and the output load power factor. Preferably, there should be sufficient headroom (offset buffer voltage) above the peak and below the valley of the desired phase output voltage to prevent the output phase voltage from reaching either DC rail. Preferably, the offset buffer voltage is set large enough to move the phase output voltage as close as possible to the desired DC rail so as to maximize conduction loss reduction and move it far enough away from the intermediate voltage.

[0077] An example of calculating the offset voltage can be based on the desired phase output voltage (related to the modulation index) and the value of the headroom or offset buffer voltage above or below the peak or valley of the desired phase output voltage to prevent the phase output voltage from reaching the DC rail.

[0078] Calculating an intermediate voltage and appropriate positive and negative intermediate target voltages, where the target voltage is a target voltage that is allowed to drift either towards a positive offset voltage or a negative offset voltage, the target can be based on one or more of a positive offset voltage or a negative offset voltage, a negative DC input voltage, a positive DC input voltage, a phase voltage demand (related to a modulation index), an intermediate target buffer voltage, and a frequency of the intermediate DC voltage. The intermediate target buffer voltage is a headroom above or below a peak or valley of a desired phase output voltage to prevent the phase output voltage from reaching or crossing the intermediate DC voltage. The intermediate target buffer voltage can be the same as the offset buffer voltage or it can be different from the offset buffer voltage. The intermediate target buffer voltage can be zero.

[0079] When using this offset voltage technique (when the intermediate DC voltage is generated from the +DC rail and the -DC rail as described above), since the intermediate voltage drifts over time and there is a benefit in reducing conduction losses when the phase voltage output is different from the intermediate DC voltage, the intermediate DC voltage can be used to determine whether this technique should be used first. For example, when the difference between each of the +offset voltage and the -offset voltage (which are each the average of the phase voltage output when the positive offset voltage and the negative offset voltage are applied to the phase voltage output, respectively) and the intermediate DC voltage is greater than a threshold value, the controller can determine that there is a benefit in using this technique and thus appropriately control the switches to implement the +offset voltage and the -offset voltage as described above.

[0080] Whether to use the offset voltage technique described above can also or instead be determined from one or more of the following parameters, namely, the output phase voltage demand, the DC input voltages (+DC and -DC), and the load power factor.

[0081] When this method is first initiated, i.e., during the first PWM period when a + offset or - offset should be applied, the controller can first determine which of the + offset voltage and the - offset voltage should be applied. This determination can be based on, for example, the voltage difference between the positive offset voltage and the intermediate DC voltage and the voltage difference between the negative offset voltage and the intermediate DC voltage.

[0082] For example, the controller can be configured to apply the positive offset voltage when the difference between the positive offset voltage and the intermediate DC voltage is greater than the difference between the negative offset voltage and the intermediate DC voltage. Further, the controller can be configured to apply the negative offset voltage when the difference between the negative offset voltage and the intermediate DC voltage is greater than the difference between the positive offset voltage and the intermediate DC voltage.

[0083] Alternatively, the controller can implement only the + offset voltage or the - offset voltage regardless of the values of the + offset voltage, the - offset voltage, and the intermediate DC voltage.

[0084] When this method is initiated, i.e., during subsequent PWM periods, the determination of which offset voltage should be applied is as described above with respect to the intermediate DC voltage approaching the respective positive intermediate target voltage or negative intermediate target voltage.

[0085] When switching between applying the + offset voltage and applying the - offset voltage, i.e., when switching between using the upper pair of switches and using the lower pair of switches respectively, preferably, a slew is applied to the switching method. This is aimed at minimizing NVH (noise, vibration, and harshness) problems that can arise from rapid changes in the phase output voltage during the transition between the + offset condition and the - offset condition.

[0086] (For example, an example was described where an intermediate DC voltage is generated from a +DC rail and a -DC rail using a voltage-dividing capacitor. However, the intermediate DC voltage may be provided by a second DC input voltage source. In one example, the second DC input voltage source may be capable of sourcing and sinking current during a period when a +offset voltage and a -offset voltage are applied to the phase voltage output, which results in the intermediate DC voltage remaining constant. In such a case, the determination of which of the +offset voltage and the -offset voltage should be applied may be based on other parameters, for example, the characteristics of the switches being used, noise considerations, switch thermal characteristics, and other parameters.)

[0087] Alternatively, the second DC input voltage source may be configured to provide a variable or fluctuating intermediate DC voltage. In that case, the controller determines which of the +offset and the -offset should be applied, as described above, along with the fluctuating intermediate DC voltage.)

[0088] The second DC input voltage source may be provided, for example, by a center tap from a battery pack that supplies the +DC rail and the -DC rail. In such a configuration, the +offset voltage and the -offset voltage may be alternately applied to control charging and discharging of different halves of the battery pack, depending on the desired performance and state of the battery pack.)

[0089] Three-phase voltage generation is described and illustrated, but the three-level converter described functions for a greater number of phase outputs. Accordingly, the present technique functions for polyphase output voltage generation.)

[0090] Presumably, many other effective alternative forms will occur to those skilled in the art. It will be understood that the present invention is not limited to the described embodiments and includes modifications obvious to those skilled in the art within the scope of the claims appended hereto.)

Claims

1. A converter for generating a polyphase voltage for supplying power to an electrical machine, an input for receiving a positive DC input voltage and a negative DC input voltage, a plurality of AC outputs, each for outputting a polyphase AC output voltage for driving the electrical machine, for each phase, a plurality of switches arranged in a T-configuration between the DC input and the respective AC phase output, the T-configuration comprising an upper switch coupled between the positive DC input and the respective AC phase output, a lower switch coupled between the respective AC phase output and the negative DC input, and a central upper switch and a central lower switch coupled between the AC phase output and an intermediate DC voltage, the switches being arranged in respective upper and lower pairs of switches, the upper pair comprising the upper switch and the central lower switch, the lower pair of switches comprising the lower switch and the central upper switch, the intermediate DC voltage being the voltage between the positive DC input voltage and the negative DC input voltage, a plurality of switches; an input for receiving data representing the required phase voltage demand for the electrical machine, a controller for controlling each of the switches using pulse width modulation (PWM) over a plurality of PWM periods to generate the polyphase AC output voltage for the electrical machine comprising, the controller, for each PWM period, controls each of the respective upper or lower pairs of switches to simultaneously apply either a positive offset voltage or a negative offset voltage, respectively, to each of the phase outputs, configured to, the positive offset voltage and the negative offset voltage each representing an average peak-to-peak voltage for the phase output voltage offset positively or negatively from the intermediate DC voltage, a converter.

2. Controlling each of the respective upper or lower pairs of switches to apply the positive offset voltage or the negative offset voltage, respectively, determining the positive offset voltage and the negative offset voltage for application to each of the phase output voltages based on one or more of an offset buffer voltage, an output phase voltage demand, the negative DC input voltage, the positive DC input voltage, and an output load power factor The converter according to claim 1, comprising an offset buffer voltage that represents a minimum voltage difference between the peak phase output voltage and each of the positive DC input voltage and the negative DC input voltage.

3. Controlling each of the upper pairs or lower pairs of switches to apply the positive offset voltage or the negative offset voltage respectively, Determining a positive intermediate target voltage and a negative intermediate target voltage based on one or more of the positive offset voltage or the negative offset voltage, the negative DC input voltage, the positive DC input voltage, the phase voltage demand, the intermediate target buffer voltage, and the frequency of the intermediate DC voltage The converter according to claim 2, comprising a positive intermediate target voltage and a negative intermediate target voltage that represent a target voltage deviation of the intermediate DC voltage.

4. The converter according to claim 2 or 3, wherein the controller applies the positive offset voltage or the negative offset voltage when a difference between each of the positive offset voltage or the negative offset voltage and the intermediate DC voltage is greater than a threshold voltage.

5. The converter according to claim 3 or 4, wherein the controller determines which of the positive offset voltage or the negative offset voltage to apply during a first PWM period based on a voltage difference between the positive offset voltage and the intermediate DC voltage and a voltage difference between the negative offset voltage and the intermediate DC voltage.

6. When the controller applies the positive offset voltage or the negative offset voltage during the first PWM period, the controller is configured to apply the positive offset voltage when the difference between the positive offset voltage and the intermediate DC voltage is greater than the difference between the negative offset voltage and the intermediate DC voltage, and the controller is configured to apply the negative offset voltage when the difference between the negative offset voltage and the intermediate DC voltage is greater than the difference between the positive offset voltage and the intermediate DC voltage. The converter according to claim 5.

7. The converter according to claim 5 or 6, wherein during a subsequent PWM period, when the controller controls the upper pair of switches to apply the positive offset voltage, and when the intermediate DC voltage approaches the positive intermediate target voltage, the controller is configured to apply a negative offset voltage to the phase output voltage by controlling the lower pair of switches.

8. The converter according to any one of claims 5 to 7, wherein during a subsequent PWM period, when the controller controls the lower pair of switches to apply the negative offset voltage, and when the intermediate DC voltage approaches the negative intermediate target voltage, the controller is configured to apply a positive offset voltage to the phase output voltage by controlling the upper pair of switches.

9. The converter according to claim 7 or 8, wherein when the controller switches between applying the positive offset voltage and applying the negative offset voltage, the controller controls the upper pair and / or the lower pair of switches to apply a slew to the offset voltage between the positive offset voltage and the negative offset voltage.

10. The converter according to any one of claims 1 to 9, wherein the intermediate DC voltage is provided by a capacitor voltage divider arranged between the positive DC input and the negative DC input.

11. The converter according to any one of claims 1 to 9, wherein the intermediate DC voltage is provided by a second DC source.

12. A method for generating a multiphase voltage for powering an electromechanical machine, comprising: receiving a positive DC input voltage and a negative DC input voltage; receiving data representing the required phase voltage demand for the electromechanical machine; To generate the multiphase AC output voltage for the electromechanical machine, a step of controlling a plurality of switches using pulse width modulation (PWM) over a plurality of PWM periods, wherein the plurality of switches are arranged in one for each phase in a plurality of groups, and for each phase, the group of switches is arranged in a T-configuration between the DC input and the respective AC phase output, the T-configuration comprising an upper switch coupled between the positive DC input and the respective AC phase output, a lower switch coupled between the respective AC phase output and the negative DC input, and a center upper switch and a center lower switch coupled between the AC phase output and the intermediate DC voltage, the switches being arranged in respective upper and lower pairs of switches, the upper pair comprising the upper switch and the center lower switch, the lower pair of switches comprising the lower switch and the center upper switch, and the intermediate DC voltage being the voltage between the positive DC input voltage and the negative DC input voltage, the step; Outputting the multiphase AC output voltage to drive the electromechanical machine; comprising; For each PWM period, the step of controlling the plurality of switches comprises: Controlling each of the respective upper or lower pairs of switches to simultaneously apply either the positive offset voltage or the negative offset voltage to each of the phase outputs; wherein the positive offset voltage and the negative offset voltage each represent the average peak-to-peak voltage for the phase output voltage offset positively or negatively from the intermediate DC voltage, a method.

13. The step of controlling each of the respective upper or lower pairs of switches to apply the positive offset voltage or the negative offset voltage respectively comprises: Determining the positive offset voltage and the negative offset voltage for application to each of the phase output voltages based on one or more of an offset buffer voltage, an output phase voltage demand, the negative DC input voltage, the positive DC input voltage, and an output load power factor; wherein the offset buffer voltage represents the minimum voltage difference between the peak phase output voltage and the respective positive and negative DC input voltages, the method according to claim 12.

14. The step of controlling each of the upper pairs or lower pairs of the switches to apply the positive offset voltage or the negative offset voltage, respectively, comprises: Determining a positive intermediate target voltage and a negative intermediate target voltage based on one or more of the positive offset voltage or the negative offset voltage, the negative DC input voltage, the positive DC input voltage, the phase voltage demand, the intermediate target buffer voltage, and the frequency of the intermediate DC voltage; The method according to claim 13, wherein the positive intermediate target voltage and the negative intermediate target voltage represent a target voltage deviation of the intermediate DC voltage. **Claim 15** The method according to claim 13 or 14, wherein the positive offset voltage or the negative offset voltage is applied when the difference between each positive offset voltage or negative offset voltage and the intermediate DC voltage is greater than a threshold voltage. **Claim 16** The method according to claim 14 or 15, wherein which of the positive offset voltage or the negative offset voltage to apply during the first PWM period is based on the voltage difference between the positive offset voltage and the intermediate DC voltage and the voltage difference between the negative offset voltage and the intermediate DC voltage. **Claim 17** The method according to claim 16, wherein when the positive offset voltage or the negative offset voltage is applied during the first PWM period, the positive offset voltage is applied when the difference between the positive offset voltage and the intermediate DC voltage is greater than the difference between the negative offset voltage and the intermediate DC voltage, and the negative offset voltage is applied when the difference between the negative offset voltage and the intermediate DC voltage is greater than the difference between the positive offset voltage and the intermediate DC voltage. **Claim 18** The method according to claim 16 or 17, wherein during a subsequent PWM period, when the upper pair of switches is controlled to apply the positive offset voltage and the intermediate DC voltage approaches the positive intermediate target voltage, the negative offset voltage is applied to the phase output voltage by controlling the lower pair of switches. **Claim 19** The method according to any one of claims 16 to 18, wherein during a subsequent PWM period, when the lower pair of switches is controlled to apply the negative offset voltage and when the intermediate DC voltage approaches the negative intermediate target voltage, the positive offset voltage is applied to the phase output voltage by controlling the upper pair of switches. **Claim 20** The method according to claim 18 or 19, wherein when the upper and / or lower pair of switches is switching between applying the positive offset voltage and applying the negative offset voltage, it is controlled to apply a slew to the offset voltage between the positive offset voltage and the negative offset voltage. **Claim 21** The method according to any one of claims 12 to 20, comprising the step of providing the intermediate DC voltage via a capacitor voltage divider arranged between the positive DC input and the negative DC input. **Claim 22** The method according to any one of claims 12 to 20, comprising the step of providing the intermediate DC voltage from a second DC source.

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