Wafer-Level Manufacturing for Multiple Chip Light-Emitting Devices

Abstract

A light-emitting device, and more specifically, wafer-level manufacturing for a plurality of chip light-emitting devices is disclosed. The light-emitting device includes a specific LED package structure such as an LED chip, a submount, and an electrical connection, which are formed by wafer-level manufacturing before individual light-emitting devices are separated. The method includes bonding an LED wafer on which a plurality of LED chips are formed to a submount wafer including a corresponding metallization pattern, and then separating the individual light-emitting devices. Each light-emitting device includes an array of LED chips already bonded to the submount using electrical connections. The array of LED chips can be electrically coupled in various electrical configurations based on the arrangement of the metallization pattern.

Description

Technical Field

[0001]

[0001] This disclosure relates to light-emitting devices, and more particularly, to wafer-level manufacturing for multiple chip light-emitting devices.

Background Art

[0002]

[0002] Solid-state light-emitting devices such as light-emitting diodes (LEDs) are increasingly used for both consumer and commercial applications. Advances in LED technology have enabled highly efficient, mechanically robust, and long-lasting light sources. Thus, modern LEDs enable a variety of new display applications and are increasingly used for general lighting applications, often replacing incandescent and fluorescent light sources.

[0003]

[0003] An LED is a solid-state device that converts electrical energy into light and generally includes an active layer (or active region) of one or more semiconductor materials disposed between oppositely doped n-type and p-type layers. When a bias is applied across the doped layers, holes and electrons are injected into one or more active layers, where they recombine to generate light emission such as visible light or ultraviolet emission. An LED chip typically includes an active region, which may be fabricated from, for example, silicon carbide, gallium nitride, gallium phosphide, indium phosphide, aluminum nitride, gallium arsenide-based materials, and / or organic semiconductor materials.

[0004]

[0004] LED packages have been developed that can provide mechanical support, electrical connection, and encapsulation for LED emitters. Multiple LED chip packages have also been developed that densely arrange an array of LED chips within the package. In such applications, there may be a problem of generating high-quality light with desired light-emitting characteristics while providing a suitable package arrangement in which multiple LED chips can be arranged within a single LED package.

[0005]

[0005] The art continues to seek improved LEDs and solid state lighting devices having desirable lighting characteristics that can overcome problems associated with conventional lighting devices.

SUMMARY OF THE INVENTION

MEANS FOR SOLVING THE PROBLEM

[0006]

[0006] The present disclosure relates to lighting devices and, more particularly, to wafer level manufacturing for multiple chip lighting devices. Such lighting devices may include specific light emitting diode (LED) package structures such as LED chips, submounts, and electrical connections that are formed by wafer level manufacturing before the individual lighting devices are separated. The method includes bonding an LED wafer having a plurality of LED chips formed thereon to a submount wafer including a corresponding metallization pattern and then separating the individual lighting devices. Each lighting device includes an array of LED chips already bonded to the submount using electrical connections. The array of LED chips may be electrically coupled in various electrical configurations based on the arrangement of the metallization pattern.

[0007]

[0007] In one aspect, the method comprises providing an LED wafer comprising a plurality of LED chips, each LED chip of the plurality of LED chips comprising an anode contact and a cathode contact; providing a submount wafer having a first metallization pattern on a front surface thereof and a second metallization pattern on a back surface thereof, the second metallization pattern being electrically coupled to the first metallization pattern; bonding the LED wafer to the front surface of the submount wafer such that the anode contacts and the cathode contacts of each LED chip are electrically coupled to the first metallization pattern; and singulating the LED wafer and the submount wafer to form a plurality of light-emitting devices, each light-emitting device of the plurality of light-emitting devices comprising a substrate formed from the LED wafer, an array of LED chips of the plurality of LED chips, and a submount formed from the submount wafer. In certain embodiments, the LED wafer comprises a substrate structure subdivided to form each substrate of the plurality of light-emitting devices, and the submount wafer comprises a submount structure subdivided to form each submount of the plurality of light-emitting devices. In certain embodiments, the substrate structure comprises a sapphire wafer on which the plurality of LED chips are formed. In certain embodiments, the submount structure comprises aluminum oxide or aluminum nitride.

[0008]

[0008] In certain embodiments, the first metallization pattern comprises another pair of an anode metal trace and a cathode metal trace, each bonded to the anode contact and the cathode contact, respectively, of each LED chip of the plurality of LED chips. In certain embodiments, the second metallization pattern comprises a first metal trace forming an anode attachment pad, a second metal trace forming a cathode attachment pad, and a third metal trace forming a part of a conductive path between the first metal trace and the second metal trace.

[0009]

[0009] In certain embodiments, the spacing between adjacent LED chips among the plurality of LED chips is 40 micrometers (μm) or less. In certain embodiments, the spacing ranges from 10 μm to 40 μm. In certain embodiments, the plurality of LED chips are subdivided from a common epitaxial LED structure. In certain embodiments, bonding the LED wafer to the front surface of the submount wafer comprises thermocompression bonding, eutectic bonding, transient liquid phase bonding, bump bonding, or solder paste bonding that bonds the anode contact and the cathode contact to a first metallization pattern.

[0010]

[0010] In certain embodiments, bonding the LED wafer to the front surface of the submount wafer comprises forming a ceramic bond between the LED wafer and the submount wafer. This method may further comprise forming an underfill material in the gap between the LED wafer and the submount wafer. In certain embodiments, the array of LED chips is electrically connected in series, parallel, or series-parallel. In certain embodiments, the second metallization pattern comprises a first metal trace pattern configured to electrically connect an array of LED chips for a first light-emitting device among the plurality of light-emitting devices to a first electrical configuration, and a second metal trace pattern configured to electrically connect an array of LED chips for a second light-emitting device among the plurality of light-emitting devices to a second electrical configuration. In certain embodiments, the submount structure comprises a multilayer ceramic structure.

[0011] In another aspect, the method comprises providing an LED wafer having a plurality of LED chips on a substrate structure, forming a first underfill material on the LED wafer, and providing a submount wafer having a first metallization pattern on a front surface of the submount wafer and a second metallization pattern on a back surface of the submount wafer, wherein the second metallization pattern is electrically coupled to the first metallization pattern, bonding the LED wafer to the front surface of the submount wafer such that the plurality of LED chips are electrically coupled to the first metallization pattern, and singulating the LED wafer and the submount wafer to form a plurality of light-emitting devices, wherein each light-emitting device of the plurality of light-emitting devices comprises an array of LED chips of the plurality of LED chips and a submount formed from the submount wafer.

[0012]

[0012] In certain embodiments, the LED wafer comprises a plurality of streets defining the boundaries of each LED chip of the plurality of LED chips, and the first underfill material is disposed to fill a portion of the plurality of streets. In certain embodiments, the first underfill material comprises a light-reflective material configured to reflect or redirect light from the plurality of LED chips. In certain embodiments, the first underfill material is formed on the LED wafer after the LED wafer is attached to the submount wafer. In certain embodiments, the first underfill material is formed on the LED wafer before the LED wafer is attached to the submount wafer. The method may further comprise forming a second underfill material on the submount wafer before the LED wafer is attached to the submount wafer. In certain embodiments, the first underfill material and the second underfill material form a ceramic bond between the LED wafer and the submount wafer. In certain embodiments, the array of LED chips is electrically coupled in series, parallel, or series-parallel.

[0013]

[0013] In another aspect, additional advantages can be obtained by taking any one or both of the foregoing aspects, and / or by combining various individual aspects and features described herein. Any of the various features and elements disclosed herein can be combined with one or more other disclosed features and elements, unless the contrary is indicated herein.

[0014]

[0014] Those skilled in the art will recognize the scope of the present disclosure and understand its additional aspects after reading the following detailed description of the preferred embodiments in connection with the accompanying drawings.

[0015] The accompanying drawings, which are incorporated herein and form a part of this specification, illustrate some aspects of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

Brief Description of the Drawings

[0015]

Figure 1

[0016] FIG. 1A is a top view of an LED wafer with an exploded portion illustrating a diagram of an LED chip formed on the LED wafer.

[0017] FIG. 1B is a top view of a submount wafer with an exploded portion illustrating a diagram of a first metallization pattern formed on the submount wafer.

Figure 2A

[0018] FIG. 23 is a cross-sectional view of a manufacturing step for forming a plurality of light-emitting devices, in which the LED wafer of FIG. 1A is arranged to be attached to the submount wafer of FIG. 1B.

Figure 2B

[0019] FIG. 27 is a cross-sectional view of a manufacturing step following FIG. 2A, in which the LED wafer is bonded to the submount wafer.

Figure 2C

[0020] FIG. 31 is a cross-sectional view of a manufacturing step following FIG. 2B, in which the light-emitting devices are separated from each other along the vertical dashed line of FIG. 2B.

Figure 3A

[0021] A cross-sectional view of a manufacturing step for forming a plurality of light-emitting devices, similar to the manufacturing steps illustrated in FIG. 2A and further including one or more underfill materials.

Figure 3B

[0022] A cross-sectional view of a manufacturing step subsequent to FIG. 3A for forming a plurality of light-emitting devices, similar to the manufacturing steps illustrated in FIG. 2B.

Figure 3C

[0023] A cross-sectional view of a manufacturing step subsequent to FIG. 3B for forming a plurality of light-emitting devices, similar to the manufacturing steps illustrated in FIG. 2C.

Figure 4A

[0024] A view of the first side of the submount wafer from FIGS. 1B to 3C, where overlapping vertical and horizontal dashed lines form a grid of 16 different device regions, and each device region includes four pairs of front metal traces.

Figure 4B

[0025] A view of the submount wafer from the same orientation as FIG. 4A, where the submount structure is shown transparently with the front metal traces removed so that the back metal traces are visible.

Figure 4C

[0026] A view from a part of FIG. 4A illustrating four pairs of front metal traces for a single device region.

Figure 4D

[0027] A view from the part of FIG. 4B that illustrates the back metal traces together with the positions of the vias.

Figure 4E

[0028] A view of the submount wafer where the image of FIG. 4C using the front metal traces is superimposed on the image of FIG. 4D aligned according to the vias.

Figure 4F

[0029] A view illustrating an equivalent circuit of an LED chip that can be later attached to the front metal traces of FIG. 4E.

Figure 5

[0030] FIG. 5A is a view of a first side of a submount wafer similar to FIG. 4C, in which one or more positions of vias with respect to each of the front metal traces are different in order to be adapted for parallel connection, as described below.

[0031] FIG. 5B is a rear view of the submount wafer from FIG. 5A.

[0032] FIG. 5C is a view of the submount wafer in which an image of FIG. 5A using the front metal trace is superimposed on an image of FIG. 5B aligned according to the vias.

[0033] FIG. 5D is a diagram illustrating an equivalent circuit of an LED chip that can be later attached to the front metal trace of FIG. 5C.

Figure 6

[0034] FIG. 6A is a view of a first side of a submount wafer similar to FIG. 4C, in which one or more positions of vias with respect to each of the front metal traces are different in order to be adapted for parallel and series configurations.

[0035] FIG. 6B is a rear view of the submount wafer of FIG. 6A.

[0036] FIG. 6C is a view of the submount wafer in which an image of FIG. 6A using the front metal trace is superimposed on an image of FIG. 6B aligned according to the vias.

[0037] FIG. 6D is a diagram illustrating an equivalent circuit of an LED chip that can be later attached to the front metal trace of FIG. 6C.

Figure 7

[0038] FIG. 7A is a front view of a part of a submount wafer similar to the figure provided by FIG. 4C, in which the submount wafer includes a multilayer structure with vias and interconnects for wiring conductive paths.

[0039] FIG. 7B is a rear view of the submount wafer of FIG. 7A, illustrating two rear metal traces that form an anode attachment pad and a cathode attachment pad of a corresponding light-emitting device.

[0040] FIG. 7C is a cross-sectional view taken along the section line 7C-7C of FIG. 7A.

[0041] FIG. 7D is a cross-sectional view taken along the section line 7D-7D of FIG. 7A.

DETAILED DESCRIPTION OF THE INVENTION

[0016]

[0042] The embodiments described below represent the information necessary for those skilled in the art to implement the embodiments and show the best mode of implementing the embodiments. Reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and recognize the applications of these concepts not specifically addressed herein. It should be understood that these concepts and their applications are included in the present disclosure and the appended claims.

[0017]

[0043] In this specification, terms such as first, second, etc. may be used to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0018]

[0044] When an element such as a layer, region, or substrate is said to be "on" or "extending on" another element, it will be understood that the element can be immediately on or extending immediately on the other element, or there may also be intervening elements. In contrast, when an element is said to be "immediately on" or "extending immediately on" another element, there are no intervening elements. Similarly, when an element such as a layer, region, or substrate is said to be "above" or "extending above" another element, it will be understood that the element can be directly above or directly extending above the other element, or there may also be intervening elements. In contrast, when an element is said to be "directly above" or "extending directly above" another element, there are no intervening elements. Also, when an element is said to be "connected" or "coupled" to another element, it will be understood that the element can be directly connected or coupled to the other element, or there may also be intervening elements. In contrast, when an element is said to be "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0019]

[0045] Relative terms such as "below" or "on" or "above" or "beneath" or "horizontal" or "vertical" in this specification may be used to describe the relationship between one element, layer, or region and another element, layer, or region as illustrated in the figures. It will be understood that these terms, as well as the terms discussed above, are intended to encompass different orientations of the device in addition to the orientation shown in the figures.

[0020]

[0046] The terms used in this specification are for the purpose of describing particular embodiments only and are not intended to limit the disclosure. As used in this specification, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Further, the terms "comprising", "comprises", "including", and / or "includes" as used herein specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0021]

[0047] Unless otherwise defined, all terms (including technical and scientific terms) used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Further, the terms used in this specification should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0022]

[0048] Embodiments are described herein with reference to the schematic diagrams of the embodiments of the present disclosure. Accordingly, the actual dimensions of the layers and elements can be different, and for example, variations from the shapes of the figures are expected as a result of manufacturing techniques and / or tolerances. For example, regions illustrated or described as square or rectangular can have rounded or curved features, and regions illustrated as straight lines can have some irregularities. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the exact shape of the regions of the device and are not intended to limit the scope of the disclosure. In addition, the size of a structure or region may be exaggerated for illustrative purposes in comparison with other structures or regions, and thus is provided to illustrate the general structure of the subject matter of the present invention and may or may not be drawn to scale. Common elements between the drawings may be shown herein with common element numbers and may not be described again later.

[0023]

[0049] The present disclosure relates to light-emitting devices, and more particularly, to wafer-level manufacturing for multiple chip light-emitting devices. Such light-emitting devices can include specific LED package structures such as light-emitting diode (LED) chips, submounts, electrical connections, etc., which are formed by wafer-level manufacturing before the individual light-emitting devices are separated. The method includes bonding an LED wafer on which a plurality of LED chips are formed to a submount wafer including a corresponding metallization pattern, and then separating the individual light-emitting devices. Each light-emitting device includes an array of LED chips that are already bonded to the submount using electrical connections. The array of LED chips can be electrically coupled in various electrical configurations based on the arrangement of the metallization pattern.

[0024]

[0050] The light-emitting devices disclosed herein may include a plurality of LED chips having a specific LED package structure such as a submount and electrical connections, which are joined together by wafer-level manufacturing. By joining a submount including electrical connections at the wafer level and a plurality of LED chips, individual groups of LED chips already bonded to the submount by electrical connections can be separated individually to form a plurality of LED chip light-emitting devices.

[0025]

[0051] Before delving into the specific details of various aspects of the present disclosure, an overview of various elements that may be included in exemplary light-emitting devices of the present disclosure is provided for context. An LED chip typically comprises an active LED structure or region that may have many different semiconductor layers arranged in many different ways. The manufacture and operation of LEDs and their active structures are generally known in the art and are discussed briefly herein. The layers of the active LED structure can be manufactured using known processes having a suitable process such as metal-organic chemical vapor deposition. The layers of the active LED structure typically comprise many different layers and generally can comprise an active layer sandwiched between n-type and p-type oppositely doped epitaxial layers, all of which are formed continuously on a growth substrate. Additional layers and elements may also be included in the active LED structure, including, but not limited to, buffer layers, nucleation layers, superlattice structures, undoped layers, cladding layers, contact layers, current spreading layers, light extraction layers and elements. The active layer can comprise a single quantum well, multiple quantum wells, a double heterostructure, or a superlattice structure.

[0026]

[0052] Active LED structures can be fabricated from different material systems, some of which are III-nitride based material systems. III-nitrides refer to semiconductor compounds formed between nitrogen (N) and the elements of Group III of the periodic table, usually aluminum (Al), gallium (Ga), and indium (In). Gallium nitride (GaN) is a common binary compound. III-nitrides also refer to ternary and quaternary compounds such as aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN). In the case of III-nitrides, silicon (Si) is a common n-type dopant and magnesium (Mg) is a common p-type dopant. Thus, the active layer, n-type layer, and p-type layer may include one or more layers of GaN, AlGaN, InGaN, and AlInGaN that are either undoped or doped with Si or Mg in the case of a III-nitride based material system. Other material systems include silicon carbide (SiC), organic semiconductor materials, and other III-V based systems such as gallium phosphide (GaP), gallium arsenide (GaAs), and related compounds.

[0027]

[0053] The active LED structure may be grown on a growth substrate that can include many materials such as sapphire, SiC, aluminum nitride (AlN), GaN, GaAs, glass, or silicon. SiC has certain advantages such as closer crystal lattice matching with III-nitrides than other substrates, and high-quality III-nitride films can be obtained. SiC also has a very high thermal conductivity, so the total output of III-nitride devices on SiC is not limited by the heat dissipation of the substrate. Sapphire is another common substrate for III-nitrides and also has certain advantages such as low cost, an established manufacturing process, and excellent optical properties of light transmission.

[0028]

[0054] Different embodiments of the active LED structure can emit light of different wavelengths depending on the composition of the active layer, n-type layer, and p-type layer. In certain embodiments, the active LED structure can emit blue light with a peak wavelength range of about 430 nanometers (nm) to 480 nm. In other embodiments, the active LED structure can emit green light with a peak wavelength range of 500 nm to 570 nm. In other embodiments, the active LED structure can emit red light with a peak wavelength range of 600 nm to 650 nm. In certain embodiments, the active LED structure can emit light having a peak wavelength in any region of the visible spectrum, for example, mainly in the range of 400 nm to 700 nm.

[0029]

[0055] In certain embodiments, the active LED structure may be configured to emit light outside the visible spectrum that includes one or more portions of the ultraviolet (UV) spectrum, infrared (IR), or near-IR spectrum. The UV spectrum is typically divided into three wavelength range categories denoted by the letters A, B, and C. In this way, UV-A light is typically defined as having a peak wavelength range of 315 nm to 400 nm, UV-B is typically defined as having a peak wavelength range of 280 nm to 315 nm, and UV-C is typically defined as having a peak wavelength range of 100 nm to 280 nm. UV LEDs are particularly important for use in applications related to the disinfection of microorganisms in air, water, and surfaces, among others. In other applications, one or more light-emitting materials may be provided to the UV LED to provide an LED package with collective emission having a wide spectrum and improved color quality for visible light applications. The near-IR and / or IR wavelengths of the LED structures of the present disclosure can have wavelengths greater than 700 nm, such as in the range of 750 nm to 1100 nm or more.

[0030]

[0056] The LED chip may be covered with one or more light emitters or other conversion materials such as phosphors, whereby at least a portion of the light from the LED chip is absorbed by one or more phosphors and converted into one or more different wavelength spectra according to the characteristic emission from the one or more phosphors. In some embodiments, the combination of the LED chip and one or more phosphors emits a generally white light combination. The one or more phosphors may include yellow (e.g., YAG:Ce), green (e.g., LuAg:Ce), and red (e.g., Ca i-x-y Sr x Eu y AlSiN3) emitting phosphors, and combinations thereof. The luminescent materials described herein may be or include one or more of phosphors, scintillators, luminescent inks, quantum dot materials, day glow tape, etc. The luminescent material may be provided by any suitable means, such as, for example, direct coating on one or more surfaces of the LED, dispersion in a encapsulant material configured to cover one or more LEDs, and / or coating on one or more optical or support elements (e.g., by powder coating, inkjet printing, etc.). In certain embodiments, the luminescent material may be downconverted or upconverted, and a combination of both downconverting and upconverting materials may be provided. In certain embodiments, a plurality of different (e.g., different in composition) luminescent materials arranged to generate different peak wavelengths may be arranged to receive the emission from one or more LED chips. In some embodiments, the one or more phosphors may include yellow phosphors (e.g., YAG:Ce), green phosphors (e.g., LuAg:Ce), and red phosphors (e.g., Ca i-x-y Sr x Eu y AlSiN3), and combinations thereof. One or more luminescent materials may be provided in various configurations on one or more portions of the LED chip and / or submount.

[0031]

[0057] As used herein, a layer or region of a light-emitting device may be considered "transparent" if at least 80% of the light emission impinging on the layer or region exits through the layer or region. Further, as used herein, a layer or region of an LED is "reflective" or considered to embody a "mirror" or "reflector" if at least 80% of the light emission impinging on the layer or region is reflected. In some embodiments, the light emission comprises visible light, such as blue and / or green LEDs, regardless of the presence of a light-emitting material. In other embodiments, the light emission may comprise non-visible light. For example, in the case of GaN-based blue and / or green LEDs, silver (Ag) may be considered a reflective material (e.g., at least 80% reflective). In the case of UV LEDs, an appropriate material may be selected to achieve a high reflectivity in some desired embodiments and / or a low absorption rate in some desired embodiments. In certain embodiments, a "light-transmissive" material may be configured to transmit at least 50% of the light emission of a desired wavelength.

[0032]

[0058] The present invention may be useful for LED chips having various shapes including a flip-chip shape. The flip-chip structure of an LED chip typically includes an anode connection and a cathode connection made from the same side or face of the LED chip. The anode side and the cathode side are typically configured as the mounting surface of the LED chip for flip-chip mounting to another surface, such as a printed circuit board. In this regard, the anode connection and the cathode connection on the mounting surface serve to mechanically attach and electrically couple the LED chip to the other surface. In the case of flip-chip mounting, the side or face opposite the LED chip corresponds to the light-emitting surface facing the intended light-emitting direction. In certain embodiments, during flip-chip mounting, the growth substrate of the LED chip can form and / or be adjacent to the light-emitting surface. During chip manufacturing, an active LED structure may be epitaxially grown on the growth substrate.

[0033]

[0059] An LED package may include one or more elements such as a light-emitting material, a sealing material, a light-changing material, a lens, and electrical contacts provided together with one or more LED chips. In certain embodiments, the LED package may include a support member such as a submount. Materials suitable for the submount include, but are not limited to, ceramic materials such as aluminum oxide, alumina, AlN, or organic insulators such as polyimide (PI) and polyphthalamide (PPA). In other embodiments, the submount may comprise a printed circuit board (PCB), sapphire, Si, or any other suitable material. In the PCB embodiment, different PCB types can be used, such as a standard FR-4 PCB, a metal-core PCB, or any other type of PCB. A metal trace pattern can be provided on one or more sides of the submount to receive and / or electrically connect one or more LED chips. A sealing material can be formed to cover the LED chips on the submount to protect the underlying LED package elements or to shape the emitted light from the LED package. The sealing material may include a material that is light-transmissive and / or optically transparent to the wavelength provided by the underlying LED chips and / or light-emitting material. Suitable encapsulation materials include silicone, plastic, epoxy, or glass. In certain embodiments, the encapsulant may include a lens shape for controlling the emission of light.

[0034]

[0060] According to aspects of the present disclosure, a light emitting device can include a plurality of LED chips with a specific LED package structure such as a submount and electrical connections, and these chips are bonded by wafer-level manufacturing. By bonding a plurality of LED chips using a submount that includes electrical connections at the wafer level, groups of individual LED chips that are already bonded to the submount using electrical connections can be separately separated to form a plurality of LED chip light emitting devices. Wafer-level manufacturing can include bonding an LED wafer to a submount wafer before various light emitting devices are individualized. As used herein, an LED wafer can include a growth substrate blanket deposited with an epitaxial LED structure. Individual LED chips along the growth substrate can be formed by post-epitaxy manufacturing that can include removing a portion of the epitaxial LED structure along a street to define the boundaries of the LED chips. The LED wafer can include other post-epitaxy manufacturing such as the formation of a reflective structure, electrical contacts for the anode and cathode of each LED chip, and / or a passivation layer. As used herein, a submount wafer can include a ceramic material such as aluminum oxide or alumina, AlN, or an organic insulator such as PI or PPA, or a PCB, sapphire, Si, or any other suitable material. As will be described in more detail below, a metal trace pattern can be provided on one or more sides of the submount to receive and / or electrically connect one or more LED chips of the LED wafer.

[0035]

[0061] In the case of multi-chip applications, wafer-level manufacturing has various advantages, such as avoiding complex pick-and-place steps for individual LED chips for which individual die attachment steps are provided. In multi-chip applications, as the number of individual die attachment steps increases, there may be an increase in bonding strength variations and / or obstacles and / or electrical short circuits associated with chip alignment variations. By bonding at the wafer level, multiple LED chips can be simultaneously bonded to the electrical connections of the submount wafer while the spacing between adjacent LED chips is fixed by the LED wafer. According to aspects of the present disclosure, the spacing between adjacent LED chips within a multi-chip light-emitting device can be provided after wafer-level manufacturing to be 40 micrometers (μm) or less, or in the range of 10 μm to 40 μm, or in the range of 20 μm to 40 μm, or in the range of 20 μm to 30 μm. At the wafer level, multiple LED chips can be defined from a common epitaxial structure by forming streets therebetween. In this way, each LED chip forms a mesa along the LED wafer, and the above spacing values are measured from the edge of one mesa to the edge of the adjacent LED chip's mesa. Such a narrow spacing can be important in multi-chip light-emitting devices where multiple LED chips are arranged to collectively provide the appearance of a single light-emitting surface or a single LED chip. In certain embodiments, the substrate on which the LED chips are formed is continuous, thereby also improving the appearance of a single LED chip. For example, in a flip-chip embodiment where light exits through the substrate, having a continuous substrate without gaps between the LED chips can provide the appearance of a single light-emitting surface. It should be understood that the principles described herein are also applicable to applications where the spacing between LED chips is large.

[0036]

[0062] Another advantage of wafer-level manufacturing is that there is no need to classify individual LED chips according to brightness, wavelength, and / or turn-on voltage before assembling them into a common device. In wafer-level manufacturing, since adjacent LED chips are formed from the same region of a common epitaxial LED structure, there is no need to classify them individually for each brightness, wavelength, and / or turn-on voltage. Yet another advantage of wafer-level manufacturing is that multiple LED chips can be electrically connected in different configurations simply by providing different patterns of metal traces on the submount wafer. For example, the submount wafer may include patterns that electrically couple multiple LED chips in series, parallel, series-parallel, and individually addressable configurations. In particular, wafer-level manufacturing provides such flexible electrical connections in combination with the narrow spacing of the LED chips described above. In certain embodiments, a monolithic high-voltage chip may be formed by a plurality of LED chips connected in series or series-parallel configurations, thereby increasing the operating voltage, reducing the voltage drop required for electrical driving, and enhancing the overall system efficiency.

[0037]

[0063] FIG. 1A is a top view of an LED wafer 10 with an exploded portion illustrating a diagram of an LED chip 12 formed on the LED wafer 10. The LED wafer 10 includes a wafer-shaped substrate structure 14. In FIG. 1A, the wafer shape is circular, and in other embodiments, the wafer shape may be square or rectangular. The substrate structure 14 can embody a growth wafer such as sapphire, SiC, AlN, or GaN, and an epitaxial LED structure as described above can be deposited on the growth wafer. Through various manufacturing steps, each LED chip 12 can be defined from the epitaxial LED structure, including the formation of one or more reflective layers, a passivation layer, an anode contact 16, and a cathode contact 18 for each LED chip 12. A street 20 is formed that defines the boundary of each of the LED chips 12. The street 20 can embody an area where the epitaxial LED structure is removed from the substrate structure 14. In this way, the street 20 defines the spacing between adjacent LED chips 12. As described above, in certain embodiments, such spacing can be 40 μm or less, or in the range of 10 μm to 40 μm, or in the range of 20 μm to 40 μm, or in the range of 20 μm to 30 μm.

[0038]

[0064] Figure 1B is a top view of the submount wafer 22 with an exploded portion illustrating a first, i.e., front, metallization pattern formed on the submount wafer 22. The submount wafer 22 includes a wafer-shaped submount structure 24. In certain embodiments, the wafer shape of the submount structure 24 corresponds to the wafer shape of the substrate structure 14 of FIG. 1A. The submount structure 24 can comprise any of the materials described above and, when divided, can form a precursor structure that provides individual submounts for a plurality of light-emitting devices. The first metallization pattern includes a repeating pattern of pairs of a first metal trace 26-1 and a second metal trace 26-2. Each pair of the first metal trace 26-1 and the second metal trace 26-2 is formed in a shape corresponding to the anode contact 16 and the cathode contact 18 of FIG. 1A. In this way, when the side surface of the LED wafer 10 as seen in FIG. 1A is attached to the side surface of the submount wafer 22 as seen in FIG. 1B, each anode contact 16 can be mechanically bonded and electrically coupled to the corresponding first metal trace 26-1. Similarly, each cathode contact 18 can be mechanically bonded and electrically coupled to the corresponding second metal trace 26-2. As will be described in more detail later, one or more vias 28 can be disposed to provide a conductive path through the submount structure 24 to a second metallization pattern on the opposite side, i.e., the back side, of the submount wafer 22.

[0039]

[0065] Figure 2A is a cross-sectional view in a manufacturing step for forming a plurality of light-emitting devices 30, where the LED wafer 10 of Figure 1A is disposed at a position to be attached to the submount wafer 22 of Figure 1B. For illustrative purposes, the figure provided in Figure 2A shows only four LED chips 12 having corresponding streets 20, and the overlapping vertical dashed lines 32 indicate positions where the individual light-emitting devices 30 will be separated later. In reality, the number of individual light-emitting devices 30 formed is much larger, and each individual light-emitting device 30 may include two or more LED chips 12. A wafer aligner can be applied to correctly position the LED wafer 10 with respect to the submount wafer 22, aligning the anode contact 16 with the first metal trace 26-1 and the cathode contact 18 with the second metal trace 26-2.

[0040]

[0066] As illustrated in Figure 2A, separate vias 28 can be disposed to electrically couple each of the first metal trace 26-1 and the second metal trace 26-2 of the first metallization pattern on the first side 22’, i.e., the front surface, of the submount wafer 22, to the second metallization pattern on the second side 22”, i.e., the back surface, of the submount wafer 22. The first metal trace 26-1 and the second metal trace 26-2 are also referred to herein as front metal traces 26-1, 26-2. The second metallization pattern can be formed by back metal traces 34-1 to 34-3 configured to provide various electrical connections between the LED chips 12. For example, the first metal trace 26-1 and the second metal trace 26-2 associated with the leftmost LED chip 12 in Figure 2A are respectively coupled to the back metal traces 34-1, 34-2, and the back metal trace 34-2 is also electrically coupled to the first metal trace 26-1 associated with the next adjacent LED chip 12. Finally, the second metal trace 26-2 associated with the adjacent LED chip 12 is electrically coupled to the back metal trace 34-3. In this way, the LED chips 12 of each light-emitting device 30 are electrically coupled in series based on the arrangement of the submount wafer 22.

[0041]

[0067] FIG. 2B is a cross-sectional view in a manufacturing step following FIG. 2A, where the LED wafer 10 is bonded to the submount wafer 22. As illustrated, the pairs of corresponding anode contacts 16 and cathode contacts 18 are bonded to the pairs of corresponding front metal traces 26-1, 26-2. Such wafer bonding can be provided by various techniques that mechanically and electrically bond the metal of each anode contact 16 and each cathode contact 18 to the metal of the corresponding front metal traces 26-1, 26-2. For example, the bonding may include thermocompression bonding of a specific same metal such as gold (Au), copper (Cu), or aluminum (Al) present at the interface formed between the anode contact 16 or cathode contact 18 and the corresponding front metal traces 26-1, 26-2. Other bonding may include die attach metal stacks formed at the interface, such as eutectic metal stacks like gold-tin (Au-Sn), gold-silicon (Au-Si), gold-germanium (Au-Ge), aluminum-germanium (Al-Ge), or gold-indium (Au-In). Still other bonding may include transient liquid phase bonding with copper-tin (Cu-Sn), Au-In, or silver-tin (Ag-Sn). Additional bonding may include bump bonding by a pattern of solder bumps or by solder paste bonding.

[0042]

[0068] Figure 2C is a cross-sectional view of the next manufacturing step of Figure 2B, in which the light-emitting devices 30 are separated from each other along the vertical dashed line 32 of Figure 2B. The separation can be performed by wafer dicing or singulation such as mechanical sawing or laser dicing. After separation, each light-emitting device 30 includes a substrate 14' separated from the substrate structure 14 of Figure 2B and a submount 24' separated from the submount structure 24 of Figure 2B. Each of the light-emitting devices 30 can embody a plurality of chip devices formed from a common region of an epitaxial LED structure, with an array of LED chips 12 disposed adjacent thereto. The spacing can be determined by the streets 20 as already explained. The light-emitting devices 30 may be suitable for placement within an LED package or within a large LED lighting system. In certain embodiments, the substrate 14' can comprise a material such as sapphire that is light transmissive or optically transparent to the wavelength generated by the LED chips 12. In other embodiments, the substrate 14' may not be required. For example, the substrate structure 14 of Figure 2B may be removed after bonding to the submount wafer 22, and the light-emitting devices 30 of Figure 2C may not include the substrate 14'.

[0043]

[0069] After singulation, the back metal traces 34-1, 34-3 of each light-emitting device 30 form an anode attachment pad and a cathode attachment pad for attachment to an external electrical connection, and the other back metal trace 34-2 forms part of the conductive path therebetween. For example, the conductive path between the back metal traces 34-1, 34-3 passes through the submount 24' via the via 28, through the left LED chip 12, back through the submount 24' to the back metal trace 34-2, back through the submount 24' to the next LED chip 12, and finally back through the submount 24' to the back metal trace 34-3.

[0044]

[0070] FIGS. 3A through 3C illustrate cross-sectional views in manufacturing steps for forming a plurality of light-emitting devices 36 that are similar to the light-emitting device 30 of FIGS. 2A through 2C and further include one or more underfill materials 38-1, 38-2. In this way, the description of the manufacturing steps of FIGS. 2A through 2C can be readily applied to the manufacturing steps of FIGS. 3A through 3C, along with the further details given below.

[0045]

[0071] Figure 3A is a cross-sectional view of a manufacturing step for forming a plurality of light-emitting devices 36, similar to the manufacturing steps illustrated in Figure 2A. In Figure 3A, a first underfill material 38-1 is formed on the LED wafer 10 and can fill other topographical changes associated with the streets 20 and the LED chips 12, anode contacts 16, and / or cathode contacts 18. The first underfill material 38-1 may first be formed to completely cover the LED chips 12, anode contacts 16, and cathode contacts 18 before applying a removal step to expose the surfaces of the anode contacts 16 and cathode contacts 18. The removal step may include grinding and / or polishing the first underfill material 38-1 to effectively planarize the anode contacts 16 and cathode contacts 18. In certain embodiments, the first underfill material 38-1 may be coplanar with the exposed surfaces of the anode contacts 16 and cathode contacts 18. The first underfill material 38-1 may include a light-modifying material and / or a light-reflecting material configured to redirect light propagating downward from the LED chips 12 to increase brightness. In certain embodiments, the first underfill material 38-1 may be formed by coating, dispensing using partial or full curing, or spin coating. The first underfill material 38-1 may include a ceramic material that enhances bonding, such as a ceramic paste, spin-on dielectric, and / or sol-gel reaction (e.g., an inorganic colloidal suspension and gelation in a continuous liquid phase). The second underfill material 38-2 can be formed on the submount wafer 22 in a manner and with materials similar to the first underfill material 38-1. In this way, the second underfill material 38-2 can cover topographical changes associated with the front metal traces 26-1, 26-2, or other features that may be present on the first side 22'. In other embodiments, the second underfill material 38-2 may be omitted.

[0046]

[0072] FIG. 3B is a cross-sectional view of a manufacturing step following FIG. 3A for forming a plurality of light-emitting devices 36 similar to the manufacturing steps illustrated in FIG. 2B. Thus, as described above, the LED wafer 10 is bonded to the submount wafer 22. As illustrated, the presence of the first underfill material 38-1 and the second underfill material 38-2 can effectively fill the gap between the submount wafer 22 and the LED wafer 10. In this way, an improved thermal contact area can be provided. As described above, in embodiments where the first underfill material 38-1 and the second underfill material 38-2 comprise a ceramic material, the ceramic material can form a ceramic bond therebetween that enhances the thermal conductivity of the light-emitting device 36 and improves mechanical integrity. In certain embodiments, the first underfill material 38-1 and the second underfill material 38-2 may not be formed prior to wafer bonding. Rather, the first underfill material 38-1 and the second underfill material 38-2 may be applied to fill the space between the LED wafer 10 and the submount wafer 22 after bonding. For example, the underfill materials 38-1, 38-2 may be applied with an appropriate viscosity to effectively suck up and fill the space between the LED wafer 10 and the submount wafer 22 before curing. In such embodiments, the first underfill material 38-1 and the second underfill material 38-2 can embody a single continuous layer.

[0047]

[0073] FIG. 3C is a cross-sectional view of a manufacturing step following FIG. 3B for forming a plurality of light-emitting devices 36 similar to the manufacturing steps illustrated in FIG. 2C. In this regard, the individual light-emitting devices 36 can be formed using the first underfill material 38-1 and the second underfill material 38-2 formed between the substrate 14' and the submount 24'. Similar to FIG. 2C, the substrate 14' may be optional in certain embodiments.

[0048]

[0074] The configurations of the front metal traces and the back metal traces of the submount wafers described above may be suitable for providing different electrical arrangements of wafer-bonded LED chips. The principles described are applicable to multiple chip light-emitting devices having electrical configurations of LED chips bonded in series, parallel, combinations of series and parallel, and individually addressable configurations. In certain embodiments, the submount wafers are formed with different patterns of back metal traces at different positions, and after wafer bonding with an LED wafer and subsequent singulation, some of the light-emitting devices may be formed with a first electrical configuration and other light-emitting devices from the same LED wafer may be formed with a second electrical configuration different from the first electrical configuration. Thus, by providing various back metallization patterns along the submount wafers, many different types of light-emitting devices can be manufactured simultaneously.

[0049]

[0075] Figures 4A and 4B illustrate a larger portion of the submount wafer 22 described above with respect to FIGS. 1B through 3C that provides a series connection between the LED chips of the corresponding light-emitting device. FIG. 4A is a view of a first side 22' of the submount wafer 22, and the overlaid vertical and horizontal dashed lines 32 form a grid of 16 different device regions, each device region including four pairs of front metal traces 26-1, 26-2. As described above, the front metal traces 26-1, 26-2 are configured to be bonded to the anode contact 16 and the cathode contact 18 of the LED chip 12, for example as illustrated in FIGS. 2A through 2C. For illustrative purposes, FIG. 4B is a view of the submount wafer 22 from the same orientation as FIG. 4A, except that the front metal traces 26-1, 26-2 have been removed and the submount structure 24 is shown transparently. The positions of the vias 28 are shown as illustrated. In this way, the positions of the back metal traces 34-1 through 34-5 are provided aligned corresponding to FIG. 4A. Thus, the illustration of FIG. 4A can be overlaid on the illustration of FIG. 4B without rotation.

[0050]

[0076] Figures 4C through 4E illustrate a portion of the submount wafer 22 from one of the device regions of FIGS. 4A and 4B. FIG. 4C is a partial view of FIG. 4A and illustrates four pairs of front metal traces 26-1, 26-2 for a single device region. In this way, four LED chips can be flip-chip attached to the pairs of front metal traces 26-1, 26-2. FIG. 4D is a view from partial FIG. 4B and illustrates back metal traces 34-1 through 34-5 along with the locations of vias 28. The back metal traces 34-1, 34-5 form an anode attachment pad and a cathode attachment pad for attachment to an external electrical connection, and the other back metal traces 34-2, 34-3, 34-4 form part of the interconnect path therebetween. To accommodate the various interconnect paths, certain back metal traces (e.g., 34-2, 34-3, 34-5) that are intended to electrically couple different LED chips together may have different shapes from each other, such as a wide shape (e.g., 34-2), a non-linear shape (e.g., 34-3), and / or a long shape (e.g., 34-4). The portion of the submount structure 24 in FIG. 4C is illustrated as a square, but other shapes such as a rectangle can also be provided by adjusting the position of the separation line corresponding to the dashed line 32 in FIGS. 4A and 4B.

[0051]

[0077] FIG. 4E is a view of the submount wafer 22 in which an image of FIG. 4C using the front metal traces 26-1, 26-2 is superimposed on an image of FIG. 4D aligned according to the vias 28. The vias 28 define the locations where specific ones of the front metal traces 26-1, 26-2 are electrically coupled through the submount structure 24 to corresponding back metal traces among 34-1 through 34-5. FIG. 4F illustrates an equivalent circuit 40 of the LED chips 12 that may be later attached to the front metal traces 26-1, 26-2 on the first side surface 22'. As illustrated, the arrangement of the vias 28 and the back metal traces 34-1 through 34-5 provides a series arrangement of LED chips applicable for high voltage applications.

[0052]

[0078] Figures 5A through 5D illustrate additional configurations of the submount wafer 22 of FIGS. 4A through 4D that provide parallel connections for corresponding light-emitting devices. FIG. 5A is a view of a first side 22' of the submount wafer 22 similar to FIG. 4C, but with different positions of one or more vias 28 for each of the front metal traces 26-1, 26-2 to accommodate parallel coupling, as will be described below. FIG. 5B is a view of the back 22'' of the submount wafer 22 from FIG. 5A. As illustrated, only two back metal traces 34-1, 34-2 are disposed with respect to the vias 28, where the back metal trace 34-1 forms an anode attachment pad and the back metal trace 34-2 forms a cathode attachment pad. FIG. 5C is a view of the submount wafer 22 with the image of FIG. 5A using the front metal traces 26-1, 26-2 overlaid on the image of FIG. 5B aligned according to the vias 28. The vias 28 define positions where specific ones of the front metal traces 26-1, 26-2 are electrically coupled to corresponding back metal traces of the back metal traces 34-1, 34-2 through the submount structure 24. As illustrated, each front metal trace 26-1 is electrically coupled to the back metal trace 34-1 and each front metal trace 26-2 is electrically coupled to the back metal trace 34-2. FIG. 5D illustrates an equivalent circuit 42 of the LED chips 12 that may be later attached to the front metal traces 26-1, 26-2 on the first side 22'. As illustrated, the arrangement of the vias 28 and the back metal traces 34-1, 34-2 provides a parallel arrangement for the LED chips 12. In certain embodiments, a single submount wafer 22 can include one or more regions configured to provide parallel connections for light-emitting devices, as illustrated in FIGS. 5A through 5D, and one or more other regions configured to provide series connections for light-emitting devices, as illustrated in FIGS. 4A through 4F.

[0053]

[0079] Figures 6A through 6D illustrate another additional configuration of the submount wafer 22 of FIGS. 4A through 4D that provides parallel and series connections for corresponding light emitting devices. FIG. 6A is a view of a first side 22' of the submount wafer 22 similar to FIG. 4C, but with the positions of one or more vias 28 for each of the front metal traces 26-1, 26-2 being different to accommodate parallel and series coupling, as will be described later. FIG. 6B is a view of the back 22'' of the submount wafer 22 from FIG. 6A. As illustrated, only three back metal traces 34-1 through 34-3 are disposed for the vias 28, with the back metal traces 34-1, 34-3 forming anode attachment pads and cathode attachment pads, and the back metal trace 34-2 forming part of the electrical interconnection therebetween. FIG. 6C is a view of the submount wafer 22 with the image of FIG. 6A using the front metal traces 26-1, 26-2 overlaid on the image of FIG. 6B aligned according to the vias 28. The vias 28 define the positions where specific ones of the front metal traces 26-1, 26-2 are electrically coupled via the submount structure 24 to corresponding ones of the back metal traces 34-1 through 34-3. FIG. 6D illustrates an equivalent circuit 44 of LED chips 12 that may be later attached to the front metal traces 26-1, 26-2 on the first side 22'. As illustrated, the arrangement of the vias 28 and the back metal traces 34-1 through 34-3 provides parallel and series arrangements for the LED chips 12. In certain embodiments, a single submount wafer 22 can include one or more regions configured to provide parallel connections for light emitting devices, as illustrated in FIGS. 6A through 6D, and one or more other regions configured to provide series connections for light emitting devices, as illustrated in FIGS. 4A through 4F. In yet further embodiments, a single submount wafer 22 can include different regions according to each of FIGS. 4A through 4F, FIGS. 5A through 5D, and FIGS. 6A through 6D.

[0054]

[0080] Figures 7A through 7D illustrate an alternative configuration for submount wafer 46 including a multilayer structure with vias and interconnects that route conductive paths between front metal traces 26-1, 26-2 and back metal traces 34-1, 34-2. The multi-layer configuration for submount structure 24 may include multiple sublayers 48-1 through 48-3 that enhance the flexibility of routing electrical connections. In certain embodiments, sublayers 48-1 through 48-3 may include a stacked structure in which vias 28 and interconnects 50 are formed. The stacked structure may include a multi-layer ceramic structure such as a multi-layer printed circuit board.

[0055]

[0081] Figure 7A is a front view of a portion of submount wafer 46 similar to the figure provided by FIG. 4C. Thus, four pairs of front metal traces 26-1, 26-2 are illustrated for a single device region. However, as with the previous embodiments, any number of pairs of front metal traces 26-1, 26-2 can be provided depending on the number of LED chips intended for each light emitting device. Figure 7B is a back view of submount wafer 46 of Figure 7A, illustrating two back metal traces 34-1, 34-2 that form anode attachment pads and cathode attachment pads for corresponding light emitting devices. Although there are only two back metal traces 34-1, 34-2, the multi-layer configuration of submount structure 24 can implement any number of series, parallel, and series-parallel arrangements. Figure 7C is a cross-sectional view taken along section line 7C-7C of Figure 7A, and Figure 7D is a cross-sectional view taken along section line 7D-7D of Figure 7A. As illustrated, front traces 26-1, 26-2 may be formed on sublayer 48-1, and a number of vias 28 extend from each of front traces 26-1, 26-2 across sublayer 48-1. Interconnect 50 can be disposed within the next sublayer 48-2 that horizontally redirects the conductive path within submount structure 24. In the cross-section of Figure 7C, another via 28 is disposed within the next sublayer 48-3, providing a conductive path to back metal trace 34-1. Conductive paths to the other back metal trace 34-2 can also be disposed at other locations outside the cross-sections of Figures 7C and 7D.

[0056]

[0082] As described above, the multilayer structure may improve the design flexibility for the submount wafer 46. For example, the backside metal traces 34-1, 34-2 may form a single anode and a single cathode having a pattern, which is not necessarily associated with each position of the vias 28 as illustrated in FIG. 7B. Thus, other areas on the backside are open for including other functions such as neutral heat pads for heat dissipation purposes. In further embodiments, the multilayer structure enables additional anode and cathode contacts and enables the provision of individual addressing for the LED chips. Light emitting devices of various shapes such as squares and rectangles can be formed from the submount wafer having the multilayer structure.

[0057]

[0083] It is contemplated that any of the foregoing aspects and / or various individual aspects and features described herein may be combined for further advantages. Any of the various embodiments disclosed herein may be combined with one or more other disclosed embodiments, unless the contrary is indicated herein.

[0058]

[0084] Those skilled in the art will recognize improvements and changes to the preferred embodiments of the present disclosure. All such improvements and changes are considered to be within the concepts disclosed herein and within the scope of the appended claims.

Claims

1. Providing an LED wafer comprising a plurality of light-emitting diode (LED) chips, each LED chip of the plurality of LED chips comprising an anode contact and a cathode contact; Providing the submount wafer having a first metallization pattern on a front surface of the submount wafer and a second metallization pattern on a back surface of the submount wafer, the second metallization pattern being electrically coupled to the first metallization pattern; Bonding the LED wafer to the front surface of the submount wafer such that the anode contact and the cathode contact of each LED chip are electrically coupled to the first metallization pattern; Individually separating the LED wafer and the submount wafer to form a plurality of light-emitting devices, each light-emitting device of the plurality of light-emitting devices comprising a substrate formed from the LED wafer, an array of LED chips of the plurality of LED chips, and a submount formed from the submount wafer; A method comprising the above steps.

2. The method according to claim 1, wherein the LED wafer comprises a substrate structure subdivided to form each substrate of the plurality of light-emitting devices, and the submount wafer comprises a submount structure subdivided to form each submount of the plurality of light-emitting devices.

3. The method according to claim 2, wherein the substrate structure comprises a sapphire wafer on which the plurality of LED chips are formed.

4. The method according to claim 2, wherein the submount structure comprises aluminum oxide or aluminum nitride.

5. The method according to claim 1, wherein the first metallization pattern comprises another pair of an anode metal trace and a cathode metal trace respectively bonded to the anode contact and the cathode contact of each LED chip of the plurality of LED chips.

6. The second metallization pattern includes a first metal trace forming an anode attachment pad, a second metal trace forming a cathode attachment pad, and a third metal trace forming a part of a conductive path between the first metal trace and the second metal trace, the method according to claim 5.

7. The method according to claim 1, wherein a distance between adjacent LED chips among the plurality of LED chips is 40 micrometers (μm) or less.

8. The method according to claim 7, wherein the distance is in a range of 10 μm to 40 μm.

9. The method according to claim 1, wherein the plurality of LED chips are subdivided from a common epitaxial LED structure.

10. Bonding the LED wafer to the front surface of the submount wafer includes thermocompression bonding, eutectic bonding, transient liquid phase bonding, bump bonding, or solder paste bonding for bonding the anode contact and the cathode contact to the first metallization pattern, the method according to claim 1.

11. Bonding the LED wafer to the front surface of the submount wafer includes forming a ceramic bond between the LED wafer and the submount wafer, the method according to claim 1.

12. The method according to claim 1, further comprising forming an underfill material in a gap between the LED wafer and the submount wafer.

13. The array of LED chips is electrically connected in series, parallel, or series-parallel, the method according to claim 1.

14. The second metallization pattern is a first metal trace pattern configured to electrically couple the array of LED chips for a first light emitting device among the plurality of light emitting devices to a first electrical configuration, and a second metal trace pattern configured to electrically couple the array of LED chips for a second light emitting device among the plurality of light emitting devices to a second electrical configuration the method according to claim 1.

15. The method according to claim 1, wherein the submount structure comprises a multilayer ceramic structure.

16. Providing an LED wafer comprising a plurality of light emitting diode (LED) chips on a substrate structure, Forming a first underfill material on the LED wafer; Providing the submount wafer having a first metallization pattern on a front surface of the submount wafer and a second metallization pattern on a back surface of the submount wafer, the second metallization pattern being electrically coupled to the first metallization pattern; Bonding the LED wafer to the front surface of the submount wafer such that the plurality of LED chips are electrically coupled to the first metallization pattern; Individualizing the LED wafer and the submount wafer to form a plurality of light emitting devices, each light emitting device of the plurality of light emitting devices comprising an array of LED chips of the plurality of LED chips and a submount formed from the submount wafer; A method comprising.

17. The method of claim 16, wherein the LED wafer comprises a plurality of streets defining boundaries of each LED chip of the plurality of LED chips, and the first underfill material is disposed to fill a portion of the plurality of streets.

18. The method of claim 16, wherein the first underfill material comprises a light reflecting material configured to reflect or redirect light from the plurality of LED chips.

19. The method of claim 16, wherein the first underfill material is formed on the LED wafer after the LED wafer is attached to the submount wafer.

20. The method of claim 16, wherein the first underfill material is formed on the LED wafer before the LED wafer is attached to the submount wafer.

21. The method of claim 20, further comprising forming a second underfill material on the submount wafer before the LED wafer is attached to the submount wafer.

22. The method of claim 21, wherein the first underfill material and the second underfill material form a ceramic bond between the LED wafer and the submount wafer.

23. The method according to claim 16, wherein the array of LED chips is electrically coupled in series, parallel, or series-parallel.

Images