Display substrate and display device

Abstract

A display substrate and a display device, in which a display region has a bottom edge extending along a horizontal direction and a left edge extending along a vertical direction, the display region includes a left display region and a right display region, the left display region includes a first edge display region and a first intermediate display region extending along the left edge, the horizontal direction intersects with the vertical direction, a frame region surrounds at least a portion of the display region, a first power supply voltage lead provides a first power supply voltage and is located in the frame region, the first power supply voltage lead includes a bottom lead extending along a portion of the bottom edge corresponding to the first edge display region and does not extend along a portion of the bottom edge corresponding to the first intermediate display region, the first power supply voltage line includes an edge voltage line located at the edge of the first edge display region and an intermediate voltage line located in the first intermediate display region, the edge voltage line is directly connected to the bottom lead to provide the first power supply voltage to sub-pixels located in the first edge display region, and the intermediate voltage line is separated from the bottom lead.

Description

[Technical Field]

[0001] This application claims priority from Chinese Patent Application No. 202210898307.2, filed on July 28, 2022, the entire contents of which are incorporated herein by reference.

[0002] At least one embodiment of the present disclosure relates to a display substrate and a display device. [Background technology]

[0003] Compared to conventional liquid crystal displays (LCDs), organic light-emitting diode (OLED) display products have advantages such as self-luminescence, a wide color gamut, high contrast, and lightness and thinness, and are therefore widely used in fields such as mobile phones and tablet computers.

[0004] Generally, multiple signal lines, e.g., data lines, in the display area need to be drawn to the fanout region and then connected to an integrated circuit (IC) through the fanout region, which is located in the border area that does not perform display functions. As people continue to pursue better visual effects in display products, narrow borders and full-screen displays have gradually become the development trend of current OLED display products. Summary of the Invention [Means for solving the problem]

[0005] At least one embodiment of the present disclosure provides a display substrate, the display substrate including a display region, a non-display region, a first power supply voltage lead, and a first power supply voltage line, wherein the display region has a subpixel disposed therein and a bottom edge extending along a horizontal direction and a left edge extending along a vertical direction, the horizontal direction intersects with the vertical direction, and a boundary line extending along the vertical direction divides the display region into a left display region and a right display region, the left display region includes a first edge display region extending along the left edge and a first middle display region located in the first edge display region and adjacent to the right display region, the non-display region includes a frame region surrounding at least a part of the display region, and the first power supply voltage lead is configured to provide a first power supply voltage. and is located in the frame region, the first power supply voltage lead includes a bottom lead extending along a portion of the bottom edge corresponding to a first edge display region and does not extend along a portion of the bottom edge corresponding to the first intermediate display region, the first power supply voltage line includes an edge voltage line located at the edge of the first edge display region and an intermediate voltage line located in the first intermediate display region, the edge voltage line is directly connected to the bottom lead to provide the first power supply voltage to the sub-pixel located in the first edge display region, and the intermediate voltage line is separated from the bottom lead.

[0006] For example, in a display substrate according to at least one embodiment of the present disclosure, the first power supply voltage line includes a vertical voltage line extending along the vertical direction and a horizontal voltage line extending along the horizontal direction, the vertical voltage line and the horizontal voltage line are installed in a different layer from each other, the vertical voltage line includes an edge vertical voltage line located in the first edge display region, the horizontal voltage line includes an edge horizontal voltage line located in the first edge display region and crossing the edge vertical voltage line, the edge vertical voltage line and the edge horizontal voltage line constitute the edge voltage line, the first power supply voltage lead further includes a left lead extending along the left edge of the display region, the edge vertical voltage line is directly connected to the bottom lead, and the edge horizontal voltage line is directly connected to the left lead.

[0007] For example, in a display substrate according to at least one embodiment of the present disclosure, the sub-pixels include a driving transistor, a light-emitting device, and a data transistor, the driving transistor is configured to control a magnitude of a driving current flowing through the light-emitting device, the light-emitting device is configured to receive the driving current and be driven by the driving current to emit light, the data transistor is configured to write a data signal to a gate of the driving transistor in response to a first control signal, the data line is configured to transmit the data signal to the sub-pixel, the display area includes a lower display area and an upper display area, the lower display area is close to the lower edge and the upper display area is located vertically away from the lower edge of the lower display area, the lower display area includes a first area and a second area, and the first area is located horizontally. the data lines passing through the first sub-region and the second region include a first connection line extending along the vertical direction in the first sub-region and a second connection line extending along the horizontal direction in the second region, the first connection line being installed in the same layer as the vertical voltage line, the second connection line being installed in the same layer as the horizontal voltage line, the first connection line and the second connection line of the same data line being electrically connected by a first connection hole, the first sub-region is located in the first intermediate display region, at least a portion of the second region is located in the intermediate display region, the first sub-region has a left end point that is closest to the left edge of the display region in the horizontal direction, and a straight line extending along the vertical direction and passing through the left end point is a boundary line between the first edge display region and the first intermediate display region.

[0008] For example, in a display substrate according to at least one embodiment of the present disclosure, the boundary line passes through the second region and divides the second region into a first sub-region close to the left edge of the display region and a second sub-region away from the left edge of the display region, the first sub-region is located in the first edge display region, the second sub-region is located in the first middle display region, the lower display region further includes a third region, the third region is located in the first edge display region and is located on a side of the second region away from the first region in the horizontal direction, the edge horizontal voltage line includes a bottom edge horizontal voltage line located in the third region, and the edge vertical voltage line passes through the third ... bottom edge horizontal a first fracture surface cuts a right end of the lower edge lateral voltage line opposite to the left end of the lower edge lateral voltage line and the second connection line in the second region; the vertical voltage lines include a plurality of the edge vertical voltage lines and a plurality of the edge lateral voltage lines; the plurality of edge vertical voltage lines and the plurality of edge lateral voltage lines are intertwined to form a lattice; the lattice includes a plurality of the first intersection points; and at each position of some of the plurality of first intersection points, one edge vertical voltage line is electrically connected to one lower edge lateral voltage line through a first via.

[0009] For example, in a display substrate according to at least one embodiment of the present disclosure, the plurality of edge vertical voltage lines are electrically connected to the plurality of edge horizontal voltage lines through a plurality of the first vias, and a planar pattern formed by the positions of the plurality of first vias is a connecting line segment located in the third region, and the extension direction of the connecting line segment intersects both the first direction and the second direction.

[0010] For example, in a display substrate according to at least one embodiment of the present disclosure, the third region is a corner region defined by a second side approaching the left edge in the horizontal direction of the second region, the left edge, and the bottom edge.

[0011] For example, in a display substrate according to at least one embodiment of the present disclosure, the frame region includes a frame corner region surrounding the corner region, and a grid-shaped auxiliary first power supply voltage line is installed in the frame corner region, and the grid-shaped auxiliary first power supply voltage line includes a plurality of vertical auxiliary voltage lines and a plurality of horizontal auxiliary voltage lines. A plurality of vertical auxiliary voltage lines extend along the vertical direction and are arranged in the same layer as the vertical voltage lines, a first end of each of the plurality of vertical auxiliary voltage lines in the vertical direction is directly connected to the first power supply voltage lead, and a second end of each of the plurality of vertical auxiliary voltage lines opposite to the first end in the vertical direction is electrically connected to one of the edge vertical voltage lines passing through the corner region; a plurality of horizontal auxiliary voltage lines extend along the horizontal direction and are arranged in the same layer as the plurality of vertical auxiliary voltage lines, one end of each of the plurality of horizontal auxiliary voltage lines in the horizontal direction is directly connected to the first power supply voltage lead, and a second end of each of the plurality of horizontal auxiliary voltage lines opposite to the first end in the horizontal direction is electrically connected to one of the edge vertical voltage lines.

[0012] For example, in a display substrate according to at least one embodiment of the present disclosure, the display area includes a pixel array including a plurality of pixel rows extending along the horizontal direction and a plurality of pixel columns extending along the vertical direction, the plurality of pixel rows including a plurality of edge pixel rows close to the bottom edge, the plurality of horizontal auxiliary voltage lines corresponding one-to-one to the plurality of edge pixel rows, each edge pixel row among the plurality of edge pixel rows including an edge sub-pixel closest to the left edge, the plurality of edge vertical voltage lines including an edge-most vertical voltage line of an edge sub-pixel passing through each of the edge pixel rows, a second end of each of the plurality of horizontal auxiliary voltage lines electrically connected to the edge-most vertical voltage line passing through the corresponding edge pixel row, and electrically connected to the edge horizontal voltage line passing through the corresponding edge pixel row via a first edge via.

[0013] For example, in a display substrate according to at least one embodiment of the present disclosure, the horizontal voltage lines further include a plurality of first horizontal voltage lines, the plurality of first horizontal voltage lines are arranged in the vertical direction and located in the upper display region, the left ends of the first horizontal voltage lines are electrically connected to the left lead, the edge horizontal voltage lines further include an upper edge horizontal voltage line located in the upper display region, the upper edge horizontal voltage line is a part of one of the first horizontal voltage lines, the vertical voltage lines further include a plurality of intermediate vertical voltage lines, which are arranged in the horizontal direction, pass through a part of the first intermediate display region along the vertical direction, pass through the upper display region, and extend to the front The plurality of intermediate vertical voltage lines, the plurality of edge vertical voltage lines, and the plurality of first horizontal voltage lines are intertwined to form a lattice, the plurality of edge vertical voltage lines and the plurality of first horizontal voltage lines intersect at a plurality of auxiliary intersections within the first edge indication region, at each position of some of the plurality of auxiliary intersections, one of the edge vertical voltage lines is electrically connected to one of the first horizontal voltage lines through an auxiliary via, and the plurality of edge vertical voltage lines are electrically connected to the plurality of first horizontal voltage lines through a plurality of the auxiliary vias, and a planar pattern formed by the positions of the plurality of auxiliary vias is an auxiliary line segment located in the first edge indication region.

[0014] For example, in a display substrate according to at least one embodiment of the present disclosure, the extension direction of the auxiliary line segments is the same as the extension direction of the connecting line segments, the display substrate includes a plurality of the auxiliary line segments, and the connecting line segments and the plurality of auxiliary line segments are arranged at intervals along the vertical direction.

[0015] For example, in a display substrate according to at least one embodiment of the present disclosure, the display area further includes an upper edge opposite to the lower edge, the first power supply voltage lead further includes an upper lead extending along the upper edge, the upper lead is electrically connected to the left lead, the upper end of the edge vertical voltage line is connected to the upper lead, the lower end of the edge vertical voltage line opposite to the upper end is directly connected to the lower lead, the vertical voltage lines include an intermediate vertical voltage line located in the first intermediate display area, and the intermediate vertical voltage line includes a first vertical voltage line and a second vertical voltage line. A first vertical voltage line passes through the upper display region and at least a part of the second region in the vertical direction, an upper end of the first vertical voltage line is electrically connected to the upper lead, a lower end of the first vertical voltage line opposite to the upper end thereof and the first connecting line in the first sub-region are cut by a second fracture surface, a second vertical voltage line passes through the upper display region and the first region in the vertical direction in the vertical direction, the horizontal voltage lines include an intermediate horizontal voltage line located in the first region, the intermediate horizontal voltage line and the second connecting line in the second region are cut by a third fracture surface, the second vertical voltage line and the intermediate horizontal voltage line intersect at a second intersection, and the second vertical voltage line is electrically connected to the intermediate horizontal voltage line at the second intersection through a second via.

[0016] For example, in a display substrate according to at least one embodiment of the present disclosure, the plurality of first horizontal voltage lines and the plurality of second vertical voltage lines intersect at a plurality of third intersections, and at each position of at least some of the plurality of third intersections, one of the first horizontal voltage lines is electrically connected to one of the second vertical voltage lines through a third via.

[0017] For example, in a display substrate according to at least one embodiment of the present disclosure, the display area further includes a right edge opposite the left edge, the first power lead further includes a right lead extending along the right edge, the right lead being electrically connected to the upper lead, each of the plurality of first horizontal voltage lines passing through the upper display area along the horizontal direction, and the right end of each of the plurality of first horizontal voltage lines opposite its left end being electrically connected to the right lead.

[0018] For example, in a display substrate according to at least one embodiment of the present disclosure, the plurality of intermediate vertical voltage lines and the plurality of first horizontal voltage lines intersect with each other at a plurality of fourth intersections within the upper display area, and at each position of some of the plurality of fourth intersections, one of the intermediate vertical voltage lines is electrically connected to one of the first horizontal voltage lines via a fourth via, and a planar pattern consisting of the positions of the plurality of fourth vias is a polygonal line.

[0019] For example, in a display substrate according to at least one embodiment of the present disclosure, the folded line includes a plurality of sub-folded lines extending from the left edge to the right edge, each of the sub-folded lines includes a plurality of folded line portions whose ends are connected to their ends, the plurality of folded line portions include a first line segment extending along a first direction and a second line segment extending along a second direction, the first direction intersects with the second direction, and both the first direction and the second direction intersect with the horizontal direction and the vertical direction, a first end of the first line segment and a first end of the second line segment intersect at an upper vertex, the vertices of the plurality of sub-folded lines are located on a second vertical voltage line, and the fourth vias at the vertex positions are all the second vias.

[0020] For example, in a display substrate according to at least one embodiment of the present disclosure, each of the plurality of sub-folded lines has a W-shape.

[0021] For example, in a display substrate according to at least one embodiment of the present disclosure, the W-shaped sub-folded line includes the first line segment, the second line segment, the third line segment, and the fourth line segment, the first line segment and the second line segment are located between the third line segment and the fourth line segment, the third line segment is connected to the first line segment, the fourth line segment is connected to the second line segment, the first line segment is approximately parallel to the fourth line segment, and the second line segment is approximately parallel to the third line segment.

[0022] For example, in a display substrate according to at least one embodiment of the present disclosure, the vertical direction is perpendicular to the horizontal direction, the angle formed between the first line segment and the horizontal direction is 45°, and the angle formed between the second line segment and the horizontal direction is 45°.

[0023] For example, in a display substrate according to at least one embodiment of the present disclosure, the auxiliary line segment is located between the third line segments of two adjacent sub-folded lines in the vertical direction.

[0024] For example, in a display substrate according to at least one embodiment of the present disclosure, the connecting line segment, the auxiliary line segment, and the third line segment are substantially parallel to each other.

[0025] For example, in a display substrate according to at least one embodiment of the present disclosure, the second vertical voltage line divides the first region into the first sub-region and the second sub-region, the structure of the first sub-region and the structure of the second sub-region are approximately axially symmetric with respect to the second vertical voltage line, the lower display region includes a fourth region, the structure of the fourth region and the structure of the second region are approximately axially symmetric with respect to the second vertical voltage line, the data line passing through the first region and the fourth region includes a third connecting line extending along the vertical direction in the second sub-region and a fourth connecting line extending along the horizontal direction in the fourth region, the third connecting line is installed in the same layer as the vertical voltage line, the fourth connecting line is installed in the same layer as the horizontal voltage line, the third connecting line and the fourth connecting line of the same data line are electrically connected by a second connecting hole, and the right end opposite to the left end of the intermediate horizontal voltage line located in the first region and the fourth connecting line in the fourth region are cut by a fourth fracture surface.

[0026] For example, in a display substrate according to at least one embodiment of the present disclosure, the display substrate includes a plurality of the first connection lines, a plurality of the second connection lines, a plurality of the third connection lines, and a plurality of the fourth connection lines, the plurality of first connection lines and the plurality of second connection lines are electrically connected to each other by a plurality of the first connection holes, the plurality of third connection lines and the plurality of fourth connection lines are electrically connected to each other by a plurality of the second connection holes, a plane pattern formed by the plurality of first connection holes is a fifth line segment, and the fifth line segment is a boundary between the first region and the second region, The plane pattern consisting of the plurality of second connection holes is a sixth line segment, the sixth line segment is the boundary between the first region and the fourth region, the lower display region further includes a fifth region, the structure of the fifth region and the structure of the third region are approximately axially symmetrical with respect to the second vertical voltage line, the plane pattern of the plurality of fifth vias symmetrical to the plurality of first vias in the fifth region is a seventh line segment, and the plane pattern formed by sequentially connecting the connection line segment, the fifth line segment, the sixth line segment and the seventh line segment is the same as the plane pattern of each sub-broken line among the plurality of sub-broken lines.

[0027] For example, in a display substrate according to at least one embodiment of the present disclosure, the planar shape of the first region is a first triangle, the planar shape of the second region is a second triangle, a first side of the first triangle that approaches the left edge in the horizontal direction overlaps with at least a portion of a first side of the second triangle that moves away from the left edge of the display region in the horizontal direction, the two lower vertices of the first triangle are located at the lower edge of the display region, the left vertex of the two lower vertices of the first triangle that approaches the left edge is the left endpoint of the first sub-region, the first triangle is an isosceles triangle, and the second vertical voltage line is approximately the perpendicular bisector of the base of the isosceles triangle.

[0028] For example, in a display substrate according to at least one embodiment of the present disclosure, the frame region includes a left frame region extending along the left edge, a plurality of auxiliary connecting lines extending along the horizontal direction are installed in the left frame region, the plurality of auxiliary connecting lines are installed in the same layer as the edge vertical voltage lines, the display region includes a pixel array, the pixel array includes a plurality of pixel rows extending along the horizontal direction and a plurality of pixel columns extending along the vertical direction, the plurality of pixel columns includes an edge pixel column closest to the left edge, the plurality of edge vertical voltage lines include an outer edge vertical voltage line passing through the edge pixel column, a left end of each of the plurality of auxiliary connecting lines in the horizontal direction electrically connected to the left lead, a right end of each of the plurality of auxiliary connecting lines opposite to the left end in the horizontal direction electrically connected to the outer edge vertical voltage line and electrically connected to the left end of a corresponding one of the first horizontal voltage lines through a second edge via.

[0029] For example, in a display substrate according to at least one embodiment of the present disclosure, the right display region includes a second edge display region extending along the right edge and a second intermediate display region located on the side of the second edge display region closer to the left display region, the second edge display region and the first edge display region being symmetrical with respect to an axis of symmetry extending along the vertical direction, and the second intermediate display region and the first intermediate display region being axially symmetrical with respect to the second vertical voltage line.

[0030] For example, in a display substrate according to at least one embodiment of the present disclosure, the display substrate further includes a second power supply voltage line configured to provide the subpixel with a second power supply voltage different from the first power supply voltage, the vertical voltage line being arranged in the same layer as the data line in the upper display area, and the horizontal voltage line being arranged in the same layer as the second power supply voltage line.

[0031] At least one embodiment of the present disclosure further provides a display device including any one of the display substrates according to the embodiments of the present disclosure. [Brief explanation of the drawings]

[0032] In order to more clearly explain the technical solutions of the embodiments of the present invention, the drawings of the embodiments are briefly described below. Obviously, the drawings described below only relate to some of the embodiments of the present invention and do not limit the present invention.

[0033] [Figure 1] 1 is a schematic overall plan view of a display substrate according to an embodiment of the present disclosure. [Figure 2] 2 is a partially enlarged schematic diagram including a lower display region and a part of an upper display region in FIG. 1. FIG. [Figure 3A] FIG. 3 is a partially enlarged schematic view of a region R1 in FIG. 2. [Figure 3B] FIG. 3 is a schematic diagram of a partial film layer in region R3 in FIG. 2. [Figure 3C] FIG. 3 is a schematic diagram of a partial film layer in region R3 in FIG. 2. [Figure 3D] FIG. 3 is a schematic diagram of a partial film layer in region R3 in FIG. 2. [Figure 4] 2 is a partially enlarged schematic view including regions R2 and R3 in FIG. 1. FIG. [Figure 5A] FIG. 5 is a partially enlarged schematic view of a region R2 in FIG. [Figure 5B] FIG. 5 is a schematic diagram of a partial film layer in region R2 in FIG. 4. [Figure 5C] FIG. 5 is a schematic diagram of a partial film layer in region R2 in FIG. 4. [Figure 5D] FIG. 5 is a schematic diagram of a partial film layer in region R2 in FIG. 4. [Figure 6A] FIG. 5 is a partially enlarged schematic view of a region R3 in FIG. [Figure 6B] FIG. 4 is a schematic diagram of a partial film layer in region R3 in FIG. 3. [Figure 6C] FIG. 4 is a schematic diagram of a partial film layer in region R3 in FIG. 3. [Figure 6D] FIG. 4 is a schematic diagram of a partial film layer in region R3 in FIG. 3. [Figure 7A] FIG. 4 is a partially enlarged schematic view of a region R4 in FIG. 3. [Figure 7B] FIG. 4 is a schematic diagram of a partial film layer in region R4 in FIG. 3. [Figure 7C]FIG. 4 is a schematic diagram of a partial film layer in region R4 in FIG. 3. [Figure 7D] FIG. 4 is a schematic diagram of a partial film layer in region R4 in FIG. 3. [Figure 8A] FIG. 4 is a partially enlarged schematic view of a region R5 in FIG. 3. [Figure 8B] FIG. 4 is a schematic diagram of a partial film layer in region R5 in FIG. 3. [Figure 8C] FIG. 4 is a schematic diagram of a partial film layer in region R5 in FIG. 3. [Figure 9] FIG. 4 is a partially enlarged schematic view of a region R6 in FIG. 3. [Figure 10] FIG. 2 is an equivalent circuit diagram of a pixel circuit according to an embodiment of the present disclosure. [Figure 11A] FIG. 2 is a schematic diagram including different film layers in a pixel circuit. [Figure 11B] FIG. 2 is a schematic diagram including different film layers in a pixel circuit. [Figure 11C] FIG. 2 is a schematic diagram including different film layers in a pixel circuit. [Figure 11D] FIG. 2 is a schematic diagram including different film layers in a pixel circuit. [Figure 11E] FIG. 2 is a schematic diagram including different film layers in a pixel circuit. [Figure 11F] FIG. 2 is a schematic diagram including different film layers in a pixel circuit. [Figure 11G] FIG. 2 is a schematic diagram including different film layers in a pixel circuit. [Figure 11H] FIG. 2 is a schematic diagram including different film layers in a pixel circuit. [Figure 11I] FIG. 11B is a schematic diagram of the film layers shown in FIGS. 11A to 11F. [Figure 12] 1 is a schematic diagram of a display substrate according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0034] In order to make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be described clearly and completely below with reference to the drawings of the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the described embodiments of the present invention, any other embodiments that a person skilled in the art can obtain without inventive efforts fall within the protection scope of the present invention.

[0035] Unless otherwise defined, technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art in the field to which the present invention belongs. The terms "first," "second," and similar terms used in the present patent application specification and claims do not denote any order, number, or importance, but are merely used to distinguish different components. Similar terms such as "comprise" or "include" indicate that the elements or components described before the term cover the elements or components listed after the term and their equivalents, and do not exclude other elements or components. Terms such as "inside," "outside," "up," and "down" only refer to relative positional relationships, and if the absolute position of the described object changes, the relative positional relationships may also change correspondingly.

[0036] The drawings in this disclosure are not strictly drawn to scale, and the numbers of horizontal voltage lines, vertical voltage lines, and vias on the display substrate are not limited to the numbers shown in the drawings, and the specific dimensions and numbers of each structure may be determined according to actual needs. The drawings described in this disclosure are merely structural schematic diagrams.

[0037] Characteristic features such as "parallel," "perpendicular," and "same" as used in this disclosure all include strict features such as "parallel," "perpendicular," and "same," as well as features with a certain degree of error such as "almost parallel," "almost perpendicular," and "almost the same," and indicate that the feature is within an acceptable deviation range from a particular value determined by a person skilled in the art, taking into account the errors involved in the measurement and measurement of a particular quantity (e.g., limitations of the measurement system). For example, "almost" can indicate that the feature is within one or more standard deviations, or within 10% or 5% of the value.

[0038] Unless the number of a component is specifically indicated below in the description of the embodiments of the present disclosure, the component may be one, may be multiple, or may be understood to be at least one. "At least one" refers to one or multiple, and "multiple" refers to at least two.

[0039] In the embodiments of the present disclosure, the term "same layer" refers to the relationship between multiple film layers formed from the same material through the same step (e.g., one-step patterning process). The term "same layer" does not necessarily mean that the thicknesses of the multiple film layers are the same or that the heights of the multiple film layers in a cross-sectional view are the same.

[0040] Terms indicating directions, such as "vertical," "horizontal," "upper," "lower," "left," and "right," used in this disclosure are merely intended to indicate relative positional relationships. If the absolute position of the described object changes, the relative positional relationships may change accordingly, and are not limited to the directions shown in the drawings of the specification. For example, the "upper edge," "lower edge," "left edge," and "right edge" are not limited to the up, down, left, and right directions shown in the drawings, but may satisfy the limited relative positional relationships. The "left display area" and the "right display area" are also not limited to the left and right directions in the drawings of the specification of the present application, but may satisfy the limited relative positional relationships. The "upper display area" and the "lower display area" are also not limited to the left and right directions in the drawings of the specification of the present application, but may satisfy the limited relative positional relationships.

[0041] At least one embodiment of the present disclosure provides a display substrate, the display substrate including a display region, a non-display region, a first power supply voltage lead, and a first power supply voltage line, the display region having subpixels disposed therein and a bottom edge extending along a horizontal direction and a left edge extending along a vertical direction, the horizontal direction intersecting the vertical direction, a boundary line extending along the vertical direction dividing the display region into a left display region and a right display region, the left display region including a first edge display region extending along the left edge and a first middle display region located in the first edge display region and adjacent to the right display region, the non-display region including a frame region surrounding at least a part of the display region, and the first power supply voltage lead configured to provide a first power supply voltage. and is located in the frame region, the first power supply voltage lead includes a bottom lead extending along a portion of the bottom edge corresponding to a first edge display region and not extending along a portion of the bottom edge corresponding to the first intermediate display region, the first power supply voltage line includes an edge voltage line located at the edge of the first edge display region and an intermediate voltage line located in the first intermediate display region, the edge voltage line is directly connected to the bottom lead to provide the first power supply voltage to the sub-pixel located in the first edge display region, and the intermediate voltage line is separated from the bottom lead.

[0042] At least one embodiment of the present disclosure further provides a display device including any one of the display substrates according to the embodiments of the present disclosure.

[0043] 1 is an exemplary overall plan view of a display substrate according to an embodiment of the present disclosure, and FIG. 2 is a partially enlarged schematic view including a lower display region and a partial upper display region in FIG. 1. For example, as shown in FIG. 1, a display substrate 10 according to at least one embodiment of the present disclosure includes a display region 1, a frame region 2, a first power supply voltage lead 4, and a first power supply voltage line vss. The display region 1 includes subpixels and has a bottom edge 1a extending along a horizontal direction X and a left edge 1b extending along a vertical direction Y. The horizontal direction intersects with the vertical direction, e.g., perpendicular to the vertical direction; of course, in another embodiment, the horizontal direction may not be perpendicular to the vertical direction. The display region 1 includes a left display region 11 and a right display region 12 arranged in the horizontal direction X. For example, a partition line ML extending along the vertical direction Y divides the display area 1 into a left display area 11 and a right display area 12, and the partition line ML is, for example, a perpendicular bisector of the lower edge 1a, thereby making the left display area 11 and the right display area 12 symmetrical and providing a uniform display effect across the entire display substrate 10. However, the partition line ML is not limited to being a perpendicular bisector of the lower edge 1a. The left display area 11 includes a first edge display area 11P extending along the left edge 1b and a first intermediate display area 11M located in the first edge display area 11P and close to the right display area 12. A frame area 2 is a non-display area that surrounds at least a portion of the display area 11. For example, the display substrate 10 may further include a pad 3, the pad 3 being located on the side of the lower edge 1a away from the display area 1, a first power supply voltage lead 4 being connected to the pad 3 to provide a first power supply voltage VSS, and being located within the frame area 2, the first power supply voltage lead 4 including a bottom lead 41 extending along a portion of the lower edge 1a corresponding to the first edge display area 11P, but not extending along a portion of the lower edge 1a corresponding to the first intermediate display area 11M, the first power supply voltage line vss including an edge voltage line LP located in the first edge display area 11P and an intermediate voltage line LM located in the first intermediate display area 11M, the edge voltage line LP contacting and electrically connected to the bottom lead 41 to provide the first power supply voltage VSS to the subpixels located in the first edge display area 11P, and the intermediate voltage line LM being separated from the bottom lead 41, i.e., the intermediate voltage line LM not being directly connected to the bottom lead 4 from the pad 3.Thus, in the display substrate 10 according to the embodiment of the present disclosure, the edge voltage line contacts and is electrically connected to the lower lead 41 to provide a VSS signal to the subpixels in the first edge display region 11P, and the intermediate voltage line LM is separated from, i.e., not in contact with, the lower lead 41, but is connected to the left lead 42, the upper lead 43, or another first power supply voltage line vss to provide a VSS signal to the first intermediate display region 11M. That is, the first power supply voltage line LM is not directly connected to the first intermediate display region 11M by the first power supply voltage lead 4 drawn out from the pad 3 located on the side away from the display region of the lower edge 1a. That is, the intermediate voltage line LM is not connected to the pad 3 by the frame region 2, and is not directly connected to the first power supply voltage line vss. Therefore, the first power supply voltage VSS is not obtained through the pad 3, but is obtained through the edge voltage line. This reduces the amount of wiring installed in the fanout region, further reducing the fanout region, thereby reducing the width of the lower frame and further realizing a narrower frame.

[0044] For example, the edge voltage line LP is directly connected to the bottom lead 41, i.e., the edge voltage line LP and the bottom lead 41 are in contact with each other, and there is no other structure between the edge voltage line LP and the bottom lead 41 as a medium connecting them. For example, the edge voltage line LP is disposed in the same layer as the bottom lead 41 and forms a continuous, integrally molded structure. In such a case, the edge voltage line LP and the bottom lead 41 may be made of the same material and formed by the same patterning process, thereby simplifying the structure and manufacturing process of the display substrate.

[0045] Of course, in other embodiments, the edge voltage line LP and the bottom lead 41 may be disposed on different layers and be in contact with each other through a via. It should be noted that in this disclosure, the term "direct connection" refers to two structures (e.g., the edge voltage line LP and the bottom lead 41) that are connected to each other and that are in contact with each other without any other structure serving as a medium connecting the two structures. For example, the two structures that are directly connected to each other may be a continuous, integrally molded structure, in which case the two structures may be made of the same material and formed using the same patterning process to simplify the manufacturing process of the display substrate. Alternatively, the two structures that are directly connected to each other may be made of different materials, for example, both structures may be conductive signal lines, and the two structures may use materials suitable for their functions to meet different performance requirements, such as different electrical conductivities.

[0046] For example, as shown in FIG. 1 , the first power supply voltage line vss includes a vertical voltage line YL extending along the vertical direction Y and a horizontal voltage line XL extending along the horizontal direction X, the vertical voltage line YL and the horizontal voltage line XL are installed in a different layer from each other, the vertical voltage line YL includes an edge vertical voltage line YLP located in the first edge display region 11P, the horizontal voltage line XL includes an edge horizontal voltage line XLP located in the first edge display region 11P and intersecting with the edge vertical voltage line YLP, the edge vertical voltage line YLP and the edge horizontal voltage line XLP constitute an edge voltage line LP, the first power supply voltage lead 4 further includes a left lead 42 extending along the left edge 1b of the display region 1, the edge vertical voltage line YLP is directly connected to the bottom lead 41, and the edge horizontal voltage line XLP is directly connected to the left lead 42. For example, the edge vertical voltage line YLP passes vertically through the entire display area of the first edge display region 11P, thereby supplying the first power supply voltage VSS to the subpixels in the entire first edge display region 11P. In this way, the edge vertical voltage line YLP is directly connected to the bottom lead 41 adjacent thereto, which can save space and contribute to reducing the frame area outside the lower edge 1a.

[0047] For example, a first first power supply voltage pin 4a is installed on the pad 3, the lower lead 41 is electrically connected to the first power supply voltage pin 4a, and the first power supply voltage pin 4a is located at a first end of the pad 3 in the horizontal direction X, which is close to the first edge display region 11P. Therefore, the first power supply voltage pin 4a, the lower lead 41, and the edge vertical voltage line YLP of the first edge display region 11P are directly connected in close order, which effectively reduces the wiring on the lower frame and makes it possible to reduce the frame area outside the lower edge 1a.

[0048] For example, as shown in FIG. 1 , in some embodiments, a second first power supply voltage pin 4 b may be further provided on the pad 3, and the second first power supply voltage pin 4 b may be located close to the right edge 1 d, i.e., at a second end of the pad 3 in the horizontal direction X close to the second edge display region 12P. The second edge display region 12P and the first edge display region 11P have structures related to the first power supply voltage line vss axially symmetrical with respect to an axis of symmetry extending along the vertical direction Y. Similar to the first first power supply voltage pin 4 a and the first power supply voltage line vss in the first edge display region 11P, the second first power supply voltage pin 4 b may be directly connected to the edge vertical voltage line in the second edge display region 12P to provide the first power supply voltage VSS to the subpixels in the second edge display region 12P.

[0049] 6A is a partially enlarged schematic view of region R3 in FIG. 4, and FIGS. 6B to 6D are schematic views of partial film layers of region R3 in FIG. 3. For example, as shown in FIGS. 1 and 6A, the lower end of the edge vertical voltage line YLP that is close to the lower lead 41 is directly connected to the lower lead 41. For example, the upper end of the edge vertical voltage line YLP that is opposite to the lower end is directly connected to the upper lead 43, thereby more reliably providing the first power supply voltage VSS through the edge vertical voltage line YLP.

[0050] For example, as shown in FIG. 1, referring to the equivalent circuit diagram of the pixel circuit shown in FIG. 8, the display substrate 10 further includes a data line DATA, the sub-pixel includes a driving transistor T3, a light-emitting element, and a data transistor T4, the driving transistor T3 is configured to control the magnitude of a driving current flowing through the light-emitting element, the light-emitting element is configured to receive the driving current and be driven by the driving current to emit light, the data transistor T4 is configured to write a data signal DATA to the gate of the driving transistor T3 in response to a first control signal, the data line DATA is configured to transmit the data signal DATA to the sub-pixel, the display area 1 includes a lower display area 14 and an upper display area 13, the lower display area 14 is close to the lower edge 1a, and the upper display area 13 is located vertically away from the lower edge 1a of the lower display area 14, and the lower display area 14 is located between the first area (1) and and a second region (2), the first region (1) including a first sub-region A approaching the left edge 1b in the horizontal direction X and a second sub-region B away from the left edge 1b, the data lines data passing through the first sub-region A and the second region (2) including a first connection line DL1 extending along the vertical direction Y in the first sub-region A, a second connection line DL2 extending along the horizontal direction X in the second region (2), and a fifth connection line DL5 located in the upper display region 13 extending along the vertical direction Y, the fifth connection line DL5 being arranged in the same layer as the first connection line DL1, the first connection line DL1 being arranged in the same layer as the vertical voltage line YL, the second connection line DL2 being arranged in the same layer as the horizontal voltage line XL, the first connection line DL1 and the second connection line DL2 of the same data line data being electrically connected by a first connection hole VC1, and the fifth connection line DL5 and the second connection line DL2 of the same data line data being electrically connected by a third connection hole VC3. This forms one transmission channel for one data line DATA, such as the data signal DATA indicated by the three arrows in Fig. 1. For example, multiple data lines DATA are respectively connected to pads 3 by multiple data signal leads CL, which are electrically connected to, for example, integrated circuits IC at pads 3, thereby providing data signals DATA to the data lines DATA.

[0051] For example, the first sub-region A is located in the first intermediate display region 11M, at least a portion of the second region (2) is located in the first intermediate display region 11M, the first sub-region A has a left end point PO that is closest to the left edge 1b of the display region 1 in the horizontal direction X, and a straight line extending along the vertical direction Y and passing through the left end point PO is the boundary line IL between the first edge display region 11P and the first intermediate display region 11M. In other words, the region between the straight line and the left edge 1b is the first edge display region 11P. The first sub-region A is located in the first intermediate display region 11M.

[0052] For example, as shown in Figures 1 and 2, the boundary line IL passes through the second region (2) and divides the second region (2) into a first sub-region A approaching the left edge 1b of the display region 1 and a second sub-region B moving away from the left edge 1b of the display region 1, with the first sub-region A being located in the first edge display region 11P and the second sub-region B being located in the first intermediate display region 11M.

[0053] FIG. 3A is a partially enlarged schematic diagram of region R1 in FIG. 2, and FIGS. 3B to 3D are schematic diagrams of partial film layers in region R3 in FIG. 1-2 and 3A-3D, or FIG. 1 and 6A-6D, the lower display area 14 further includes a third area (3), the third area (3) is located in the first edge display area 11P and is located on the side of the second area (2) away from the first area (1) in the horizontal direction X, the edge horizontal voltage line XLP includes a lower edge horizontal voltage line XLP1 located in the third area (3), the edge vertical voltage line YLP passes through the third area (3) and intersects with the lower edge horizontal voltage line XLP1 at a first intersection point P1, the left end of the lower edge horizontal voltage line XLP1 is electrically connected to the left lead 42, and the right end of the lower edge horizontal voltage line XLP1 opposite to the left end is cut off from the second connection line DL2 in the second area (2) by a first fracture surface OP1. 1 and 2 for the first fracture surface OP1, and Figures 3A and 3B are partial schematic diagrams showing only a limited number of pixels and therefore not showing the first fracture surface OP1. The vertical voltage lines YL include a plurality of edge vertical voltage lines YLP and a plurality of edge horizontal voltage lines XLP, and the plurality of edge vertical voltage lines YLP and the plurality of edge horizontal voltage lines XLP are intertwined with each other to form a lattice, and the lattice includes a plurality of first intersection points P1, and at each position of some of the plurality of first intersection points P1, one edge vertical voltage line YLP is electrically connected to one lower edge horizontal voltage line XLP1 through a first via V1, so that a plurality of first vias V1 are present at the plurality of first intersection points P1. In this way, the plurality of edge vertical voltage lines YLP and the plurality of lower edge horizontal voltage lines XLP1 are electrically connected in a lattice structure in the third region (3), and the resistance of the first power supply voltage lines vss transmitting the first power supply voltage VSS in the third region (3) in the first power supply voltage lines vss can be reduced, and the voltage drop on the lattice-shaped first power supply voltage lines vss formed by the edge vertical voltage lines YLP and the lower edge horizontal voltage lines XLP1 in the third region (3) is relatively low.

[0054] For example, a first insulating layer exists between the film layer shown in FIG. 4B and the film layer shown in FIG. 4C, and a first via V1 penetrates the first insulating layer, and a first connection structure C1 passing through the first via V1 electrically connects the edge vertical voltage line YLP and the lower edge horizontal voltage line XLP1.

[0055] For example, all first power voltage lines vss (vertical voltage lines YL) located in the display area 1 and extending along the vertical direction Y are arranged in the same layer as the data lines data in the upper display area 13, the horizontal voltage lines XL located in the display area 1 are arranged in the same layer as the second power voltage lines, and all first power voltage lines vss (horizontal voltage lines XL) extending along the X direction are arranged on the side of the vertical voltage lines YL closer to the base substrate. For example, the vertical voltage lines YL are arranged on the sixth conductive layer 580 below, and the horizontal voltage lines XL are arranged on the fifth conductive layer 570 below. Of course, in other embodiments, the voltage lines YL and the horizontal voltage lines XL may be arranged on different metal layers, with a first insulating layer arranged between the two metal layers.

[0056] Although three first vias V1 are shown in FIGS. 3A and 3B as an example, the number of first vias V1 is not limited.

[0057] 1 and 2, for example, a plurality of edge-vertical voltage lines YLP are electrically connected to a plurality of edge-lateral voltage lines XLP through a plurality of first vias V1, and a planar pattern consisting of the positions of the plurality of first vias V1 is a connection line segment SC located in a third region (3) (the dotted line in the third region (3) in FIG. 1 represents the connection line segment SC), and the extending direction of the connection line segment SC intersects both the horizontal direction X and the vertical direction Y. Here, the "planar pattern consisting of the positions of a plurality of first vias V1" refers to the overall pattern formed by arranging the positions of the plurality of first vias V1.

[0058] For example, in the embodiment shown in Figures 1-2, the connecting line segment SC is a straight line segment, thereby maintaining consistency with the shape of the W-shaped broken line below. Of course, in other embodiments, the connecting line segment SC may be a curved line segment if desired.

[0059] 1, the third region (3) is a corner region defined by a first side SL1 approaching the left edge 1b of the second region (2) in the horizontal direction X, the left edge 1b, and the lower edge 1a. By defining the third region (3) as the corner region, a first fracture surface OP1 is provided in the corner region to realize a design (fanout in pixel, FIP technology) in which the data line DATA passes through the second region (2) and the first region (1), thereby providing floating access to the first power supply voltage signal, thereby preventing signal interference due to floating wires, such as electrostatic interference due to static electricity that is easily accumulated in the floating wires.

[0060] The planar patterns of the fifth connection line DL5 and the multiple third connection holes VC3 of the second connection line DL2 for respectively connecting multiple data lines data are line segments, for example straight line segments, and the line segments may be the first side SL1 of the second region (2) and may be the boundary line between the third region (3) and the second region (2).

[0061] For example, referring to Figures 1 and 2, the frame region 2 includes a frame corner region 20 surrounding the corner region (3), and an auxiliary first power supply voltage line vss having a grid pattern is installed in the frame corner region 20, thus significantly reducing the voltage drop of the first power supply voltage line in the first edge display region 11P.

[0062] Fig. 4 is a partially enlarged schematic view including regions R2 and R3 in Fig. 1, where region R2 includes frame corner region 20, Fig. 5A is a partially enlarged schematic view of region R2 in Fig. 4, and Figs. 5B to 5D are schematic views of partial film layers of region R2 in Fig. 4. Referring to Fig. 4 and Figs. 5A to 5D, the lattice-shaped auxiliary first power supply voltage lines vss include a plurality of vertical auxiliary voltage lines YAL and a plurality of horizontal auxiliary voltage lines XAL. The multiple vertical auxiliary voltage lines YAL extend along the vertical direction Y and are installed in the same layer as the vertical voltage lines YL, and a first end in the vertical direction Y of each of the multiple vertical auxiliary voltage lines YAL is directly connected to a first power supply voltage lead 4 (e.g., the lower lead 41, or a corner lead connecting the lower lead 41 and the left lead 42), and a second end opposite to the first end in the vertical direction Y of each of the multiple vertical auxiliary voltage lines YAL is electrically connected, for example directly connected, to one edge vertical voltage line YLP passing through the corner region (3). The plurality of horizontal auxiliary voltage lines XAL extend along the horizontal direction X and are arranged in the same layer as the plurality of vertical auxiliary voltage lines YAL, with one end of each of the plurality of horizontal auxiliary voltage lines XAL in the horizontal direction X directly connected to a first power supply voltage lead 4 (e.g., the left lead 42 or a corner lead connecting the bottom lead 41 and the left lead 42), and a second end of each of the plurality of horizontal auxiliary voltage lines XAL opposite to the first end in the horizontal direction X electrically connected to one edge vertical voltage line YLP. As shown in FIG. 5D , the plurality of vertical auxiliary voltage lines YAL are arranged in the same layer as the plurality of horizontal auxiliary voltage lines, for example, in the same layer as the vertical voltage line YL, and the vertical auxiliary voltage lines YAL, the horizontal auxiliary voltage lines, and the vertical voltage line YL are simultaneously formed by the same patterning process, thereby simplifying the structure and manufacturing process of the display substrate.

[0063] 5A to 5D, the display area 1 includes a pixel array, the pixel array including a plurality of pixel rows extending along the horizontal direction X and a plurality of pixel columns extending along the vertical direction Y, the plurality of pixel rows including a plurality of edge pixel rows PXR close to the bottom edge 1a, a plurality of horizontal auxiliary voltage lines XAL corresponding one-to-one to the plurality of edge pixel rows PXR, each edge pixel row PXR including an edge sub-pixel P closest to the left edge 1b, a plurality of edge vertical voltage lines YLP including an edge-most vertical voltage line YLP0 of the edge sub-pixel P passing through each edge pixel row PXR, a second end of each of the plurality of horizontal auxiliary voltage lines XAL electrically connected, for example directly connected, to the edge-most vertical voltage line YLP0 passing through the corresponding edge pixel row PXR, and a second end of each of the plurality of horizontal auxiliary voltage lines XAL electrically connected to the edge horizontal voltage line XLP passing through the corresponding edge pixel row PXR via a first edge via VP1. As shown in Figure 5C, a first edge connection structure CP1 passing through the first insulating layer electrically connects the second end of the horizontal auxiliary voltage line XAL to the edge horizontal voltage line XLP of the corresponding edge pixel row PXR. Figures 5A to 5D show the connection relationship between one horizontal auxiliary voltage line XAL and the edge pixel row PXR closest to the corresponding lower edge 1a. The connections of the other edge pixel rows PXR are similar. However, in this embodiment, the lengths of the horizontal auxiliary voltage lines XAL corresponding to each edge pixel row PXR are different to accommodate the shape of the corner region. In other embodiments, the lengths of the horizontal auxiliary voltage lines XAL of each edge pixel row PXR can be designed to accommodate the pixel arrangement of the display substrate, if necessary.

[0064] For example, as shown in Figures 1 and 5A-5B, the second power supply voltage lead 4b-1 is located in the lower frame region surrounding the lower edge 1a and is electrically connected to the second power supply voltage pin 4b, and the second power supply voltage line passing through multiple pixel columns is electrically connected to the second power supply voltage lead 4b-1, thereby providing the second power supply voltage VDD to the pixels of the multiple pixel columns.

[0065] For example, as shown in FIG. 1, the horizontal voltage line XL further includes a plurality of first horizontal voltage lines XLU, which are arranged in the vertical direction Y and located in the upper display area 13, the left ends of the first horizontal voltage lines XLU are electrically connected to the left lead 42, and the edge horizontal voltage line XLP further includes an upper edge horizontal voltage line XLP2 located in the upper display area 13, and the upper edge horizontal voltage line XLP2 is part of one first horizontal voltage line XLU. The vertical voltage line YL further includes a plurality of intermediate vertical voltage lines YLM, and a plurality of first horizontal voltage lines XLU are arranged in the horizontal direction X and pass through a part 11M of the first middle display area 11M along the vertical direction Y through the upper display area 13, and the plurality of intermediate vertical voltage lines YLM, the plurality of edge vertical voltage lines YLP and the plurality of first horizontal voltage lines XLU are intertwined to form a lattice, thereby reducing the resistance of the first power supply voltage line vss and reducing the voltage drop on the first power supply voltage line vss.

[0066] A plurality of edge vertical voltage lines YLP and a plurality of first horizontal voltage lines XLU intersect at a plurality of auxiliary intersections AP within the first edge display region 11P, and at each position of some of the plurality of auxiliary intersections AP, one edge vertical voltage line YLP is electrically connected to one first horizontal voltage line XLU through an auxiliary via AV within the first edge display region 11P, and the plurality of edge vertical voltage lines YLP are electrically connected to the plurality of first horizontal voltage lines XLU through a plurality of auxiliary vias AV, and the planar pattern formed by the positions of the plurality of auxiliary vias AV is an auxiliary line segment SA located in the first edge display region 11P, and the end of the auxiliary line segment SA away from the left edge 1b is suspended, that is, a via pattern without it is connected to the end of the auxiliary line segment SA away from the left edge 1b, and the auxiliary line segment SA is different from the third line segment S3 of the W-shaped broken line below. In this way, the resistance of the first power supply voltage line vss in the first edge display region 11P can be further effectively reduced, and the voltage drop of the first power supply voltage line vss in the first edge display region 11P can be reduced.

[0067] The structure in which one edge vertical voltage line YLP is electrically connected to one first horizontal voltage line XLU at the position of the auxiliary line segment SA within the first edge display area 11P via an auxiliary via AV is similar to the structure of area R1 shown in Figures 3A to 3D, and you may refer to Figures 3A to 3D, so a detailed description will be omitted here.

[0068] 1, the extension direction of the auxiliary line segments SA is the same as the extension direction of the connecting line segments SC, and for example, the lengths of the auxiliary line segments SA and the connecting line segments SC are also the same, thereby maintaining uniformity in the arrangement tendency of the connection points connected through the vias and preventing unevenness defects from occurring on the display substrate. For example, the display substrate 10 includes a plurality of auxiliary line segments SA, and the connecting line segments SC and the plurality of auxiliary line segments SA are arranged at intervals from each other along the vertical direction Y.

[0069] For example, as shown in FIG. 1, the display area 1 further includes an upper edge 1c opposite to the lower edge 1a, the first power supply voltage lead 4 further includes an upper lead 43 extending along the upper edge 1c, the upper lead 43 is electrically connected to the left lead 42, the upper end of the edge vertical voltage line YLP is connected to the upper lead 43, and the lower end of the edge vertical voltage line YLP opposite to the upper end is directly connected to the lower lead 41.

[0070] 3. FIG. 7A is a partially enlarged schematic diagram of region R4 in FIG. 3, and FIGS. 7B to 7D are schematic diagrams of partial film layers of region R4 in FIG. 3. For example, as shown in FIG. 1, the vertical voltage line YL includes an intermediate vertical voltage line YLM located in the first intermediate display region 11M, and the intermediate vertical voltage line YLM includes a first vertical voltage line YLM1 and a second vertical voltage line YML2. The first vertical voltage line YLM1 passes through the upper display region 13 and at least a part of the second region (2) in the vertical direction Y. Referring to FIGS. 1 and 7A to 7D, the upper end of the first vertical voltage line YLM1 is electrically connected to the upper lead 43, and the lower end of the first vertical voltage line YLM1 opposite to the upper end thereof and the first connecting line DL1 in the first sub-region A are cut by a second fracture surface OP2. FIGS. 7A and 7D partially show two second fracture surfaces OP2 located in region (2). The second vertical voltage line YML2 passes through the upper display region 13 and the first region (1) in this order along the vertical direction Y, the horizontal voltage lines XL include the intermediate horizontal voltage line XLM located in the first region (1), the intermediate horizontal voltage line XLM and the second connection line DL2 in the second region (2) are cut by the third fracture surface OP3, and as shown in Figures 1 and 2, the right end opposite to the left end of the intermediate horizontal voltage line XLM located in the first region (1) and the fourth connection line DL4 in the fourth region (4) are cut by the fourth fracture surface OP4. Therefore, both ends in the horizontal direction X of each of the multiple intermediate horizontal voltage lines XLM are cut from the corresponding second connection line D2 and the corresponding fourth connection line DL4, respectively.

[0071] As shown in the figure, the second vertical voltage line YML2 and the intermediate horizontal voltage line XLM intersect at a second intersection P2, and the second vertical voltage line YML2 is electrically connected to the intermediate horizontal voltage line XLM at the second intersection P2 through a second via V2.

[0072] For example, the second vertical voltage line YML2 is electrically connected to a plurality of intermediate horizontal voltage lines XLM arranged in the vertical direction Y through a plurality of second vias V2 arranged in the vertical direction Y. Although the portion shown in Figures 7A to 7D has three second vias V2, this does not represent that the display substrate has only three second vias V2. For example, each of the plurality of intermediate horizontal voltage lines XLM is connected to the second vertical voltage line YML2 through the second via V2, thereby transmitting the first power supply voltage VSS to each pixel in the first region (1). For example, as shown in Figure 7B, the second vertical voltage line YML2 and the intermediate horizontal voltage line XLM are connected by a second connection structure C2 passing through the second vias V2.

[0073] For example, as shown in FIG. 1, a plurality of first horizontal voltage lines XLU and second vertical voltage lines YML2 located in the upper display area 13 intersect at a plurality of third intersection points P3, and at each position of at least some of the plurality of third intersection points P3, one first horizontal voltage line XLU is electrically connected to the second vertical voltage line YML2 via a third via V3. As a result, the intermediate horizontal voltage line XLM and the second vertical voltage line YLM2 are electrically connected through the second via V2, and the second vertical voltage line YLM2 is electrically connected to the first horizontal voltage line XLU through the third via V3, so that the first horizontal voltage line XLU is electrically connected to the first power supply voltage lead 4 (left lead 42), thereby providing the first power supply voltage VSS to the second vertical voltage line YML2 through the first horizontal voltage line XLU, and providing the first power supply voltage VSS to the intermediate horizontal voltage line XLM through the second vertical voltage line YML2.As a result, it is possible to provide the first power supply voltage VSS to the pixels in the first region (1) without providing the first power supply voltage VSS to the sub-pixels of the first region (1) by directly connecting the first power supply voltage line located in the first region (1) to the first power supply voltage lead from the pad 3 in the frame region surrounding the lower edge 1b. As can be seen from Figures 1, 6A, and 6D, the lower lead 41 is not connected to the intermediate vertical voltage line YLM located in the first intermediate display area 11M and the second intermediate display area 12M, but is directly connected only to the edge vertical voltage line YLP located in the first edge display area 11P.

[0074] For example, the second via V2 and the third via V3 both penetrate the first insulating layer.

[0075] For example, the first power supply voltage lead 4 and the vertical voltage line YLP are disposed on the same layer, and the first power supply voltage lead 4 and the vertical voltage line YLP are made of the same material and have a continuous, integrally formed structure. They may be formed by the same patterning process, which simplifies the structure and manufacturing process of the display substrate.

[0076] For example, as shown in FIG. 1 , the display area 1 further includes a right edge 1d opposite to the left edge 1b, and the first power lead further includes a right lead 44 extending along the right edge 1d, the right lead 44 being electrically connected to the upper lead 43, each of the plurality of first horizontal voltage lines XLU penetrating the upper display area 13 along the horizontal direction X, and the right end of each of the plurality of first horizontal voltage lines XLU opposite to its left end being electrically connected to the right lead 44, thereby simultaneously transmitting the first power supply voltage VSS from the left end and right end of the first horizontal voltage line XLU to the display area 1, improving the signal transmission speed and contributing to improving the display quality of the display substrate.

[0077] For example, a plurality of intermediate vertical voltage lines YLM and a plurality of first horizontal voltage lines XLU in the upper display region 13 intersect with each other at a plurality of fourth intersection points P4 in the upper display region 13, thereby connecting them in a grid pattern, which contributes to making the upper area smaller. At each position of some of the plurality of fourth intersection points P4, one intermediate vertical voltage line YLM is electrically connected to one first horizontal voltage line XLU through a fourth via V4, thereby connecting the plurality of first horizontal voltage lines XLU extending along the horizontal direction X in the upper display region 13 and the intermediate vertical voltage line YLM extending along the vertical direction Y in a grid pattern, thereby reducing the resistance of the first power supply voltage line vss located in this part of the upper display region 13 and reducing the voltage drop on the first power supply voltage line vss.

[0078] The planar pattern consisting of the positions of multiple fourth vias V4 is a broken line (dotted line), which corresponds to the shape of a W-shaped broken line consisting of the boundary SL1 (dotted line) between the second region (2) and the third region (3), the boundary of the fourth region (4) between the second region (2) and the first region (1), i.e., the fifth line segment S5 (dotted line), the boundary between the first region (1) and the fourth region (4), i.e., the sixth line segment S6 (dotted line), and the boundary SL3 (dotted line) between the fourth region (4) and the fifth region (5) (at least all of which are broken lines), which contributes to maintaining uniformity in the arrangement tendency of the connection points connected via vias in the lower display region 14 and the connection points connected via vias in the upper display region 13, thereby preventing uneven display defects from occurring on the display substrate.

[0079] The structure in which one intermediate vertical voltage line YLM is electrically connected to one first horizontal voltage line XLU through the fourth via V4 is similar to the structure of the region R1 shown in Figures 3A to 3D, and Figures 3A to 3D may be referred to, and detailed description thereof will be omitted here.

[0080] For example, as shown in FIG. 1, the broken line includes a plurality of sub-broken lines extending from the left edge 1b to the right edge 1d, each of the sub-broken lines including a plurality of broken line portions whose leading ends are connected to their trailing ends, the plurality of broken line portions including a first line segment S1 (dotted line) extending along a first direction and a second line segment S2 (dotted line) extending along a second direction, the first direction intersects with the second direction, and both the first direction and the second direction intersect with the horizontal direction X and the vertical direction Y, a first end of the first line segment S1 overlaps with a first end of the second line segment S2, for example, the first end of the first line segment S1 and the first end of the second line segment S2 intersect at the upper vertex TP, the plurality of vertices of the sub-broken lines are located on the second vertical voltage line YML2, and all of the fourth vias V4 at the vertex positions are the second vias V2.

[0081] For example, as shown in Fig. 1, each of the plurality of sub-bent lines exhibits a W-shape. A dotted wiring line exhibiting one W-shape in Fig. 1 is one sub-bent line.

[0082] For example, the W-shaped sub-broken line includes a first line segment S1 (dotted line) and a second line segment S2 (dotted line), and a third line segment S3 (dotted line) and a fourth line segment S4 (dotted line), where the first line segment S1 and the second line segment S2 are located between the third line segment S3 and the fourth line segment S4, the third line segment S3 is connected to the first line segment S1, the fourth line segment S4 is connected to the second line segment S2, the first line segment S1 is approximately parallel to the fourth line segment S4, and the second line segment S2 is approximately parallel to the third line segment S3.

[0083] For example, the vertical direction is perpendicular to the horizontal direction, the angle between the first line segment S1 and the horizontal direction is 45°, and the angle between the second line segment S2 and the horizontal direction is 45°, thereby ensuring that the W-shaped wiring is maintained so that the intermediate vertical voltage line YLM is connected to the first horizontal voltage line XLU at as many intersections as possible through the fourth via V4.

[0084] For example, in the vertical direction Y, the supplemental line segment SA is located between the third line segments S3 of two adjacent sub-polygonal lines.

[0085] For example, by making the connection line SC, auxiliary line SA and third line S3 approximately parallel to each other, the uniformity of the arrangement tendency of the connection points connected to each position in the first edge display area 11P through vias is maintained, thereby preventing uneven display defects from occurring on the display substrate.

[0086] For example, as shown in FIG. 2, the second vertical voltage line YML2 divides the first region (1) into a first sub-region A and a second sub-region B, and the structure of the first sub-region A and the structure of the second sub-region B are substantially symmetrical about the second vertical voltage line YML2. The lower display region 14 includes a fourth region (4), and the structure of the fourth region (4) and the structure of the second region (2) are substantially symmetrical about the second vertical voltage line YML2. The data lines DATA passing through the first region (1) and the fourth region (4) are the third connection line DL3 extending in the second sub-region B along the vertical direction Y and the fourth connection line DL4 extending in the fourth region (4) along the horizontal direction X. The data line DATA includes a fourth connection line DL4 and a sixth connection line DL6 extending along the vertical direction Y located in the upper display area 13, the sixth connection line DL6 being arranged in the same layer as the first connection line DL1, the third connection line DL3 being arranged in the same layer as the vertical voltage line YL, the fourth connection line DL4 being arranged in the same layer as the horizontal voltage line XL, and the same data line DATA is electrically connected to the third connection line DL3 and the fourth connection line DL4 by the second connection hole VC2, and the sixth connection line DL6 and the fourth connection line DL4 are electrically connected by the fourth connection hole VC4, thereby forming a transmission channel for a data signal on the data line DATA.

[0087] For example, the display substrate 10 includes a plurality of first connection lines DL1, a plurality of second connection lines DL2, a plurality of third connection lines DL3, and a plurality of fourth connection lines DL4, the plurality of first connection lines DL1 and the plurality of second connection lines DL2 are electrically connected by a plurality of first connection holes VC1, the plurality of third connection lines DL3 and the plurality of fourth connection lines DL4 are electrically connected by a plurality of second connection holes VC2, and the plane pattern consisting of the plurality of first connection holes VC1 is a fifth line segment S5, and the fifth line The line segment S5 is the boundary between the first region (1) and the second region (2), the planar pattern consisting of the plurality of second connection holes VC2 is the sixth line segment S6, the sixth line segment S6 is the boundary between the first region (1) and the fourth region (4), the lower display region 14 further includes a fifth region (5), the structure of the fifth region (5) and the structure of the third region (3) are approximately axially symmetrical with respect to the second vertical voltage line YML2, and the planar pattern of the plurality of fifth vias V5 that are symmetrical to the plurality of first vias V1 in the fifth region (5) is the seventh line segment S7. As shown in Figure 1, the planar pattern formed by sequentially connecting the connection line SC (dotted line), the fifth line S5 (dotted line), the sixth line S6 (dotted line), and the seventh line S7 (dotted line) is the same as the planar pattern of each of the multiple sub-broken lines (for example, the W-shaped sub-broken lines), thereby maintaining uniformity in the arrangement tendency of the connection points connected through vias in the lower display area 14 and the connection points connected through vias in the upper display area 13, thereby preventing uneven display defects from occurring on the display substrate.

[0088] For example, as shown in FIG. 1, the boundary between the second region (2) and the third region (3) is also the first side SL1 of the second region (2), and the included angle formed between the first line segment S1 and the horizontal direction X is smaller than the included angle formed between the first side SL1 and the horizontal direction X.

[0089] 1 and 2, the planar shape of the first region (1) is a first triangle, the planar shape of the second region (2) is a second triangle, the second side of the first triangle approaching the left edge 1b in the horizontal direction X (i.e., the second connection line SL2) overlaps at least a part of the first side of the second triangle away from the left edge 1b of the display region 1 in the horizontal direction X (i.e., the second connection line SL2), the two lower vertices DP1 and DP2 of the first triangle are located at the lower edge 1a of the display region 1, the left vertex of the two lower vertices of the first triangle approaching the left edge 1b is the left endpoint PO of the first sub-region A, the first triangle is an isosceles triangle, and the second vertical voltage line YML2 is approximately the perpendicular bisector of the base of the isosceles triangle. This arrangement allows the data lines and first power voltage lines to be uniformly and consistently arranged throughout the entire display region 1, thereby preventing unevenness defects from occurring on the display substrate.

[0090] 8A is a partially enlarged schematic diagram of region R5 in FIG. 3, and FIGS. 8B-8C are schematic diagrams of partial film layers of region R5 in FIG. 3. For example, referring to FIGS. 1 and 8A-8C, frame region 2 includes left frame region 2a extending along left edge 1b, and multiple auxiliary connection lines ACL extending along the horizontal direction X are provided in left frame region 2, and the multiple auxiliary connection lines ACL are provided in the same layer as the edge vertical voltage lines YLP. Display region 1 includes a pixel array, which includes multiple pixel rows extending along the horizontal direction X and multiple pixel columns extending along the vertical direction Y. For example, the multiple auxiliary connection lines ACL correspond one-to-one to the multiple first horizontal voltage lines XLU and one-to-one to the multiple pixel rows in upper display region 13. The plurality of pixel columns includes an edge pixel column PXC0 closest to the left edge 1b, the plurality of edge vertical voltage lines YLP includes an outer edge vertical voltage line YLP-1 passing through the edge pixel column PXC0, the left end of each of the plurality of auxiliary connection lines ACL in the horizontal direction X is electrically connected, for example directly connected, to the left lead 42, and the right end of each of the plurality of auxiliary connection lines ACL opposite to the left end in the horizontal direction X is electrically connected to the outer edge vertical voltage line YLP and is electrically connected to the left end of a corresponding one of the first horizontal voltage lines XLU through a second edge via VP2.

[0091] For example, the auxiliary connecting line ACL is disposed in the same layer as the left lead 42, and for example, the two are made of the same material, forming a continuous, integrally molded structure. Naturally, the two may be made of different materials.

[0092] Here, taking the situation in the left frame region 2a as an example, multiple auxiliary connection lines ACL are also installed in the right frame region opposite the left frame region in the horizontal direction X, and the connection method between the auxiliary connection lines ACL and the right ends of the first horizontal voltage lines XLU in the right frame region is the same as the connection method between the auxiliary connection lines ACL and the left ends of the first horizontal voltage lines XLU in the left frame region 2a, so detailed explanation will be omitted here.

[0093] 1, the right display region 12 includes a second edge display region 12P extending along the right edge 1d and a second intermediate display region 12M located on the side of the second edge display region 12P closer to the left display region 11, the second edge display region 12P and the first edge display region 11P being symmetrical with respect to an axis of symmetry extending along the vertical direction Y, and the second intermediate display region 12M and the first intermediate display region 11M being axially symmetrical with respect to the second vertical voltage line YML2. The first intermediate display region 11M and the second intermediate display region 12M constitute an intermediate display region, the second sub-region B is located in the second intermediate display region 12M, and the first region (1) is located in the intermediate display region.

[0094] For example, the first power supply voltage lead 4 further includes another lower lead 451 extending along the portion of the lower edge 1a corresponding to the second edge display region 12P, and for example, the edge voltage line providing the first power supply voltage VSS to the second edge display region 12P is electrically connected by contacting the another lower lead 45, for example, the two are directly connected, i.e., the edge voltage line providing the first power supply voltage VSS in the second edge display region 12P and the another lower lead 451 are in contact with each other, and there is no other structure as a medium connecting the two between the edge voltage line providing the first power supply voltage VSS in the second edge display region 12P and the another lower lead 45, for example, the edge voltage line providing the first power supply voltage VSS in the second edge display region 12P is installed in the same layer as the another lower lead 45, and forms a continuous, integrally molded structure.

[0095] Of course, in other embodiments, the edge voltage line providing the first power supply voltage VSS in the second edge display area 12P may be located on a different layer from the separate bottom lead 45, and the two may contact each other through a via.

[0096] For example, the display substrate 10 may further include a second power supply voltage line vdd (not shown in FIG. 1) configured to provide the subpixels with a second power supply voltage different from the first power supply voltage VSS, for example, the polarities of the first power supply voltage VSS and the second power supply voltage VDD may be reversed. For example, the first power supply voltage VSS may be at a low level and the second power supply voltage VDD may be at a high level. Of course, the first power supply voltage VSS may be at a high level and the second power supply voltage VDD may be at a low level.

[0097] For example, the vertical voltage line YL is disposed in the same layer as the data line DATA in the upper display area 13, and the horizontal voltage line XL is disposed in the same layer as the second power supply voltage line.

[0098] Fig. 10 is an equivalent circuit diagram of a pixel circuit according to an embodiment of the present disclosure, Figs. 11A to 11H are schematic diagrams including different film layers in the pixel circuit, and Fig. 11I is a stacking schematic diagram of the film layers shown in Figs. 11A to 11F. The dotted frame in Fig. 11A represents the area of one sub-pixel.

[0099] In some examples, as shown in FIG. 10, the display substrate further includes a plurality of sub-pixels, and at least some of the sub-pixels include a light-emitting element 120 and a pixel circuit 110 electrically connected to the light-emitting element 120.

[0100] 10 to 11I, the pixel circuit includes a plurality of transistors and at least one capacitor, such as a second reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data write transistor T4, a second light-emitting control transistor T5, a first light-emitting control transistor T6, a first reset control transistor T7, a third reset transistor T8, and a storage capacitor C.

[0101] For example, as shown in FIGS. 10 to 11I, the display substrate further includes reset power signal lines 561, 551, and 554, scan signal lines 552, 531, and 523, a second power voltage line vdd, reset control signal lines 522, 532, and 553, a light emission control signal line 521, and a data line 582.

[0102] 10 to 11I, for example, a first electrode of the threshold compensation transistor T2 is electrically connected to a first electrode of the driving transistor T3, a second electrode of the threshold compensation transistor T2 is electrically connected to a gate of the driving transistor T3, a gate of the threshold compensation transistor T2 is electrically connected to the scanning signal lines 531 and 552 to receive a compensation control signal, a first electrode of the first reset control transistor T7 is electrically connected to a reset power supply signal line 561 to receive a reset signal Vinit2, a second electrode of the first reset control transistor T7 is electrically connected to a first electrode (i.e., node N4) of the light-emitting element, a gate of the first reset control transistor T7 is electrically connected to a reset control signal line 522 to receive a reset control signal Reset(N+1), a first electrode of the third reset transistor T8 is electrically connected to the reset power supply signal line 551 to receive a reset signal Vref, a second electrode of the third reset transistor T8 is electrically connected to a second electrode of the driving transistor T3, a gate of the third reset transistor T8 is electrically connected to the reset control signal line 522, and a data write transistor T8 is electrically connected to the reset power supply signal line 561. a first electrode of the data write transistor T4 electrically connected to the second electrode of the driving transistor T3, a second electrode of the data write transistor T4 electrically connected to the data line 200 (data line data) to receive a data signal Data, a gate of the data write transistor T4 electrically connected to the scanning signal line 523 to receive a scanning signal Gate, a first electrode of the storage capacitor C electrically connected to the second power supply voltage line vdd, a second electrode of the storage capacitor C electrically connected to the gate of the driving transistor T3, a first electrode of the second reset transistor T1 electrically connected to the reset power supply signal line 554 to receive a reset signal Vinit1, a second electrode of the second reset transistor T1 electrically connected to the gate of the driving transistor T3, a gate of the second reset transistor T1 electrically connected to the reset control signal lines 553 and 532 to receive a reset control signal Reset(N), a gate of the first light-emitting control transistor T6 electrically connected to the light-emitting control signal line 521 to receive a light-emitting control signal EM, and a first electrode of the first light-emitting control transistor T6 electrically connected to the first electrode of the driving transistor T3,The second electrode of the first light-emitting control transistor T6 is electrically connected to the first electrode of the light-emitting element 120, the first electrode of the second light-emitting control transistor T5 is electrically connected to the second power supply voltage line vdd to receive the first power supply signal VDD, the second electrode of the second light-emitting control transistor T5 is electrically connected to the second electrode of the driving transistor T3, the gate of the second light-emitting control transistor T5 is electrically connected to the light-emitting control signal line 521 to receive the light-emitting control signal EM, and the second electrode of the light-emitting element 120 is electrically connected to the voltage terminal VSS (the subsequent third signal line 600). The power supply signal line refers to a signal line that outputs a voltage signal VDD, and can output a constant voltage signal, for example a positive voltage signal, by being connected to a voltage source.

[0103] It should be noted that in the embodiments of the present disclosure, each pixel circuit may have an 8T1C (i.e., 8 transistors and 1 capacitor) structure as shown in FIG. 10 , but may also have a structure including other numbers of transistors, such as a 7T1C structure, a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, and the embodiments of the present disclosure are not limited thereto.

[0104] 11A shows an active semiconductor pattern 510. For example, as shown in FIG. 11A, the active semiconductor pattern 510 may be used to fabricate active layers of the driving transistor T3, data writing transistor T4, second light-emitting control transistor T5, first light-emitting control transistor T6, first reset control transistor T7, and third reset control transistor T8 to form channel regions of the transistors. The active semiconductor pattern 510 includes an active layer pattern (channel region) and a doped region pattern (source / drain region) of the transistors of each sub-pixel, and the active layer patterns and doped region patterns of the transistors in the same pixel circuit are integrally formed.

[0105] For example, the active semiconductor pattern 510 may include an integrally formed low-temperature polysilicon layer, and the source and drain regions may be doped to be conductive to realize electrical connection between the respective structures. For example, the source and drain regions may be doped with p-type impurities.

[0106] 11B shows a first conductive layer pattern 520 located on the side of the active semiconductor pattern 510 that is away from the base substrate. For example, as shown in FIG. 11B, the first conductive layer pattern 520 includes a reset control signal line 522, a scan signal line 523, one electrode of a capacitor 524, and an emission control signal line 521. For example, the first conductive layer pattern 520 may include gates of a driving transistor T3, a data writing transistor T4, a second emission control transistor T5, a first emission control transistor T6, a first reset control transistor T7, and a third reset control transistor T8.

[0107] It should be noted that each dotted rectangular frame in FIG. 11A represents a portion where the active semiconductor pattern 510 and the first conductive layer pattern 520 overlap, i.e., a channel region. The active semiconductor layers on both sides of each channel region of each transistor are converted into conductors by a process such as ion doping, forming the first and second poles of each transistor. The source and drain electrodes of a transistor may be structurally symmetrical, and therefore the source and drain electrodes may be indistinguishable from each other physically. In the embodiments of the present disclosure, in addition to the gate serving as a control pole, one pole is directly described as a first pole and the other pole as a second pole to distinguish between transistors. Therefore, the first pole and the second pole of all or some of the transistors in the embodiments of the present disclosure may be interchangeable as needed.

[0108] 11B and 11I, the gate of the data write transistor T4 may be the overlapping portion of the scan signal line 523 and the active semiconductor pattern 510, the gate of the first light-emitting control transistor T6 may be the first overlapping portion of the light-emitting control signal line 521 and the active semiconductor pattern 510, and the gate of the second light-emitting control transistor T5 may be the second overlapping portion of the light-emitting control signal line 521 and the active semiconductor pattern 510. The gate of the third reset transistor T8 is the first overlapping portion of the reset control signal line 522 and the active semiconductor pattern 510, and the gate of the first reset control transistor T7 is the second overlapping portion of the reset control signal line 522 and the active semiconductor pattern 510.

[0109] 11C shows a second conductive layer pattern 530 on the side away from the base substrate of the first conductive layer pattern 520. For example, as shown in FIG. 11C, the second conductive layer pattern 530 includes a scan signal line 531, a second pole 533 of the capacitor C, and a reset control signal line 532.

[0110] 11D shows an active layer pattern 540 on the side of the second conductive layer pattern 530 that is farther from the base substrate. For example, as shown in FIG. 11D, the active layer pattern 540 includes the channel regions of the second reset transistor T1 and the threshold compensation transistor T2. For example, when the active layers of the second reset transistor T1 and the threshold compensation transistor T2 use an oxide semiconductor, transistors using an oxide semiconductor have good hysteresis characteristics, low leakage current, and relatively low mobility. Therefore, a low-temperature polysilicon material in the transistor can be replaced with a transistor using an oxide semiconductor to form a low-temperature polysilicon-oxide (LTPO) pixel circuit, which achieves low leakage current and contributes to improving the stability of the transistor gate voltage.

[0111] For example, as shown in FIGS. 11C, 11D, and 11I, the gate of the second reset transistor T1 may be the overlapping portion of the reset control signal line 532 and the active layer pattern 540, and the gate of the threshold compensation transistor T2 may be the overlapping portion of the scanning signal line 531 and the active layer pattern 540.

[0112] 11E shows the third conductive layer 550 on the side away from the base substrate of the active layer pattern 540. For example, as shown in FIG. 11E, the third conductive layer 550 includes a reset power signal line 554, a reset control signal line 553, a scanning signal line 552, and a reset power signal line 551.

[0113] For example, as shown in Figures 11C to 11F and 11I, the reset control signal line 553 overlaps with the channel region of the second reset transistor T1, the second reset transistor T1 includes double gates located on both sides of the active layer, and the second reset transistor T1 is a double-gate transistor; the scanning signal line 552 overlaps with the channel region of the threshold compensation transistor T2, the threshold compensation transistor T2 includes double gates located on both sides of the active layer, and the threshold compensation transistor T2 is a double-gate transistor.

[0114] For example, the second reset transistor T1 and the threshold compensation transistor T2 may be N-type transistors, and the data write transistor T4, the second light-emitting control transistor T5, the first light-emitting control transistor T6, the first reset control transistor T7, and the third reset control transistor T8 may be P-type transistors.

[0115] 11F shows a fourth conductive layer 560 located on the side away from the base substrate of the third conductive layer 550. For example, as shown in FIG. 11F, the fourth conductive layer 560 includes a reset power supply signal line 561, a connection portion 568, a connection portion 569, a connection portion 563, a connection portion 567, a connection portion 562, a connection portion 564, a connection portion 565, and a connection portion 566.

[0116] For example, as shown in FIGS. 10 to 11I, the connection portion 568 has both ends connected to the reset power supply signal line 551 and the center connected to the first pole of the third reset transistor T8, the connection portion 569 connects the data line DATA and the second pole of the data write transistor T4, the connection portion 563 is for electrically connecting the first pole of the data write transistor T4 and the second pole of the third reset transistor T8 so as to introduce the reset signal Vref to the N2 node, and the connection portion 567 is for electrically connecting the first pole of the drive transistor T3 and the first pole of the threshold compensation transistor T2. The center of the connection portion 562 is connected to the second power supply voltage line vdd (for example, FIG. 11H, i.e., the second power supply voltage line vdd), both ends of the connection portion 562 are connected to one pole 533 of the capacitor, one end of the connection portion 564 is connected to the second pole 533 of the storage capacitor C, the other end of the connection portion 564 is connected to the first pole of the second light-emitting control transistor T5, the connection portion 565 is for electrically connecting the first electrode of the light-emitting element and the second pole of the first light-emitting control transistor T6, and the connection portion 566 is for electrically connecting the reset power supply signal line 554 and the first pole of the second reset transistor T1.

[0117] 11G shows a fifth conductive layer 570 located on the side of the fourth conductive layer 560 away from the base substrate. For example, as shown in FIG. 11G, the fifth conductive layer 570 includes a connection portion 573, a connection portion 575, a second power supply voltage line 572 (transmitting a second power supply voltage VDD), a connection portion 574, and a lateral voltage line XL (e.g., a middle lateral voltage line XLM). For example, the fifth conductive layer 570 further includes a fourth connection line.

[0118] 10 to 11G, the connection portion 573 is for electrically connecting to the data line DATA. For example, the data line DATA is electrically connected to several connection lines installed in a different layer from the data line DATA extending along the horizontal direction X in the display area 1 through the connection portion 573, thereby transmitting a data signal DATA to the connection lines. The connection portion 575 is an auxiliary pad, and a first connection line may be electrically connected to a second connection line through the auxiliary pad, or a vertical voltage line may be electrically connected to a horizontal voltage line through the auxiliary pad. For example, the electrical connection between the connection portion 574 and the connection portion 565 realizes an electrical connection between the second electrode of the first light-emitting control transistor T6 and the first electrode of the light-emitting element. For example, the second power supply voltage line 572 is electrically connected to the second power supply voltage line vdd.

[0119] 11H shows a sixth conductive layer 580 located on the side away from the base substrate of the fifth conductive layer 570. For example, as shown in FIG. 11H, the sixth conductive layer 580 includes a data line DATA, a second power supply voltage line VDD, a fifth connection line 450, a connection portion 584, and a connection portion 585.

[0120] For example, the connection portion 584 and the connection portion 585 are electrically connected to the first electrodes of different light-emitting elements.

[0121] 11G and 11H, the data line DATA includes a relay pad 290, and the data line DATA is connected to a connection portion 573 via the relay pad 290, thereby electrically connecting to several connection lines installed in a different layer from the data line DATA extending along the horizontal direction X in the display area 1, thereby transmitting a data signal DATA to the connection lines. For example, each vertical voltage line YL may include a relay pad 459, and the vertical voltage line YL may be electrically connected to a connection portion 575 via the relay pad 459, and the connection portion 575 is electrically connected to the corresponding horizontal voltage line XL that should be electrically connected to the vertical voltage line YL, thereby realizing the electrical connection between the vertical voltage line YL and the horizontal voltage line XL.

[0122] As shown in FIG. 12, at least one embodiment of the present disclosure further provides a display device 100, which includes any one kind of display substrate 10 according to at least one embodiment of the disclosure.

[0123] The above descriptions are only exemplary embodiments of the present invention, and are not intended to limit the protection scope of the present invention, which is determined by the appended claims.

Claims

1. A display substrate, a display area in which sub-pixels are disposed and which has a bottom edge extending along a horizontal direction and a left edge extending along a vertical direction, the horizontal direction intersecting the vertical direction, the display area including a left display area and a right display area arranged in the horizontal direction, the left display area including a first edge display area extending along the left edge and a first intermediate display area located in the first edge display area and adjacent to the right display area; a non-display area including a frame area surrounding at least a part of the display area; a first power supply voltage lead configured to provide a first power supply voltage and located in the frame region, the first power supply voltage lead including a bottom lead extending along a portion of the bottom edge corresponding to a first border display region, the first power supply voltage lead not extending along a portion of the bottom edge corresponding to the first middle display region; a first power supply voltage line including an edge voltage line located at an edge of the first edge display area and an intermediate voltage line located at the first intermediate display area, the edge voltage line contacting and electrically connecting to the bottom lead to provide the first power supply voltage to the sub-pixel located in the first edge display area, and the intermediate voltage line being separated from the bottom lead.

2. the first power supply voltage line includes a vertical voltage line extending along the vertical direction and a horizontal voltage line extending along the horizontal direction, the vertical voltage line and the horizontal voltage line being disposed on different layers; the vertical voltage lines include edge vertical voltage lines located in the first edge display area, and the horizontal voltage lines include edge horizontal voltage lines located in the first edge display area and crossing the edge vertical voltage lines, and the edge vertical voltage lines and the edge horizontal voltage lines constitute the edge voltage lines; 2. The display substrate of claim 1, wherein the first power supply voltage lead further includes a left lead extending along a left edge of the display area, the edge vertical voltage line being directly connected to the bottom lead, and the edge horizontal voltage line being directly connected to the left lead.

3. a data line configured to transmit the data signal to the sub-pixel; and a data transistor configured to control a magnitude of a drive current through the light-emitting device, the light-emitting device configured to receive the drive current and be driven by the drive current to emit light. The data transistor is configured to write a data signal to a gate of the drive transistor in response to a first control signal. the display area includes a lower display area and an upper display area, the lower display area being close to the lower edge, and the upper display area being located on a side away from the lower edge of the lower display area in a vertical direction; the lower display area includes a first area and a second area, the first area includes a first sub-area close to the left edge in the horizontal direction and a second sub-area away from the left edge, the data lines passing through the first sub-area and the second area include a first connection line extending along the vertical direction in the first sub-area and a second connection line extending along the horizontal direction in the second area, the first connection line is disposed in the same layer as the vertical voltage line, the second connection line is disposed in the same layer as the horizontal voltage line, the first connection line and the second connection line of the same data line are electrically connected by a first connection hole, the first sub-area is located in the first intermediate display area, and at least a part of the second area is located in the intermediate display area, 3. The display substrate of claim 2, wherein the first sub-region has a left end point closest to the left edge of the display region in the horizontal direction, and a straight line extending along the vertical direction and passing through the left end point is a boundary line between the first edge display region and the first intermediate display region.

4. the boundary line passes through the second region and divides the second region into a first sub-region closer to a left edge of the display region and a second sub-region further from the left edge of the display region, the first sub-region being located in the first edge display region and the second sub-region being located in the first intermediate display region; The lower display area is a third region located in the first edge display region and located laterally of the second region away from the first region, the edge lateral voltage lines include a lower edge lateral voltage line located in the third region, the edge longitudinal voltage line passes through the third region and intersects with the lower edge lateral voltage line at a first intersection point, a left end of the lower edge lateral voltage line is electrically connected to the left lead, and a right end of the lower edge lateral voltage line opposite to the left end thereof and the second connecting line in the second region are cut by a first fracture surface; the vertical voltage lines include a plurality of the edge vertical voltage lines and a plurality of the edge horizontal voltage lines, the plurality of the edge vertical voltage lines and the plurality of the edge horizontal voltage lines are intertwined with each other to form a lattice, and the lattice includes a plurality of the first intersections; 4. The display substrate of claim 3, wherein at each position of some of the first intersections, one of the edge vertical voltage lines is electrically connected to one of the lower edge horizontal voltage lines through a first via.

5. 5. The display substrate of claim 4, wherein the plurality of edge vertical voltage lines are electrically connected to the plurality of edge horizontal voltage lines through the plurality of first vias, and a planar pattern formed by the positions of the plurality of first vias is a connecting line segment located in the third region, and the extension direction of the connecting line segment intersects both the first direction and the second direction.

6. 6. The display substrate of claim 4, wherein the third region is a corner region defined by a second side of the second region that is close to the left edge in the horizontal direction, the left edge, and the bottom edge.

7. The frame region includes a frame corner region surrounding the corner region, and a lattice-shaped auxiliary first power supply voltage line is disposed in the frame corner region, and the lattice-shaped auxiliary first power supply voltage line comprises: a plurality of auxiliary vertical voltage lines extending along the vertical direction and disposed in the same layer as the vertical voltage lines, wherein a first end of each of the auxiliary vertical voltage lines in the vertical direction is directly connected to the first power supply voltage lead, and a second end of each of the auxiliary vertical voltage lines opposite to the first end in the vertical direction is electrically connected to one of the edge vertical voltage lines passing through the corner region; 7. The display substrate of claim 6, further comprising: a plurality of horizontal auxiliary voltage lines extending along the horizontal direction and disposed in the same layer as the plurality of vertical auxiliary voltage lines, wherein one end of each of the horizontal auxiliary voltage lines in the horizontal direction is directly connected to the first power supply voltage lead, and a second end of each of the horizontal auxiliary voltage lines opposite to the first end in the horizontal direction is electrically connected to one of the edge vertical voltage lines.

8. the display area includes a pixel array, the pixel array including a plurality of pixel rows extending along the horizontal direction and a plurality of pixel columns extending along the vertical direction, the plurality of pixel rows including a plurality of edge pixel rows close to the bottom edge, the plurality of horizontal auxiliary voltage lines corresponding one-to-one to the plurality of edge pixel rows, each edge pixel row among the plurality of edge pixel rows including an edge sub-pixel closest to the left edge, and the plurality of edge vertical voltage lines including an edge-most vertical voltage line of an edge sub-pixel passing through each of the edge pixel rows; 8. The display substrate of claim 7, wherein a second end of each of the plurality of horizontal auxiliary voltage lines is electrically connected to an edge-most vertical voltage line passing through the corresponding edge pixel row, and is electrically connected to the edge horizontal voltage line passing through the corresponding edge pixel row through a first edge via.

9. The lateral voltage line is The display device further includes a plurality of first horizontal voltage lines arranged in the vertical direction and located in the upper display area, the left ends of the first horizontal voltage lines being electrically connected to the left lead, the edge horizontal voltage lines further include an upper edge horizontal voltage line located in the upper display area, and the upper edge horizontal voltage line is a part of one of the first horizontal voltage lines; The vertical voltage line is The display device further includes a plurality of intermediate vertical voltage lines arranged in the horizontal direction, passing through a portion of the first intermediate display area along the vertical direction and passing through the upper display area, wherein the plurality of intermediate vertical voltage lines, the plurality of edge vertical voltage lines and the plurality of first horizontal voltage lines are intertwined to form a lattice; the plurality of edge vertical voltage lines and the plurality of first horizontal voltage lines intersect at a plurality of auxiliary intersections within the first edge display area, and at each position of some of the plurality of auxiliary intersections, one edge vertical voltage line is electrically connected to one first horizontal voltage line through an auxiliary via, and the plurality of edge vertical voltage lines are electrically connected to the plurality of first horizontal voltage lines through a plurality of the auxiliary vias; The display substrate of claim 5 , wherein the plane pattern formed by the positions of the plurality of auxiliary vias is an auxiliary line segment located in the first edge display region, and an end of the auxiliary line segment away from the left edge is suspended.

10. the extension direction of the auxiliary line segment is the same as the extension direction of the connecting line segment, The display substrate of claim 9 , wherein the display substrate includes a plurality of the auxiliary line segments, and the connecting line segment and the plurality of auxiliary line segments are arranged at intervals along the vertical direction.

11. the display area further includes an upper edge opposite the lower edge, the first power supply voltage lead further includes an upper lead extending along the upper edge, the upper lead being electrically connected to the left lead; an upper end of the edge vertical voltage line is connected to the upper lead, and a lower end of the edge vertical voltage line opposite to the upper end is directly connected to the lower lead; The vertical voltage lines include an intermediate vertical voltage line located in the first intermediate display area, and the intermediate vertical voltage line is a first vertical voltage line that passes through the upper display region and at least a part of the second region in the vertical direction, an upper end of the first vertical voltage line electrically connected to the upper lead, and a lower end of the first vertical voltage line opposite to the upper end of the first vertical voltage line and the first connecting line in the first sub-region are cut by a second fracture surface; 11. The display substrate of claim 9, further comprising: a second vertical voltage line passing through the upper display region and the first region in the vertical direction, the horizontal voltage line including an intermediate horizontal voltage line located in the first region, the intermediate horizontal voltage line and a second connection line in the second region being cut by a third fracture surface, the second vertical voltage line and the intermediate horizontal voltage line intersecting at a second intersection, and the second vertical voltage line being electrically connected to the intermediate horizontal voltage line at the second intersection via a second via.

12. 12. The display substrate of claim 11, wherein the plurality of first horizontal voltage lines and the plurality of second vertical voltage lines intersect at a plurality of third intersections, and at each of at least some of the plurality of third intersections, one of the first horizontal voltage lines is electrically connected to one of the second vertical voltage lines through a third via.

13. the display area further includes a right edge opposite the left edge, the first power supply lead further includes a right lead extending along the right edge, the right lead being electrically connected to the top lead; 13. The display substrate according to claim 11, wherein each of the plurality of first horizontal voltage lines passes through the upper display area along the horizontal direction, and a right end of each of the plurality of first horizontal voltage lines opposite its left end is electrically connected to the right lead.

14. the plurality of intermediate vertical voltage lines and the plurality of first horizontal voltage lines intersect with each other at a plurality of fourth intersections in the upper display area, and at each position of some of the plurality of fourth intersections, one of the intermediate vertical voltage lines is electrically connected to one of the first horizontal voltage lines through a fourth via; The display substrate according to claim 13 , wherein a plane pattern formed by the positions of the plurality of fourth vias is a polygonal line.

15. the broken line includes a plurality of sub-broken lines extending from the left edge to the right edge, and each of the sub-broken lines includes a plurality of broken line portions whose leading ends are connected to their respective trailing ends; the plurality of bent line portions include a first line segment extending along a first direction and a second line segment extending along a second direction, the first direction intersects with the second direction, and both the first direction and the second direction intersect with the horizontal direction and the vertical direction, and a first end of the first line segment and a first end of the second line segment intersect at an upper vertex; The display substrate of claim 14 , wherein the vertices of the plurality of sub-bent lines are located on a second vertical voltage line, and the fourth vias at the vertex positions are all the second vias.

16. The display substrate of claim 15 , wherein each of the plurality of sub-folded lines has a W-shape.

17. the W-shaped sub-broken line includes the first line segment, the second line segment, a third line segment, and a fourth line segment, the first line segment and the second line segment are located between the third line segment and the fourth line segment, the third line segment is connected to the first line segment, and the fourth line segment is connected to the second line segment; the first line segment is substantially parallel to the fourth line segment; 17. The display substrate of claim 16, wherein the second line segment is substantially parallel to the third line segment.

18. 18. The display substrate of claim 17, wherein the vertical direction is perpendicular to the horizontal direction, the angle between the first line segment and the horizontal direction is 45 degrees, and the angle between the second line segment and the horizontal direction is 45 degrees.

19. 19. The display substrate according to claim 17, wherein the auxiliary line segment is located between third line segments of two adjacent sub-folded lines in the vertical direction.

20. 20. The display substrate of claim 19, wherein the connecting line segment, the auxiliary line segment, and the third line segment are substantially parallel to each other.

21. the second vertical voltage line divides the first region into the first sub-region and the second sub-region, and the structure of the first sub-region and the structure of the second sub-region are substantially axially symmetric with respect to the second vertical voltage line; the lower display area includes a fourth area, a structure of the fourth area and a structure of the second area are substantially axially symmetrical with respect to the second vertical voltage line, the data line passing through the first area and the fourth area includes a third connection line extending along the vertical direction in the second sub-area and a fourth connection line extending along the horizontal direction in the fourth area, the third connection line is disposed in the same layer as the vertical voltage line, the fourth connection line is disposed in the same layer as the horizontal voltage line, and the third connection line and the fourth connection line of the same data line are electrically connected by a second connection hole; A display substrate as described in any one of claims 15 to 20, wherein the right end opposite to the left end of the intermediate horizontal voltage line located in the first region and the fourth connection line in the fourth region are cut by a fourth fracture surface.

22. the display substrate includes a plurality of the first connection lines, a plurality of the second connection lines, a plurality of the third connection lines, and a plurality of the fourth connection lines, the plurality of first connection lines and the plurality of second connection lines being electrically connected to each other by a plurality of the first connection holes, and the plurality of third connection lines and the plurality of fourth connection lines being electrically connected to each other by a plurality of the second connection holes, a plane pattern formed by the plurality of first connection holes is a fifth line segment, the fifth line segment being a boundary between the first region and the second region; a plane pattern formed by the plurality of second connection holes is a sixth line segment, the sixth line segment being a boundary between the first region and the fourth region; the lower display area further includes a fifth area, a structure of the fifth area and a structure of the third area are substantially symmetrical with respect to the second vertical voltage line, and a plane pattern of a plurality of fifth vias symmetrical with respect to the plurality of first vias in the fifth area is a seventh line segment; 22. The display substrate of claim 21, wherein a plane pattern formed by sequentially connecting the connecting line segment, the fifth line segment, the sixth line segment, and the seventh line segment is the same as a plane pattern of each of the plurality of sub-folded lines.

23. a planar shape of the first region is a first triangle, a planar shape of the second region is a second triangle, a first side of the first triangle approaching the left edge in the horizontal direction overlaps with at least a part of a first side of the second triangle moving away from the left edge of the display region in the horizontal direction, two lower vertices of the first triangle are located at the lower edge of the display region, and a left vertex of the two lower vertices of the first triangle approaching the left edge is the left end point of the first sub-region, 23. The display substrate of claim 21 or 22, wherein the first triangle is an isosceles triangle, and the second vertical voltage line is approximately the perpendicular bisector of the base of the isosceles triangle.

24. the frame region includes a left frame region extending along the left edge, a plurality of auxiliary connection lines extending along the horizontal direction are disposed in the left frame region, and the plurality of auxiliary connection lines are disposed in the same layer as the edge vertical voltage lines; the display area includes a pixel array, the pixel array including a plurality of pixel rows extending along the horizontal direction and a plurality of pixel columns extending along the vertical direction, the plurality of pixel columns including an edge pixel column closest to the left edge, and the plurality of edge vertical voltage lines including an outer edge vertical voltage line passing through the edge pixel column; A display substrate as described in any one of claims 9 to 23, wherein the left end of each of the plurality of auxiliary connection lines in the horizontal direction is electrically connected to the left lead, and the right end of each of the plurality of auxiliary connection lines opposite to the left end in the horizontal direction is electrically connected to the outer edge vertical voltage line and is electrically connected to the left end of a corresponding one of the first horizontal voltage lines via a second edge via.

25. the right display area includes a second edge display area extending along the right edge and a second intermediate display area located on a side of the second edge display area closer to the left display area, A display substrate described in any one of claims 13 to 23, wherein the second edge display region and the first edge display region are symmetrical with respect to an axis of symmetry extending along the vertical direction, and the second intermediate display region and the first intermediate display region are axially symmetrical with respect to the second vertical voltage line.

26. The display substrate is a second power supply voltage line configured to provide the sub-pixel with a second power supply voltage different from the first power supply voltage; The display substrate of any one of claims 2 to 23, wherein the vertical voltage lines are arranged in the same layer as the data lines in the upper display area, and the horizontal voltage lines are arranged in the same layer as the second power supply voltage lines.

27. A display device comprising the display substrate according to any one of claims 1 to 26.

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