Light-emitting module and its driving assembly, display device

Abstract

The embodiments of the present disclosure provide a display device, a light-emitting module, and a driving assembly related to the field of display technology. The driving assembly includes a main control chip (MIC), a circuit selection chip set (MUXS), and a channel chip set (CHS). The circuit selection chip set (MUXS) includes a plurality of circuit selection chips (MUX) for electrically connecting to each light source voltage wiring (PVDDL) in one-to-one correspondence, and the circuit selection chip set (MUXS) is configured such that, under the control of the main control chip (MIC), each circuit selection chip (MUX) loads a light source voltage (PVDD) to the connected light source voltage wiring (PVDDL) one by one. The channel chip set (CHS) includes a plurality of channel control chips (CH), each of which is used for electrically connecting to one or more channel wirings (CHL). The channel chip set (CHS) is configured such that, under the control of the main control chip (MIC), the channel control chip (CH) controls the driving current of each connected channel wiring (CHL). The driving assembly can reduce the impact of the light-emitting substrate on the bezel.

Description

[Technical Field]

[0001] The present disclosure relates to the field of display technology, and in particular to a light emitting module and its driving assembly, a display device. [Background technology]

[0002] In a passively driven lamp substrate, a large number of anode and cathode wirings are provided on the lamp substrate, and the anodes of the light source are electrically connected to the anode wirings, and the cathodes are electrically connected to the cathode wirings. Accordingly, the driver chip needs to have a large number of pins to control the anode and cathode wirings, respectively. However, the driver chip has too many pins and a large chip area, which makes it difficult to integrate and is a disadvantage in reducing the bezel of the lamp substrate.

[0003] Please note that the information disclosed in the background section above is used only to enhance understanding of the background of the present disclosure and may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention [Means for solving the problem]

[0004] SUMMARY OF THE INVENTION An object of the present disclosure is to provide a light emitting module, a driving assembly thereof, and a display device that overcome the above-mentioned drawbacks of the prior art and reduce the impact of the driving assembly on the bezel of the light emitting substrate.

[0005] According to one aspect of the present disclosure, there is provided a driving assembly for a light emitting module, the light emitting module further comprising a light emitting substrate, the light emitting substrate including a plurality of light source voltage wirings extending along a first direction, a plurality of channel wirings extending along a second direction, and a plurality of light emitting circuits distributed in an array, each of the light emitting circuits having one end connected to the light source voltage wiring and the other end connected to the channel wiring, one of the first direction and the second direction being a row direction and the other being a column direction; The driving assembly includes a main control chip, a circuit selection chip set, and a channel chip set; the circuit selection chip set includes a plurality of circuit selection chips for electrically connecting to the light source voltage wirings in one-to-one correspondence, and the circuit selection chip set is configured such that, under the control of the main control chip, each of the circuit selection chips loads a light source voltage onto the light source voltage wirings connected thereto one by one; The channel chipset includes a plurality of channel control chips, each of which is used to electrically connect to one or more channel wirings, and the channel chipset is configured such that, under the control of the main control chip, the channel control chip controls the drive current in each of the connected channel wirings.

[0006] According to an embodiment of the present disclosure, the driving assembly further includes a flexible circuit board for coupling and connecting to the light emitting substrate, and the main control chip is provided on the flexible circuit board; The circuit selection chip and the channel control chip are used by being coupled to the light emitting substrate, and are electrically connected to the flexible circuit board through wiring provided on the light emitting substrate.

[0007] According to one embodiment of the present disclosure, the circuit selection chip set is provided at one end of the light emitting substrate in the first direction, and the channel chip set is provided at one end of the light emitting substrate in the second direction.

[0008] According to an embodiment of the present disclosure, the circuit selection chip is a pure analog module, including a selection control module and a voltage output unit, the control end of the voltage output unit is electrically connected to the selection control module, the first end of the voltage output unit is used to load the light source voltage, and the second end of the voltage output unit is electrically connected to the light source voltage wiring; The selection control module is configured to electrically conduct the voltage output units under the control of a clock signal and a column start signal, and the circuit selection chip is further configured to load the light source voltage onto the light source voltage line.

[0009] According to an embodiment of the present disclosure, the circuit selection chip includes a light source voltage input pin for loading the light source voltage, a clock pin for loading the clock signal, a column start signal pin for loading the column start signal, and an output pin for electrically connecting to the light source voltage wiring; Each of the circuit selection chips in the circuit selection chip set is cascaded in sequence, and the clock pins of each of the circuit selection chips are both used to load a clock signal from the main control chip, and the column start signal pin of the first stage circuit selection chip is used to load a column start signal from the main control chip, and in two adjacent stages of circuit selection chips, the output pin of the previous stage circuit selection chip is electrically connected to the column start signal pin of the next stage circuit selection chip so that the output of the previous stage circuit selection chip becomes the column start signal of the next stage circuit selection chip.

[0010] According to an embodiment of the present disclosure, the channel control chip includes a synchronous clock pin, a data pin, and an output pin, and the channel control chip is configured to acquire the first received driving data in one data transmission stage, and after acquiring the driving data, transfer each subsequent driving data through the output pin; Each channel control chip in the channel chip set is cascaded in sequence, and the synchronous clock pins of each channel control chip are both used to receive a synchronous clock signal from the main control chip, and the data pins of the first-stage channel control chip are used to receive driving data from the main control chip. In adjacent two-stage channel control chips, the output pins of the previous-stage channel control chip are electrically connected to the data pins of the next-stage channel control chip.

[0011] According to an embodiment of the present disclosure, the channel control chip includes at least one driving unit group, and the driving unit group includes a waveform modulation unit, an output control unit, and a waveform control unit; a first end of the waveform control unit is used to load a voltage signal that electrically makes the output control unit conductive, a control end of the waveform control unit is electrically connected to the waveform modulation unit, a second end of the waveform control unit is electrically connected to the control end of the output control unit, the first end of the output control unit is electrically connected to the channel wiring, and the second end of the output control unit is used to load a ground voltage; The logic module of the channel control chip is configured to obtain a waveform modulation signal according to the obtained driving data, and the waveform modulation unit is used to control the electrical conduction state of the waveform control unit according to the waveform modulation signal.

[0012] According to one embodiment of the present disclosure, the waveform control unit and the output control unit are both MOS tubes.

[0013] According to one embodiment of the present disclosure, the driving unit group further includes a power amplifier, the input end of the power amplifier is electrically connected to the logic module of the channel control chip, and the output end of the power amplifier is electrically connected to the first end of the waveform control unit.

[0014] According to an embodiment of the present disclosure, the driving unit group further includes a source current control unit; a first end of the source current control unit is electrically connected to a second end of the output control unit, the second end of the source current control unit is used to load the ground voltage, and a control end of the source current control unit is electrically connected to a logic module of the channel control chip; The logic module of the channel control chip is configured to obtain an amplitude control signal according to the obtained driving data, and send it to the source current control unit; The source current control unit is used to control the magnitude of the current flowing through the source current control unit according to the amplitude control signal.

[0015] According to an embodiment of the present disclosure, the driving unit group further includes a local dimming unit, an input end of the local dimming unit is electrically connected to the logic module of the channel control chip, and an output end of the local dimming unit is electrically connected to a first end of the waveform control unit; The logic module of the channel control chip is configured to obtain an amplitude modulation signal according to the obtained driving data and send it to the local dimming unit; The local dimming unit outputs different voltage signals according to the amplitude modulation signal to control the current amplitude when the output control unit is electrically conducted.

[0016] According to an embodiment of the present disclosure, the driving unit group further includes a source current control unit; a first end of the source current control unit is electrically connected to a second end of the output control unit, the second end of the source current control unit is used to load the ground voltage, and a control end of the source current control unit is electrically connected to a logic module of the channel control chip; The logic module of the channel control chip is configured to obtain an amplitude control signal according to the obtained driving data, and send it to the source current control unit; The source current control unit is used to control the magnitude of the current flowing through the source current control unit according to the amplitude control signal.

[0017] According to an embodiment of the present disclosure, the driving unit group further includes a current detection unit; The current detection unit is used to detect the current amplitude of the first end of the output control unit and feed it back to the logic module of the channel control chip; The logic module of the channel control chip adjusts the amplitude modulation signal and / or the amplitude control signal according to the feedback of the current detection unit.

[0018] According to an embodiment of the present disclosure, the channel control chip includes a driving unit group and a plurality of channel pins for connecting to different channel wirings, and the channel control chip further includes a switching unit; A first end of the output control unit is electrically connected to the switching unit, and each of the channel pins is electrically connected to the switching unit, and the switching unit is configured such that each of the channel pins forms an electrical path with the output control unit one by one.

[0019] According to an embodiment of the present disclosure, the channel control chip includes a plurality of driving unit groups and channel pins corresponding to each of the driving unit groups one-to-one, the channel pins being used to connect to the channel wirings; A first end of the output control unit of each of the driving unit groups is electrically connected to the corresponding channel pin.

[0020] According to an embodiment of the present disclosure, the circuit selection chip includes a logic module and an output control module; The output control module is configured to output the light source voltage with a modulated current amplitude under the control of the logic module.

[0021] According to one embodiment of the present disclosure, the circuit selection chip includes a synchronous clock pin, a data input pin, and a data output pin; The circuit selection chip is configured to, in one data transmission stage, acquire the first driving data received by the data input pin, and after acquiring the driving data, transfer each subsequent driving data through the data output pin; Each circuit selection chip in the circuit selection chip set is cascaded in sequence, and the synchronous clock pins of each circuit selection chip are both used to receive a synchronous clock signal from the main control chip, and the data input pin of the first stage circuit selection chip is used to receive driving data from the main control chip, and in two adjacent stages of circuit selection chips, the data output pin of the previous stage circuit selection chip is electrically connected to the data input pin of the next stage circuit selection chip.

[0022] According to an embodiment of the present disclosure, the logic module of the circuit selection chip includes a selection control module and a current control register, and the output control module of the circuit selection chip includes a power amplifier, a local dimming unit, and a voltage output unit; The input terminal of the local dimming unit is used to load a substrate power supply voltage, and the output terminal of the local dimming unit is electrically connected to the control terminal of the voltage output unit; a first control end of the local dimming unit electrically connected to the current control register, for controlling the magnitude of the voltage signal to be output under the control of the current control register, and for controlling the amplitude of the current flowing through the voltage output unit when the voltage output unit is electrically conducted; a second control end of the local dimming unit electrically connected to the power amplifier, and configured to output the voltage signal under the control of the power amplifier; the power amplifier is electrically connected to the selection control module; a first end of the voltage output unit is electrically connected to the light source voltage wiring, and a second end of the voltage output unit is used to load the light source voltage; The logic module of the circuit selection chip is configured to obtain timing information and amplitude information according to the obtained driving data; The selection control module is used to control the power amplifier according to the timing information, and further to control whether the circuit selection chip outputs the light source voltage, and the current control register is used to control the second control end of the local dimming unit according to the amplitude information, and further to control the amplitude of the current output by the circuit selection chip.

[0023] According to one embodiment of the present disclosure, the main control chip is configured to provide the clock signal and the column start signal to the circuit selection chipset.

[0024] According to an embodiment of the present disclosure, the main control chip is configured to provide the circuit selection chip set with each driving data required by the circuit selection chip set; The circuit selection chip can output a light source voltage whose current amplitude is modulated according to the acquired driving data.

[0025] According to an embodiment of the present disclosure, the driving data sent by the main control chip to the circuit selection chip includes timing information and amplitude information required by the circuit selection chip; The timing information is used to control when the circuit selection chip outputs the light source voltage, and the amplitude information is used to control the amplitude of the current output by the circuit selection chip.

[0026] According to an embodiment of the present disclosure, the main control chip is configured to provide the channel chipset with each driving data required by the channel chipset, the driving data including waveform modulation information; The channel control chip can obtain a waveform modulation signal according to the obtained driving data, and control the waveform of the driving current in the channel wiring according to the waveform modulation signal.

[0027] According to an embodiment of the present disclosure, the main control chip is configured to provide the channel chipset with each driving data required by the channel chipset, and the driving data includes current amplitude information; The channel control chip can control the current amplitude of the driving current in the channel wiring according to the acquired driving data.

[0028] According to one embodiment of the present disclosure, the number of circuit selection chips in the circuit selection chip set is greater than the number of channel control chips in the channel chip set.

[0029] According to a second aspect of the present disclosure, there is provided a light emitting module including the above-described drive assembly and the light emitting substrate.

[0030] According to a third aspect of the present disclosure, there is provided a display device including a liquid crystal display panel and a backlight module, wherein the backlight module includes the above-mentioned light-emitting module.

[0031] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure.

[0032] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without any creative efforts. [Brief explanation of the drawings]

[0033] [Figure 1] 1 is a schematic configuration diagram of a display device according to an embodiment of the present disclosure. [Figure 2] 1 is a schematic diagram illustrating the configuration of a liquid crystal display panel according to one embodiment of the present disclosure. [Figure 3]1 is a schematic configuration diagram of a light-emitting module according to an embodiment of the present disclosure. [Figure 4] FIG. 1 is a schematic configuration diagram of a channel control chip according to an embodiment of the present disclosure. [Figure 5] FIG. 1 is a schematic diagram of a cascade of channel control chips according to an embodiment of the present disclosure. [Figure 6] FIG. 1 is a schematic configuration diagram of a circuit selection chip according to an embodiment of the present disclosure. [Figure 7] FIG. 1 is a schematic diagram of a cascade of circuit selection chips according to an embodiment of the present disclosure. [Figure 8] FIG. 2 is a schematic configuration diagram of a main control chip according to an embodiment of the present disclosure. [Figure 9] 1 is a timing diagram illustrating a channel control chip receiving driving data and a circuit selection chip outputting a light source voltage in one embodiment of the present disclosure. [Figure 10] FIG. 1 is a schematic configuration diagram of a channel control chip according to an embodiment of the present disclosure. [Figure 11] FIG. 1 is a schematic configuration diagram of a channel control chip according to an embodiment of the present disclosure. [Figure 12] FIG. 1 is a schematic structural diagram of a channel control chip according to an embodiment of the present disclosure. [Figure 13] FIG. 1 is a schematic configuration diagram of a circuit selection chip according to an embodiment of the present disclosure. [Figure 14] FIG. 1 is a schematic configuration diagram of a channel control chip according to an embodiment of the present disclosure. [Figure 15] FIG. 1 is a schematic configuration diagram of a channel control chip according to an embodiment of the present disclosure. [Figure 16] 1 is a schematic configuration diagram of a light-emitting module according to an embodiment of the present disclosure. [Figure 17] 1 is a schematic configuration diagram of a light-emitting module according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0034] Next, exemplary embodiments will be described in more detail with reference to the accompanying drawings. However, exemplary embodiments may be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the illustrative concepts to those skilled in the art. Note that the same reference numerals in the various drawings indicate the same or similar components, and detailed descriptions thereof will be omitted. Furthermore, the drawings are merely schematic diagrams of the present disclosure and are not necessarily drawn to scale.

[0035] Relative terms such as "above," "below," and the like are used herein to describe the relative relationship of one component of an icon to another, and these terms are used solely for convenience herein, e.g., according to exemplary orientations set forth in the drawings. It is understood that if the device of the icon is turned upside down, the component described as "above" becomes the "below" component. When a structure is "above" another structure, it indicates whether the structure is integrally formed with the other structure, or whether the structure is "directly" disposed on the other structure, or whether the structure is "indirectly" disposed on the other structure via another structure.

[0036] The terms "a," "one," "this," "said," and "at least one" indicate the presence of one or more elements / components / etc. The terms "including" and "having" are used to indicate an open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc. The terms "first," "second," "third," etc. are used merely as tags and not as quantitative limitations on their subject matter.

[0037] A transistor is an element that has at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, channel region, and source electrode. The channel region refers to the region through which current mainly flows.

[0038] The present disclosure provides a display device including a display module and a control module that drives the display module. The display module may be a liquid crystal display module, or a display module that directly displays using self-luminous light-emitting elements (e.g., a panel with an array of LEDs, OLEDs, QLEDs, micro LEDs, mini LEDs, or other self-luminous elements). In the embodiments of the present disclosure, a liquid crystal display module is used as an example of the display module, and the display device and its control module of the present disclosure will be described as an example.

[0039] FIG. 1 shows a schematic configuration diagram of a display device according to one embodiment of the present disclosure. In the example of FIG. 1, the display module includes a liquid crystal display panel and a backlight module BLU that provides backlight to the liquid crystal display panel. The control module CTR can simultaneously drive the liquid crystal display panel and the backlight module BLU. In other examples of the present disclosure, the display module may be another type of display panel. For example, it may be an OLED (organic electroluminescent diode) display panel, a micro LED (micro light-emitting diode) display panel, a QD-OLED (quantum dot organic electroluminescent diode) display panel, a QLED (quantum dot light-emitting diode) display panel, a PLED (polymer organic electroluminescent diode) display panel, an LED (light-emitting diode) display panel, or another display panel equipped with light-emitting elements. In this case, the control module CTR can directly drive the light-emitting elements on the display panel to display images and provide illumination.

[0040] In the embodiments of the present disclosure, a liquid crystal display device is taken as an example of a display device, and the structure, function, and driving method of the display device of the present disclosure will be introduced as an example.

[0041] From the perspective of the laminated structure, a liquid crystal display panel includes an array substrate and a color filter substrate stacked in order. The array substrate, the color filter substrate, and a frame seal adhesive disposed between them form a closed box-shaped region, which is filled with liquid crystal. The liquid crystal display panel further includes a first polarizer located on the side of the array substrate far from the color filter substrate and a second polarizer located on the side of the color filter substrate far from the array substrate. The array substrate is provided with pixel electrodes and pixel driving circuits for loading data voltages to the pixel electrodes. A common electrode is also provided on the array substrate or the color filter substrate. Controlling the electric field strength between the pixel electrode and the common electrode adjusts the degree of twist or collapse of the liquid crystal within the corresponding area of the pixel electrode, which in turn adjusts the polarization direction of polarized light passing through the liquid, ultimately adjusting the light extraction efficiency of the liquid crystal display panel within the corresponding area of the pixel electrode.

[0042] FIG. 2 shows a schematic diagram of a liquid crystal display panel PNL according to one embodiment of the present invention. In a plan view, the liquid crystal display panel PNL includes a display area AA and a peripheral area BB surrounding the display area AA. In the display area AA, the array substrate is provided with gate lines GTW extending along the row direction and data lines DW extending along the column direction. The gate lines GTW and data lines DW define a plurality of pixel areas in which pixel electrodes and pixel driving circuits are arranged. In one example, the pixel driving circuit is a thin-film transistor (TFT) functioning as a switching transistor. One end of the switching transistor is electrically connected to the data line DW, the other end of the switching transistor is connected to the pixel electrode, and the gate of the switching transistor is connected to the gate line GTW. The peripheral area BB of the array substrate includes a first peripheral area B1 coupled to the source driving circuit SIC and a second peripheral area B2 in which the gate driving circuit GOA is arranged. Of these, the first peripheral area B1 extends along the column direction, and the second peripheral area B2 extends along the row direction. The gate driving circuit GOA is electrically connected to each gate line GTW and is used to load scanning signals to the gate lines GTW to turn on the switching transistors, and the source driving circuit SIC is electrically connected to the data lines DW and is used to generate data voltages according to screen synchronization data and load them onto the data lines DW.

[0043] Referring to FIG. 2, in this example, the liquid crystal display panel PNL has a plurality of source driver circuits SIC, each capable of driving a plurality of data wirings DW. The source driver circuits SIC are chips, and the array substrate has a first peripheral region B1 provided with an FPC (flexible circuit board) coupling area and a source driver circuit coupling area. The source driver circuit coupling area can be coupled to the source driver circuits SIC, and the source driver circuit coupling area is electrically connected to the data wirings DW and the flexible circuit board FPC coupling area via wiring. The FPC coupling area can be coupled to and connected to the control module CTR via the flexible circuit board. In this way, signals and voltages from the control module CTR can be transmitted to the source driver circuits SIC via the flexible circuit board. Furthermore, signals between the source driver circuits SIC and the control module CTR can be LVDS (low-voltage differential signaling) signals or mini-LVDS signals to reduce signal crosstalk.

[0044] Of course, in other embodiments of the present invention, the liquid crystal display panel PNL may have other structures. For example, the gate driving circuit GOA may not be provided on the array substrate, and an additional gate driving circuit substrate may be coupled to the array substrate. As another example, the array substrate may have gate driving circuits GOA on both sides in the row direction to reduce the voltage drop of the scanning signal or increase the scanning frequency. As another example, source driving circuits SIC may be provided on both ends in the column direction of the array substrate to drive the liquid crystal display panels PNL on both sides, thereby reducing the voltage drop of the data wiring DW in a large liquid crystal display panel PNL, especially in a junction screen. As another example, the source driving circuit SIC may not be provided on the liquid crystal display panel PNL but may be provided on a COF (Chip On Film). The present disclosure does not limit the relative positional relationship or arrangement between the source driving circuit SIC and the liquid crystal display panel PNL, as long as the source driving circuit SIC can directly drive each pixel in the display area of the liquid crystal display panel PNL.

[0045] A backlight module BLU according to an embodiment of the present disclosure includes a light-emitting substrate BPNL. FIG. 3 illustrates an example of the structure of the light-emitting substrate BPNL in the present disclosure. Referring to FIG. 3, the light-emitting substrate BPNL is provided with at least one lamp area (each lamp area is provided with a light-emitting circuit LEDA), e.g., a plurality of lamp areas distributed in an array. In one example, the lamp areas are distributed in an array, e.g., a plurality of lamp area rows and a plurality of lamp area columns, each lamp area row including a plurality of lamp areas arranged along the row direction, and each lamp area column including a plurality of lamp areas arranged along the column direction. In this way, the backlight module BLU can exhibit good light-emitting uniformity, which is advantageous for debugging the backlight module BLU.

[0046] Each lamp area includes one or more light-emitting elements (e.g., Mini LEDs or Micro LEDs). When multiple light-emitting elements are present in the same lamp area, the light-emitting elements can be connected in series, parallel, or series-parallel to drive each light-emitting element, for example, so that each light-emitting element is in an electrical path with the same current amplitude. Multiple light-emitting elements in an electrical path constitute a light-emitting circuit LEDA. In the present disclosure, the CTR controls the brightness of each light-emitting element in the lamp area to control the brightness of the entire lamp area. Optionally, under the control of the control module CTR, the brightness of each light-emitting element in the lamp area is controlled, and the brightness of the lamp area is also controlled, so that the brightness of the backlight module BLU cooperates with the image of the liquid crystal display panel PNL to improve display effects, such as enhancing contrast.

[0047] The light-emitting substrate BPNL is further provided with a plurality of light-source voltage wirings PVDDL extending along a first direction and a plurality of channel wirings CHL extending along a second direction. One of the first and second directions is the row direction DH, and the other is the column direction DV. For example, referring to the example of FIG. 3 , the light-emitting substrate BPNL is further provided with a plurality of light-source voltage wirings PVDDL extending along the row direction DH and a plurality of channel wirings CHL extending along the column direction DV. Of these, one end of any of the light-emitting circuits LEDA is connected to the light-source voltage wiring PVDDL, and the other end is connected to the channel wiring CHL. In this way, when the light source voltage PVDD is loaded to the light-source voltage wiring PVDDL connected to the light-emitting circuit LEDA, and the channel wiring CHL connected to the light-emitting circuit LEDA is electrically connected to the ground voltage wiring, an electrical path is formed between the light-source voltage wiring PVDDL, the light-emitting circuit LEDA, and the ground voltage wiring, thereby allowing a drive current to pass through the light-emitting circuit LEDA, driving the light-emitting circuit LEDA to emit light.

[0048] In one example, the light-emitting substrate BPNL includes 72*8 light-emitting circuits LEDA (i.e., 72*8 lamp areas). In this way, the light-emitting substrate BPNL can be provided with 72 channel wirings CHL for driving the 72 columns of light-emitting circuits LEDA, and 8 light source voltage wirings PVDDL for driving the 8 rows of light-emitting circuits LEDA.

[0049] In the liquid crystal display device of the present disclosure, the control module CTR may include a data processing module and a driver assembly for directly driving the light-emitting modules. The data processing module may receive and process screen data and obtain screen synchronization data and backlight synchronization data. The screen synchronization data may be sent to the source driver circuit of the light-emitting substrate BPNL to drive the light-emitting substrate BPNL to display the screen. The backlight synchronization data may be sent to the driver assembly, which may drive the light-emitting substrate BPNL according to the obtained backlight synchronization data.

[0050] Conventionally, a driver chip for driving a light-emitting substrate BPNL simultaneously drives each light source voltage wiring PVDDL and each channel wiring CHL. Specifically, the driver chip has a first pin corresponding to each light source voltage wiring PVDDL and a second pin corresponding to each channel wiring CHL. Each first pin is electrically connected to the corresponding light source voltage wiring PVDDL via wiring, and each second pin is electrically connected to the corresponding channel wiring CHL via wiring. When the driver chip is mounted on a flexible circuit board FPC and the flexible circuit board FPC is coupled to the light-emitting substrate BPNL, multiple pins must be provided on the flexible circuit board FPC and the light-emitting substrate BPNL. This increases the difficulty of coupling the flexible circuit board FPC to the light-emitting substrate BPNL and increases the fan-out wiring area of the light-emitting substrate BPNL, making it difficult to reduce the bezel size of the light-emitting substrate BPNL. If the driving chip is directly bonded to the light emitting substrate BPNL, the driving chip has a large area and occupies a large space, which still increases the fan-out wiring area of the light emitting substrate BPNL and is therefore disadvantageous to reducing the bezel of the light emitting substrate BPNL.

[0051] To this end, an embodiment of the present disclosure provides a light emitting module including a light emitting substrate BPNL and a driving assembly for driving the light emitting substrate. It should be understood that the light emitting substrate in the embodiment of the present disclosure may be used as a lamp substrate in a backlight module of a liquid crystal display device, or may be used as a display panel for directly displaying a screen. Hereinafter, a light emitting substrate and its driving assembly according to an embodiment of the present disclosure will be described by way of example, taking a lamp substrate as the light emitting substrate.

[0052] 3, the driving assembly includes a main control chip MIC, a circuit selection chip set MUXS, and a channel chip set CHS, wherein the circuit selection chip set MUXS includes a plurality of circuit selection chips MUX for electrically connecting to the light source voltage wirings PVDDL in one-to-one correspondence, and the circuit selection chip set MUXS is configured such that each of the circuit selection chips MUX loads a light source voltage PVDD to the connected light source voltage wirings PVDDL one by one under the control of the main control chip MIC.

[0053] The channel chip set CHS includes a plurality of channel control chips CH, each of which is electrically connected to one or more channel wirings CHL, and the channel chip set CHS is configured to control the driving current in the connected channel wirings CHL under the control of the main control chip MIC, and the light-emitting circuit LEDA emits light by being driven by the driving current.

[0054] According to the driving assembly provided by the present disclosure, the main control chip MIC does not need to have pins corresponding one-to-one to each light source voltage wiring PVDDL and each channel wiring CHL, but only needs to have pins on the driving circuit selection chip set MUXS and the channel chip set CHS, which can significantly reduce the number of pins on the main control chip MIC and is advantageous for the main control chip MIC to be directly coupled to the light emitting substrate BPNL or coupled to the light emitting substrate BPNL via a flexible printed circuit board FPC.The main control chip MIC does not need to directly control the light source voltage PVDD loaded to each light source voltage wiring PVDDL or the driving current loaded to each channel wiring CHL, which reduces the functions of the main control chip MIC, further reducing the area and cost of the main control chip MIC. Correspondingly, each circuit selection chip MUX only needs to control the light source voltage PVDD loaded on the light source voltage wiring PVDDL under direct or indirect control of the main control chip MIC, and the function and structure are relatively simple, without the bezel of the light emitting substrate BPNL being affected by the installation of too many signal wirings, a large occupied area, etc., and there is no significant increase in costs due to the increase in the circuit selection chip MUX. Correspondingly, each channel control chip CH only needs to control the drive current (e.g., the PWM waveform of the drive current) on the control channel wiring CHL under direct or indirect control of the main control chip MIC, and the function and structure are relatively simple, without the bezel of the light emitting substrate BPNL being affected by the installation of too many signal wirings, a large occupied area, etc., and there is no significant increase in costs due to the increase in the channel control chip CH.

[0055] In one embodiment of the present disclosure, referring to FIG. 3 , the driving assembly further includes a flexible circuit board FPC coupled to and connected to the light emitting substrate BPNL. The main control chip MIC is mounted on the flexible circuit board FPC, and the circuit selection chip MUX and the channel control chip CH are coupled to the light emitting substrate BPNL and electrically connected to the flexible circuit board FPC via wiring provided on the light emitting substrate BPNL. In this manner, the difficulty of assembling the driving assembly and the bezel of the light emitting substrate BPNL can be both reduced, thereby achieving the objective of reducing the bezel of the light emitting substrate BPNL. Furthermore, the flexible circuit board FPC is coupled to the back surface of the light emitting substrate BPNL, i.e., the flexible circuit board FPC and the light emitting circuit LEDA are located on both sides of the base substrate of the light emitting substrate BPNL. This further reduces the bezel of the light emitting substrate BPNL, which is particularly advantageous when joining multiple different light emitting substrates BPNL to form a large panel.

[0056] In one embodiment of the present disclosure, the circuit selection chip MUX and the channel control chip CH may be coupled to the back surface of the light emitting substrate BPNL, i.e., the circuit selection chip MUX and the channel control chip CH may be disposed on the side of the base substrate (e.g., a glass substrate) away from the light emitting circuit LEDA. Of course, the circuit selection chip MUX and the channel control chip CH may also be disposed on the front surface of the light emitting substrate BPNL, i.e., the circuit selection chip MUX and the channel control chip CH may be disposed on the same side of the light emitting substrate BPNL as the light emitting circuit LEDA.

[0057] In one embodiment of the present disclosure, the circuit selection chip set MUXS is provided at one end of the light-emitting substrate BPNL in the first direction XA, and the channel chip set CHS is provided at one end of the light-emitting substrate BPNL in the second direction XB. Exemplarily, referring to FIG. 3 , the light source voltage wiring PVDDL extends along the row direction DH, the channel wiring CHL extends along the column direction DV, the circuit selection chip MUX is provided at an end of the light-emitting substrate BPNL in the row direction, and the channel control chip CH is provided at an end of the light-emitting substrate BPNL in the column direction. Exemplarily, the circuit selection chips MUX of the circuit selection chip set MUXS are provided at the left or right end of the light-emitting substrate BPNL and are arranged in the column direction DV. The channel control chips CH of the channel chip set CHS are provided at the bottom end of the light-emitting substrate BPNL and are arranged in the row direction DH.

[0058] In another embodiment of the present disclosure, referring to FIG. 17 , the light source voltage wiring PVDDL extends along the column direction DV, and the channel wiring CHL extends along the row direction DH. Correspondingly, the channel control chips CH are provided at the row-direction ends of the light-emitting substrate BPNL, and the circuit selection chips MUX are provided at the column-direction ends of the light-emitting substrate BPNL. Exemplarily, the circuit selection chips MUX of the circuit selection chip set MUXS are provided at the bottom end of the light-emitting substrate BPNL and are arranged along the row direction DH. The channel control chips CH of the channel chip set CHS are provided at the left or right end of the light-emitting substrate BPNL and are arranged along the column direction DV. This embodiment is particularly suitable for light-emitting substrates BPNL with a large ratio of length (dimension along the row direction) to width (dimension along the column direction), such as strip advertising screens. In this embodiment, the usage of the channel control chip CH can be reduced and the usage of the circuit selection chip MUX can be increased. Since the channel control chip CH generally occupies a larger area and is more expensive than the circuit selection chip MUX, this method can reduce the bezel of the light emitting substrate BPNL and reduce the cost of the light emitting module.

[0059] In one embodiment of the present disclosure, the light-emitting substrate BPNL includes a drive layer and a device layer. The drive layer includes wiring for driving the light-emitting circuit LEDA, such as a light source voltage wiring PVDDL and a channel wiring CHL, as well as wiring for driving the circuit selection chip MUX and the channel control chip CH. The drive layer may further include pads for coupling devices, which are electrically connected to the wiring or form part of the wiring. The device layer may include the light-emitting elements of the light-emitting circuit LEDA, which may be coupled to pads in the drive layer. When the circuit selection chip MUX and the channel control chip CH are coupled to the light-emitting substrate BPNL, the circuit selection chip MUX and the channel control chip CH may also be coupled to pads in the drive layer as electronic components. In this way, in a light-emitting module (the light-emitting substrate BPNL to which the circuit selection chip MUX and the channel control chip CH are coupled), the electronic components in the device layer include the light-emitting elements, the circuit selection chip MUX, and the channel control chip CH. Of course, the light emitting substrate BPNL may be provided with other electronic components such as a temperature detecting component for detecting temperature and a light detecting component for detecting the intensity of light, as required.

[0060] 4, in one embodiment of the present disclosure, the channel control chip CH is a digital chip including at least one logic module, and may have pins such as a chip power supply pin VCCP, a synchronous clock pin SCKP, a data pin DataP, an output pin OUTP, a channel pin CHP, and a wire pin GNDP.

[0061] The chip power supply pins VCCP of the channel control chips CH load the required chip power supply voltage to the channel control chips CH so that the channel control chips CH obtain the power necessary for operation. In one example, the light emitting substrate BPNL is provided with chip power supply wiring for loading the chip power supply voltage required by the channel control chips CH, and the chip power supply pins VCCP of the channel control chips CH are electrically connected to the chip power supply wiring.

[0062] The wire pin GNDP of the channel control chip CH is used to load a ground voltage GND to the channel control chip CH. In one example, a ground line for loading the ground voltage GND is provided on the light emitting substrate BPNL, and the wire pin GNDP of the channel control chip CH is electrically connected to the ground line.

[0063] The channel pin CHP is electrically connected to the channel wiring CHL in order to control the drive current of the channel wiring CHL.

[0064] The synchronous clock pin SCKP of the channel control chip CH loads the synchronous clock signal SCK so that the channel control chip CH and the main control chip MIC maintain clock synchronization. Furthermore, referring to Fig. 8, the main control chip MIC has a synchronous clock output pin SCKPO for outputting the synchronous clock signal SCK. Referring to Fig. 5, the light emitting substrate BPNL has a synchronous clock wiring SCKL for loading the synchronous clock signal SCK. The synchronous clock wiring SCKL is electrically connected to the synchronous clock output pin SCKPO of the main control chip MIC and to the synchronous clock pin SCKP of each channel control chip CH. In this way, the synchronous clock signal SCK output by the main control chip MIC can be loaded to each channel control chip CH.

[0065] The data pins DataP of the channel control chip CH are used to receive drive data Data, configure the channel control chip CH according to the received drive data Data, and control the drive current in the channel wiring CHL. Among these, the control of the drive current in the channel wiring CHL by the channel control chip CH includes control of the PWM waveform of the drive current in the channel wiring CHL, and in some embodiments, the control of the drive current in the channel wiring CHL by the channel control chip CH further includes control of the amplitude of the drive current.

[0066] The output pin OUTP of the channel control chip CH is used to transfer signals. If the driving data Data received by the data pin DataP of a channel control chip CH does not belong to this channel control chip CH, the channel control chip CH can transfer the driving data Data through the output pin OUTP. In this way, referring to FIG. 5, a plurality of channel control chips CH can be sequentially cascaded, and the output pin OUTP of the channel control chip CH of the previous stage is electrically connected to the data pin DataP of the channel control chip CH of this stage (for example, electrically connected by a second connection line TRLB provided on the light-emitting substrate BPNL), and the output pin OUTP of the channel control chip CH of this stage is electrically connected to the data pin DataP of the channel control chip CH of the next stage (for example, electrically connected by a second connection line TRLB provided on the light-emitting substrate BPNL), and the data pin DataP of the channel control chip CH of the first stage (i.e., CH(1) in FIG. 5) is electrically connected to the data output pin DataPO of the main control chip MIC by a data wiring DataL provided on the light-emitting substrate BPNL. In FIG. 5, CH(N) represents the final-stage channel control chip CH. Here, N is the total number of channel control chips CH in the channel chipset CHS. In this way, the main control chip MIC does not need to set a data output pin DataPO for each channel control chip CH. Instead, it can set one data output pin DataPO for the channel chipset CHS. This data output pin DataPO can output the driving data Data required by each channel control chip CH. These driving data Data are respectively acquired by each channel control chip CH. This further reduces the area and number of pins of the main control chip MIC, and further reduces the number of wirings required to drive the channel chipset CHS. In particular, it reduces the wiring area required to drive the channel chipset CHS.

[0067] In one example, the channel control chip CH is configured to acquire the first driving data Data received in one data transmission stage, and after acquiring the driving data Data, transfer each subsequent driving data Data through the output pin OUTP. That is, when the channel control chip CH receives the driving data Data for the first time, the driving data Data is used as the driving data Data required by the channel control chip CH, and after acquiring the required driving data Data, each received driving data Data (i.e., the driving data Data received for the second time and thereafter) is transferred to the channel control chip CH of the next stage through the output pin OUTP as unnecessary driving data Data. 9, each driving data Data sequentially transmitted by the main control chip MIC through the data output pin DataPO can be sequentially received by each channel control chip CH in cascade order, where the first driving data Data (i.e., driving data Data1 in FIG. 9) is received by the first-stage channel control chip CH (i.e., CH(1) in FIG. 5), the second driving data Data (i.e., driving data Data2 in FIG. 9) is received by the second-stage channel control chip CH (i.e., CH(2) in FIG. 5), and so on until the last driving data Data is received by the last-stage channel control chip CH. In a further example, the size and format of each driving data Data are fixed, and in one data transmission stage, each channel control chip CH receives its own driving data Data and then transmits the next transmitted driving data Data to the next-stage channel control chip CH through the output pin OUTP, thereby realizing the writing of the driving data Data of the channel control chip CH in stage order.

[0068] Of course, it should be understood that in other embodiments of the present disclosure, the interaction between the main control chip MIC and the channel control chips CH can be implemented in other ways as long as the main control chip MIC can assign the required driving data Data to each channel control chip CH. For example, in another example, the channel control chips CH may be sequentially cascaded, and each channel control chip CH may be electrically connected to the same data line DataL for loading the driving data Data. Before assigning the driving data Data to each channel control chip CH, the main control chip MIC can set an address for each channel control chip CH. For example, the main control chip MIC provides address information to the first-stage channel control chip CH, and each channel control chip CH determines address information for the current-stage channel control chip CH based on the address information of the previous-stage channel control chip CH. After each channel control chip CH sets its address information, the main control chip MIC can load the driving data Data of each channel control chip CH onto the data line DataL, and the driving data Data of each channel control chip CH is related to the address information. The channel control chip CH determines address information corresponding to each drive data Data based on each drive data Data of the data wiring DataL, and can acquire the drive data Data when the address information corresponding to the drive data Data matches its own address information.

[0069] In one implementation mode of the present disclosure, referring to FIG. 4, the channel control chip CH is provided with a signal receiving unit CH-Rx, which receives a synchronous clock signal SCK and driving data Data, and is electrically connected to a synchronous clock pin SCKP, a data pin DataP, and an output pin OUTP for transmitting the driving data Data.

[0070] In one embodiment of the present disclosure, the channel control chip CH is provided with at least one driving unit group, which includes at least a waveform modulation unit PWMD, a power control unit MOSB, and a waveform control unit MOSC.

[0071] The first end of the waveform control unit MOSC is used to load a signal that can turn on the output control unit MOSB. The control end of the waveform control unit MOSC is electrically connected to the waveform modulation unit PWMD, and the second end of the waveform control unit MOSC is electrically connected to the control end of the output control unit MOSB. The first end of the output control unit MOSB is electrically connected to the channel pin CHP, and the second end of the output control unit MOSB is used to load the ground voltage GND. The logic module of the channel control chip CH can obtain a waveform modulation signal based on the obtained driving data Data. For example, the driving data Data obtained by the signal receiving unit CH-Rx can extract a waveform modulation signal that is sent to the waveform modulation unit PWMD. The waveform modulation unit PWMD controls the on / off of the waveform control unit MOSC based on the waveform modulation signal. When the waveform control unit MOSC is turned on, the signal from the first end of the waveform control unit MOSC is loaded to the control end of the output control unit MOSB, turning on the output control unit MOSB. When the waveform control unit MOSC is turned off, the signal from the first end of the waveform control unit MOSC is not loaded to the control end of the output control unit MOSB, and the output control unit MOSB is turned off. In this way, the waveform modulation unit PWMD controls the on / off of the waveform control unit MOSC, which in turn controls the on / off of the output control unit MOSB, thereby achieving waveform modulation of the driving current flowing through the output control unit MOSB and controlling the waveform of the driving current on the control channel pin CHP. For example, the waveform modulation unit PWMD can control the PWM waveform of the driving current on the channel wiring CHL by controlling the control end of the waveform control unit MOSC.

[0072] In this way, the main control chip MIC is configured to provide the channel chip set CHS with each driving data Data required by the channel chip set CHS, the driving data Data including waveform modulation information, the channel control chip CH acquires a waveform modulation signal according to the acquired driving data Data, and controls the waveform of the driving current on the channel wiring CHL based on the waveform modulation signal.

[0073] Optionally, the waveform control unit MOSC may be a MOS tube, a first end of which is used to load a signal that can turn on the output control unit MOSB, a second end of which is electrically connected to the control end of the output control unit MOSB, and a gate of which is electrically connected to the waveform modulation unit PWMD.

[0074] Optionally, the output control unit MOSB may be a MOS tube, a first end of which is used to load a ground voltage GND, for example, electrically connected to a wire pin GNDP, a second end of which is electrically connected to a channel pin CHP, and a gate of which is electrically connected to a second end of the waveform control unit MOSC.

[0075] In one embodiment of the present disclosure, referring to FIG. 4 , the driving unit group may be provided with a local dimming unit LI-CTR, the input terminal of which is electrically connected to the logic module of the channel control chip CH, and the output terminal of which is electrically connected to the first terminal of the waveform control unit MOSC. The signal output by the local dimming unit LI-CTR not only turns on the output control unit MOSB, but also the local dimming unit LI-CTR can output different signals to change the current when the output control unit MOSB is turned on, and further control the amplitude of the driving current on the channel pin CHP and the channel wiring CHL to which the channel pin CHP is connected.

[0076] In one example, the logic module of the channel control chip CH can obtain an amplitude modulation signal according to the driving data Data, for example, extract the amplitude modulation signal, which can be sent to the local dimming unit LI-CTR, which can output different voltage signals according to the amplitude modulation signal, and the output control unit MOSB outputs different currents under the control of the different voltage signals.

[0077] When the output control unit MOSB is a MOS tube, in this example, the local dimming unit LI-CTR controls the gate voltage of the MOS tube to control the current amplitude. The MOS tube in the output control unit MOSB operates in the saturation region, and the local dimming unit LI-CTR outputs the gate voltage of the MOS tube. By changing the gate voltage, the magnitude of the on-current of the source and drain of the MOS tube (one of the source and drain is the first end of the MOS tube, and the other is the second end of the MOS tube) can be controlled. This control method has a wide control range and is simple.

[0078] In another embodiment, referring to FIG. 12 , the channel control chip CH may not be provided with a local dimming unit LI-CTR to provide a signal to the first end of the waveform control unit MOSC, but may be provided with a power amplifier OP to provide a signal to the first end of the waveform control unit MOSC. Specifically, the logic module of the channel control chip CH may be electrically connected to the power amplifier OP, and the output end of the power amplifier OP may be electrically connected to the first end of the waveform control unit MOSC. In this manner, the power amplifier OP can provide a signal to the first end of the waveform control unit MOSC that can turn on the output control unit MOSB. In this embodiment, the power amplifier OP can improve the driving capability of the signal loaded to the first end of the waveform control unit MOSC, thereby avoiding the problem of insufficient driving capability caused by directly using a logic module to provide a signal to the waveform control unit MOSC. In this embodiment, the channel control chip CH may not be provided with a means for modulating the amplitude of the driving current, and therefore may not have the ability to modulate the amplitude of the current. Correspondingly, the circuit selection chip MUX may have the function of modulating the amplitude of the current on the light source voltage wiring PVDDL.

[0079] Of course, in the above-described embodiment of the present disclosure, the method of modulating the amplitude of the driving current on the channel wiring CHL by the local dimming unit LI-CTR is described as an example. In other embodiments of the present disclosure, other means may be used to modulate the amplitude of the driving current on the channel wiring CHL.

[0080] In one embodiment of the present disclosure, referring to FIG. 10 , the driving unit group may include a local dimming unit LI-CTR and a source current control unit SI-CTR. The first end of the source current control unit SI-CTR is electrically connected to the second end of the output control unit MOSB. The second end of the source current control unit SI-CTR is used to load the ground voltage GND, and the control end of the source current control unit SI-CTR is electrically connected to the logic module of the channel control chip CH. In this manner, the logic module can generate an amplitude control signal according to the driving data Data. The amplitude control signal is sent to the source current control unit SI-CTR, and the source current control unit SI-CTR is configured to control the magnitude of the current flowing through the source current control unit SI-CTR according to the amplitude control signal. In this manner, when a driving current is present in the output control unit MOSB, the driving current is controlled by both the local dimming unit LI-CTR and the source current control unit SI-CTR, thereby significantly improving the amplitude modulation accuracy of the driving current by the channel control chip CH.

[0081] In one example, the driving unit group further includes a current detection unit CC, which detects the amplitude of the driving current on the channel pin CHP and feeds it back to the logic module of the channel control chip CH. The logic module of the channel control chip CH adjusts at least one of the amplitude control signal and the amplitude modulation signal according to the feedback result of the current detection unit CC, thereby further improving the modulation accuracy of the driving current amplitude so that the deviation between the driving current on the channel wiring CHL and the target current is reduced. In this way, the provision of the current detection unit CC overcomes the problem of current unevenness caused by various differences, such as differences in the processes of the light-emitting circuits LEDA connected to each channel wiring CHL and differences in the process of the channel control chip CH itself. This significantly improves the accuracy of the driving current amplitude and improves the brightness uniformity of the light-emitting substrate BPNL. This allows the channel control chip CH to accurately control the amplitude of the driving current on the channel line CHL, which helps to accurately control the brightness of each light-emitting circuit LEDA and also improves the uniformity of the display brightness of the light-emitting substrate BPNL. This allows the light-emitting substrate BPNL to be used as a display panel.

[0082] 10 illustrates that the source current control unit SI-CTR is located at the second end of the output control unit MOSB. In other examples of the present disclosure, the source current control unit SI-CTR may be located at other positions, for example, a first end of the source current control unit SI-CTR may be electrically connected to the channel pin CHP, a second end of the source current control unit SI-CTR may be electrically connected to the first end of the output control unit MOSB, and a control end of the source current control unit SI-CTR may be electrically connected to the logic module of the channel control chip CH.

[0083] In the embodiment illustrated in FIG. 10, the source current control unit SI-CTR and the local dimming unit LI-CTR cooperate to overcome the influence of fluctuations in the process characteristics of the MOS tubes in the output control unit MOSB, thereby reducing the dependency of the MOS tubes on the process characteristics.

[0084] In one example, the source current control unit SI-CTR may be a resistive digital-to-analog converter.

[0085] In another embodiment of the present disclosure, referring to FIG. 11, the driving unit group may not set the local dimming unit LI-CTR, but may set the source current control unit SI-CTR to modulate the current amplitude of the driving circuit on the channel wiring CHL. Referring to FIG. 11, the channel control chip CH includes a power amplifier OP and a source current control unit SI-CTR. The logic module of the channel control chip CH is electrically connected to the power amplifier OP, and the output terminal of the power amplifier OP may be electrically connected to a first terminal of the waveform control unit MOSC. In this manner, the power amplifier OP provides a signal to the first terminal of the waveform control unit MOSC that can turn on the output control unit MOSB. The first terminal of the source current control unit SI-CTR is electrically connected to the second terminal of the output control unit MOSB, and the second terminal of the source current control unit SI-CTR is used to load the ground voltage GND, and the control terminal of the source current control unit SI-CTR is electrically connected to the logic module of the channel control chip CH. In this way, the logic module can generate an amplitude control signal according to the driving data Data. The amplitude control signal is sent to the source current control unit SI-CTR, which is configured to control the magnitude of the current flowing through the source current control unit SI-CTR according to the amplitude control signal. Furthermore, in one example, if the channel control chip CH configures the source current control unit SI-CTR and the power amplifier OP but not the local dimming unit LI-CTR, the channel control chip CH does not need to configure the current detection unit CC. This simplifies the channel control chip CH, achieving smaller size and lower costs, while also controlling the current amplitude of the driving current on the channel wiring CHL. In particular, when the light-emitting substrate BPNL is used as a lamp substrate for a backlight module, the waveform and deviation of the current amplitude of the driving current do not significantly affect the quality of the backlight module.

[0086] 11 illustrates that the source current control unit SI-CTR is located at the second end of the output control unit MOSB. In other examples of the present disclosure, the source current control unit SI-CTR may be located at other positions, for example, a first end of the source current control unit SI-CTR may be electrically connected to the channel pin CHP, a second end of the source current control unit SI-CTR may be electrically connected to the first end of the output control unit MOSB, and a control end of the source current control unit SI-CTR may be electrically connected to the logic module of the channel control chip CH.

[0087] In the above-mentioned examples such as Figures 4, 10, and 11, the driving unit group has a current amplitude modulation function. Correspondingly, the main control chip MIC is configured to provide the channel chipset CHS with each driving data Data required by the channel chipset CHS, where the driving data Data includes current amplitude information. The channel control chip CH can control the current amplitude of the driving current on the connected channel wiring CHL according to the acquired driving data Data.

[0088] In the example of FIG. 5, one channel control chip CH drives one channel wiring CHL. In another embodiment of the present disclosure, referring to FIG. 16, one channel control chip CH can drive multiple channel wirings CHL, for example, two channel wirings CHL, which can reduce the number of channel control chips CH and the cost of the light-emitting module. In the example of FIG. 16, each channel wiring CHL is electrically connected to one column or one row of light-emitting circuits LEDA. In another embodiment of the present disclosure, one column or one row of light-emitting circuits LEDA can be driven by multiple channel wirings CHL. For example, the light-emitting circuits LEDA in odd-numbered rows are electrically connected to one channel wiring CHL, and the light-emitting circuits LEDA in even-numbered rows are electrically connected to another channel wiring CHL.

[0089] Hereinafter, the structure, principle and effect of the channel control chip CH capable of driving a plurality of channel wirings CHL will be further described, taking as an example a case where one channel control chip CH drives two channel wirings CHL.

[0090] 14 and 15, the channel control chip CH may be provided with a plurality of channel pins CHP corresponding one-to-one to a plurality of channel wirings CHL to be driven, and each channel pin CHP is electrically connected to one channel wiring CHL. For example, in FIGS. 14 and 15, one channel control chip CH includes two pins, a first channel pin CHP1 and a second channel pin CHP2, and each pin is connected to a channel wiring CHL.

[0091] 14, in one embodiment of the present disclosure, the channel control chip CH includes an output control unit MOSB, a waveform control unit MOSC, and other units, and also includes a switching unit US. A first end of the output control unit MOSB is electrically connected to the switching unit US, and each channel pin CHP is electrically connected to the switching unit US. In this way, when the channel control chip CH is operating, the switching unit US allows each channel pin CHP to form an electrical path with the output control unit MOSB. When a channel pin CHP forms an electrical path with the output control unit MOSB, the channel control chip CH controls the driving current on the channel wiring CHL connected to that channel pin CHP. In this way, when the driving frequency requirement of the light-emitting substrate BPNL is not high, the channel control chip CH can drive multiple channel wirings CHL connected to it by driving each channel wiring CHL one by one.

[0092] Optionally, if necessary, the channel control chip CH may further include one or more units such as a power amplifier OP, a local dimming unit LI-CTR, a source current control unit SI-CTR, a current detection unit CC, etc. For example, in the example of Figure 14, the channel control chip CH is provided with a local dimming unit LI-CTR to modulate the current amplitude of the drive current on each channel wiring CHL.

[0093] In another embodiment of the present disclosure, referring to FIG. 15 , a channel control chip CH includes multiple driver groups corresponding to the multiple channel wirings CHL to be driven. Each driver group is used to drive a corresponding channel wiring CHL. Each driver group may include a waveform modulation unit PWMD, a waveform control unit MOSC, an output control unit MOSB, and a channel pin CHP. If necessary, each driver group may further include one or more units, such as a power amplifier OP, a local dimming unit LI-CTR, a source current control unit SI-CTR, and a current detection unit CC. In the example of FIG. 15 , each driver group includes a first local dimming unit LI-CTR1. In other embodiments of the present disclosure, some units within a driver group may be shared. For example, if multiple driver groups each include a power amplifier OP, the power amplifier OP may be the same, or each driver group may use the same power amplifier independently.

[0094] 15, the channel control chip CH includes two driving unit groups. The first driving unit group includes a first waveform modulation unit PWMD1, a first local dimming unit LI-CTR1, a first waveform control unit MOSC1, a first output control unit MOSB1, and a first channel pin CHP1, which is used to connect to one channel wiring CHL. The second driving unit group includes a second waveform modulation unit PWMD2, a second local dimming unit LI-CTR2, a second waveform control unit MOSC2, a second output control unit MOSB2, and a second channel pin CHP2, which is used to connect to one channel wiring CHL.

[0095] In some embodiments of the present disclosure, referring to FIG. 6 , the circuit selection chip MUX may be an analog chip, thereby reducing the number of signals required by the circuit selection chip MUX and the number of wirings required to drive the circuit selection chip MUX, which is advantageous for reducing the bezel size of the light-emitting substrate BPNL. In this disclosure, this analog chip-based circuit selection chip MUX may be referred to as the first circuit selection chip MUXA. In this configuration, the first circuit selection chip MUXA can operate without additional power, and the light-emitting substrate BPNL does not need to provide special chip power supply wiring and ground voltage wiring for supplying power to the first circuit selection chip MUXA.

[0096] Optionally, the first circuit selection chip MUXA may include a selection control module MCTR and a voltage output unit MOSA, and is provided with pins such as a column start signal pin STVP, a clock pin CLKP, a light source voltage input pin PVDDP, and an output pin OUTP, among which the selection control module MCTR is electrically connected to the column start signal pin STVP, the clock pin CLKP, and the control end of the voltage output unit MOSA, a first end of the voltage output unit MOSA is electrically connected to the light source voltage input pin PVDDP, and a second end of the voltage output unit MOSA is electrically connected to the output pin OUTP.

[0097] The clock pin CLKP is used to load a clock signal CLK to the selection control module MCTR of the first circuit selection chip MUXA. In one example, referring to Figures 7 and 8, the main control chip MIC has a clock output pin CLKPO, the light emitting substrate BPNL has a clock wiring CLKL for loading the clock signal CLK, the clock pin CLKP of each first circuit selection chip MUXA is electrically connected to the clock wiring CLKL, and the clock output pin CLKPO can load the clock signal CLK to the clock wiring CLKL.

[0098] The light source voltage input pin PVDDP is used to receive the light source voltage PVDD. In one example, the main control chip MIC has a light source voltage output pin PVDDPO for outputting the light source voltage PVDD, the light emitting substrate BPNL has a light source voltage distribution line PVDDLx for transmitting the light source voltage PVDD, and the light source voltage input pin PVDDP of each first circuit selection chip MUXA is electrically connected to the light source voltage distribution line PVDDLx. Of course, in another example, the flexible circuit board FPC can provide the light source voltage PVDD to the light source voltage distribution line PVDDLx, for example, a power management chip provided on the flexible circuit board FPC can provide the light source voltage PVDD to the light source voltage distribution line PVDDLx.

[0099] The output pin OUTP of the first circuit selection chip MUXA is electrically connected to the connected light source voltage wiring PVDDL, so that the first circuit selection chip MUXA loads the light source voltage PVDD onto the light source voltage wiring PVDDL.

[0100] The column start signal pin STVP of the first circuit selection chip MUXA is used to load the column start signal STV to the selection control module MCTR of the first circuit selection chip MUXA. The selection control module MCTR is configured to control the voltage output unit MOSA under the control of the clock signal CLK and the column start signal STV so that the light source voltage PVDD loaded to the light source voltage input pin PVDDP is loaded to the output pin OUTP, and the output pin OUTP outputs the light source voltage PVDD. For example, referring to Figure 9, after receiving the column start signal STV, the first circuit selection chip MUXA outputs the light source voltage PVDD in the next clock cycle. Also, the column start signal STV is a high-level signal.

[0101] 7, in the circuit selection chip set MUXS, the first circuit selection chips MUXA are sequentially cascaded so that the output pin OUTP of each first circuit selection chip MUXA sequentially outputs the light source voltage PVDD in cascade order. In this way, the wiring area required to drive the circuit selection chip set MUXS can be further reduced, which is advantageous for further reducing the bezel of the light emitting substrate BPNL.

[0102] The main control chip MIC may be provided with a column start signal output pin STVPO for outputting the column start signal STV, and the light emitting substrate BPNL may be provided with a column start signal line STVL for transmitting the column start signal STV. The column start signal pin STVP of the first circuit selection chip MUXA of the first stage (i.e., the circuit selection chip MUX(1) in FIG. 7) is electrically connected to the column start signal line STVL for loading the column start signal STV. In this way, the main control chip MIC can load the column start signal STV to the first circuit selection chip MUXA of the first stage to control the output of the first circuit selection chip MUXA of the first stage. In the first circuit selection chips MUXA of two adjacent stages, the output pin OUTP of the first circuit selection chip MUXA of the previous stage is electrically connected to the column start signal pin STVP of the first circuit selection chip MUXA of the next stage (for example, electrically connected via a first connection line TRLA provided on the light emitting substrate BPNL). In this way, until the column start signal pin STVP of the first circuit selection chip MUXA of the final stage (i.e., the circuit selection chip MUX(M) in FIG. 7, where M is the total number of circuit selection chips MUX in the circuit selection chip set MUXS) is electrically connected to the output pin OUTP of the first circuit selection chip MUXA of the previous stage, the output of the first circuit selection chip MUXA of the previous stage is used as the column start signal STV of the first circuit selection chip MUXA of the next stage. Further, referring to FIG. 9, the column start signal STV is a high-level signal with a length of one clock cycle.

[0103] In another embodiment of the present invention, referring to FIG. 13, the circuit selection chip MUX may be a digital chip, i.e., the circuit selection chip MUX has a logic module. In this way, although the number of wirings required to drive the circuit selection chip MUX increases, the circuit selection chip MUX can be made smaller in area and can be configured with enhanced functionality as needed. When the circuit selection chip MUX is a digital chip, the impact on the area occupied by the driving assembly is reduced and a significant increase in the bezel of the light emitting substrate BPNL is not incurred. This circuit selection chip MUX in the form of a digital chip may be referred to as a second circuit selection chip MUXB in this disclosure.

[0104] In one embodiment of the present disclosure, the second circuit selection chip MUXB can have a local current amplitude control function, eliminating the need to provide a current control function in the channel control chip CH. On the one hand, because the channel control chip CH is often heavily used, migrating the local current control function of the channel control chip CH to the second circuit selection chip MUXB can simplify the channel control chip CH, reduce its area, and further reduce the overall area of the driver assembly. In particular, the channel control chip CH does not need to simultaneously integrate a drive current waveform modulation function and a drive current amplitude modulation function to avoid the channel control chip CH occupying too much area. On the other hand, the second circuit selection chip MUXB has a smaller size as a digital chip than the first circuit selection chip MUXA, and integrating the local current amplitude control function does not result in an increase in area.

[0105] 13, the second circuit selection chip MUXB includes a logic module and an output control module, and the output control module is configured to output a light source voltage PVDD whose current amplitude is modulated under the control of the logic module. In other words, the main control chip MIC is configured to provide the circuit selection chip set MUXS with a synchronous clock signal SCK and each driving data Data required by the circuit selection chip set MUXS, and the circuit selection chip MUX can output a light source voltage PVDD whose current amplitude is modulated according to the acquired driving data Data.

[0106] In one example, the logic module may include a selection control module MCTR, a signal receiving unit MUX-Rx, a current control register STR, etc. The output control module may further include a power amplifier OP, a local dimming unit LI-CTR, a voltage output unit MOSA, etc. The second circuit selection chip MUXB may further include a low-dropout linear regulator LDO for supplying power to the logic module. The second circuit selection chip MUXB is provided with pins such as a light source voltage input pin PVDDP, a synchronization clock pin SCKP, a data input pin DataPA, a data output pin DataPB, a wire pin GNDP, an output pin OUTP, and a substrate power supply voltage pin VDDP.

[0107] The synchronous clock pin SCKP of the second circuit selection chip MUXB is used to load the synchronous clock signal SCK so that the second circuit selection chip MUXB maintains clock synchronization with the main control chip MIC. Furthermore, the main control chip MIC has a synchronous clock output pin SCKPO for outputting the synchronous clock signal SCK, and the light emitting substrate BPNL has a synchronous clock wiring SCKL for loading the synchronous clock signal SCK. The synchronous clock wiring SCKL is electrically connected to the synchronous clock output pin SCKPO of the main control chip MIC and to the synchronous clock pin SCKP of each second circuit selection chip MUXB. In this way, the synchronous clock signal SCK output by the main control chip MIC can be loaded to each second circuit selection chip MUXB. In one example, the synchronous clock pin SCKP of the second circuit selection chip MUXB and the synchronous clock pin SCKP of the channel control chip CH can be connected to the same synchronous clock wiring SCKL so that the second circuit selection chip MUXB, the main control chip MIC, and the channel control chip CH maintain clock synchronization.

[0108] The data input pin DataPA of the second circuit selection chip MUXB is used to receive driving data Data, and based on the received driving data Data, the second circuit selection chip MUXB is configured to, for example, control the light source voltage PVDD output to the output pin OUTP, and particularly control the timing at which the light source voltage PVDD is output. Specifically, the second circuit selection chip MUXB obtains its corresponding driving data Data according to the signal on the data input pin DataPA, and controls the timing at which the output pin OUTP outputs the light source voltage PVDD according to this driving data Data. The second circuit selection chip MUXB can also control the amplitude of the current output to the light source voltage wiring PVDDL according to the obtained driving data Data.

[0109] The data output pin DataPB of the second circuit selection chip MUXB is used to transfer driving data Data so that each second circuit selection chip MUXB in the circuit selection chip set MUXS is sequentially cascaded. Specifically, the data input pin DataPA of the second circuit selection chip MUXB in the first stage may be used to receive driving data Data from the main control chip MIC. In the second circuit selection chip MUXBs of two adjacent stages, the data output pin DataPB of the second circuit selection chip MUXB in the previous stage is electrically connected to the data input pin DataPA of the second circuit selection chip MUXB in the next stage via a transfer wiring. In this way, the main control chip MIC sequentially transmits the driving data Data required by each second circuit selection chip MUXB to the circuit selection chip set MUXS, specifically to the second circuit selection chip MUXB in the first stage. The signal receiving unit MUX-Rx of the second circuit selection chip MUXB is configured so that the first drive data Data received within one signal period is the drive data Data required by this second circuit selection chip MUXB, and each drive data Data after obtaining the required drive data Data is all transferred to the second circuit selection chip MUXB of the next stage via the data output pin DataPB. In this way, the main control chip MIC sequentially outputs the drive data Data required by each second circuit selection chip MUXB of the circuit selection chip set MUXS, and these drive data Data are transferred in stage order and can be received by the corresponding second circuit selection chip MUXB.

[0110] The wire pin GNDP of the second circuit selection chip MUXB is used to load the ground voltage GND of the second circuit selection chip MUXB. In one example, the light emitting substrate BPNL is provided with a ground line for loading the ground voltage GND, and the wire pin GNDP of the second circuit selection chip MUXB is electrically connected to the ground line. Furthermore, the wire pin GNDP of the second circuit selection chip MUXB and the wire pin GNDP of the channel control chip CH can be connected to the same ground line.

[0111] The substrate power supply voltage pin VDDP of the second circuit selection chip MUXB is used to obtain the substrate power supply voltage VDD. The input terminal of the low-dropout linear regulator LDO is electrically connected to the substrate power supply voltage pin VDDP, and the output terminal is electrically connected to the logic module of the second circuit selection chip MUXB. The low-dropout linear regulator LDO can convert the substrate power supply voltage VDD to supply power to the logic module, for example, by reducing the substrate power supply voltage VDD to 1.8V.

[0112] The local dimming unit LI-CTR may include an input terminal, an output terminal, and two control terminals. The input terminal of the local dimming unit LI-CTR is electrically connected to the substrate power supply voltage pin VDDP, and the substrate power supply voltage VDD is used as the operating power supply. The output terminal of the local dimming unit LI-CTR is electrically connected to the control terminal of the voltage output unit MOSA. The first control terminal of the local dimming unit LI-CTR is electrically connected to the current control resistor STR and is used to control the magnitude of the output voltage under the control of the current control resistor STR. The second control terminal of the local dimming unit LI-CTR is electrically connected to the power amplifier OP and is used to control whether to output a voltage under the control of the power amplifier OP. The power amplifier OP is electrically connected to the selection control module MCTR. The first terminal of the voltage output unit MOSA is electrically connected to the output pin OUTP, and the second terminal of the voltage output unit MOSA is electrically connected to the light source voltage input pin PVDDP.

[0113] The driving data Data acquired by the second circuit selection chip MUXB can be used to acquire timing information and amplitude information, for example, to extract timing information and amplitude information. The selection control module MCTR controls the power amplifier OP according to the timing information, and further controls the second control end of the local dimming unit LI-CTR through the power amplifier OP. When the local dimming unit LI-CTR can output a voltage under the control of the power amplifier OP, the voltage output unit MOSA is turned on, allowing the second circuit selection chip MUXB to output the light source voltage PVDD. When the local dimming unit LI-CTR cannot output a voltage under the control of the power amplifier OP, the voltage output unit MOSA is turned off, preventing the second circuit selection chip MUXB from outputting the light source voltage PVDD. In this way, the selection control module MCTR can control the timing at which the second circuit selection chip MUXB outputs the light source voltage PVDD according to the timing information.

[0114] Furthermore, in the circuit selection chip set MUXS, the timing information obtained by different second circuit selection chips MUXB corresponds to different time points, so that different second circuit selection chips MUXB can output the light source voltage PVDD at different time points, for example, each second circuit selection chip MUXB sequentially cascaded can sequentially output the light source voltage PVDD.

[0115] The amplitude information can be stored in the current control register STR, which controls the second control terminal of the local dimming unit LI-CTR according to the stored amplitude information, thereby controlling the magnitude of the voltage that the local dimming unit LI-CTR can output. The magnitude of the voltage output by the local dimming unit LI-CTR is related to the magnitude of the current when the voltage output unit MOSA is turned on. In this way, by controlling the voltage output by the local dimming unit LI-CTR, the magnitude of the current of the light source voltage PVDD output by the second circuit selection chip MUXB can be controlled. In one example, the voltage output unit MOSA can be a transistor operating in the saturation region.

[0116] In one example, the driving data Data sent by the main control chip MIC to the circuit selection chip MUX includes timing information and amplitude information required by the circuit selection chip MUX, the timing information is used to control the timing at which the circuit selection chip MUX outputs the light source voltage PVDD, and the amplitude information is used to control the current amplitude of the light source voltage PVDD output by the circuit selection chip MUX.

[0117] In one embodiment of the present disclosure, the light emitting substrate BPNL may be provided with a substrate power supply voltage wiring VDDL for loading a substrate power supply voltage VDD to the circuit selection chip set MUXS, and the flexible circuit board FPC may load the substrate power supply voltage VDD to the substrate power supply voltage wiring VDDL and further load the substrate power supply voltage VDD to each second circuit selection chip MUXB. In addition, the substrate power supply voltage VDD loaded to the second circuit selection chip MUXB and the substrate power supply voltage VDD loaded to the main control chip MIC may have the same voltage magnitude, or of course, they may be different.

[0118] In one example, when the second circuit selection chip MUXB receives the driving data Data for the first time in one data transmission stage, the second circuit selection chip MUXB regards the driving data Data as driving data required by the second circuit selection chip MUXB, and each driving data Data received after receiving the required driving data Data (i.e., each driving data Data received for the second time or later) is regarded as unnecessary driving data Data and is transferred to the second circuit selection chip MUXB of the next stage via the output pin OUTP. In this way, each driving data Data sequentially transmitted by the main control chip MIC via the second data output pin DataPO2 can be sequentially acquired by each second circuit selection chip MUXB in cascade order, with the first driving data Data being acquired by the second circuit selection chip MUXB of the first stage, the Nth driving data Data being acquired by the second circuit selection chip MUXB of the Nth stage, and the last driving data Data being acquired by the second circuit selection chip MUXB of the last stage.

[0119] The above introduction for the second circuit selection chip MUXB is only a possible method for the second circuit selection chip MUXB, but it is understood that in other embodiments of the present disclosure, the second circuit selection chip MUXB can also adopt other architectures, such as using different transmission logic, setting different pins, etc., as long as the second circuit selection chip MUXB is provided with a logic module and can realize the stage-order output of the light source voltage PVDD.

[0120] In the driving assembly of the light emitting module provided by the present disclosure, the main control chip MIC is used to control the circuit selection chipset MUXS and the channel chipset CHS.

[0121] Referring to FIG. 8, the main control chip MIC includes a main logic controller MIC-CTR, a signal receiving unit MIC-Rx, a signal transmitting unit MIC-Tx, and a global current control unit GI-CTR, and also includes required pins.

[0122] Referring to FIG. 8 , the pins of the main control chip MIC may include a synchronous clock input pin SCKPI, an input pin MOSI, an output pin MISO, and a chip select signal pin CSP, which are electrically connected to the signal receiving unit MIC-Rx. The synchronous clock input pin SCKPI, the input pin MOSI, the output pin MISO, and the chip select signal pin CSP form a set of SPI interfaces of the main control chip MIC, which communicate with an external control component such as an MCU, FPGA, or SOC card board to control the light-emitting substrate BPNL according to control signals provided by the external control component. For example, the synchronous clock input pin SCKPI is used to receive a synchronous clock signal sent to the main control chip MIC by the external control component. The input pin MOSI is used to receive a serial data input signal. The output pin MISO is used to output a serial data output signal. The chip select signal CSP is used to receive a chip select signal. In this way, the data receiving module of the main control chip MIC is a data communication module using a serial synchronous communication protocol.

[0123] The main control chip MIC is provided with a chip power supply pin VCCP for supplying power to the main control chip MIC and a wire pin GNDP, the chip power supply pin VCCP receives the chip power supply voltage VCC to provide the main control chip MIC with the power required for operation, for example, to supply power to the main logic control module, and the wire pin GNDP is used to load the ground voltage GND to the main control chip MIC.

[0124] The global current control unit GI-CTR is connected to the substrate power supply voltage pin VDDP and the light source voltage output pin PVDDPO. Under the control of the main logic controller MIC-CTR, the global current control unit GI-CTR adjusts the substrate power supply voltage VDD and adjusts the magnitude of the current to generate the light source voltage PVDD, which is output to the circuit selection chip MUX via the light source voltage output pin PVDDPO.

[0125] The main logic controller MIC-CTR receives signals received by the signal receiving unit MIC-Rx, generates data and signals required by the channel chip set CHS and the circuit selection chip set MUXS based on the received signals, and transmits these data and signals to the circuit selection chip set MUXS and the channel chip set CHS directly or via the signal transmitting unit MIC-Tx. The main logic controller MIC-CTR loads the required data into the circuit selection chip set MUXS and the channel chip set CHS, while controlling the timing of the channel control chip CH and the circuit selection chip MUX, thereby enabling the channel control chip CH and the circuit selection chip MUX to coordinate their timing, thereby enabling the light-emitting substrate BPNL to achieve local dimming.

[0126] In one embodiment of the present disclosure, after receiving control signals from external control components, the main logic controller MIC-CTR can analyze these signals into a global current control signal, a PWM signal, and a local current control signal. The global current control signal is sent to the global current control unit GI-CTR to control the current of the light source voltage PVDD output by the main control chip MIC, thereby achieving global dimming, such as increasing or decreasing the overall brightness. The PWM signal and the local current control signal are packaged and configured in each channel control chip CH and / or circuit selection chip MUX, which controls each channel control chip CH and circuit selection chip MUX, and ultimately realizes local dimming of each light-emitting circuit LEDA.

[0127] In one embodiment of the present disclosure, when the circuit selection chip MUX is the first circuit selection chip MUXA, the main logic controller MIC-CTR can transmit the driving data Data required by the channel chip set CHS and the synchronous clock signal SCK to the channel chip set CHS via the signal transmitting unit MIC-Tx. Specifically, the main control chip MIC is provided with a data output pin DataPO and a synchronous clock output pin SCKPO. Under the control of the main logic controller MIC-CTR, the signal transmitting unit MIC-Tx can transmit the driving data Data required by each channel control chip CH to the channel chip set CHS via the data output pin DataPO, and can transmit the synchronous clock signal SCK required by each channel control chip CH to the channel chip set CHS via the synchronous clock output pin SCKPO.

[0128] The main control chip MIC further includes a column start signal output pin STVPO and a clock output pin CLKPO. The main logic controller MIC-CTR can directly transmit the column start signal STV to the circuit selection chip set MUXS via the column start signal output pin STVPO, for example, to the column start signal pin STVP of the first circuit selection chip MUXA in the first stage. The main logic controller MIC-CTR can directly transmit the clock signal CLK to each circuit selection chip MUX in the circuit selection chip set MUXS via the clock output pin CLKPO.

[0129] In another embodiment of the present disclosure, when the circuit selection chip MUX is the second circuit selection chip MUXB, the main control chip MIC can transmit the driving data Data and the synchronous clock signal SCK required by the second circuit selection chip MUXB to the second circuit selection chip MUXB via the signal transmitting unit MIC-Tx. Of course, the signal transmitting unit MIC-Tx that transmits the driving data Data and the synchronous clock signal SCK to the channel control chip CH and the signal transmitting unit MIC-Tx that transmits the driving data Data and the synchronous clock signal SCK to the circuit selection chip MUX can be the same signal transmitting unit MIC-Tx or two different signal transmitting units MIC-Tx.

[0130] In one example, the main control chip MIC is provided with a synchronous clock output pin SCKPO, a first data output pin DataPO1, and a second data output pin DataPO2, which are all electrically connected to the same signal transmitting unit MIC-Tx, which transmits a synchronous clock signal SCK to the circuit selection chip set MUXS and the channel chip set CHS via the synchronous clock output pin SCKPO, transmits driving data Data required by each channel control chip CH to the channel chip set CHS via the first data output pin DataPO1, and transmits driving data Data required by each circuit selection chip MUX to the circuit selection chip set MUXS.

[0131] Other embodiments of the present disclosure will be readily apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure in accordance with the general principles of the present disclosure, including common knowledge or customary technical means in the art that are not disclosed in the present disclosure. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the present disclosure being indicated by the following claims. [Explanation of symbols]

[0132] BLU Backlight Module CTR control module PNL LCD panel

Claims

1. 1. A drive assembly for a light emitting module, comprising: The light emitting module further includes a light emitting substrate; the light-emitting substrate includes a plurality of light source voltage wirings extending along a first direction, a plurality of channel wirings extending along a second direction, and a plurality of light-emitting circuits distributed in an array; One end of any of the light emitting circuits is connected to the light source voltage wiring and the other end is connected to the channel wiring, one of the first direction and the second direction is a row direction and the other is a column direction; The driving assembly includes a main control chip, a circuit selection chip set, and a channel chip set; the circuit selection chip set includes a plurality of circuit selection chips for electrically connecting to the light source voltage wirings in one-to-one correspondence, and the circuit selection chip set is configured such that, under the control of the main control chip, each of the circuit selection chips loads a light source voltage onto the light source voltage wirings connected thereto one by one; the channel chipset includes a plurality of channel control chips, each of which is used to electrically connect to one or more channel wirings; The channel chipset is configured such that, under the control of the main control chip, the channel control chip controls the drive current in each of the channel wirings connected thereto.

10. A driving assembly for a light emitting module, comprising:

2. the drive assembly further includes a flexible circuit board for coupling to and connecting with the light emitting substrate; the main control chip is mounted on the flexible circuit board; The circuit selection chip and the channel control chip are coupled to the light emitting substrate and electrically connected to the flexible circuit board via wiring provided on the light emitting substrate. The driving assembly for a light emitting module according to claim 1 .

3. The circuit selection chip set is provided at one end of the light emitting substrate in the first direction, and the channel chip set is provided at one end of the light emitting substrate in the second direction. The driving assembly for a light emitting module according to claim 1 .

4. The circuit selection chip is a purely analog module, including a selection control module and a voltage output unit; The control end of the voltage output unit is electrically connected to the selection control module, the first end of the voltage output unit is used to load the light source voltage, and the second end of the voltage output unit is electrically connected to the light source voltage wiring; The selection control module electrically conducts the voltage output unit under the control of a clock signal and a column start signal, and the circuit selection chip is further configured to load the light source voltage onto the light source voltage wiring. The driving assembly for a light emitting module according to claim 1 .

5. the circuit select chip includes a light source voltage input pin for loading the light source voltage, a clock pin for loading the clock signal, a column start signal pin for loading the column start signal, and an output pin for electrically connecting to the light source voltage wiring; The circuit selection chips in the circuit selection chip set are sequentially cascaded, and the clock pins of the circuit selection chips are both used to load the clock signal from the main control chip, and the column start signal pin of the first stage circuit selection chip is used to load the column start signal from the main control chip. In two adjacent stages of circuit selection chips, the output pin of the previous stage circuit selection chip is electrically connected to the column start signal pin of the next stage circuit selection chip, so that the output of the previous stage circuit selection chip becomes the column start signal of the next stage circuit selection chip.

5. The driving assembly for a light emitting module according to claim 4.

6. The channel control chip includes a synchronous clock pin, a data pin, and an output pin, and the channel control chip is configured to acquire the first driving data received in one data transmission stage, and after acquiring the driving data, transfer each subsequent driving data through the output pin; The channel control chips in the channel chip set are sequentially cascaded, and the synchronous clock pins of the channel control chips are both used to receive the synchronous clock signal from the main control chip, and the data pins of the first-stage channel control chip are used to receive the driving data from the main control chip. In the adjacent two-stage channel control chips, the output pins of the previous-stage channel control chip are electrically connected to the data pins of the next-stage channel control chip. The driving assembly for a light emitting module according to claim 1 .

7. The channel control chip includes at least one driving unit group; The driving unit group includes a waveform modulation unit, an output control unit, and a waveform control unit; a first end of the waveform control unit is used to load a voltage signal that electrically makes the output control unit conductive, a control end of the waveform control unit is electrically connected to the waveform modulation unit, a second end of the waveform control unit is electrically connected to the control end of the output control unit, the first end of the output control unit is electrically connected to the channel wiring, and the second end of the output control unit is used to load a ground voltage; The logic module of the channel control chip is configured to obtain a waveform modulation signal according to the obtained driving data, and the waveform modulation unit is used to control the electrical conduction state of the waveform control unit according to the waveform modulation signal. The driving assembly for a light emitting module according to claim 1 .

8. The waveform control unit and the output control unit are both MOS tubes.

8. The driving assembly for a light emitting module according to claim 7.

9. The driving unit group further includes a power amplifier; The input end of the power amplifier is electrically connected to the logic module of the channel control chip, and the output end of the power amplifier is electrically connected to the first end of the waveform control unit.

8. The driving assembly for a light emitting module according to claim 7.

10. The driving unit group further includes a source current control unit; a first end of the source current control unit is electrically connected to a second end of the output control unit, the second end of the source current control unit is used to load the ground voltage, and a control end of the source current control unit is electrically connected to a logic module of the channel control chip; The logic module of the channel control chip is configured to obtain an amplitude control signal according to the obtained driving data, and send it to the source current control unit; The source current control unit is used to control the magnitude of the current flowing through the source current control unit according to the amplitude control signal.

10. The driving assembly for a light emitting module according to claim 9.

11. The driving unit group further includes a local dimming unit; The input end of the local dimming unit is electrically connected to the logic module of the channel control chip, and the output end of the local dimming unit is electrically connected to a first end of the waveform control unit; The logic module of the channel control chip is configured to obtain an amplitude modulation signal according to the obtained driving data and send it to the local dimming unit; The local dimming unit outputs different voltage signals according to the amplitude modulation signal to control the current amplitude when the output control unit is electrically conducted.

8. The driving assembly for a light emitting module according to claim 7.

12. The driving unit group further includes a source current control unit; a first end of the source current control unit is electrically connected to a second end of the output control unit, the second end of the source current control unit is used to load the ground voltage, and a control end of the source current control unit is electrically connected to a logic module of the channel control chip; The logic module of the channel control chip is configured to obtain an amplitude control signal according to the obtained driving data, and send it to the source current control unit; The source current control unit is used to control the magnitude of the current flowing through the source current control unit according to the amplitude control signal.

12. The driving assembly for a light emitting module according to claim 11.

13. The driving unit group further includes a current detection unit; The current detection unit is used to detect the current amplitude of the first end of the output control unit and feed it back to the logic module of the channel control chip; The logic module of the channel control chip adjusts the amplitude modulation signal and / or the amplitude control signal according to the feedback of the current detection unit.

13. The driving assembly for a light emitting module according to claim 12.

14. The channel control chip includes a driving unit group and a plurality of channel pins for connecting to different channel wirings, and the channel control chip further includes a switching unit; A first end of the output control unit is electrically connected to the switching unit, and each of the channel pins is electrically connected to the switching unit, and the switching unit is configured such that each of the channel pins forms an electrical path with the output control unit one by one.

8. The driving assembly for a light emitting module according to claim 7.

15. the channel control chip includes a plurality of driving unit groups and channel pins corresponding one-to-one to each of the driving unit groups, the channel pins being used to connect to the channel wiring; A first end of the output control unit of each of the driving unit groups is electrically connected to the corresponding channel pin.

8. The driving assembly for a light emitting module according to claim 7.

16. the circuit selection chip includes a logic module and an output control module; The output control module is configured to output the light source voltage with a modulated current amplitude under the control of the logic module. The driving assembly for a light emitting module according to claim 1 .

17. the circuit selection chip includes a synchronous clock pin, a data input pin, and a data output pin; The circuit selection chip is configured to acquire the first driving data received by the data input pin in one data transmission stage, and after acquiring the driving data, transfer each subsequent driving data through the data output pin; The circuit selection chips in the circuit selection chip set are sequentially cascaded, and the synchronous clock pins of the circuit selection chips are both used to receive the synchronous clock signal from the main control chip, and the data input pins of the first stage circuit selection chips are used to receive the driving data from the main control chip, and in two adjacent stages of the circuit selection chips, the data output pins of the previous stage circuit selection chips are electrically connected to the data input pins of the next stage circuit selection chips.

17. The driving assembly for a light emitting module according to claim 16.

18. The logic module of the circuit selection chip includes a selection control module and a current control register, and the output control module of the circuit selection chip includes a power amplifier, a local dimming unit, and a voltage output unit; The input terminal of the local dimming unit is used to load a substrate power supply voltage, and the output terminal of the local dimming unit is electrically connected to the control terminal of the voltage output unit; a first control end of the local dimming unit electrically connected to the current control register, for controlling the magnitude of the voltage signal to be output under the control of the current control register, and for controlling the amplitude of the current flowing through the voltage output unit when the voltage output unit is electrically conducted; a second control end of the local dimming unit electrically connected to the power amplifier, and configured to output the voltage signal under the control of the power amplifier; the power amplifier is electrically connected to the selection control module; a first end of the voltage output unit is electrically connected to the light source voltage wiring, and a second end of the voltage output unit is used to load the light source voltage; The logic module of the circuit selection chip is configured to obtain timing information and amplitude information according to the obtained driving data; The selection control module controls the power amplifier according to the timing information, and is further used to control whether the circuit selection chip outputs the light source voltage. The current control register controls the second control end of the local dimming unit according to the amplitude information, and is further used to control the amplitude of the current output by the circuit selection chip.

17. The driving assembly for a light emitting module according to claim 16.

19. The main control chip is configured to provide the clock signal and the column start signal to the circuit selection chipset.

5. The driving assembly for a light emitting module according to claim 4.

20. The main control chip is configured to provide the circuit selection chip set with each driving data required by the circuit selection chip set; The circuit selection chip can output a light source voltage whose current amplitude is modulated according to the acquired driving data.

17. The driving assembly for a light emitting module according to claim 16.

21. The driving data sent by the main control chip to the circuit selection chip includes timing information and amplitude information required by the circuit selection chip; The timing information is used to control the timing at which the circuit selection chip outputs the light source voltage, and the amplitude information is used to control the amplitude of the current output by the circuit selection chip.

21. The driving assembly for a light emitting module according to claim 20.

22. the main control chip is configured to provide the channel chipset with each driving data required by the channel chipset, the driving data including waveform modulation information; The channel control chip can obtain a waveform modulation signal according to the obtained driving data, and control the waveform of the driving current in the channel wiring according to the waveform modulation signal.

21. The driving assembly for a light emitting module according to claim 20.

23. The main control chip is configured to provide the channel chipset with each driving data required by the channel chipset, the driving data including current amplitude information; The channel control chip can control the current amplitude of the driving current in the connected channel wiring according to the acquired driving data. A driving assembly for a light emitting module according to any one of claims 10 to 13.

24. The number of circuit selection chips in the circuit selection chip set is greater than the number of channel control chips in the channel chip set. The driving assembly for a light emitting module according to claim 1 .

25. A drive assembly comprising the drive assembly of any one of claims 1 to 24 and the light emitting substrate. A light-emitting module characterized by:

26. A liquid crystal display panel and a backlight module are included. The backlight module includes a light emitting module according to claim 25. A display device characterized by:

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