Printed circuit board with pads and communication device

Abstract

The present disclosure relates to a printed circuit board and a communication device having a pad, the printed circuit board including a signal layer and a reference layer, a pad disposed on the signal layer, the pad including a stub, a first anti-pad disposed on the reference layer, a vertically inverted image of the stub on the reference layer located within a coverage area of the first anti-pad, and the first anti-pad is used to reduce the impedance of the stub.

Description

[Technical Field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This disclosure claims priority to Chinese patent application CN202211042562.3, entitled "Printed Circuit Board with Pads and Communication Device," filed on August 29, 2022, the entire contents of which are incorporated herein by reference. [Technical field] The present disclosure relates to the field of printed circuit board design, and more particularly to printed circuit boards with pads and communication devices. [Background technology]

[0002] As signal speeds increase, the performance requirements for signal integrity (SI) of high-speed channels also increase, and signal reflections caused by impedance discontinuities have a significant impact on high-speed signals. Therefore, optimizing the impedance of high-speed channels becomes increasingly important.

[0003] When designing pads for printed circuit boards (PCBs), the reliability of welding must be taken into consideration, so pads are designed to be long, which makes it easy for low impedance points to appear. Long pads are prone to forming stubs, and the coupling between the stub and the reference ground creates a sudden change in capacitive impedance, degrading the transmission quality of high-speed signals. Therefore, how to reduce the capacitive coupling between the pad stub and the reference ground is a technical problem that needs to be solved. Summary of the Invention [Problem to be solved by the invention]

[0004] The present disclosure provides a printed circuit board and a communication device with pads to solve the technical problem of how to reduce the capacitive coupling between a pad stub and a reference ground. [Means for solving the problem]

[0005] According to a first aspect, the present disclosure provides a printed circuit board having a pad, the printed circuit board including a signal layer and a reference layer, the pad being disposed on the signal layer, the pad including a stub, a first anti-pad being disposed on the reference layer, a vertically inverted image of the stub on the reference layer being located within a coverage area of the first anti-pad, and the first anti-pad being used to reduce impedance of the stub.

[0006] According to a second aspect, the present disclosure provides a communication device including the printed circuit board according to the first aspect. [Brief description of the drawing] The drawings herein are incorporated in and constitute a part of this disclosure, illustrate embodiments consistent with the present disclosure, and together with the description serve to explain the principles of the present disclosure.

[0007] In order to more clearly explain the technical solutions in the present disclosure or the prior art, the following briefly introduces drawings necessary for describing the embodiments or the prior art, and it is obvious that those skilled in the art can further derive other drawings based on these drawings without any creative work. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic diagram of a printed circuit board with possibly surface mount component pads, superimposed in plan view; [Figure 2] FIG. 1 is a side view of a printed circuit board with optional surface mount component pads. [Figure 3] FIG. 1 is a side view of a printed circuit board with optional gold finger pads. [Figure 4] FIG. 1 is an equivalent circuit diagram of a pad fan-out structure for a printed circuit board with optional pads. [Figure 5] 1 is a side view 1 of a printed circuit board having pads provided in the present disclosure. [Figure 6] 2 is a side view 2 of a printed circuit board having pads provided in the present disclosure. [Figure 7]1 is a schematic diagram of a printed circuit board having pads provided in the present disclosure, superimposed at a plan view angle; [Figure 8] 10A-10C are schematic diagrams illustrating the effect of adding stub anti-pads of different lengths provided in the present disclosure on the channel impedance. [Figure 9] 1A and 1B are schematic diagrams of signal insertion loss effects before and after adding a stub anti-pad provided in the present disclosure. [Figure 10] 1A and 1B are schematic diagrams of signal return loss effects before and after adding a stub anti-pad provided in the present disclosure; [Figure 11] FIG. 2 is a schematic diagram of a fan-out structure of a first sub-reference layer provided in the present disclosure. [Figure 12] 1 is a schematic diagram 1 of a fan-out structure of the second sub-reference layer provided in the present disclosure; [Figure 13] FIG. 2 is a schematic diagram 2 of the fan-out structure of the second sub-reference layer provided in the present disclosure. [Figure 14] 3 is a schematic diagram 3 of the fan-out structure of the second sub-reference layer provided in the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0009] In order to clarify the objectives, technical solutions and advantages of the present disclosure, the technical solutions in the present disclosure will be described clearly and completely below with reference to the drawings in the present disclosure, and it is obvious that the described embodiments are only some embodiments of the present disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments in the present disclosure without creative work belong to the protection scope of the present disclosure.

[0010] As signal speeds increase, the performance requirements for signal integrity (SI) of high-speed channels also increase. Among them, signal reflection due to impedance discontinuity has a significant impact on high-speed signals. Excessive signal reflection can affect the transmission quality of high-speed signals, causing phenomena such as signal rise / fall, ringing, and ringback. Therefore, impedance optimization of high-speed channels is very important.

[0011] When designing pads on a printed circuit board (PCB), such as surface-mounted device (SMD) pads or gold finger pads, the pads are typically designed to be long due to welding reliability considerations. This creates low impedance points. As shown in Figure 1, a conventional high-speed differential SMD pad (111) must be connected to a differential via (300) via a differential microstrip line (113) on the surface layer, and the inner layer is fanned out via a differential stripline (121). The signal flow in this design is high-speed differential SMD pad (111) → differential microstrip line (113) → differential via (300) → differential stripline (121). To ensure welding reliability, the high-speed differential SMD pad (111) must be longer than the end of the L-shaped fillet (400). As shown in Figure 2, this branching structure forms a stub (112), which affects the impedance of the high-speed differential SMD pad (111). As with the surface mount component pad, to ensure the reliability of the gold finger contact, a stub (112) remains at the end of the gold finger pad (111) at the contact point with the elastic sheet (500), affecting the impedance of the gold finger, as shown in Figure 3. Therefore, when the stub at the end of the surface mount component pad or gold finger pad is connected to the reference ground, a sudden change in capacitive impedance is formed, the equivalent circuit of which is shown in Figure 4, where C1 and C2, i.e., the equivalent capacitance of the pad stub, fillet, path, etc., are equivalent parts as indicated by the subscripts. Due to the influence of C1 and C2, the differential signal (P P-IN and P N-IN ) is easily reflected, which deteriorates the transmission quality of high-speed signals. Therefore, the technical problem to be solved is how to reduce the values of C1 and C2, which are the capacitive couplings between the pad stub and the reference ground, and improve the transmission quality of high-speed signals.

[0012] 5, which is a side view of a printed circuit board having a pad provided in the present disclosure. As shown in FIG. 5, the printed circuit board includes a signal layer 100 and a reference layer 200. A pad 111 is provided on the signal layer 100, and the pad 111 includes a stub 112. A first anti-pad 221 is provided on the reference layer 200. A vertically inverted image of the stub 112 on the reference layer 200 is located within the coverage area of the first anti-pad 221, and the first anti-pad 221 is used to reduce the impedance of the stub 112.

[0013] In an exemplary embodiment, the pad 111 may be a surface mount component pad, a gold finger pad, or other types of pads similar to a surface mount component pad or a gold finger pad, and the present disclosure is not particularly limited thereto. Whether the pad 111 is a surface mount component pad or a gold finger pad, both pads have a stub 112, and the principle is illustrated in Figures 2 and 3. For ease of explanation, all subsequent embodiments will be generally described using a surface mount component pad.

[0014] The signal layer 100 is used for accessing and transmitting high-speed signals, and the reference layer 200 is used to install the first anti-pad 221, increase the distance between the stub 112 and the reference ground, reduce capacitive coupling, optimize impedance, and improve signal transmission quality. In an exemplary embodiment, the portion of the pad 111 extending beyond the weld end a of the L-shaped fillet 400 in the length direction (i.e., the direction parallel to the information transmission direction) forms the stub 112. The signal layer 100 may have N pads 111, where N is an integer greater than or equal to 1, and each pad 111 may consist of two sub-pads, and is used for accessing high-speed differential signals. The portion of each pad 111 extending beyond the weld end a of the L-shaped fillet 400 in the length direction forms the corresponding stub 112. The reference layer 200 may have N first anti-pads 221, which correspond one-to-one to the N pads 111, i.e., one first anti-pad 221 is provided below the stub 112 region of each pad 111, to reduce the impedance of the stub 112 region of each pad 111 and thereby improve the transmission quality of each high-speed signal.

[0015] In an exemplary embodiment, as shown in FIG. 6 , the signal layer 100 includes a first sub-signal layer 110 and a second sub-signal layer 120, the reference layer 200 includes a first sub-reference layer 210 and a second sub-reference layer 220, the first sub-signal layer 110, the first sub-reference layer 210, the second sub-reference layer 220 and the second sub-signal layer 120 are stacked in order, and the first sub-signal layer 110, the first sub-reference layer 210, the second sub-reference layer 220 and the second sub-signal layer 120 are all provided with vias 300 penetrating through them, the first sub-signal layer 110 is provided with a pad 111 and a first signal path 113, and the pad 111 is connected to a first signal path 113, a second signal path 121 is provided on a second sub-reference layer 120, the first signal path 113 is connected to the second signal path 121 through a via 300, the second signal path 121 is used to fan out signals, a second anti-pad 211 is provided on the first sub-reference layer 210, a first anti-pad 221 is provided on the second sub-reference layer 220, the second anti-pad 211 is used to lower the impedance of the pad 111, and a vertically inverted image of the second anti-pad 211 on the second sub-reference layer 220 includes the area covered by the first anti-pad 221.

[0016] In an exemplary embodiment, the signal layer 100 may include a first sub-signal layer 110 and a second sub-signal layer 120 used for signal access and transmission, and the signal flow is from the pad 111 to the first signal path 113, via 300, and then to the second signal path 121. The reference layer 200 may include a first sub-reference layer 210 and a second sub-reference layer 220, so that the second anti-pad 211 on the first sub-reference layer 210 can be used to lower the impedance of the entire pad 111, and the first anti-pad 221 on the second sub-signal layer 120 can be used to lower the impedance of the stub 112, thereby further improving the signal transmission quality.

[0017] The first antipad 221 and the second antipad 211 are both installed by removing metal from a portion of the metal reference layer and replacing the metal with an insulating medium in this region. To ensure that the impedance of the pad 111 can be reduced using the second antipad 211 on the first sub-reference layer 210 and the impedance of the stub 112 can be reduced using the first antipad 221 on the second sub-signal layer 120, the vertically inverted image of the second antipad 211 on the second sub-reference layer 220 must include the area covered by the first antipad 221, i.e., the size of the second antipad 211 must be larger than the size of the first antipad 221. This prevents the space between the stub 112 and the first antipad 221 from being blocked by the metal portion of the first sub-reference layer 210, thereby optimizing the impedance of the first antipad 221 relative to the stub 112.

[0018] In one exemplary embodiment, refer to FIG. 7, which is a superimposed schematic diagram of a plan view angle of a printed circuit board having pads provided in the present disclosure. As shown in FIG. 7 , the pad 111 includes a first subpad 1111 and a second subpad 1112, the first signal path 113 includes a first microstrip line 1131 and a second microstrip line 1132, the second signal path 121 includes a first stripline 1211 and a second stripline 1212, the first subpad 1111 is connected to the first microstrip line 1131, the first microstrip line 1131 is connected to the first stripline 1211 through a via 300, the first subpad 1111 includes a first stub 1121, the second subpad 1112 is connected to the second microstrip line 1132, the second microstrip line 1132 is connected to the second stripline 1212 through a via 300, and the second subpad 1112 includes a second stub 1122.

[0019] In an exemplary embodiment, the number of first antipads 221 corresponds one-to-one to the number of pads 111, and the first antipads 221 are used to optimize the impedance of the first stub 1121 on the first subpad 1111 and the second stub 1122 on the second subpad 1112 of the pad 111. In this way, when the first subpad 1111 and the second subpad 1112 access the high-speed differential signal, the channel impedance of the high-speed differential signal can be optimized, the influence of signal reflection on the high-speed differential signal can be reduced, and the integrity of the high-speed differential signal can be improved.

[0020] In one exemplary embodiment, still referring to FIG. 7 , the vertically inverted image of the first subpad 1111 on the first sub-reference layer 210 and the vertically inverted image of the second subpad 1112 on the first sub-reference layer 210 are both located within the covered area of the second antipad 211, and the vertically inverted image of the first stub 1121 on the second sub-reference layer 220 and the vertically inverted image of the second stub 1122 on the second sub-reference layer 220 are both located within the covered area of the first antipad 221.

[0021] In one exemplary embodiment, the second antipad 211 is added below the first subpad 1111 and the second subpad 1112 as the first reference layer 200 of the pad 111, and the size of the second antipad 211 can be determined through simulation. Adding the second antipad 211 below the first subpad 1111 and the second subpad 1112 reduces the capacitive coupling between the first subpad 1111 and the second subpad 1112 and the reference ground, thereby achieving the effect of lowering the impedance of the first subpad 1111 and the second subpad 1112. The first antipad 221 is added below the second antipad 211 as the second reference layer 200 of the pad 111. The size of the first antipad 221 can be determined through simulation. By adding a first anti-pad 221 below the first stub 1121 and the second stub 1122 and reducing the capacitive coupling between the first stub 1121 and the second stub 1122 and the reference ground, the effect of lowering the impedance of the first stub 1121 and the second stub 1122 can be achieved, thereby avoiding low points in impedance, further reducing impedance fluctuations, and improving the channel bandwidth.

[0022] In this way, the second antipad 211 can effectively optimize the impedance of the first subpad 1111 and the second subpad 1112, and the first antipad 221 can further optimize the impedance of the first stub 1121 and the second stub 1122, thereby improving the signal transmission quality.

[0023] In one exemplary embodiment, still referring to FIG. 7 , a first end of the vertically inverted image of the first stub 1121 and a first end of the vertically inverted image of the second stub 1122 both coincide with a first side edge of the covered area of the first antipad 221, a second end of the vertically inverted image of the first stub 1121 and a second end of the vertically inverted image of the second stub 1122 do not extend beyond a second side edge of the covered area of the first antipad 221, the first end of the vertically inverted image of the first stub 1121 is an end of the vertically inverted image of the first stub 1121 that is close to the via 300, and the second end of the vertically inverted image of the first stub 1121 is an end of the vertically inverted image of the first stub 1121 that is close to the via 300. The first end of the vertically inverted image of the first stub 1121 is one end opposite to the first end of the vertically inverted image of the second stub 1122, the first end of the vertically inverted image of the second stub 1122 is one end closer to the via 300 of the vertically inverted image of the second stub 1122, the second end of the vertically inverted image of the second stub 1122 is one end opposite to the first end of the vertically inverted image of the second stub 1122, the first side edge of the covering area of the first antipad 221 is one side edge of the covering area of the first antipad 221 closer to the via 300, and the second side edge of the covering area of the first antipad 221 is one side edge opposite to the first side edge of the covering area of the first antipad 221.

[0024] The size and position of the first antipad 221 can be determined by simulation. When the first end of the vertically inverted image of the first stub 1121 and the first end of the vertically inverted image of the second stub 1122 are both coincident with the first side edge of the covering area of the first antipad 221, and the second end of the vertically inverted image of the first stub 1121 and the second end of the vertically inverted image of the second stub 1122 are both not beyond the second side edge of the covering area of the first antipad 221, the impedance optimization of the first stub 1121 and the second stub 1122 is relatively obvious.

[0025] In one exemplary embodiment, the ratio of the distance that the second side edge of the covering area of the first antipad 221 extends beyond the second end of the vertically inverted image of the first stub 1121 to the length of the first stub 1121 is less than 1, and the ratio of the distance that the second side edge of the covering area of the first antipad 221 extends beyond the second end of the vertically inverted image of the second stub 1122 to the length of the second stub 1122 is less than 1.

[0026] In one exemplary embodiment, adding a stub antipad (i.e., the first antipad 221) effectively reduces impedance discontinuity issues at the SMD pad end, improving impedance matching and signal integrity performance, and optimizing channel return loss and insertion loss. Specifically, referring to FIGS. 8-10, FIG. 8 illustrates the effect on channel impedance when no stub antipad is added and when stub antipads of different lengths are added, assuming a 0.5 mm length of stub 112 on pad 111. The horizontal axis of FIG. 8 represents the measurement time using a time domain reflectometer (TDR), and the vertical axis represents the measured value (i.e., channel impedance) corresponding to each measurement time. As can be seen from FIG. 8, the impedance continuity without the stub antipad is lower than that with the stub antipad. However, as the stub antipad length increases, the channel impedance continuity gradually increases, reaching an optimum when the stub antipad length is 0.75 mm. At the same time, when the stub anti-pad length is 0.75 mm, the optimization effect on the insertion loss and return loss of high-speed signals is relatively clear, as shown in Figures 9 and 10. In Figure 9, the horizontal axis represents signal frequency, and the vertical axis represents the corresponding insertion loss for each signal frequency. When the signal frequency reaches a certain frequency value, the insertion loss with the stub anti-pad is higher than the insertion loss without the stub anti-pad. In Figure 10, the horizontal axis represents signal frequency, and the vertical axis represents the corresponding return loss for each signal frequency. When the signal frequency reaches a certain frequency value, the return loss with the stub anti-pad is lower than the return loss without the stub anti-pad. Compared with the prior art, the present disclosure offers a revolutionary advance in technical value, achieving both signal integrity and design reliability solely from the perspective of inner-layer anti-pad design for printed circuit boards and resolving the signal distortion problem of optimizing pad stub impedance, which was not possible with prior art.

[0027] Note that the longer the stub anti-pad, the better. If the length of the stub anti-pad exceeds one time the length of the stub 112, the impedance continuity will be reduced. Therefore, when providing the length of the stub anti-pad, the distance that the stub anti-pad extends over the stub 112 is usually less than one time the length of the stub 112. As shown in Figures 11 and 12, after adding the stub anti-pad, the fan-out structure of the first sub-reference layer 210 of the pad 111 is shown in Figure 11, and the fan-out structure of the second sub-reference layer 220 of the pad 111 is shown in Figure 12.

[0028] In an exemplary embodiment, the shape of the covering area of the first anti-pad 221 is one of a rectangle, an oval, and a playground shape.

[0029] In an exemplary embodiment, as long as the covering area of the first antipad 221 satisfies the above size requirements, the shape of the covering area of the first antipad 221 may be any regular or irregular shape. In an exemplary embodiment, the shape of the covering area of the first antipad 221 may be rectangular, elliptical, playground-shaped, etc. For example, the shape of the covering area of the first antipad 221 may be elliptical or playground-shaped in addition to rectangular, as shown in FIGS. 13 and 14. That is, the rectangular first antipad 221 in FIG. 12 may be replaced with an elliptical first antipad 221 or a playground-shaped first antipad 221 to achieve the same effect.

[0030] 6 and 7, in an exemplary embodiment, a third anti-pad 310 is further provided on the first sub-reference layer 210, and a fourth anti-pad 320 is further provided on the second sub-reference layer 220, and both the third anti-pad 310 and the fourth anti-pad 320 are used to reduce the impedance of the via 300. In this way, the transmission quality of high-speed signals can be further improved.

[0031] In one exemplary embodiment, the first sub-reference layer 210 and the second sub-reference layer 220 are both metal layers connected to ground.

[0032] In this way, the first anti-pad 221 and the second anti-pad 211 can be placed on the metal layer connected to the ground terminal, and can also serve as the reference ground for the pad 111, thereby optimizing the impedance of the pad and pad stub 112.

[0033] The method for designing a printed circuit board with pads provided in this disclosure is as follows.

[0034] Step 1: Optimize the simulation. Step 1) Confirm pad size and printed circuit board stack-up based on connector pin specifications and system design requirements.

[0035] Step 2) Perform simulation optimization on the printed circuit board, add pad anti-pads (i.e., the second anti-pad 211), via anti-pads (i.e., the third anti-pad 310 and the fourth anti-pad 320), adjust the fan-out lines, and optimize the channel impedance.

[0036] Step 3) Add a pad stub anti-pad (ie, the first anti-pad 221) to precisely optimize the impedance at the pad end position, and its size is determined based on the simulation results.

[0037] Step 2: Create a light painting Gerber material. Step 1) Create a circuit principle diagram, add components such as connectors, and perform layout and wiring.

[0038] Step 2) Output the circuit network table and design the PCB. Based on the simulation optimization results, design the wiring method and anti-pads.

[0039] Step 3) Export the light painting file and place it in the PCB.

[0040] In this way, when the pad anti-pad and via anti-pad cannot continuously improve the bandwidth, the pad stub anti-pad can reduce the impedance variation of the entire channel. This eliminates the need for pad resizing or pad scraping. While ensuring the reliability of welding, it not only optimizes the impedance variation of the SMD pad, but also reduces the reflection of high-speed signals and improves signal integrity.

[0041] The present disclosure also provides a communication device, including the printed circuit board of any of the above embodiments. The communication device may be a printed circuit board including surface mount component pads or gold finger pads, and is suitable for wired and wireless communication devices of 112 Gbps or more.

[0042] The present disclosure provides a printed circuit board and a communication device having pads, and solves the problem that in some cases, a stub at the end of the pad is coupled to a reference ground, resulting in a change in capacitive impedance and deteriorating the transmission quality of high-speed signals.

[0043] In the present disclosure, the printed circuit board includes a signal layer and a reference layer. A pad is provided on the signal layer, the pad including a stub. A first antipad is provided on the reference layer, and a vertically inverted image of the stub on the reference layer is located within the coverage area of the first antipad, and the first antipad is used to reduce the impedance of the stub. In this way, the first antipad is provided below the stub area of the pad, and the first antipad can be used to reduce the capacitive coupling between the stub and the reference ground, thereby improving the transmission quality of high-speed signals.

[0044] It should be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another and do not necessarily require or imply that any such actual relationship or ordering exists between those entities or operations. Furthermore, the terms "comprise," "comprises," or any other variation thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not expressly listed or inherent in such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprises" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes that element.

[0045] The foregoing are only specific embodiments of the present disclosure, enabling those skilled in the art to understand or practice the present disclosure. Various modifications to these examples will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other examples without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not limited to the examples shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. a printed circuit board having pads, the printed circuit board including a signal layer and a reference layer; A pad is provided on the signal layer, the pad including a stub; A printed circuit board having a pad, wherein a first antipad is provided on the reference layer, a vertically inverted image of the stub on the reference layer is located within a coverage area of the first antipad, and the first antipad is used to lower the impedance of the stub.

2. the signal layer includes a first sub-signal layer and a second sub-signal layer, the reference layer includes a first sub-reference layer and a second sub-reference layer, the first sub-signal layer, the first sub-reference layer, the second sub-reference layer and the second sub-signal layer are stacked in order, and the first sub-signal layer, the first sub-reference layer, the second sub-reference layer and the second sub-signal layer are all provided with vias penetrating through each other; The pad and a first signal path are provided on the first sub-signal layer, and the pad is connected to the first signal path; a second signal path is provided on the second sub-signal layer, the first signal path is connected to the second signal path through the via, and the second signal path is used to fan out signals; 2. The printed circuit board of claim 1, wherein a second antipad is provided on the first sub-reference layer, the first antipad is provided on the second sub-reference layer, the second antipad is used to lower the impedance of the pad, and a vertically inverted image of the second antipad on the second sub-reference layer includes a covered area of the first antipad.

3. the pad includes a first subpad and a second subpad, the first signal path includes a first microstrip line and a second microstrip line, and the second signal path includes a first stripline and a second stripline; the first subpad is connected to the first microstrip line, the first microstrip line is connected to the first strip line through the via, and the first subpad includes a first stub; 3. The printed circuit board of claim 2, wherein the second subpad is connected to the second microstrip line, the second microstrip line is connected to the second strip line through the via, and the second subpad includes a second stub.

4. a vertically inverted image of the first subpad on the first sub-reference layer and a vertically inverted image of the second subpad on the first sub-reference layer are both located within a coverage area of the second antipad; 4. The printed circuit board of claim 3, wherein a vertically inverted image of the first stub on the second sub-reference layer and a vertically inverted image of the second stub on the second sub-reference layer are both located within a covered area of the first antipad.

5. a first end of the vertically inverted image of the first stub and a first end of the vertically inverted image of the second stub both coincide with a first side edge of a covered area of the first antipad, and a second end of the vertically inverted image of the first stub and a second end of the vertically inverted image of the second stub both do not extend beyond a second side edge of a covered area of the first antipad; 5. The printed circuit board of claim 4, wherein a first end of the vertically inverted image of the first stub is an end of the vertically inverted image of the first stub that is closer to the via, a second end of the vertically inverted image of the first stub that is opposite to the first end of the vertically inverted image of the first stub, a first end of the vertically inverted image of the second stub that is an end of the vertically inverted image of the second stub that is closer to the via, and a second end of the vertically inverted image of the second stub that is opposite to the first end of the vertically inverted image of the second stub, a first side edge of the covered area of the first antipad that is a side edge of the covered area of the first antipad that is closer to the via, and a second side edge of the covered area of the first antipad that is a side edge opposite to the first side edge of the covered area of the first antipad.

6. 6. The printed circuit board of claim 5, wherein a ratio of a distance that the second side edge of the covered area of the first antipad exceeds a second end of the vertically inverted image of the first stub to a length of the first stub is less than 1, and a ratio of a distance that the second side edge of the covered area of the first antipad exceeds a second end of the vertically inverted image of the second stub to a length of the second stub is less than 1.

7. 7. The printed circuit board according to claim 6, wherein the shape of the covering area of the first anti-pad is one of a rectangle, an oval, and a playground shape.

8. a third anti-pad is further provided on the first sub-reference layer, and a fourth anti-pad is further provided on the second sub-reference layer; The printed circuit board of claim 2 , wherein the third anti-pad and the fourth anti-pad are both used to lower the impedance of the via.

9. The printed circuit board of claim 8 , wherein the first sub-reference layer and the second sub-reference layer are both metal layers connected to a ground terminal.

10. A communication device comprising the printed circuit board according to any one of claims 1 to 9.

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