Capacitor, memory, and method of manufacturing the memory

Abstract

The present application relates to a capacitor, a memory, and a method for manufacturing a memory, the capacitor including a first electrode layer, a second electrode layer, and a strontium titanate dielectric layer formed between the first electrode layer and the second electrode layer, wherein the Sr / (Sr+Ti) ratio in the strontium titanate dielectric layer gradually decreases from the center of the strontium titanate dielectric layer toward both opposing sides of the strontium titanate dielectric layer, one of the opposing sides of the strontium titanate dielectric layer being closer to the first electrode layer and the other being closer to the second electrode layer.

Description

Detailed Description of the Invention

[0001] [Related Applications] This disclosure of the present application claims priority to Chinese patent application No. 2023109241479, filed on July 25, 2023, entitled "Capacitor, Memory, and Method for Manufacturing Memory," and Chinese patent application No. 2023219866424, filed on July 25, 2023, entitled "Capacitor, Memory, and Method for Manufacturing Memory," the entire contents of which are incorporated herein by reference.

[0002] [Technical Field] The present application is in the field of chips, and in particular relates to capacitors, memories and methods for manufacturing memories.

[0003] [Background technology] With the development of the chip industry, market demand for DRAM (Dynamic Random Access Memory) chips with higher memory density is increasing, and how to achieve higher memory density in DRAM chips is an important research topic in many chip industries.

[0004] For DRAM chips containing 1T1C (one transistor + one capacitor) structure, the capacitor is a key element that limits the critical size of the DRAM chip. To increase the memory density of DRAM while reducing the critical size of the DRAM chip, and ensure that the DRAM chip has sufficient signal resolution, that is, how to achieve a high dielectric constant (abbreviated as K value) and low leakage density of the capacitor, has become an urgent issue to be solved.

[0005] Summary of the Invention The embodiments of the present application provide a capacitor, a memory, and a method for manufacturing a memory that can achieve the effects of high K value and low leakage.

[0006] A first aspect of the present application provides a capacitor, a first electrode layer; a second electrode layer; and a strontium titanate dielectric layer formed between the first electrode layer and the second electrode layer; the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer gradually decreases in a direction from the center of the strontium titanate dielectric layer toward opposite sides of the strontium titanate dielectric layer; One of the opposing sides of the strontium titanate dielectric layer is close to the first electrode layer, and the other side is close to the second electrode layer.

[0007] A second aspect of the present application provides a memory, comprising a substrate and any of the capacitors described above, the capacitor being formed on the substrate.

[0008] A second aspect of the present application provides a method for manufacturing a memory, the method comprising: providing a substrate; forming a first electrode layer on the substrate; forming a strontium titanate dielectric layer on a side of the first electrode layer away from the substrate, wherein a ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer gradually decreases in a direction from a center of the strontium titanate dielectric layer toward opposite sides of the strontium titanate dielectric layer, one of the opposite sides of the strontium titanate dielectric layer being close to the first electrode layer and the other side being far from the first electrode layer; forming a second electrode layer on a side of the strontium titanate dielectric layer remote from the first electrode layer to form a capacitor.

[0009] The technical solution provided by the embodiments of the present application has at least the following advantages: The Sr content in the strontium titanate dielectric layer gradually decreases from the center to the opposing sides of the layer, and the Ti content gradually increases from the center to the opposing sides of the layer. This ensures that the entire strontium titanate dielectric layer has a high Sr content, resulting in a high K value. This also helps relieve or alleviate stress caused by the high Sr content of the strontium titanate dielectric layer, which tends to crystallize. That is, stress is gradually released from the center to the opposing sides of the strontium titanate dielectric layer, reducing the internal stress of the strontium titanate dielectric layer, thereby reducing the occurrence of cracks in the strontium titanate dielectric layer and improving the surface uniformity of the strontium titanate dielectric layer, thereby achieving low leakage performance.

[0010] BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the specification, serve to explain the principles of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can derive other drawings based on these drawings without any creative efforts.

[0011] 1 to 5 show structural schematic diagrams of memories corresponding to various solutions described in Example 1 of the present application.

[0012] FIG. 6 shows a schematic diagram of the three-dimensional structure of the memory described in Example 1 of the present application.

[0013] FIG. 7 shows a structural schematic diagram of a capacitor according to one solution described in Example 1 of this application.

[0014] 8 to 10 show the corresponding changes when different gradients of Sr / (Sr+Ti) ratio in the strontium titanate dielectric layer are designed in Example 1 of the present application.

[0015] FIG. 11 shows a structural schematic diagram of a capacitor according to another solution described in Example 1 of the present application.

[0016] 12 to 14 show structural schematic diagrams of capacitors corresponding to various solutions in Example 2 of the present application.

[0017] 15 to 25 show structural schematic diagrams corresponding to each step of the manufacturing method of the memory provided in Example 3 of the present application.

[0018] Explanation of reference symbols: 10, substrate; 100, semiconductor base; 101, insulating isolation layer; 11, capacitor; 11a, ruthenium element film layer; 11b, titanium nitride film layer; 110, first electrode layer; 111, dielectric layer; 111a, dielectric material film; 112, second electrode layer; 112a, second electrode material film; 1110, strontium titanate dielectric layer; 11101, strontium titanate film layer; 1111, first titanium oxide dielectric layer; 1112, second titanium oxide dielectric layer; 1113, first aluminum titanate dielectric layer; 1114, second aluminum titanate dielectric layer; 12, insulating medium layer; 13, etch stop layer; 14, measurement electrode material film; 14a, first measurement electrode; 14b, second measurement electrode; 140, via hole conductive portion; 141, measurement conductive portion; 15, interlayer medium layer; 150, through hole; 15a, interlayer medium material membrane; 16, transistor; 17, Wordline; 18, bit line; 19, the first photoresist mask layer; 20, second photoresist mask layer; 21, First Beer Hall; 22, second beer hall; 23, the third photoresist mask layer; 24, fourth photoresist mask layer.

[0019] [Mode for Carrying Out the Invention]

[0023] Exemplary embodiments will now be described in more detail with reference to the accompanying drawings. However, exemplary embodiments may be embodied in various forms and should not be construed as being limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of exemplary embodiments to those skilled in the art.

[0020] Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to provide a thorough understanding of the embodiments of the present application. However, those skilled in the art will understand that the technical solutions of the present application may be implemented without one or more of the specific details, or may employ other methods, components, devices, steps, etc. In other instances, well-known methods, devices, implementations, or operations have not been shown or described in detail to avoid obscuring aspects of the present application.

[0021] The present application will be described in more detail below in conjunction with the accompanying drawings and specific examples. It should be noted that the technical features contained in the various embodiments of the present application described below can be combined with each other as long as they are not mutually contradictory. The embodiments described below with reference to the drawings are illustrative and are intended to explain the present application, and should not be construed as limiting the present application.

[0022] Example 1 Although the embodiments of the present application provide a memory, and the memory may be a DRAM such as a 3D DRAM, i.e., a memory in which multiple layers of DRAM are stacked, it should be understood that the memory in the embodiments is not limited to a DRAM and may be other types of memory depending on the specific situation.

[0023] As shown in FIG. 1, the memory of this embodiment may include a substrate 10 and a plurality of memory units formed on the substrate 10, and the memory unit may include one capacitor 11 formed on the substrate 10.

[0024] The capacitor 11 may include a first electrode layer 110, a dielectric layer 111, and a second electrode layer 112 that are sequentially stacked on the substrate 10. That is, the dielectric layer 111 is formed between the first electrode layer 110 and the second electrode layer 112.

[0025] For example, the capacitor 11 may have a MIM (Metal-Isolation-Metal) structure, in which the first electrode layer 110 and the second electrode layer 112 contain a metal or a metal compound and are conductive, and the dielectric layer 111 is an insulator and is used to insulate the first electrode layer 110 from the second electrode layer 112.

[0026] As shown in FIG. 2 , the substrate 10 may include a semiconductor base 100 such as a silicon base, but is not limited to this, and may also be a base made of other semiconductor materials (e.g., silicon carbide, gallium compounds, germanium compounds). To isolate the influence of the semiconductor base 100 on the MIM structure, the substrate 10 may further include an insulating isolation layer 101 formed between the first electrode layer 110 and the semiconductor base 100. That is, before forming the first electrode layer 110 on the semiconductor base 100, the insulating isolation layer 101 can be formed on the semiconductor base 100, and then the first electrode layer 110 can be formed, and the insulating isolation layer 101 can be used to insulate the semiconductor base 100 from the first electrode layer 110.

[0027] For example, the insulating isolation layer 101 may be, but is not limited to, a SiO2 (silicon dioxide) material, and may be other insulating materials depending on the specific situation.

[0028] In order to measure the electrical properties of the dielectric layer 111 in the capacitor 11, a measurement electrode for measuring the capacitor 11 can also be fabricated during the process of fabricating the capacitor 11 on the substrate 10. Specifically, the relationship between the capacitor 11 and the measurement electrode is as follows:

[0029] 3, in the capacitor 11, the orthogonal projections of the second electrode layer 112 and the dielectric layer 111 onto the substrate 10 are located in the central region of the orthogonal projection of the first electrode layer 110 onto the substrate 10. That is, the edge regions of the first electrode layer 110 are not covered by the second electrode layer 112 and the dielectric layer 111 to facilitate contact between the measurement electrode (to be fabricated later) and the first electrode layer 110. Here, the orthogonal projection of the second electrode layer 112 onto the first electrode layer 110 overlaps with the orthogonal projection of the dielectric layer 111 onto the first electrode layer 110, ensuring the storage capacitance of the capacitor 11.

[0030] As shown in FIG. 4, after the capacitor 11 is formed on the substrate 10, the memory further includes an insulating medium layer 12, an etching stop layer 13, and a first measurement electrode 14a and a second measurement electrode 14a arranged at a distance from each other, formed on the substrate 10.

[0031] The insulating medium layer 12 covers the edge region of the first electrode layer 110 and the second electrode layer 112, and the etching stop layer 13 is formed on the side of the insulating medium layer 12 away from the substrate 10, and the etching stop layer 13 completely covers the insulating medium layer 12. The first measurement electrode 14a and the second measurement electrode 14b both include a via hole conductive portion 140 and a measurement conductive portion 141 that are connected to each other. The measurement conductive portions 141 of the first measurement electrode 14a and the second measurement electrode 14b are formed on the side of the etching stop layer 13 away from the substrate 10 and are used to connect to an external measurement device for measuring the performance of the capacitor 11.

[0032] The orthogonal projection of the via hole conductive portion 140 of the first measurement electrode 14a onto the substrate 10 is located within the orthogonal projection of the edge region of the first electrode layer 110 onto the substrate 10, and the via hole conductive portion 140 of the first measurement electrode 14a passes through the etching stop layer 13 and the insulating medium layer 12 in order to contact the edge region of the first electrode layer 110, resulting in one pole of the measurement device contacting the first electrode layer 110 via the first measurement electrode 14a. The orthogonal projection of the via hole conductive portion 140 of the second measurement electrode 14b onto the substrate 10 is located within the orthogonal projection of the second electrode layer 112 onto the substrate 10, and the via hole conductive portion 140 of the second measurement electrode 14b passes through the etching stop layer 13 and the insulating medium layer 12 in order to contact the second electrode layer 112, resulting in the other pole of the measurement device contacting the second electrode layer 112 via the second measurement electrode 14b.

[0033] In this embodiment, the material of the first measurement electrode 14a and the second measurement electrode 14b may be TiN (titanium nitride) or the like, but is not limited to this and may be other conductive materials depending on the specific situation.

[0034] Because the dielectric layer 111 in the capacitor 11 is very thin, typically only a few nanometers, the leakage at the edges of the dielectric layer 111 is very large, and the edge leakage is not an inherent property of the material and affects the measurement results. Based on this, as shown in FIG. 5, the memory of this embodiment can further include an interlayer medium layer 15 to increase the distance between the edge of the second electrode layer 112 and the first electrode layer 110.

[0035] 5, the interlayer medium layer 15 may be formed between the first electrode layer 110 and the insulating medium layer 12. The via-hole conductive portion 140 of the first measurement electrode 14a described above penetrates the etching stop layer 13 and the insulating medium layer 12, and also penetrates the interlayer medium layer 15, to contact the edge region of the first electrode layer 110. The interlayer medium layer 15 also has a through-hole 150 that exposes a portion of the first electrode layer 110.

[0036] 5, the dielectric layer 111 has a central portion and an edge portion surrounding the central portion, and the central portion of the dielectric layer 111 is formed in the through-hole 150 and contacts the first electrode layer 110. The edge portion of the dielectric layer 111 is disposed on a surface of the interlayer medium layer 15 away from the first electrode layer 110, thereby increasing the distance between the edge of the second electrode layer 112 and the first electrode layer 110. Furthermore, the orthogonal projection of the via hole conductive portion 140 of the second measurement electrode 14b onto the substrate 10 is located within the orthogonal projection of the through-hole 150 onto the substrate 10, i.e., the orthogonal projection of the via hole conductive portion 140 of the second measurement electrode 14b onto the substrate 10 is located within the orthogonal projection of the central portion of the dielectric layer 111 onto the substrate 10, thereby accurately measuring the K value and leakage at the center of the dielectric layer 111.

[0037] 4 and 5, the first measurement electrode 14a and the second measurement electrode 14b are provided with a plurality of via hole conductive parts 140 at equal intervals around the axis of the through hole 150. This makes the electric field more uniformly distributed during the measurement process, and the measurement effect more accurate.

[0038] In addition, if there are multiple via hole conductive portions 140 in both the first measurement electrode 14a and the second measurement electrode 14b, there may be only one measurement conductive portion 141 in the first measurement electrode 14a and the second measurement electrode 14b, but this is not limited to this. Multiple measurement conductive portions 141 may be arranged at equal intervals around the axis of the through hole 150 and connected to the via hole conductive portions 140 in a one-to-one or one-to-many manner.

[0039] The first measurement electrode 14a and the second measurement electrode 14b described in this embodiment are not limited to being retained in the final manufactured memory, and may be completely or partially cut during the die cutting process after the test is completed, depending on the specific cutting situation, but this does not affect the final use of the product.

[0040] 6, in addition to the capacitor 11, the memory unit may also include one transistor 16, a word line 17, and a bit line 18. The transistor 16, the word line 17, and the bit line 18 may all be formed on the substrate 10, and the gate of the transistor 16 may be connected to the word line, one of the source and drain of the transistor 16 may be connected to the bit line 18, and the other may be connected to the capacitor 11, specifically, to the first electrode layer 110 of the capacitor 11, to realize data read and write operations, that is, the memory unit may have a 1T1C structure.

[0041] For memories including a 1T1C (one transistor 16 + one capacitor 11) structure, the capacitor 11 is a key element that limits the critical size of the memory, and how to increase the storage density of DRAM while reducing the critical size and ensuring that the DRAM chip has sufficient signal resolution has become an urgent issue to be solved.

[0042] When the memory is a 3D DRAM, the capacitor 11 can be arranged horizontally as shown in FIG. 6, and the storage density can be effectively increased by shortening the horizontal length of the capacitor 11. The first electrode layer 110, the second electrode layer 112, and the dielectric layer 111 of the capacitor 11 can also be adjusted so that the capacitor 11 has a higher dielectric constant (abbreviated as K value), i.e., to increase the storage density and reduce leakage. This method is not only applicable to 3D DRAM, but also to other memories including capacitive structures. The structure of the capacitor 11 in the embodiments of the present application will be described in detail below with reference to the drawings.

[0043] In this embodiment, as shown in FIG. 7, the dielectric layer 111 of the capacitor can include a strontium titanate dielectric layer 1110 (referred to as an STO dielectric layer), where the strontium titanate dielectric layer 1110 includes strontium (Sr) and titanium (Ti).

[0044] Research has shown that when the entire strontium titanate dielectric layer 111 is designed to have a high Sr content, i.e., when the Sr content is greater than the Ti content in the overall design of the strontium titanate dielectric layer 1110 and the strontium titanate dielectric layer 1110 is a strontium-rich layer (Sr Rich), the K value is relatively large and the memory density is high, but the strontium titanate dielectric layer 1110 is prone to cracking, which makes the electric field distribution of the formed capacitor uneven and therefore the capacitor 11 is prone to leakage. In addition, because Sr is a heavy metal, oxygen deficiency is likely to occur, further increasing leakage. If the entire strontium titanate dielectric layer 1110 is designed to have a high Ti content, i.e., the Ti content is greater than the Sr content in the overall design of the strontium titanate dielectric layer 1110, and this strontium titanate dielectric layer 1110 is a titanium-rich layer (Ti Rich), it will be less likely to crack and will have low leakage effects, but its relatively small K value will not be useful for reducing the size of the capacitor, nor will it be useful for increasing the memory density of DRAM chips.

[0045] Therefore, the embodiment of the present application implements a gradient design for the structure of the strontium titanate dielectric layer 1110. Specifically, the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer 1110 gradually decreases from the center of the strontium titanate dielectric layer 1110 toward both opposing sides of the strontium titanate dielectric layer 1110 (i.e., the Sr content gradually decreases and the Ti content gradually increases in the strontium titanate dielectric layer 1110). In other words, the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer 1110 gradually increases from the opposing sides of the strontium titanate dielectric layer 1110 toward the center of the strontium titanate dielectric layer 1110 (i.e., the Sr content gradually increases and the Ti content gradually decreases in the strontium titanate dielectric layer 1110).

[0046] One of the opposing sides of the strontium titanate dielectric layer 1110 is close to the first electrode layer 110, and the other side is close to the second electrode layer 112. The Sr / (Sr+Ti) ratio in the strontium titanate dielectric layer 1110 gradually decreases in the direction from the center of the strontium titanate dielectric layer 1110 toward the first electrode layer 110, and the Sr / (Sr+Ti) ratio in the strontium titanate dielectric layer 1110 gradually decreases in the direction from the center of the strontium titanate dielectric layer 1110 toward the second electrode layer 112.

[0047] In the solution of this embodiment, compared with the technical solution in which the entire strontium titanate dielectric layer 1110 is a titanium-rich or strontium-rich layer, the Sr content ratio in the strontium titanate dielectric layer 1110 gradually decreases from the center of the strontium titanate dielectric layer 1110 toward the opposing sides of the strontium titanate dielectric layer 1110, and the Ti content ratio gradually increases from the center of the strontium titanate dielectric layer 1110 toward the opposing sides of the strontium titanate dielectric layer 1110. In this way, it is ensured that the entire strontium titanate dielectric layer 1110 has a high Sr content, resulting in a high K value, which may also be beneficial to the release or relaxation of stress caused by the strontium titanate dielectric layer 1110 being easily crystallized due to its high Sr content. That is, the stress is gradually released from the center of the strontium titanate dielectric layer 1110 to both sides thereof, which reduces the internal stress of the strontium titanate dielectric layer 1110, thereby reducing the occurrence of cracks in the strontium titanate dielectric layer 1110, improving the surface uniformity of the strontium titanate dielectric layer 1110, and thereby resulting in lower leakage performance.

[0048] In other words, this solution improves the K value of the capacitor 11, i.e., effectively increasing the packing density of the capacitor 11 and reducing its leakage, which is helpful for the significant size reduction in the 1T1C structure and the improvement of the packing density of the 3D DRAM.

[0049] Illustratively, in this embodiment, the Sr / (Sr+Ti) ratio at the center of the strontium titanate dielectric layer 1110 is greater than 50%, i.e., the Sr content at the center of the strontium titanate dielectric layer 1110 is greater than the Ti content, and the center of the strontium titanate dielectric layer 1110 is in an Sr-rich state, which ensures that the center of the strontium titanate dielectric layer 1110 has a high K value, thereby ensuring that the entire strontium titanate dielectric layer 1110 has good memory density.

[0050] It should be noted that the design of the Sr / (Sr+Ti) ratio at the center of the strontium titanate dielectric layer 1110 can be related to its thickness to ensure the performance of the entire strontium titanate dielectric layer 1110.

[0051] The thickness of the strontium titanate dielectric layer 1110 can be in the range of 5 nm to 7 nm, such as 5 nm, 5.5 nm, 6 nm, 6.5 nm, 7 nm, and the Sr / (Sr+Ti) ratio at the center of the strontium titanate dielectric layer 1110 can be in the range of 60% to 65%, such as 60%, 61%, 62%, 63%, 64%, 65%, etc.

[0052] For example, when the thickness of the strontium titanate dielectric layer 1110 is about 6 nm, the Sr / (Sr+Ti) ratio at the center of the strontium titanate dielectric layer 1110 can basically reach 62%, so that the capacitor can achieve high K value (>60) and low leakage (<10-5) performance.

[0053] 7, the entire strontium titanate dielectric layer 1110 has a one-time cast single-layer structure. That is, when forming the strontium titanate dielectric layer 1110 on the side of the first electrode layer 110 away from the substrate 10, a film formation process, for example, an atomic layer deposition (ALD) process, can be used to deposit a strontium titanate material on the side of the first electrode layer 110 away from the substrate 10 to form the strontium titanate dielectric layer 1110.

[0054] In the atomic layer deposition process, by adjusting the flow rates of the Sr precursor and / or Ti precursor, the Sr content percentage in the strontium titanate dielectric layer 1110 is first gradually increased and then gradually decreased, thereby causing the Sr / (Sr+Ti) ratio in the strontium titanate material to first gradually increase and then gradually decrease, forming the above-mentioned strontium titanate dielectric layer 1110. That is, the Sr / (Sr+Ti) ratio in the strontium titanate dielectric layer 1110 gradually increases in the direction from the opposing sides of the strontium titanate dielectric layer 1110 toward the center of the strontium titanate dielectric layer 1110.

[0055] 7 , in the strontium titanate dielectric layer 1110, the surface closer to the first electrode layer 110 is defined as a first boundary surface a1, and the surface closer to the second electrode layer 112 is defined as a second boundary surface a2, and the Sr content at the first boundary surface a1 and the second boundary surface a2 may be 0. In other words, when fabricating the strontium titanate dielectric layer 1110, the initial strontium titanate material deposited at the start of a single atomic layer deposition process contains no Sr or has a very small Sr content of approximately 0. Thereafter, the proportion of Sr in the strontium titanate material is gradually increased until a set amount is reached, and then the proportion of Sr in the strontium titanate material is gradually decreased until the Sr content in the strontium titanate material is 0 or approximately 0 when the single atomic layer deposition process is completed.

[0056] In addition, when the Sr content of the first boundary surface a1 and the second boundary surface a2 in the strontium titanate dielectric layer 1110 is 0, the first boundary surface a1 and the second boundary surface a2 can be regarded as titanium dioxide (TiO2) surfaces, and the use of TiO2 at the boundaries can effectively reduce oxygen vacancies in the strontium titanate dielectric layer 1110 and reduce the occurrence of leakage.

[0057] For example, when fabricating a single-layer strontium titanate dielectric layer 1110, the strontium titanate material deposited at the beginning and end of a single atomic layer deposition process can be Sr-free and can also be doped with Al (aluminum), i.e., the first interface a1 and the second interface a2 can be ATO (aluminum titanate) interfaces to improve the conduction band offset (CBO) and further reduce leakage.

[0058] It should be understood that when a semiconductor and a semiconductor or an insulator and a semiconductor come into contact to form an interface structure, a discontinuous step, i.e., an energy band offset, is formed at the bottom of the conduction band and the top of the valence band of both materials due to the difference in band gaps. Here, the energy band offset at the bottom of the conduction band is called the conduction band offset (CBO), and the energy band offset at the top of the valence band is called the valence band offset (VBO).

[0059] In an optional embodiment, the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer 1110 gradually decreases according to a linear relationship in a direction from the center of the strontium titanate dielectric layer 1110 (which center passes through the dotted line in FIG. 7 ) toward opposite sides of the strontium titanate dielectric layer 1110 (in the direction of the bold black arrows in FIG. 7 ). In other words, the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer 1110 can decrease at a uniform rate in a direction from the center of the strontium titanate dielectric layer 1110 toward opposite sides of the strontium titanate dielectric layer 1110 to achieve a good balance between high-K and low leakage performance of the strontium titanate dielectric layer 1110.

[0060] For example, referring to FIG. 8, the above linear relationship can be specifically expressed as follows:

[0061]

number

[0062] For example, if C is 0.62 and H is 6 nm, the linear relationship can be expressed as follows:

[0063]

number

[0064] 9 , the Sr / (Sr+Ti) ratio in the strontium titanate dielectric layer 1110 gradually decreases from the center of the layer 1110 to the opposing sides of the layer 1110. In other words, the Sr / (Sr+Ti) ratio in the layer 1110 gradually decreases from the opposing sides of the layer 1110 to the center of the layer 1110. That is, when fabricating the entire layer 1110, the Sr content is first rapidly increased, then slowly increased to a maximum value, then slowly decreased, and then rapidly decreased. This can ensure that the layer 1110 has low leakage performance while also increasing the K value of the layer 1110.

[0065] Illustratively, the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer 1110 may satisfy the following relationship:

[0066]

number

[0067] For example, when C is 0.62 and H is 6 nm, the relationship satisfied by the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer 1110 can be expressed as follows:

[0068]

number

[0069] 10 , the rate of decrease of the Sr / (Sr+Ti) ratio in the strontium titanate dielectric layer 1110 gradually decreases in a direction from the center of the strontium titanate dielectric layer 1110 toward the opposing sides of the strontium titanate dielectric layer 1110. In other words, the rate of increase of the Sr / (Sr+Ti) ratio in the strontium titanate dielectric layer 1110 gradually increases in a direction from the opposing sides of the strontium titanate dielectric layer 1110 toward the center of the strontium titanate dielectric layer 1110. That is, when fabricating the entire strontium titanate dielectric layer 1110, the Sr content is first slowly increased, then the Sr content is rapidly increased to a maximum value, then the Sr content is first rapidly decreased, and then the Sr content is slowly decreased, thereby ensuring that the strontium titanate dielectric layer 1110 has a high K value, while also improving the surface uniformity of the opposing sides of the strontium titanate dielectric layer 1110, thereby resulting in low leakage performance.

[0070] The X-axis in Figures 8 to 10 is used to represent the distance from the strontium titanate dielectric layer 1110, with units of nm (nanometers), the Y-axis is used to represent the ratio of Sr / (Sr+Ti), the line on the left side of the Y-axis represents the change in the ratio of Sr / (Sr+Ti) between the center of the strontium titanate dielectric layer 1110 and the first electrode layer 110, and the line on the right side of the Y-axis is used to represent the change in the ratio of Sr / (Sr+Ti) between the center of the strontium titanate dielectric layer 1110 and the second electrode layer 112.

[0071] In addition, to further improve the performance of the capacitor, 11 As shown in Fig. 1, the first electrode layer 110 and the second electrode layer 112 of this embodiment may include a ruthenium element film layer 11a. This ruthenium element film layer 11a is a metal ruthenium (Ru) film layer or a ruthenium oxide (RuO2) film layer, and has a high work function. Here, the work function, also called the electron work function, is defined in solid state physics as the minimum energy required to move one electron from the interior of a solid to the surface of the object.

[0072] For example, the dielectric layer 111 of the capacitor may only include the above-mentioned strontium titanate dielectric layer 1110, with the first boundary surface a1 of the strontium titanate dielectric layer 1110 contacting the ruthenium element film layer 11a of the first electrode layer 110 and the second boundary surface a2 of the strontium titanate dielectric layer 1110 contacting the ruthenium element film layer 11a of the second electrode layer 112. When the first boundary surface a1 and the second boundary surface a2 of the strontium titanate dielectric layer 1110 are TiO2 surfaces, the ruthenium element film layer 11a can promote the TiO2 at the interface to form a rutile structure, thereby reducing leakage and increasing the K value. As a result, the K value of the strontium titanate dielectric layer 1110 first decreases and then increases from the center to both sides, mainly increasing the dielectric constant at the center and the boundary, and mainly reducing leakage in the region between the middle and the boundary.

[0073] figure 11As shown in Figure 1, the first electrode layer 110 and the second electrode layer 112 further include a titanium nitride film layer 11b formed on the side of the ruthenium element film layer 11a away from the strontium titanate dielectric layer 1110. This allows the overall thickness and work function of the first electrode layer 110 and the second electrode layer 112 to meet requirements, while the titanium nitride film layer 11b can appropriately reduce the thickness of the ruthenium element film layer 11a, promoting the formation of a rutile structure of TiO2 at the interface, reducing leakage, increasing the K value, and appropriately reducing the cost of the first electrode layer 110 and the second electrode layer 112.

[0074] Example 2 The main difference between the examples of the present application and Example 1 is that the strontium titanate dielectric layer 1110 of the capacitor in Example 1 is designed to have a single-layer structure, while the strontium titanate dielectric layer 1110 of the capacitor in Example 2 can have a multi-layer laminated structure.

[0075] Hereinafter, the structure of a capacitor according to an embodiment of the present application will be described in detail with reference to the accompanying drawings.

[0076] 12 , the strontium titanate dielectric layer 1110 may have a multi-layer structure, and may include N strontium titanate film layers 11101 stacked in sequence, where N is a positive integer greater than or equal to 3. It should be understood that each forming process forms one film layer, i.e., the strontium titanate dielectric layer 1110 is formed by multiple forming processes. For example, the step of forming the strontium titanate dielectric layer 1110 on the side of the first electrode layer 110 away from the substrate 10 may specifically include the step of forming N strontium titanate film layers 11101 stacked in sequence on the side of the first electrode layer 110 away from the substrate 10 using atomic layer deposition N times to form the stacked strontium titanate dielectric layer 1110.

[0077] It should be noted that the strontium titanate film layer 11101 in this embodiment is a film layer containing both Sr and Ti, i.e., the ratio of Sr / (Sr+Ti) in each strontium titanate film layer 11101 is greater than 0.

[0078] In the direction from the center of the strontium titanate dielectric layer 1110 toward opposite sides of the strontium titanate dielectric layer 1110, the ratio of Sr / (Sr+Ti) within the strontium titanate dielectric layer 1110 decreases from layer to layer. As shown in Figure 12, for example, when N is equal to 3, the strontium titanate dielectric layer 1110 may include a first strontium titanate film layer 11101, a second strontium titanate film layer 11101, and a third strontium titanate film layer 11101 stacked in sequence, wherein the Sr / (Sr+Ti) ratio in the second strontium titanate film layer 11101 is the largest, and the Sr / (Sr+Ti) ratios in the first strontium titanate film layer 11101 and the third strontium titanate film layer 11101 are smaller than the Sr / (Sr+Ti) ratio in the second strontium titanate film layer 11101. It should be noted that the strontium titanate dielectric layer 1110 is not limited to including the three strontium titanate film layers 11101 shown in FIG. 12, but may also include four, five, etc. layers depending on the particular situation.

[0079] In this embodiment, the strontium titanate dielectric layer 1110 is designed into a multi-layer laminate structure, thereby realizing a gradient design of the strontium titanate dielectric layer 1110, ensuring that the strontium titanate dielectric layer 1110 has high K value and low leakage characteristics. At the same time, the manufacturing method is simple, and the thickness of the strontium titanate dielectric layer 1110 remains the same, but is produced in layers, resulting in a thinner layer. This makes it easier to control the uniformity of the film formation, improves product performance, and is also useful for rapid use. Existing equipment can be used to form each layer of the strontium titanate film layer 11101 in order, eliminating the need to redevelop the equipment and reducing research and development costs.

[0080] In addition, in this embodiment, the strontium titanate dielectric layer 1110 is designed to be stacked with at least three strontium titanate film layers 11101, thereby realizing a gradient design in both the area close to the first electrode layer 110 and the area close to the second electrode layer 112, and ensuring that the strontium titanate dielectric layer 1110 has high K value and low leakage characteristics between the first electrode layer 110 and the second electrode layer 112.

[0081] Illustratively, N in this embodiment may be an odd number greater than or equal to 3. That is, the number of strontium titanate film layers 11101 in the strontium titanate dielectric layer 1110 is an odd number greater than or equal to 3, for example, N=3, 5, 7, 9, etc., depending on specific circumstances.

[0082] In this embodiment, by making the number of strontium titanate film layers 11101 in the strontium titanate dielectric layer 1110 an odd number, the number of film layers on both sides of the centrally located strontium titanate film layer 11101 is the same, thereby ensuring that both the region close to the first electrode layer 110 and the region close to the second electrode layer 112 of the strontium titanate dielectric layer 1110 achieve a balanced gradient design and improve product quality.

[0083] The Sr / (Sr+Ti) ratio may be equal at each location in the strontium titanate film layer 11101. In other words, since the flow rates of the Sr precursor and Ti precursor are constant in each atomic layer deposition process, each layer of the strontium titanate film 11101 can be formed sequentially using existing equipment, eliminating the need for equipment redevelopment and reducing research and development costs.

[0084] The Sr / (Sr+Ti) ratio between each strontium titanate film layer 11101 in the strontium titanate dielectric layer 1110 can be designed according to formulas (1) and (2) described in Example 1. In this Example 2, parameter C described in formulas (1) and (2) is the Sr / (Sr+Ti) ratio in the centralmost strontium titanate film layer 11101, and parameter D is the distance between the center of the other film layers and the center of the centralmost strontium titanate film layer 11101.

[0085] In an optional embodiment, referring to FIG. 13, the dielectric layer 111 of the capacitor 11 can include, in addition to the aforementioned strontium titanate dielectric layer 1110, a first titanium oxide dielectric layer 1111 and a second titanium oxide dielectric layer 1112, wherein the first titanium oxide dielectric layer 1111 is formed between the first electrode layer 110 and the strontium titanate film layer 11101 of the strontium titanate dielectric layer 1110, and the second titanium oxide dielectric layer 1112 is formed between the second electrode layer 112 and the strontium titanate dielectric layer 1110, and by forming the first titanium oxide dielectric layer 1111 and the second titanium oxide dielectric layer 1112 on opposite sides of the strontium titanate dielectric layer 1110, a gradient design of the dielectric layer 111 is further realized. That is, compared to the central strontium titanate film layer 11101, the film layers located on both outermost sides of the dielectric layer 111 do not contain Sr and form a first titanium oxide dielectric layer 1111 and a second titanium oxide dielectric layer 1112. This ensures uniformity of the outermost surfaces of the entire dielectric layer 111 in the capacitor 11, resulting in low leakage performance.

[0086] Furthermore, when the first electrode layer 110 and the second electrode layer 112 of this embodiment include the ruthenium element film layer 11a described in the above-mentioned Example 1, the first titanium oxide dielectric layer 1111 can be in contact with the ruthenium element film layer 11a of the first electrode layer 110, and the second titanium oxide dielectric layer 1112 can be in contact with the ruthenium element film layer 11a of the second electrode layer 112, and the ruthenium element film layer 11a can promote the first titanium oxide dielectric layer 1111 and the second titanium oxide dielectric layer 1112 to form a rutile structure in contact therewith, thereby reducing leakage and increasing the K value. The K value of the entire dielectric layer 111 in the first electrode layer 110 and the second electrode layer 110 first decreases and then increases from the center to both sides, with the center and the boundaries mainly increasing the dielectric constant and the area between the middle and the boundaries mainly providing the effect of reducing leakage.

[0087] In another optional embodiment, referring to FIG. 14 , the dielectric layer 111 of the capacitor 11 can include, in addition to the aforementioned strontium titanate dielectric layer 1110, a first aluminum titanate dielectric layer 1113 and a second aluminum titanate dielectric layer 1114, with the first aluminum titanate dielectric layer 1113 formed between the first electrode layer 110 and the strontium titanate dielectric layer 1110, and the second aluminum titanate dielectric layer 1114 formed between the second electrode layer 112 and the strontium titanate dielectric layer 1110.

[0088] For example, the first aluminum titanate dielectric layer 1113 can be in contact with the elemental ruthenium film layer 11a of the first electrode layer 110, and the second aluminum titanate dielectric layer 1114 can be in contact with the elemental ruthenium film layer 11a of the second electrode layer 112. This design can increase the K value and enhance the conduction band offset (CBO), further reducing leakage.

[0089] It should be noted that, except for the differences from the first embodiment described above, the rest of the design of the second embodiment can refer to the contents of the first embodiment, and will not be repeated here.

[0090] Example 3 The embodiments of the present application also provide a memory manufacturing method that can manufacture the memory provided in the above embodiments. For detailed descriptions of the memory, please refer to the above embodiments, and will not be described in detail here.

[0091] Referring to FIGS. 1 to 25, the method for manufacturing a memory may include at least step S100, step S200, step S300, and step S400.

[0092] In step S100, a substrate 10 is provided. For example, as shown in Figures 2 to 5, a semiconductor base 100 may be provided first, and then an insulating isolation layer 101 may be formed on the semiconductor base 100. Here, the semiconductor base 100 may be silicon-based, the insulating isolation layer 101 may be SiO2, and the deposition thickness of the insulating isolation layer 101 may be 2000 Å (angstroms).

[0093] In step S200, a first electrode layer 110 is formed on the substrate 10. For example, the first electrode layer 110 may be formed on the side of the insulating isolation layer 101 away from the semiconductor base 100, where the first electrode layer 110 may include a TiN layer and a RuO layer sequentially formed on the side of the insulating isolation layer 101 away from the semiconductor base 100.

[0094] In step S300, a dielectric layer 111 is formed on the side of the first electrode layer 110 away from the substrate 10, the dielectric layer 111 including at least a strontium titanate dielectric layer 1110, wherein the Sr / (Sr+Ti) ratio in the strontium titanate dielectric layer 1110 gradually decreases from the center of the strontium titanate dielectric layer 1110 toward the opposing sides of the strontium titanate dielectric layer 1110. For example, the strontium titanate dielectric layer 1110 can be formed on the side of a RuO2 layer away from the semiconductor base 100.

[0095] In an optional embodiment, step S300 specifically includes depositing a strontium titanate material on the side of the first electrode layer 110 away from the substrate 10 using a single-stage atomic layer deposition process to form the strontium titanate dielectric layer 1110, as shown in FIG. 7, wherein, in the single-stage atomic layer deposition process, by adjusting the flow rate of the Sr precursor and / or the Ti precursor, the ratio of Sr / (Sr+Ti) in the strontium titanate material initially gradually increases and then gradually decreases according to a set rule.

[0096] 12 to 14, step S300 specifically includes using N atomic layer deposition processes to sequentially form N strontium titanate film layers 11101 on the side of the first electrode layer 110 away from the substrate 10 to form the strontium titanate dielectric layer 1110, where N is a positive integer greater than or equal to 3. Here, in each atomic layer deposition process, the flow rates of the Sr precursor and the Ti precursor may be essentially constant, i.e., within a tolerance range.

[0097] In step S400, a capacitor can be formed by forming a second electrode layer 112 on a side of the strontium titanate dielectric layer 1110 away from the first electrode layer 110. Here, the second electrode layer 112 can include a RuO layer and a TiN layer sequentially formed on a side of the strontium titanate dielectric layer 1110 away from the first electrode layer 110.

[0098] In an optional embodiment, as shown in FIG. 13, before step S300 and after step S200, the manufacturing method may further include a step of forming a first titanium oxide dielectric layer 1111 on the side of the first electrode layer 110 away from the substrate 10, and after step S300 and before step S400, the manufacturing method may further include a step of forming a second titanium oxide dielectric layer 1112 on the side of the strontium titanate dielectric layer 1110 away from the first electrode layer 110.

[0099] In another optional embodiment, as shown in FIG. 14, before step S300 and after step S200, the manufacturing method further includes a step of forming a first aluminum titanate dielectric layer 1113 on the side of the first electrode layer 110 away from the substrate 10, and after step S300 and before step S400, the manufacturing method further includes a step of forming a second aluminum titanate dielectric layer 1114 on the side of the strontium titanate dielectric layer 1110 away from the first electrode layer 110.

[0100] The step of forming the first aluminum titanate dielectric layer 1113 on the side of the first electrode layer 110 away from the substrate 10 can specifically include the steps of forming a first titanium oxide dielectric layer 1111 on the side of the first electrode layer 110 away from the substrate 10, and then doping aluminum elements into the first titanium oxide dielectric layer 1111 to form the first aluminum titanate dielectric layer 1113, and the step of forming the second aluminum titanate dielectric layer 1114 on the side of the strontium titanate dielectric layer 1110 away from the first electrode layer 110 includes the steps of forming a second titanium oxide dielectric layer 1112 on the side of the strontium titanate dielectric layer 1110 away from the first electrode layer 110, and then doping aluminum elements into the second titanium oxide dielectric layer 1112 to form the second aluminum titanate dielectric layer 1114.

[0101] It should be understood that the aluminum element can be doped into the interface of the first titanium oxide dielectric layer 1111 toward the first electrode layer 110 to form a first aluminum titanate dielectric layer 1113, and can also extend inward to a certain extent. Similarly, the aluminum element can be doped into the interface of the second titanium oxide dielectric layer 1112 toward the second electrode layer 112 to form a second aluminum titanate dielectric layer 1114, and can also extend inward to a certain extent.

[0102] Before step S300 and after step S200, the manufacturing method further includes the steps of forming an interlayer medium material film 15a on the side of the first electrode layer 110 away from the substrate 10, and forming a through hole 150 in the interlayer medium material film 15a by a patterning process to expose a portion of the first electrode layer 110, thereby forming an interlayer medium layer 15, as shown in FIG.

[0103] For example, as shown in Fig. 16, a photoresist layer can be formed on the side of the interlayer medium material film 15a away from the first electrode layer 110, and then the photoresist layer can be exposed and developed to form a first photoresist mask layer 19. Then, as shown in Fig. 17, the interlayer medium material film 15a is etched using the first photoresist mask layer 19 to form through-holes 150, and finally the first photoresist mask layer 19 is removed.

[0104] It should be understood that at least a portion of the strontium titanate dielectric layer 1110 is located within the through-hole 150 and in contact with the first electrode layer 110 .

[0105] The steps of sequentially forming the strontium titanate dielectric layer 1110 and the second electrode layer 112 on the side of the first electrode layer 110 away from the substrate 10 may specifically include the following steps:

[0106] After forming the interlayer medium layer 15, as shown in Fig. 18, a dielectric material film (strontium titanate dielectric material film) 111a and a second electrode material film 112a are sequentially formed to be located in the through-hole 150 and cover the interlayer medium layer 15. Then, as shown in Fig. 20, portions of the dielectric material film (strontium titanate dielectric material film) 111a and the second electrode material film 112a that cover the interlayer medium layer 15 are removed to form a strontium titanate dielectric layer 1110 and a second electrode layer 112.

[0107] For example, as shown in FIG. 19, first, a photoresist layer is formed on the second electrode material film 112a, and the photoresist layer is exposed and developed to form a second photoresist mask layer 20. Then, the dielectric material film (strontium titanate dielectric material film) 111a and the second electrode material film 112a are etched using the second photoresist mask layer 20 to remove portions of the dielectric material film (strontium titanate dielectric material film) 111a and the second electrode material film 112a that cover the interlayer medium layer 15, thereby forming a strontium titanate dielectric layer 1110 and the second electrode layer 112. Finally, as shown in FIG. 20, the second photoresist mask layer 20 is removed.

[0108] After step S400, the manufacturing method further includes steps S500, S600, S700, and S800.

[0109] 21, an insulating medium layer 12 and an etching stop layer 13 are sequentially formed on the interlayer medium layer 15 and the second electrode layer 112 on the side away from the substrate 10. For example, the material of the insulating medium layer 12 can be SiO2, and the material of the etching stop layer 13 can be SiN, but is not limited thereto. The materials of the insulating medium layer 12 and the etching stop layer 13 can also be selected according to actual circumstances.

[0110] 23 , a first via hole 21 and a second via hole 22 are formed spaced apart, with the orthogonal projection of the first via hole 21 onto the substrate 10 being located within the orthogonal projection of the first electrode layer 110 onto the substrate 10 and not overlapping with the orthogonal projections of the second electrode layer 112 and the strontium titanate dielectric layer 1110 onto the substrate 10. The first via hole 21 passes through the insulating medium layer 12, the etching stop layer 13, and the interlayer medium layer 15 in this order, exposing a portion of the first electrode layer 110. The orthogonal projection of the second via hole 22 onto the substrate 10 being located within the orthogonal projection of the through hole 150 onto the substrate 10, with the second via hole 22 passing through the insulating medium layer 12 and the etching stop layer 13 in this order, exposing a portion of the second electrode layer 112.

[0111] 22, a photoresist layer may be first formed on the side of the etching stop layer 13 away from the insulating medium layer 12, and then the photoresist layer may be exposed and developed to form a third photoresist mask layer 23. Next, as shown in FIG. 23, etching is performed using the third photoresist mask layer 23 to form the first via hole 21 and the second via hole 22, and finally the third photoresist mask layer 23 is removed.

[0112] 24, a measurement electrode material film 14 is formed to cover the surface of the etching stop layer 13 away from the insulating medium layer 12 and to fill the first via hole 21 and the second via hole 22. For example, the material of the measurement electrode material film 14 may be TiN, but is not limited to this, and other conductive materials may also be used.

[0113] 5, the measurement electrode material film 14 is patterned to form a first measurement electrode 14a and a second measurement electrode 14b. As shown in FIG. 5, the first measurement electrode 14a and the second measurement electrode 14b each include a via hole conductive portion 140 and a measurement conductive portion 141. The measurement conductive portions 141 of the first measurement electrode 14a and the second measurement electrode 14b are formed apart from each other and are both formed on the side of the etching stop layer 13 away from the substrate 10. The measurement conductive portion 141 of the first measurement electrode 14a is the measurement electrode material film 14 filled in the first via hole 21, and the measurement conductive portion 141 of the second measurement electrode 14b is the measurement electrode material film 14 filled in the second via hole 22.

[0114] For example, as shown in Figure 25, first, a photoresist layer is formed on the side of the measurement electrode material film 14 away from the etching stop layer 13, then the photoresist layer is exposed and developed to form a fourth photoresist mask layer 24, and then the fourth photoresist mask layer 24 is used to etch the measurement electrode material film 14 on the surface of the etching stop layer 13 to form the measurement conductive portions 141 of the first measurement electrode 14a and the second measurement electrode 14b, and finally, as shown in Figure 25, the fourth photoresist mask layer 24 can be removed.

[0115] After forming the first measurement electrode 14a and the second measurement electrode 14b, an external measurement device can be used to connect to the first measurement electrode 14a and the second measurement electrode 14b and measure the performance of the capacitor.

[0116] It should be understood that after testing the performance of the capacitor using the first measurement electrode 14a and the second measurement electrode 14b, the first measurement electrode 14a and the second measurement electrode 14b may be cut off when cutting the die, or may be retained on the substrate 10, depending on the particular situation.

[0117] Additionally, terms such as "first," "second," and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or quantity of the indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "plurality" means two or more unless otherwise expressly limited.

[0118] In the description herein, the use of terms such as "some embodiments," "exemplary," and the like means that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present application. In the present specification, schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the described particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine different embodiments or examples and features of different embodiments or examples described herein, as long as they are not mutually inconsistent.

[0119] Although the embodiments of the present application have been shown and described above, the above embodiments are illustrative and should not be construed as limitations of the present application. Those skilled in the art can change, modify, substitute and alter the above embodiments within the scope of the present application, and therefore, it is understood that all changes or modifications made in accordance with the claims and descriptions of the present application should be included within the patent scope of the present application. [Brief explanation of the drawings]

[0120] [Figure 1] 1 shows structural schematic diagrams of memories corresponding to various solutions described in Example 1 of the present application; [Figure 2] 1 shows structural schematic diagrams of memories corresponding to various solutions described in Example 1 of the present application; [Figure 3] 1 shows structural schematic diagrams of memories corresponding to various solutions described in Example 1 of the present application; [Figure 4] 1 shows structural schematic diagrams of memories corresponding to various solutions described in Example 1 of the present application; [Figure 5] 1 shows structural schematic diagrams of memories corresponding to various solutions described in Example 1 of the present application; [Figure 6] 1 shows a schematic diagram of the three-dimensional structure of the memory described in Example 1 of the present application. [Figure 7] 1 shows a schematic diagram of the structure of a capacitor according to one solution described in Example 1 of the present application. [Figure 8] 1 shows the corresponding changes when the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer is designed with different gradients in Example 1 of the present application. [Figure 9] 1 shows the corresponding changes when the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer is designed with different gradients in Example 1 of the present application. [Figure 10] 1 shows the corresponding changes when the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer is designed with different gradients in Example 1 of the present application. [Figure 11] 1 shows a schematic structural diagram of a capacitor according to another solution described in Example 1 of the present application. [Figure 12] 1 shows structural schematic diagrams of capacitors corresponding to various solutions in Example 2 of the present application. [Figure 13] 1 shows structural schematic diagrams of capacitors corresponding to various solutions in Example 2 of the present application. [Figure 14] 1 shows structural schematic diagrams of capacitors corresponding to various solutions in Example 2 of the present application. [Figure 15] 1 shows structural schematic diagrams corresponding to each step of the manufacturing method of the memory provided in Example 3 of the present application; [Figure 16] 1 shows structural schematic diagrams corresponding to each step of the manufacturing method of the memory provided in Example 3 of the present application; [Figure 17] 1 shows structural schematic diagrams corresponding to each step of the manufacturing method of the memory provided in Example 3 of the present application; [Figure 18] 1 shows structural schematic diagrams corresponding to each step of the manufacturing method of the memory provided in Example 3 of the present application; [Figure 19] 1 shows structural schematic diagrams corresponding to each step of the manufacturing method of the memory provided in Example 3 of the present application; [Figure 20] 1 shows structural schematic diagrams corresponding to each step of the manufacturing method of the memory provided in Example 3 of the present application; [Figure 21] 1 shows structural schematic diagrams corresponding to each step of the manufacturing method of the memory provided in Example 3 of the present application; [Figure 22] 1 shows structural schematic diagrams corresponding to each step of the manufacturing method of the memory provided in Example 3 of the present application; [Figure 23] 1 shows structural schematic diagrams corresponding to each step of the manufacturing method of the memory provided in Example 3 of the present application; [Figure 24] 1 shows structural schematic diagrams corresponding to each step of the manufacturing method of the memory provided in Example 3 of the present application; [Figure 25] 1 shows structural schematic diagrams corresponding to each step of the manufacturing method of the memory provided in Example 3 of the present application;

Claims

1. a first electrode layer; a second electrode layer; and a strontium titanate dielectric layer formed between the first electrode layer and the second electrode layer; the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer gradually decreases in a direction from the center of the strontium titanate dielectric layer toward opposite sides of the strontium titanate dielectric layer; One of the opposing sides of the strontium titanate dielectric layer is close to the first electrode layer, and the other side is close to the second electrode layer. A capacitor characterized by:

2. The strontium titanate dielectric layer has a single layer structure.

2. The capacitor according to claim 1 .

3. In the strontium titanate dielectric layer, a surface close to the first electrode layer is defined as a first boundary surface, a surface close to the second electrode layer is defined as a second boundary surface, and the Sr content at the first boundary surface and the second boundary surface is 0.

3. The capacitor according to claim 2.

4. the strontium titanate dielectric layer has a multilayer structure, and the strontium titanate dielectric layer includes N strontium titanate film layers stacked in order, where N is a positive integer of 3 or more; The ratio of Sr / (Sr+Ti) within the strontium titanate dielectric layer decreases from layer to layer in a direction from the center of the strontium titanate dielectric layer toward opposite sides of the strontium titanate dielectric layer.

2. The capacitor according to claim 1 .

5. The ratio of Sr / (Sr+Ti) at each location in the strontium titanate film layer is equal 5. The capacitor according to claim 4.

6. In a direction from the center of the strontium titanate dielectric layer toward both opposing sides of the strontium titanate dielectric layer, the ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer gradually decreases according to a linear relationship.

2. The capacitor according to claim 1 .

7. Specifically, the linear relationship is [Equation 1] and where C is the ratio of Sr / (Sr+Ti) at the center of the strontium titanate dielectric layer, D is the distance from the center of the strontium titanate dielectric layer in the strontium titanate dielectric layer, and H is the thickness of the strontium titanate dielectric layer, and 0≦D≦H / 2.

7. The capacitor according to claim 6.

8. The rate of decrease of the Sr / (Sr+Ti) ratio in the strontium titanate dielectric layer gradually increases in a direction from the center of the strontium titanate dielectric layer toward both opposing sides of the strontium titanate dielectric layer.

2. The capacitor according to claim 1 .

9. The ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer satisfies the following relationship: [Equation 2] where C is the ratio of Sr / (Sr+Ti) at the center of the strontium titanate dielectric layer, D is the distance from the center of the strontium titanate dielectric layer, and H is the thickness of the strontium titanate dielectric layer, and 0≦D≦H / 2.

9. The capacitor according to claim 8.

10. The rate of decrease of the Sr / (Sr+Ti) ratio in the strontium titanate dielectric layer gradually decreases in a direction from the center of the strontium titanate dielectric layer toward both opposing sides of the strontium titanate dielectric layer.

2. The capacitor according to claim 1 .

11. The ratio of Sr / (Sr+Ti) at the center of the strontium titanate dielectric layer is greater than 50%.

2. The capacitor according to claim 1 .

12. The thickness of the strontium titanate dielectric layer ranges from 5 nm to 7 nm, and the Sr / (Sr+Ti) ratio at the center of the strontium titanate dielectric layer ranges from 60% to 65%.

12. The capacitor of claim 11.

13. The capacitor is a first titanium oxide dielectric layer formed between the first electrode layer and the strontium titanate dielectric layer; and a second titanium oxide dielectric layer formed between the second electrode layer and the strontium titanate dielectric layer.

2. The capacitor according to claim 1 .

14. The capacitor is a first aluminum titanate dielectric layer formed between the first electrode layer and the strontium titanate dielectric layer; and a second aluminum titanate dielectric layer formed between the second electrode layer and the strontium titanate dielectric layer.

2. The capacitor according to claim 1 .

15. The first electrode layer and the second electrode layer include a ruthenium element film layer, and the ruthenium element film layer is a metal ruthenium film layer or a ruthenium oxide film layer.

15. The capacitor according to claim 1, wherein the first and second electrodes are electrically connected to each other.

16. The first electrode layer and the second electrode layer further include a titanium nitride film layer, and the titanium nitride film layer is formed on the side of the ruthenium element film layer away from the strontium titanate dielectric layer.

16. The capacitor of claim 15.

17. 17. A capacitor according to claim 1, wherein the capacitor is formed on the substrate. A memory characterized by:

18. an orthogonal projection of the second electrode layer onto the first electrode layer overlaps with an orthogonal projection of the strontium titanate dielectric layer onto the first electrode layer, and orthogonal projections of the second electrode layer and the strontium titanate dielectric layer onto the substrate are located in a central region of an orthogonal projection of the first electrode layer onto the substrate; The memory includes: an insulating medium layer covering an edge region of the first electrode layer and the second electrode layer; an etch stop layer formed on a side of the insulating medium layer away from the substrate; further comprising a first measurement electrode and a second measurement electrode spaced apart; the first measurement electrode and the second measurement electrode each include a via hole conductive portion and a measurement conductive portion connected to each other; the first measurement electrode and the second measurement electrode have measurement conductive portions formed on a side of the etching stop layer away from the substrate; an orthogonal projection of a via hole conductive portion of the first measurement electrode onto the substrate is located within an orthogonal projection of an edge region of the first electrode layer onto the substrate, and the via hole conductive portion of the first measurement electrode passes through the etching stop layer and the insulating medium layer in order to contact the edge region of the first electrode layer; An orthogonal projection of a via hole conductive portion of the second measurement electrode onto the substrate is located within an orthogonal projection of the second electrode layer onto the substrate, and the via hole conductive portion of the second measurement electrode passes through the etching stop layer and the insulating medium layer in order to contact the second electrode layer.

18. The memory of claim 17.

19. The memory further includes an interlayer medium layer, the interlayer medium layer being formed between the first electrode layer and the insulating medium layer, the interlayer medium layer having a through hole for exposing a portion of the first electrode layer; the strontium titanate dielectric layer has a central portion and an edge portion surrounding the central portion, the central portion being formed within the through hole and in contact with the first electrode layer, and the edge portion being disposed on a surface of the interlayer medium layer away from the first electrode layer; a via hole conductive portion of the first measurement electrode penetrates the etching stop layer and the insulating medium layer, and also penetrates the interlayer medium layer, and contacts an edge region of the first electrode layer; The orthogonal projection of the via hole conductive portion of the second measurement electrode onto the substrate is located within the orthogonal projection of the through hole onto the substrate.

20. The memory of claim 18.

20. Both the first measurement electrode and the second measurement electrode are provided with a plurality of via-hole conductive portions at equal intervals around the axis of the through-hole.

20. The memory of claim 19.

21. the substrate includes a semiconductor base and an insulating isolation layer, the insulating isolation layer being formed between the first electrode layer and the semiconductor base; 18. The memory of claim 17.

22. providing a substrate; forming a first electrode layer on the substrate; forming a strontium titanate dielectric layer on a side of the first electrode layer away from the substrate, wherein a ratio of Sr / (Sr+Ti) in the strontium titanate dielectric layer gradually decreases in a direction from a center of the strontium titanate dielectric layer toward opposite sides of the strontium titanate dielectric layer, one of the opposite sides of the strontium titanate dielectric layer being close to the first electrode layer and the other side being far from the first electrode layer; forming a second electrode layer on a side of the strontium titanate dielectric layer remote from the first electrode layer to form a capacitor. A method for manufacturing a memory comprising the steps of:

23. forming a strontium titanate dielectric layer on a side of the first electrode layer away from the substrate, depositing a strontium titanate material on a side of the first electrode layer away from the substrate using a single atomic layer deposition process to form the strontium titanate dielectric layer; In this case, by adjusting the flow rate of the Sr precursor and / or the Ti precursor in the single atomic layer deposition process, the Sr / (Sr+Ti) ratio in the strontium titanate material first gradually increases and then gradually decreases according to a set rule.

23. The method of manufacturing a memory according to claim 22.

24. forming a strontium titanate dielectric layer on a side of the first electrode layer away from the substrate, forming N sequential strontium titanate film layers on a side of the first electrode layer away from the substrate using an atomic layer deposition process N times, where N is a positive integer greater than or equal to 3, to form the strontium titanate dielectric layer; 23. The method of manufacturing a memory according to claim 22.

25. Prior to the step of forming a strontium titanate dielectric layer on the side of the first electrode layer away from the substrate, the manufacturing method further includes the step of forming a first titanium oxide dielectric layer on the side of the first electrode layer away from the substrate; Prior to the step of forming a second electrode layer on the side of the strontium titanate dielectric layer remote from the first electrode layer, the method further includes the step of forming a second titanium oxide dielectric layer on the side of the strontium titanate dielectric layer remote from the first electrode layer.

23. The method of manufacturing a memory according to claim 22.

26. Prior to the step of forming a strontium titanate dielectric layer on the side of the first electrode layer away from the substrate, the manufacturing method further includes the step of forming a first aluminum titanate dielectric layer on the side of the first electrode layer away from the substrate; Prior to the step of forming a second electrode layer on the side of the strontium titanate dielectric layer remote from the first electrode layer, the method further includes the step of forming a second aluminum titanate dielectric layer on the side of the strontium titanate dielectric layer remote from the first electrode layer.

23. The method of manufacturing a memory according to claim 22.

27. forming a first aluminum titanate dielectric layer on the side of the first electrode layer away from the substrate includes forming a first titanium oxide dielectric layer on the side of the first electrode layer away from the substrate, and then doping aluminum element into the first titanium oxide dielectric layer to form the first aluminum titanate dielectric layer; The step of forming a second aluminum titanate dielectric layer on the side of the strontium titanate dielectric layer away from the first electrode layer includes the steps of forming a second titanium oxide dielectric layer on the side of the strontium titanate dielectric layer away from the first electrode layer, and then doping aluminum element into the second titanium oxide dielectric layer to form the second aluminum titanate dielectric layer.

27. The method of manufacturing a memory according to claim 26.

28. Prior to the step of forming a strontium titanate dielectric layer on the side of the first electrode layer away from the substrate, the method further comprises: forming an interlayer medium material film on a side of the first electrode layer away from the substrate; forming a through hole exposing a central region of the first electrode layer on the interlayer medium material film by a patterning process to form an interlayer medium layer; At least a portion of the strontium titanate dielectric layer is located within the through-hole and contacts the first electrode layer.

23. The method of manufacturing a memory according to claim 22.

29. sequentially forming a strontium titanate dielectric layer and a second electrode layer on a side of the first electrode layer away from the substrate, After forming the interlayer medium layer, sequentially forming a strontium titanate dielectric material film and a second electrode material film located in the through hole and covering the interlayer medium layer; and removing a portion of the strontium titanate dielectric material film and the second electrode material film that covers the interlayer medium layer to form the strontium titanate dielectric layer and the second electrode layer.

29. The method of claim 28, wherein the memory is made of a silicon dioxide gas.

30. After sequentially forming a strontium titanate dielectric layer and a second electrode layer on the side of the first electrode layer away from the substrate, the manufacturing method further comprises: sequentially forming an insulating medium layer and an etch stop layer on sides of the interlayer medium layer and the second electrode layer away from the substrate; forming a first via hole and a second via hole spaced apart, the orthogonal projection of the first via hole onto the substrate being located within the orthogonal projection of an edge region of the first electrode layer onto the substrate and not overlapping with the orthogonal projections of the second electrode layer and the strontium titanate dielectric layer onto the substrate, the first via hole sequentially penetrating the insulating medium layer, the etch stop layer, and the interlayer medium layer and exposing a portion of the first electrode layer, the orthogonal projection of the second via hole onto the substrate being located within the orthogonal projection of the through hole onto the substrate, the second via hole sequentially penetrating the insulating medium layer and the etch stop layer and exposing a portion of the second electrode layer; forming a measurement electrode material film, the measurement electrode material film covering a surface of the etching stop layer away from the insulating medium layer and filling the first via hole and the second via hole; and patterning the measurement electrode material film to form the first measurement electrode and the second measurement electrode, the first measurement electrode and the second measurement electrode each including a via hole conductive portion and a measurement conductive portion, the measurement conductive portions of the first measurement electrode and the second measurement electrode being formed apart from each other and both being formed on the etching stop layer on a side away from the substrate, the measurement conductive portion of the first measurement electrode being the measurement electrode material film filled in the first via hole, and the measurement conductive portion of the second measurement electrode being the measurement electrode material film filled in the second via hole.

30. The method of claim 29, wherein the memory is made of a silicon dioxide film.

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