DC offset generation in a flux-variable transmon with a persistent current loop.

Abstract

The quantum circuit device includes a qubit chip including a plurality of qubits and a plurality of variable flux couplers. The plurality of fixed frequency qubits are arranged in a lattice structure, and each pair of the plurality of fixed frequency qubits is coupled to one variable flux coupler. An interconnect layer is coupled to the qubit chip, and the interconnect layer includes a loop composed of a superconducting material inductively coupled to the variable flux couplers. A flux bias line is composed of a superconducting material different from the superconducting material of the loop, and the flux bias line is inductively coupled to both the loop and the variable flux couplers (Figure 7).

Description

[Technical Field]

[0001] The present disclosure relates generally to superconducting quantum computing, and more particularly to generating a constant flux offset in a tunable transmon qubit with a persistent current loop or with a continuous flux bias line coupling multiple qubits. [Background technology]

[0002] A flux-tunable qubit (also known as a "flux-tunable bus") uses a DC current, which generates a magnetic flux Φ_0, to tune the frequency of an object, such as a flux-tunable transmon bus. The DC current flows through a superconducting wire adjacent to the flux-tunable transmon to generate an evanescent magnetic field that generates the magnetic flux. However, the DC current can adversely affect the operation of the cryostat by generating unwanted heating. In a qubit-under-bus (BBQ) architecture, the DC current is adjusted until minimal ZZ exchange occurs between fixed-frequency qubits (e.g., Q0 and Q1) coupled between the flux-tunable transmons. The DC current in the flux-tunable transmon is adjusted to approach a minimum value corresponding to the magnetic flux Φ_DC. The bias current range can be approximately 100 μA to 1 mA, depending on device parameters. Due to device fabrication variability, each flux-tunable qubit requires its own unique magnetic field. These DC currents cause steady-state heating, ground loops, and on-chip crosstalk. Summary of the Invention

[0003] According to one embodiment, a quantum circuit device includes a qubit chip including a plurality of qubits and a plurality of flux-variable transmon couplers. The plurality of fixed frequency transmon qubits are arranged in a lattice structure, with each pair of the plurality of fixed frequency transmon qubits coupled to one flux-variable transmon coupler. An interconnect layer is coupled to the qubit chip, the interconnect layer including a loop made of a superconducting material inductively coupled to the flux-variable transmon couplers. A flux bias line is made of a superconducting material different from the superconducting material of the loop, and the flux bias line is inductively coupled to both the loop and the flux-variable transmons. This structure provides the advantage of reducing the current through the cryostat and reducing or eliminating the adverse effects of increased heat on the superconducting components.

[0004] In one embodiment, the wiring layer further includes a first flux bias line constructed from a first superconducting material, and a DC current and at least one current pulse (i pulse ) through the first variable flux transmon. A first loop is formed by a second superconducting material, is inductively coupled to the first flux bias line, and is inductively coupled to the first variable flux transmon. A magnetic field generated from the first flux bias line induces a sustaining current in the first loop formed by the second superconducting material, and generates a static flux offset (Φ offset ) This structure provides an offset magnetic flux to reduce the sustaining current in the superconducting loop and keep the temperature within an operable range.

[0005] In one embodiment that may be combined with the preceding embodiments, the signal generating module configured to provide the DC current to induce the sustained current in the first loop is configured to adjust the DC current to reduce always-on entanglement (ZZ) between a pair of fixed frequency qubits coupled to the first flux-tunable transmon to a substantial minimum. Minimizing entanglement ZZ between fixed frequency qubits of a flux-tunable transmon is advantageous in providing a simpler and more efficient construction.

[0006] In one embodiment that may be combined with the preceding embodiment, the signal generating module generates the at least one current pulse (i pulse ), and each value of the current pulse is offset Based on the value of . The current pulses can provide fine control of the current entering the cryostat through the flux wires.

[0007] In one embodiment that may be combined with the preceding embodiment, the first superconducting material comprises niobium and the second superconducting material comprises aluminum. Niobium has a higher T C whereas aluminum has a lower T C These two metals are sometimes used in their respective components. C The lower the value, the more the sustained current can be reset at low temperatures.

[0008] In one embodiment that can be combined with the preceding embodiments, the flux bias line includes one or more gradiometric loops, the gradiometric loops having a structure that reduces crosstalk problems with other loops on the interposer and allows the flux-tunable transmons to operate more efficiently.

[0009] In one embodiment that may be combined with the preceding embodiments, the first flux-variable transmon and the fixed frequency qubit are arranged in a lattice structure to form a multi-qubit device, which may be more efficient, especially when there are additional dimensional components such as multiple stacks.

[0010] In one embodiment, the magnetic flux bias line includes a serpentine bias line that is continuous with the plurality of magnetic flux variable couplers and configured to bias the plurality of magnetic flux variable couplers substantially simultaneously. The use of the serpentine bias line may reduce crosstalk.

[0011] In one embodiment that can be combined with the preceding embodiments, each of the flux-variable transmons is capacitively coupled to two fixed frequency qubits, and each fixed frequency qubit is capacitively coupled to two flux-variable transmons. This alternative structure offers more flexibility in construction and operation.

[0012] In one embodiment that may be combined with the preceding embodiments, global magnetic flux lines are configured to generate a magnetic field in the persistent current loop in response to the DC current input and are located in a wiring layer adjacent to the persistent current loop. Induction from the global magnetic flux lines reduces inductive coupling in the flux-variable transmon. The global magnetic flux lines reduce or eliminate parasitic effects resulting from locating loops SC1 and SC2 on the same chip.

[0013] In one embodiment that may be combined with the preceding embodiment, the second superconducting material is shorted between two sections of a continuous flux bias line, where a loop is formed on each flux bias line. The second superconducting material has a lower critical temperature (T C ) and a persistent current (i pThe sustained current loop is configured to generate a calibrated flux offset (Φ) based on temperature variations applied to the superconducting material in the flux-variable transmon. offset ) by using a second material to short out the first material, providing a simpler way to trap current.

[0014] According to one embodiment, a quantum circuit device includes a qubit chip having a plurality of qubits and an interconnection layer coupled to the qubit chip. The qubit chip includes a plurality of flux-variable elements, each including a respective flux-variable superconducting quantum interference (SQUID) loop, each coupled between a respective pair of fixed-frequency qubits. The interconnection layer includes a continuous flux bias line made of a first superconducting material disposed adjacent to the flux-variable elements and configured to output a DC current to provide an offset to the flux-variable elements. A plurality of non-continuous flux bias lines are disposed in the flux-variable elements, each configured to output a flux pulse and independently offset a current due to mutual inductance with the flux-variable elements. This structure provides the advantage of reducing the current flow through the cryostat and reducing or eliminating adverse effects of increased heat on superconducting components.

[0015] In one embodiment, the continuous flux bias line is disposed on a first surface of the magnetic flux variable element, and the discontinuously arranged flux bias lines are adjacent to a second surface of the magnetic flux variable element.

[0016] In one embodiment that can be combined with the preceding embodiments, the plurality of magnetic flux bias lines are gradiometric magnetic flux coils. This structure can reduce / eliminate crosstalk due to mutual inductance between the common DC line and the pulse line.

[0017] In one embodiment, the flux coupler on the qubit chip comprises two spatially separated pickup coils separately coupled to the continuous bias line and the independent flux bias line, respectively.

[0018] According to one embodiment, a method for generating a DC offset in a flux variable element includes: C ), a DC current is input to a flux bias line adjacent to the flux variable element, inductively coupling the flux bias line to both the flux variable element and a loop of a first superconducting material surrounding the flux variable element. The flux bias line is made of a second superconducting material different from the first superconducting material. The first superconducting material is inductively coupled to a T of the first superconducting material to trap a sustained current within the superconducting loop. C Continue to apply DC current to the flux bias wires while cooling them down. This method provides a quantum circuit with reduced current through the cryostat, reducing or eliminating the adverse effects of increased heat on the superconducting components.

[0019] In one embodiment, the input of the DC current is continued until the sustained current produces a minimum ZZ exchange rate between the first fixed frequency qubit and the second fixed frequency qubit, which minimizes entanglement between the fixed frequency qubits and provides a simpler and more efficient construction. [Brief explanation of the drawings]

[0020] The drawings illustrate exemplary embodiments. Not all embodiments are shown. Other embodiments may additionally or alternatively be used. Details that may be obvious or unnecessary may be omitted to save space or for a more effective illustration. Some embodiments may be practiced using additional components or steps, or without all of the components or steps shown, or combinations thereof. The same numerals appearing in different drawings refer to the same or similar components or steps.

[0021] [Figure 1A] 10A-10C are graphs illustrating an example of a flux-variable transmon and range calculation, respectively, consistent with an illustrative embodiment; [Figure 1B] 10A-10C are graphs illustrating an example of a flux-variable transmon and range calculation, respectively, consistent with an illustrative embodiment;

[0022] [Figure 2] FIG. 10 illustrates a structure for generating a DC offset using a sustained current loop for magnetic flux offset, consistent with an example embodiment.

[0023] [Figure 3] FIG. 1 illustrates a structure for generating a sustaining current with a continuous magnetic flux bias line, consistent with an example embodiment.

[0024] [Figure 4] FIG. 10 illustrates a structure for generating a sustained current trapped in a shorted loop due to a magnetic flux offset, consistent with an example embodiment.

[0025] [Figure 5] FIG. 10 illustrates a structure including a continuous flux bias line adjacent to a flux-variable transmon, consistent with an example embodiment.

[0026] [Figure 6] FIG. 10 illustrates a structure including a continuous flux bias line with a gradiometric flux coupler to a flux-tunable transmon, consistent with an example embodiment.

[0027] [Figure 7] FIG. 10 illustrates a structure including a metal with a TC lower than the TC of the superconductor of the flux bias line, consistent with an example embodiment.

[0028] [Figure 8] FIG. 10 illustrates a structure including a lower TC short, consistent with an example embodiment.

[0029] [Figure 9] FIG. 10 illustrates another structure including a lower TC short, consistent with an example embodiment.

[0030] [Figure 10] FIG. 10 illustrates yet another structure including a lower TC short illustrating the path of current flow, consistent with an illustrative embodiment.

[0031] [Figure 11] FIG. 10 illustrates a structure using mutual inductance, consistent with an example embodiment.

[0032] [Figure 12] FIG. 10 illustrates a structure having magnetic flux lines inductively coupled to a loop capable of carrying a sustained current, consistent with an illustrative embodiment.

[0033] [Figure 13] FIG. 1 illustrates a structure including multiple qubits and multiple flux-variable buses, consistent with an example embodiment.

[0034] [Figure 14] 10 is a flowchart illustrating a method for generating a DC offset in a flux transmon, consistent with respective illustrative embodiments.

[0035] [Figure 15] A functional block diagram representation of a computer hardware platform that can be used to implement a specially configured computing device capable of generating a DC offset in a flux-tunable plasmon is provided. DETAILED DESCRIPTION OF THE INVENTION

[0036] overview

[0037] In the following detailed description, numerous specific details are set forth, by way of example, to provide a thorough understanding of the relevant teachings. However, it should be understood that the present teachings may be practiced without such details. In other instances, well-known methods, procedures, components, and / or circuits have been described at a relatively high level without detailed description to avoid unnecessarily obscuring aspects of the present teachings. It should be understood that the present disclosure is not limited to the depictions in the drawings, and that there may be fewer or more elements than shown and described.

[0038] In describing the present technology, it may be helpful to explain various notable terms. In one aspect, spatially related terms such as “front,” “back,” “top,” “bottom,” “below,” “lower,” “upper,” “above,” “side,” “left,” and “right” are used with reference to the orientation of the figures being described. Because components of embodiments of the present disclosure may be positioned in many different orientations, directional terms are used for purposes of explanation and are in no way limiting. Thus, it will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is rotated, elements described as “below” or “beneath” other elements or features will be oriented “above” the other elements or features. Thus, for example, the term “below” can encompass both an orientation of being above and an orientation of being below. The device may be in other orientations (rotated 90 degrees, viewed in other directions, or referenced), and the spatially relative descriptors used herein should be interpreted accordingly.

[0039] As used herein, the terms "coupled" and / or "electrically coupled" are not intended to imply that elements must be directly coupled together; intervening elements may be provided between "coupled" or "electrically coupled" elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. The term "electrically connected" refers to a low-resistance electrical connection between elements that are electrically connected together. As used herein, the term "mechanical tolerance" relates to electrical properties that are not significantly affected by mechanical alignment between the components in question.

[0040] As used herein, certain terms are used to indicate what are considered idealized behavior, such as "lossless," "superconductor," "superconducting," and "absolute zero," which are intended to cover functionality that may not be exactly ideal, but is within acceptable limits for a given application. For example, some level of loss or tolerance may be acceptable, thereby allowing the resulting materials and structures to still be referred to in these "idealized" terms.

[0041] In this specification, terms such as first, second, and third may be used to describe various elements, but these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the exemplary embodiments. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0042] Example embodiments are described herein with reference to schematic illustrations of idealized or simplified embodiments (and intermediate structures). As such, variations in the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Accordingly, the regions illustrated in the figures are schematic in nature and their shapes are not necessarily indicative of the actual shape of, or limiting the scope of, a region of a device.

[0043] It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the spirit and scope of the invention as defined by the appended claims. The description of the embodiments is not intended to be limiting. In particular, elements of the embodiments described below may be combined with elements of different embodiments.

[0044] Superconducting quantum computing is the realization of quantum computers with superconducting electronic circuits. Quantum computing studies the application of quantum phenomena for information processing and communication. Various models of quantum computing exist, the most popular of which include the concepts of qubits and quantum gates. A qubit is a generalization of a bit that has two possible states, but can also be a quantum superposition of both states. A quantum gate is a generalization of a logic gate, but a quantum gate describes the transformation that one or more qubits undergo from their initial state after a gate is applied to them.

[0045] To realize the potential of quantum computers, it is important to be able to incorporate many more superconducting qubits. However, it is difficult to realize quantum processors with desirable qubit characteristics, such as frequency and fidelity, on monolithic qubit chips. Large-scale quantum processors may become more feasible if modular architectures that interconnect devices comprised of smaller modules are adopted. However, such modular architectures may involve connections between qubits on separate physical chips and / or support circuitry for the qubit chips. Because various quantum phenomena, such as superposition and entanglement, have no analogue in classical computing, assembling electronic devices capable of operating in cryogenic environments can involve special structures, techniques, and materials.

[0046] As used herein, "critical temperature" (T C The term "ZZ" is defined as a superconductor that has a characteristic temperature at which the resistance drops abruptly to zero. Furthermore, the term "ZZ" is understood herein to refer to the entanglement rate between two bits.

[0047] In certain aspects, the teachings herein are based on the inventors' insight that directly applying conventional integrated circuit techniques for interacting with computing elements to superconducting quantum circuits may not be effective due to the unique challenges that quantum circuits present that are not present in classical computing architectures. Indeed, many of the systems and architectures discussed herein operate in cryogenic environments and may involve superconductivity. Accordingly, embodiments of the present disclosure are further based on the recognition that issues unique to quantum circuits are taken into consideration when evaluating the applicability of conventional integrated circuit techniques to building superconducting quantum circuits, particularly when selecting the methods and architectures used to connect the components of a quantum computer. The techniques described herein can be implemented in many ways. Exemplary implementations are provided below with reference to the following figures.

[0048] According to some embodiments of the present disclosure, the current injected into the cryostat can be minimized / reduced through the use of sustaining currents, overcoming the problem of heat transfer to the cryostat. Because the individual flux offsets of each transmon bus can vary such that the global flux offset is unusable, the bulk current can be supplemented with sustaining currents to fine-tune the flux offset of each individual transmon bus. A shared flux bias line is provided for operating multi-qubit devices, and in some embodiments, a gradiometric flux coupler is present. Embodiments of the present disclosure reduce the on-chip current per flux line, resulting in reduced power dissipation per flux line. The effects of crosstalk between adjacent couplers are reduced by reduced power usage, as well as reduced heat to alleviate the problem of currents potentially heating the cryostat. Exemplary Architecture

[0049] 1A and 1B are diagrams illustrating a flux-variable transmon 100A and a graph 100B showing an example of a range calculation, respectively, consistent with an illustrative embodiment. The present disclosure presents numerous ways in which a DC offset may be generated to limit the current provided to the cryostat, which may adversely affect superconductivity. A flux-variable transmon 110 is coupled to a first fixed frequency qubit 120 and a second fixed frequency qubit 130. A DC current (iDC) 140 passes through a line representative of a cryogenic refrigerator line passing through an inductor 145, causing the magnetic field to vary the magnetic flux, corresponding to the x-axis shown in FIG. 1B. A minimum value ZZ 150 corresponds to the minimum amount of entanglement between the two qubits 120, 130 shown in FIG. 1A. As a result, the current entering the cryostat is reduced, preventing heat from adversely affecting superconducting operation. Further features of the present disclosure are disclosed herein. Exemplary Embodiments

[0050] 2 shows a structure for generating a DC offset using a persistent current loop for flux offset, consistent with an example embodiment. A DC current 203 (iDC) is supplied through a flux bias line 205 comprised of superconductor SC1. A loop 210 comprised of superconductor SC2 generates a DC offset for an applied magnetic flux Φ P The opposing current i P Generates Φ P The value of is: Φ P =i DC M1, where M1 is the inductance between the flux bias line 205 and the loop 210. If there is a magnetic flux during the transition from the normal state to the SC state, the current i P becomes persistent. The persistent current in the loop i P generates a magnetic flux passing through the loop of the flux-variable transmon, resulting in a flux offset: Φ offset =i p M3, where M3 is the inductance between the flux transmon 220 and the loop 210. Φ offset is calibrated by thermally cycling the device and repeating the trapping experiment until the Z between the fixed-frequency qubits is close to a minimum. pulse is fed through the flux bias line to generate the 2Q gates. The pulse is Φ offset occurs only after the device has been calibrated and cooled. It should be understood that although the persistent current loop is shown in Figure 2 as being in wiring layer 201 above qubit chip 250, it is not limited to an interposer. For example, other types of structures may be used as long as there is mutual inductance to the superconducting quantum interference (SQUID) loop of qubit chip 250.

[0051] FIG. 3 illustrates a structure 300 for generating a persistent current with a continuous magnetic flux bias line, consistent with an exemplary embodiment. While FIG. 3 focuses on transmons for illustrative purposes, it should be understood that the present disclosure is not limited to transmon couplers. Other types of flux-tunable elements may be provided. For example, superconducting qubits tunable by magnetic flux loops (or SQUIDs) are potential applications for the flux-tunable couplers disclosed herein. Flux-tunable transmon qubits, phasemons, and even Xmons may all benefit from application of the apparatus and methods disclosed herein. When the qubit has a SQUID loop, an adjustable DC offset may be provided to bias the qubit at an ideal frequency.

[0052] Loop 305 is inductively coupled to transmon 320 and loop 310 by current iDC input to global magnetic flux lines 330. Current pulses applied on magnetic flux lines inductively coupled to a sustained current loop can have unintended consequences and affect the signal integrity of the magnetic flux pulse. However, in the embodiment shown in FIG. 3, some adverse effects (e.g., crosstalk) associated with inductive coupling M1 are reduced, and a sustained current is generated using a global bias line 330 continuous with loop 310 with inductive coupling M4. Transmon 320 is inductively coupled to loop 310, as shown by coupling M3. It should be understood that a fixed-frequency qubit at the edge of a wiring layer (e.g., an interposer) may be coupled to a single flux-variable transmon. The transmon can operate without two coupled flux-variable transmons for a simpler construction.

[0053] FIG. 4 shows a structure 400 for generating a sustained current trapped in a shorted loop for a magnetic flux offset, consistent with an example embodiment. A DC current (iDC) is supplied through a flux bias line 405 composed of superconductor SC1. The flux bias line is shorted with a second superconducting material SC2 410, which has a lower critical temperature than SC1. The DC current is applied before the SC2 critical temperature and remains on even as the device cools. The DC current is applied before the SC2 critical temperature and remains on until the device cools, trapping the sustained current in a shorted loop with mutual inductance M1. Additional DC current and flux pulses are used to further bias a coupler with a second mutual inductance M2.

[0054] 5 shows a structure 500 including a continuous flux bias line adjacent to a flux variable transmon, consistent with an example embodiment. A long continuous flux bias line 530 is adjacent to a flux variable transmon 520 with a mutual inductance M1. A DC current (iDC) applied to the continuous line 530 provides an offset to all the flux variable transmons simultaneously. A flux pulse 540 and a small DC offset current 550 can be applied by a standard flux bias line with a mutual inductance M2.

[0055] 6 shows a structure 600 including a continuous flux bias line 630 with a gradiometric flux coupler 605 to a flux-variable transmon 620, consistent with an example embodiment. The gradiometric flux bias line reduces the effects of stray magnetic fields, which are substantially canceled by this gradiometric coil structure.

[0056] FIG. 7 illustrates the T of a superconductor in a flux bias line, consistent with an example embodiment. C Lower T C The magnetic flux bias line 730 is a low T C T higher than metal C It consists of a superconductor with a .DELTA. and is arranged in a loop around the qubit.

[0057] FIG. 8 illustrates a lower T C The structure 800 includes a short circuit. The magnetic flux lines 830 are located at the lower T C Short metal consisting of metal with higher T than 810 C It is made of SC metal with

[0058] FIG. 9 illustrates a lower T C The current flow in a structure 900 containing a short is shown. The structure is similar to that of FIG. 8, with high T flux lines 930 and lower T C There is a short circuit wire 910 made of SC material having a temperature above the low TC.

[0059] FIG. 10 illustrates a lower T C Shown is a structure 1000 containing a short. An electric current is applied to the magnetic flux lines 1030 at a temperature above the low TC of the short material 1010. The temperature is then reduced to a temperature below the TC of the material 1010 to cause the material 1010 to form a short. The external current is then removed. Because the magnetic flux in the small loop is constant, the current is persistent.

[0060] 11 shows a structure 1100 using mutual inductance, consistent with an example embodiment. There are high TC magnetic flux lines 1130 and low TC short circuit lines 1110. A current is applied when the temperature is higher than the low TC. In operation, after the current is applied, the temperature is reduced to below the TC of the short circuit material 1110. The external current is then removed from the magnetic flux lines 1130. Because the magnetic flux in the small loop 1140 is constant, the current in the small loop 1140 is persistent. An additional current, either DC or AC, is then applied, which also biases the qubit without changing the value of the persistent current.

[0061] 12 shows a structure 1200 having magnetic flux lines inductively coupled to a loop that may contain a persistent current, consistent with an exemplary embodiment. As shown, loop 1240 straddles interposer 1260 and qubit chip 1270. The use of aluminum wire allows the persistent current to be reset to a value that operates at a lower temperature. It should be understood that the present disclosure is not limited to the use of interposer 1260, and that other structures may be used, including, but not limited to, wiring layers.

[0062] FIG. 13 illustrates a structure including multiple qubits and multiple flux variable buses consistent with an exemplary embodiment. A single serpentine line 1330 simultaneously biases all of the flux variable buses. The illustrated unit cell 1350 has five qubits (e.g., Q1-Q5) and six flux variable buses (F1-F5), resulting in 1.2 flux lines per qubit. The serpentine flux lines 1330 may be long enough to flux bias many qubits with a single current. The serpentine flux lines 1330 may be gradiometric with respect to other flux lines, but not with respect to the qubits. The serpentine flux lines 1330 may have RF chokes (not shown) to reduce crosstalk. Exemplary Processing

[0063] Given the foregoing overview of an exemplary architecture, it may be helpful to now consider a high-level discussion of exemplary processing. To that end, Figure 14 is a flowchart illustrating a method for generating a DC offset in a flux transmon, consistent with respective exemplary embodiments.

[0064] 14 is illustrated as a collection of blocks in a logical order that represents a sequence of operations that can be performed in hardware, software, or a combination thereof. In each process, the order in which the operations are described is not intended to be construed as a limitation, and any number of the described blocks can be combined in any order and / or performed in parallel to perform the process.

[0065] In operation 1402, the critical temperature (T C ) is specified. For example, there may be two different superconducting materials used for each purpose. In one embodiment, the flux bias line includes a first superconducting material configured to receive a DC current that is inductively coupled to the flux variable element. The first superconducting material has a higher T than the second superconducting material. C and a current loop is formed on a wiring layer (not limited to an interposer) from the second superconducting material.

[0066] In operation 1404, when the temperature of the first superconducting material exceeds Tc, a DC current is input to the flux bias line (see, e.g., FIG. 3, line 330) to inductively couple the flux bias line to both loop 310 and flux-variable transmon 320.

[0067] In operation 1408, a current source (e.g., a DAC, etc.) generates a T of the first superconducting material so that the first superconducting material traps a sustained current (ip) in the superconducting loop. C When cooled to a lower temperature, the input of DC current to the flux bias line 330 continues.

[0068] In operation 1410, the temperature of the first superconducting material is increased to T C This operation can be repeated until the sustained current results in an applied DC current that produces a minimum ZZ exchange rate between the first fixed frequency qubit and the second fixed frequency qubit.

[0069] 14, this embodiment is not exhaustive of the scope of the present disclosure. For example, the method may include one or more operations in addition to or instead of other operations. Examples of computer platforms

[0070] 15 provides a functional block diagram illustration of a computer hardware platform 1500 that may be used to implement a particularly configured computing device capable of generating a DC offset in a flux-tunable plasmon according to an embodiment of the present disclosure. In particular, FIG. 15 illustrates a network or host computer platform 1500 such as may be used to implement a suitably configured server.

[0071] The computer platform 1500 may include a central processing unit (CPU) 1504, a hard disk drive (HDD) 1506, a random access memory (RAM) and / or a read-only memory (ROM) 1508, a keyboard 1510, a mouse 1512, a display 1514, and a communication interface 1516, which are connected to the system bus 1502.

[0072] In one embodiment, HDD 1506 has functionality that includes storing programs capable of executing various processes, such as quantum computing engine 1540, in the manner described herein. Quantum computing engine 1540 can have various modules configured to perform different functions, as described in the context of the figures described herein. For example, 1540 can include modules such as cryostat control module 1572, which controls the temperature of the cryostat and adjusts it accordingly as needed; signal generation module 1576, which can use DC and pulsed currents as courses and fine-tune the current entering the cryostat to ensure quantum operation of components; and machine learning module 1578. Signal generation module 1576 may be configured to provide a DC current to induce a sustained current in the first loop, where the signal generation module is configured to adjust the DC current to reduce to a substantial minimum the always-on entanglement (ZZ) between a pair of fixed-frequency qubits coupled to the first flux-variable coupler. Signal generation module 1576 also generates at least one current pulse (i pulse ) and Φoffset The current may be configured to provide each current pulse at a value based on the value of .

[0073] The machine learning module 1578 may be trained by supervised learning using examples of how device parameter behavior may require adjustment. The modules shown in Figure 15 may be combined into fewer modules, and these modules are not exhaustive or required to perform a particular operation.

[0074] Although modules 1572, 1576, and 1578 are illustrated in FIG. 15 as being part of HDD 1506, in some embodiments, one or more of these modules may be implemented in hardware in computing device 1500. For example, the modules described herein may be implemented partially in hardware and partially in software. That is, one or more of the components of quantum computing engine 1540 shown in FIG. 15 may be implemented in the form of electronic circuits comprising transistors, diodes, capacitors, resistors, inductors, varactors, and / or memristors. In other words, quantum computing engine 1540 may be implemented with one or more specially designed electronic circuits that perform the specific tasks and functions described herein. [Conclusion]

[0075] The description of various embodiments of the present teachings has been presented for illustrative purposes and is not intended to be exhaustive or limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein have been selected to best explain the principles, practical applications, or technical improvements of the embodiments over technologies found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0076] While the foregoing describes what is considered to be the best mode and / or alternative embodiments, it is understood that various modifications may be made thereto, that the subject matter disclosed herein may be embodied in various forms and embodiments, and that the present teachings may be applied to numerous applications, only a few of which have been described herein. It is intended by the following claims to claim all such applications, modifications, and variations that fall within the true scope of the present teachings.

[0077] The components, operations, steps, features, objects, benefits, and advantages described herein are merely exemplary. None of them, nor the discussion associated therewith, are intended to limit the scope of protection. While various advantages have been described herein, it will be understood that not all embodiments necessarily include all advantages. Unless otherwise specified, all measurements, values, ratings, positions, dimensions, sizes, and other specifications described herein, including the following claims, are approximate and not exact. They are intended to have a reasonable range consistent with the functions to which they pertain and that which is customary in the art to which they pertain.

[0078] Numerous other embodiments are contemplated, including those having fewer, additional, or different, or combinations of, components, steps, features, objects, benefits, and advantages. These also include those in which the components and / or steps are arranged and / or ordered differently.

[0079] The flowcharts and diagrams in the figures herein illustrate the architecture, functionality, and operation of possible implementations according to various embodiments of the present disclosure.

[0080] While the foregoing has been described in conjunction with exemplary embodiments, it is understood that the term "exemplary" is meant merely as exemplary, not as best or optimal. Except as noted immediately above, nothing described or illustrated is intended to, or should be construed to, generally dedicate any component, step, feature, object, benefit, advantage, or the like, whether or not claimed.

[0081] Terms and expressions used herein will be understood to have the ordinary meanings ascribed to such terms and expressions with respect to their respective corresponding fields of study and research, unless a special meaning is provided herein. Relative terms such as first, second, etc. may be used solely to distinguish one entity or act from another and do not necessarily require or imply an actual relationship or sequence between such entities or acts. The terms "comprises," "comprising," or other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements may include not only those elements, but also other elements not inherent in or expressly described within such process, method, article, or apparatus. An element preceded by "a" or "an" does not, in the absence of further constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that includes that element.

[0082] An Abstract is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. It can also be seen that in the foregoing Detailed Description, various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments have more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Accordingly, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as separately claimed subject matter.

Claims

1. a qubit chip including a plurality of qubits and a plurality of variable flux couplers; a plurality of fixed frequency qubits having a lattice structure, wherein each pair of the plurality of fixed frequency qubits is coupled to one flux-variable coupler; and a wiring layer coupled to the qubit chip, wherein the wiring layer comprises: a loop including a superconducting material inductively coupled to the variable flux coupler; and a flux bias line comprising a superconducting material different from the superconducting material of the loop, wherein the flux bias line is inductively coupled to both the loop and the flux variable coupler. wiring layer including A quantum circuit device comprising:

2. The wiring layer is a first superconducting material and a DC current and at least one current pulse (i ｐｕｌｓｅ a first magnetic flux bias line configured to receive the a first loop formed of a second superconducting material, the first loop inductively coupled to the first flux bias line and inductively coupled to the first flux variable coupler; further comprising Here, the magnetic field generated from the first magnetic flux bias line induces a sustained current in the first loop formed by the second superconducting material, and generates a static magnetic flux offset (Φ) through the first magnetic flux variable coupler. ｏｆｆｓｅｔ ) is configured to induce The quantum circuit device according to claim 1 .

3. the plurality of fixed frequency qubits including a fixed frequency transmonqubit; and The quantum circuit device of claim 2 , wherein the plurality of variable flux couplers include variable flux transmon couplers.

4. 3. The quantum circuit device of claim 2, further comprising a signal generating module configured to supply the DC current to induce the sustained current in the first loop, the signal generating module configured to adjust the DC current to reduce always-on entanglement (ZZ) between a pair of fixed-frequency qubits coupled to the first flux-variable coupler to a substantial minimum.

5. The at least one current pulse (i ｐｕｌｓｅ ), wherein the value of each of the current pulses is ｏｆｆｓｅｔ The quantum circuit device of claim 2 , based on a value of

6. the first superconducting material comprises niobium; and the second superconducting material comprises aluminum; The quantum circuit device according to claim 2 .

7. 3. The quantum circuit device of claim 2, further comprising: a global magnetic flux line disposed in a wiring layer in proximity to the sustained current loop, the global magnetic flux line being configured to generate a magnetic field within the sustained current loop upon receiving the DC current input.

8. the second superconducting material is shorted between two sections of successive flux bias lines, where a loop is formed on each flux bias line; The second superconducting material has a critical temperature (T Ｃ ) and a persistent current (i ｐ ) configured to generate; and The sustained current loop includes a flux offset (Φ) calibrated based on the temperature variation applied to the superconducting material in the flux-variable transmon. ｏｆｆｓｅｔ ), The quantum circuit device according to claim 2 .

9. The quantum circuit device of claim 2 , wherein the magnetic flux bias line includes one or more gradiometric loops.

10. 10. The quantum circuit device of claim 9, wherein flux-variable transmons on a qubit chip are coupled to the pair of fixed frequency qubits on the qubit chip, and the qubit chip is coupled to the wiring layer that generates a flux offset from a flux bias line and a loop of a persistent current.

11. 10. The quantum circuit device of claim 9, wherein a first flux-variable transmon is capacitively coupled to a first fixed frequency qubit and a second fixed frequency qubit of the pair of fixed frequency qubits.

12. The quantum circuit device of claim 11 , wherein the first flux-variable transmon and the fixed frequency qubit are arranged in a lattice structure to form a multi-qubit device.

13. 13. The quantum circuit device according to claim 1, wherein the magnetic flux bias line comprises a serpentine bias line that is continuous with the plurality of magnetic flux variable couplers and is configured to bias the plurality of magnetic flux variable couplers substantially simultaneously.

14. a qubit chip including a plurality of qubits; and a plurality of flux-tunable elements, each including a respective flux-tunable superconducting quantum interference (SQUID) loop, each flux-tunable element coupled between a respective pair of fixed frequency qubits; and a wiring layer coupled to the qubit chip, the wiring layer comprising: a continuous flux bias line including a first superconducting material disposed proximate to the flux variable element, the continuous flux bias line configured to output a DC current for simultaneously providing an offset to the flux variable element; and a plurality of magnetic flux bias lines arranged discontinuously on the magnetic flux variable element, each of the magnetic flux bias lines configured to output a magnetic flux pulse and independently offset a current due to mutual inductance with the magnetic flux variable element; wiring layer including A quantum circuit device comprising:

15. 15. The quantum circuit device of claim 14, wherein the continuous flux bias line is disposed on a first surface of the variable magnetic flux element, and the plurality of discontinuously arranged flux bias lines are proximate a second surface of the variable magnetic flux element.

16. 16. The quantum circuit device of claim 14, wherein the plurality of magnetic flux bias lines include gradiometric magnetic flux coils.

17. 17. A quantum circuit device as claimed in any one of claims 14 to 16, previously described, wherein the flux coupler on the qubit chip comprises two spatially separated pickup coils separately coupled to the continuous bias line and the independent flux bias line, respectively.

18. 1. A method for generating a DC offset in a flux variable element, the method comprising: When the temperature of the first superconducting material reaches the critical temperature (T Ｃ ), inputting a DC current into a flux bias line proximate to the flux variable element to inductively couple the flux bias line to both the flux variable element and a loop including the first superconducting material surrounding the flux variable element, wherein the flux bias line includes a second superconducting material different from the first superconducting material; and and trapping a sustained current within the superconducting loop by applying a voltage to the first superconducting material. Ｃ continuing to apply the DC current to the flux bias line while cooling to a lower temperature. A method for providing the above.

19. 20. The method of claim 18, wherein the input of the DC current is continued until the sustained current produces a minimum ZZ exchange rate between a first fixed frequency qubit and a second fixed frequency qubit.

20. biasing the flux variable element to a zero ZZ state; and pulsing the flux bias line for each of the tunable elements to pulse them to an ON state; 20. The method of any one of claims 18 to 19, further comprising:

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