Light-emitting substrate, manufacturing method thereof, and display device

Abstract

A light-emitting substrate is provided having a display area and a peripheral area located on at least one side of the display area, the peripheral area including a first peripheral area, the first peripheral area and the display area being spaced apart along the first direction, the light-emitting substrate including a base, a first conductive layer located on the base, the first conductive layer including a plurality of signal lines located in the display area, an insulating layer covering the plurality of signal lines, and a second conductive layer located on the insulating layer, the insulating layer including a first insulating layer and a second insulating layer sequentially stacked along a direction away from the base, and at least between the first peripheral area and the display area, at least a portion of an edge of the first insulating layer extends beyond an edge of the second insulating layer.

Description

[Technical Field]

[0001] The present disclosure relates to the field of display technology, and more particularly to a light-emitting substrate, a manufacturing method thereof, and a display device. [Background technology]

[0002] Micro-type light-emitting diodes, such as Mini-LEDs (Mini Light-Emitting Diodes) and Micro LEDs (Micro Light-Emitting Diodes), have dimensions of less than about 500 μm and have advantages such as smaller dimensions, high brightness, and long life, and are therefore showing a tendency for increasing use in the display field. Summary of the Invention

[0003] In one embodiment, a light-emitting substrate is provided. The light-emitting substrate has a display area and a peripheral area located on at least one side of the display area, the peripheral area including a first peripheral area, and the first peripheral area and the display area are spaced apart along the first direction. The light-emitting substrate includes a base, a first conductive layer located on the base, the first conductive layer including a plurality of signal lines located in the display area, an insulating layer covering the plurality of signal lines, and a second conductive layer located on the insulating layer. The insulating layer includes a first insulating layer and a second insulating layer sequentially stacked in a direction away from the base, and at least between the first peripheral area and the display area, at least a portion of an edge of the first insulating layer extends beyond an edge of the second insulating layer.

[0004] In some embodiments, at least between the first peripheral region and the display region, the inclination angle of at least a portion of the edge of the first insulating layer and the inclination angle of the edge of the second insulating layer are both 45° or less.

[0005] In some embodiments, at least a portion of an edge of the first insulating layer includes a first slope, an edge of the second insulating layer includes a second slope, and the first slope and the second slope are connected by a first plane on the first insulating layer.

[0006] In some embodiments, the second conductive layer includes a plurality of pads located in the display area, and the plurality of signal lines and the plurality of pads are located in the display area. The plurality of signal lines extend along a first direction and are spaced apart along a second direction, and the second direction intersects with the first direction. The light-emitting substrate includes a plurality of conductive portions located in the first peripheral area, and the plurality of conductive portions are located in the second conductive layer. Ends of the conductive portions close to the display area are stacked on edges of the first insulating layer and the second insulating layer, extend to the display area, and penetrate the insulating layers to be connected to the signal lines.

[0007] In some embodiments, the second insulating layer is located in the first peripheral region and between the base and the conductive portion.

[0008] In some embodiments, the distance by which at least a portion of the edge of the first insulating layer extends beyond the edge of the second insulating layer is in the range of 20 μm to 40 μm.

[0009] In some embodiments, the insulating layer has a thickness h1, the first conductive layer has a thickness h2, and h1 and h2 satisfy the following formula:

[0010]

number

[0011] In some embodiments, the ratio of the thickness of the first insulating layer to the thickness of the second insulating layer is greater than 0.9 and less than 1.1.

[0012] In some embodiments, the thickness of the first insulating layer is equal to or less than the thickness of the first conductive layer, and the first insulating layer surrounds each of the signal lines.

[0013] In some embodiments, the thickness of the second conductive layer is less than the thickness of the first conductive layer.

[0014] In some embodiments, the second insulating layer has a thickness of 7.5 μm or more.

[0015] In some embodiments, the light-emitting substrate further comprises a first passivation layer disposed between the first insulating layer and the second insulating layer, the second conductive layer including a plurality of pads located in the display area, and at least some of the pads are connected to the signal lines through the insulating layer and the first passivation layer.

[0016] In some embodiments, at least some edges of the first insulating layer extend beyond edges of the first passivation layer, and at least some edges of the first passivation layer extend beyond edges of the second insulating layer.

[0017] In some embodiments, the second insulating layer includes a first sub-insulating layer and a second sub-insulating layer stacked sequentially along a direction away from the base, the light-emitting substrate further includes a second passivation layer disposed between the first sub-insulating layer and the second sub-insulating layer, and the pad further passes through the second passivation layer to be connected to the signal line.

[0018] In some embodiments, at least a portion of the edge of the first sub-insulating layer extends beyond an edge of the second passivation layer, and at least a portion of the edge of the second passivation layer extends beyond an edge of the second sub-insulating layer.

[0019] In some embodiments, the peripheral region further includes a binding region, the binding region and the display region being spaced apart along the first direction, the light-emitting substrate including a plurality of binding pins located in the binding region, and the plurality of binding pins being located on the first conductive layer.

[0020] In some embodiments, the light-emitting substrate has a display area, the display area including a plurality of display unit areas. The second conductive layer includes a plurality of pad pairs located in each display unit area, each pad pair including two pads, the two pads being a first pad and a second pad, respectively. The light-emitting substrate further includes at least one light-emitting element and a driver chip located in the display unit area and on the second conductive layer, the light-emitting element being connected to one pad pair, the driver chip being connected to at least two pad pairs, and a first pad of each pad pair being connected to a signal line. Of the plurality of pad pairs located in the same display unit area, a second pad of the pad pair connected to the light-emitting element is connected to a second pad of the pad pair connected to the driver chip.

[0021] In some embodiments, the light-emitting substrate includes a third passivation layer disposed between the insulating layer and the second conductive layer, and at least one raised portion located in the display unit area, and the third passivation layer is disposed between the insulating layer and the second conductive layer. Third and a raised portion disposed between the pad and the passivation layer, and an orthogonal projection of the pad on the base is base It overlaps with the orthographic projection in

[0022] In some embodiments, the first pad includes a first sub-portion and a second sub-portion connected together, the first sub-portion being connected to the signal line, and an orthogonal projection of the second sub-portion on the base of the raised portion being base It is located within the orthographic projection at

[0023] In some embodiments, the light-emitting substrate further comprises a reflective layer disposed on a side of the third passivation layer away from the insulating layer, the reflective layer including a plurality of third openings, at least one pad being located within one of the third openings, and the raised portion being located within the third opening.

[0024] In some embodiments, the thickness of the raised portion is h3, the thickness of the reflective layer is h4, and h3 and h4 satisfy the following formula:

[0025]

number

[0026] In some embodiments, the signal lines include a plurality of element power signal lines, a plurality of data signal lines, a plurality of first chip power signal lines, and a plurality of ground signal lines. A first pad of the pad pair connected to the light emitting element is connected to the element power signal line. Each first pad of the at least two pad pairs connected to the driver chip is connected to a data signal line, a first chip power signal line, and a ground signal line, respectively.

[0027] In some embodiments, the number of light-emitting elements located in the display unit area is plural, and the plural light-emitting elements include a red light-emitting element, a green light-emitting element, and a blue light-emitting element, and a first pad of a pad pair connected to the green light-emitting element and a first pad of a pad pair connected to the blue light-emitting element are connected to each other and have an integral structure.

[0028] In some embodiments, the light-emitting substrate further includes: a buffer layer disposed between the first conductive layer and the base; a first insulating barrier layer located between the buffer layer and the insulating layer and also between the first conductive layer and the insulating layer; a second insulating barrier layer disposed on a side of the second conductive layer away from the base; a light-shielding layer disposed on a side of the second insulating barrier layer away from the base, the light-shielding layer including a plurality of light-shielding patterns, the orthogonal projections of the plurality of light-shielding patterns on the base at least partially overlapping the orthogonal projections of the first conductive layer and the second conductive layer on the base; and a third insulating layer disposed on the light-shielding layer away from the base, wherein the light-emitting element is connected to one pad pair through the third insulating layer, the light-shielding layer, and the second insulating barrier layer; and the driving chip is connected to at least two pad pairs through the third insulating layer, the light-shielding layer, and the second insulating barrier layer.

[0029] In another aspect, a method for manufacturing a light-emitting substrate is provided. The light-emitting substrate has a display area and a peripheral area located on at least one side of the display area. The method includes providing a base; forming a first conductive layer on the base, the first conductive layer including a plurality of signal lines; forming a first insulating layer on the first conductive layer; placing a first mask plate on a side of the first insulating layer away from the base, the first mask plate having a frame that blocks at least a portion of an edge of the first insulating layer; forming a second insulating layer through a fourth opening surrounded by the frame of the first mask plate to obtain an insulating layer including the first insulating layer and the second insulating layer, wherein at least a portion of an edge of the first insulating layer extends beyond an edge of the second insulating layer; and forming a second conductive layer on a side of the second insulating layer away from the base, the second conductive layer including a plurality of pads, at least a portion of the pads penetrating the insulating layer and connected to the signal lines.

[0030] In some embodiments, the step of forming a first conductive layer on one side of the base includes the steps of: forming a first conductive film layer on one side of the base; applying a photoresist to a side of the first conductive film layer away from the base; placing a second mask plate on the side of the first conductive film layer away from the base; exposing and developing the photoresist using the second mask plate to form a plurality of photoresist patterns; and etching the first conductive film layer using the plurality of photoresist patterns as a mask to form a first conductive layer, the first conductive layer including a plurality of signal lines located in the display area. The step of forming a first insulating layer on one side of the base includes the steps of: forming an organic insulating film on the first conductive layer, wherein a first portion of the organic insulating film covers the plurality of signal lines and a second portion of the organic insulating film surrounds the signal lines; placing the second mask plate on a side of the organic insulating film away from the base; and exposing and developing the organic insulating film using the second mask plate to remove the first portion and retain the second portion, thereby forming the first insulating layer, wherein one of the material of the organic insulating film and the photoresist is a photodecomposable material and the other is a photocurable material.

[0031] In another aspect, there is provided a display device comprising a light emitting substrate according to any of the above embodiments. [Brief explanation of the drawings]

[0032] In order to more clearly explain the technical solutions according to the present disclosure, the drawings used in some embodiments of the present disclosure will be briefly described below. It is clear that the drawings in the following description are only a portion of the drawings in some embodiments of the present disclosure. Those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams and do not limit the actual dimensions of the products, the actual flow of the methods, etc. according to the embodiments of the present disclosure. [Figure 1] 1A to 1C are structural diagrams of light emitting substrates according to some embodiments. [Figure 2] 1A to 1C are cross-sectional structural views of light emitting substrates according to some embodiments. [Figure 3] 5 is an electron microscope photograph of an insulating layer according to some examples. [Figure 4] 10A to 10C are structural diagrams of light emitting substrates according to some other embodiments. [Figure 5] FIG. 5 is a cross-sectional view taken along the line DD′ in FIG. 4. [Figure 6] 10A to 10C are structural diagrams of light emitting substrates according to some other embodiments. [Figure 7] 10A to 10C are structural diagrams of light emitting substrates according to some other embodiments. [Figure 8] 10A to 10C are structural diagrams of a display unit area of ​​a light emitting substrate according to some embodiments. [Figure 9] 1A to 1C are cross-sectional structural views of light emitting substrates according to some embodiments. [Figure 10] 10A to 10C are cross-sectional structural views of light emitting substrates according to some other embodiments. [Figure 11] 1 is a flowchart of a method for manufacturing a light emitting substrate according to some embodiments. [Figure 12A] 3A to 3C are structural diagrams corresponding to steps in a method for manufacturing a light emitting substrate according to some embodiments. [Figure 12B] 3A to 3C are structural diagrams corresponding to steps in a method for manufacturing a light emitting substrate according to some embodiments. [Figure 12C] 3A to 3C are structural diagrams corresponding to steps in a method for manufacturing a light emitting substrate according to some embodiments. [Figure 12D] 3A to 3C are structural diagrams corresponding to steps in a method for manufacturing a light emitting substrate according to some embodiments. [Figure 12E] 3A to 3C are structural diagrams corresponding to steps in a method for manufacturing a light emitting substrate according to some embodiments. [Figure 12F] 3A to 3C are structural diagrams corresponding to steps in a method for manufacturing a light emitting substrate according to some embodiments. [Figure 12G] 3A to 3C are structural diagrams corresponding to steps in a method for manufacturing a light emitting substrate according to some embodiments. [Figure 12H]3A to 3C are structural diagrams corresponding to steps in a method for manufacturing a light emitting substrate according to some embodiments. [Figure 12I] 3A to 3C are structural diagrams corresponding to steps in a method for manufacturing a light emitting substrate according to some embodiments. [Figure 12J] 3A to 3C are structural diagrams corresponding to steps in a method for manufacturing a light emitting substrate according to some embodiments. [Figure 13A] 3A to 3C are structural diagrams corresponding to steps in a method for manufacturing a first conductive layer and a first insulating layer according to some embodiments. [Figure 13B] 3A to 3C are structural diagrams corresponding to steps in a method for manufacturing a first conductive layer and a first insulating layer according to some embodiments. [Figure 13C] 3A to 3C are structural diagrams corresponding to steps in a method for manufacturing a first conductive layer and a first insulating layer according to some embodiments. [Figure 13D] 3A to 3C are structural diagrams corresponding to steps in a method for manufacturing a first conductive layer and a first insulating layer according to some embodiments. [Figure 13E] 3A to 3C are structural diagrams corresponding to steps in a method for manufacturing a first conductive layer and a first insulating layer according to some embodiments. [Figure 13F] 3A to 3C are structural diagrams corresponding to steps in a method for manufacturing a first conductive layer and a first insulating layer according to some embodiments. [Figure 14] 1 is a structural diagram of a display device according to some embodiments; DETAILED DESCRIPTION OF THE INVENTION

[0033] The following clearly and completely describes the technical solutions in some embodiments of the present disclosure with reference to the drawings. Of course, the embodiments described herein are only a part of the embodiments of the present disclosure, and are not all of the embodiments. All other embodiments that can be obtained by those skilled in the art based on the embodiments in the present disclosure shall fall within the scope of protection of the present disclosure.

[0034] Unless the context indicates otherwise, in this specification and claims, the term "comprise" and other forms thereof, such as the third-person singular "comprises" and the present participle form "comprising," should be interpreted in an open, inclusive sense, i.e., "including, but not limited to." In the description, the terms "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," "some examples," and the like, are intended to indicate that a particular feature, structure, material, or characteristic associated with this embodiment or examples is included in at least one embodiment or example of the present disclosure. General references to the above terms do not necessarily refer to the same embodiment or example. Furthermore, a described particular feature, structure, material, or characteristic may be included in any one or more embodiments or examples in any appropriate manner.

[0035] Hereinafter, the terms "first" and "second" are for descriptive purposes only and should not be understood as indicating or implying the relative importance or quantity of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In describing the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0036] "A and / or B" includes three combinations: A only, B only, and a combination of A and B.

[0037] In this specification, the use of "applied to" or "configured to" is intended to mean open and inclusive language and does not exclude equipment that is adapted or arranged to perform additional tasks or steps.

[0038] Also, the use of "based on" is meant to be open and inclusive, as a process, step, calculation, or other action performed "based on" one or more stated conditions or values ​​may, in fact, be based on additional conditions or values ​​beyond those stated.

[0039] As used herein, "about," "approximately," or "approximately" includes the stated value and the mean within an acceptable range of deviation of the specified value, where the acceptable range of deviation is determined by one of ordinary skill in the art considering the measurement and the error associated with measuring the specified quantity (i.e., limitations of the measurement system).

[0040] When a layer or element is referred to as being on another layer or substrate, it is understood that the layer or element may be located directly on the other layer or substrate, or there may be intermediate layers between the layer or element and the other layer or substrate.

[0041] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized illustrative drawings. In the drawings, thicknesses of layers and regions are exaggerated for clarity. As such, variations in shape relative to the drawings due, for example, to manufacturing techniques and / or tolerances are to be expected. Thus, exemplary embodiments of the present disclosure are not limited to the shapes of regions illustrated herein, but should be construed to include deviations in shape due to manufacturing or otherwise. For example, an etching region shown as a rectangle typically has curved features. Thus, regions shown in the drawings are exemplary in nature, and their shapes are not intended to represent the actual shape of regions of a facility, nor are they intended to limit the scope of exemplary embodiments.

[0042] In some embodiments of the present disclosure, a light-emitting substrate 10 is provided. As shown in FIG. 1, the light-emitting substrate 10 includes a display area AA and a peripheral area AN disposed on at least one side of the display area AA. Here, FIG. 1 shows an example in which the peripheral area AN surrounds the periphery of the display area AA. In some other examples, the peripheral area AN is disposed on the display area A.A It is understood that the conductors may be located on only one, both, or three sides of the conductor.

[0043] In some examples, as shown in FIG. 1, the peripheral area AN includes a first peripheral area BN.

[0044] For example, the first peripheral area BN and the display area AA are disposed along the first direction X with a gap therebetween.

[0045] For example, a plurality of signal lines 21 are provided in the display area AA.

[0046] For example, the peripheral area AN is provided with a plurality of binding pins 22. Here, the plurality of binding pins 22 are used to connect an external driving chip to some of the signal lines 21.

[0047] Hereafter, the light-emitting substrate 2 2, the light emitting substrate 10 includes a base 1, a first conductive layer 2, an insulating layer 3, and a second conductive layer 4. As shown in FIG.

[0048] In addition, in order to clearly show the film layer pattern in the display area AA and the film layer pattern between the first peripheral area BN and the display area AA, the cross-sectional views obtained along the cross-sectional lines N-N' and M-M' in Figure 1 were combined to obtain the cross-sectional view shown in Figure 2.

[0049] There are various types of the base 1, and it can be selected and installed according to actual needs.

[0050] For example, the base 1 may be a rigid base, which may be a glass base or a PMMA (Polymethyl methacrylate) base.

[0051] Exemplarily, the base 1 may be a flexible base, where the material of the flexible base may include any of plastic, FR-4 grade material, resin, glass, quartz, polyimide (English name: Polyimide, English abbreviation: PI), or polymethyl methacrylate (English abbreviation: PMMA).

[0052] In some examples, the first conductive layer 2 is disposed on a base 1, as shown in FIG.

[0053] Exemplarily, the first conductive layer 2 includes a plurality of the signal lines 21.

[0054] For example, the thickness of the first conductive layer 2 may be in the range of 1.5 μm to 7 μm. For example, the thickness of the first conductive layer 2 may be 1.5 μm, 3 μm, 5 μm, 6 μm, 7 μm, or the like.

[0055] Illustratively, the material of the first conductive layer 2 includes copper (Cu).

[0056] For example, the first conductive layer 2 may be formed by sputtering, using a laminated material such as MoNb (molybdenum niobium alloy) / Cu / MoNb (molybdenum niobium alloy). Here, the bottom layer MoNb may be used to improve adhesion, the middle layer Cu is used to transmit electrical signals, and the top layer MoNb is used to prevent oxidation. The first conductive layer 2 may also be formed by electroplating, using a seed layer MoNiTi (molybdenum titanium nickel alloy) first to increase the nucleation density of crystal grains, and then an oxidation prevention layer MoNiTi is produced after electroplating.

[0057] In some embodiments, the insulating layer 3 covers a plurality of signal lines 21, as shown in FIG.

[0058] The insulating layer 3 may have a variety of structures, and may be selected and installed according to the actual situation. The number of layers in the insulating layer 3 may be one or more.

[0059] In some instances, the second conductive layer 4 is disposed on the insulating layer 3, as shown in FIG.

[0060] Illustratively, the second conductive layer 4 includes a plurality of pads 41 .

[0061] Illustratively, at least some of the pads 41 are connected to the signal lines 21 through the insulating layer 3 .

[0062] For example, the pads 41 may include pads for connecting functional elements (e.g., light-emitting elements) to corresponding signal lines. The pads 41 may further include pads for connecting functional element driving chips to corresponding signal lines.

[0063] For example, the thickness of the second conductive layer 4 is about 6000 Å.

[0064] Exemplarily, the material of the second conductive layer 4 includes copper.

[0065] For example, the material of the second conductive layer 4 is MoNb (molybdenum niobium alloy) / Cu / CuNi ( copper The material may be a laminated material of MoNb (nickel alloy), where the bottom layer is used to improve adhesion, the middle layer is used to transmit electrical signals, and the top layer is CuNi, which can both prevent oxidation and provide the robustness of a solid crystal.

[0066] For example, when manufacturing the second conductive layer 4, first, a layer of metal film is manufactured on the insulating layer 3, then a layer of photoresist is manufactured on the metal film, and the photoresist portion corresponding to the required portion of the metal film to be removed by etching can be removed by exposure and development, and then the required portion of the metal film to be removed by etching is removed.

[0067] In the manufacturing process of the light-emitting substrate 10, the insulating layer 3 is prone to film formation defects due to the influence of foreign particles, or if the materials of the first conductive layer 2 and the second conductive layer 4 both contain copper, copper ions are likely to migrate and grow and break through the insulating layer 3, further worsening the film defects of the insulating layer 3, destroying the insulating layer 3 and connecting the first conductive layer 2 and the second conductive layer 4, causing a short circuit (i.e., a DGS (Data Gate Short, a short circuit between the power line and the data line) defect), which reduces the product stability of the light-emitting substrate 10.

[0068] In some embodiments, in order to improve the product stability of the light emitting substrate 10, the thickness of the insulating layer 3 is increased to reduce the probability of DGS defects occurring between the first conductive layer 2 and the second conductive layer 4. However, the inventors of the present disclosure have found that as the thickness of the insulating layer 3 increases, the step at some edges of the insulating layer 3 increases. As a result, in the process of forming the second conductive layer 4, the photoresist may not be sufficiently exposed or developed in areas of the metal film that need to be etched away. As such, when the metal film is etched, metal residues may be generated in areas where the photoresist is not sufficiently exposed or developed, causing defects in the light emitting substrate 10 or affecting the reliability of the light emitting substrate 10.

[0069] Based on this, in some embodiments of the present disclosure, as shown in FIG. 2, the insulating layer 3 includes a first insulating layer 31 and a second insulating layer 32 stacked in sequence along the direction away from the base 1.

[0070] For example, the thicknesses of the first insulating layer 31 and the second insulating layer 32 may be the same or different, but the embodiments of the present disclosure are not limited thereto.

[0071] For example, the first insulating layer 31 and the second insulating layer 32 may be made of the same material or different materials. However, the present disclosure is not limited thereto. For example, the first insulating layer 31 and the second insulating layer 32 may be made of the same material, and both the first insulating layer 31 and the second insulating layer 32 may be overcoating (OC) adhesive layers.

[0072] For example, at least a portion of the edge of the first insulating layer 31 extends beyond the edge of the second insulating layer 32 at least between the first peripheral area BN and the display area AA.

[0073] It should be noted that the above phrase "at least a portion of the edge of the first insulating layer 31 extends beyond the edge of the second insulating layer 32 at least between the first peripheral region BN and the display region AA" means that, in addition to the edge of the first insulating layer 31 extending beyond the edge of the second insulating layer 32 between the first peripheral region BN and the display region AA, the edge of the first insulating layer 31 may extend beyond the edge of the second insulating layer 32 in other regions, and the embodiments of the present disclosure are not limited to this.

[0074] For example, at least a portion of the edge of the first insulating layer 31 extends beyond the edge of the second insulating layer 32 between the first peripheral region BN and the display region AA and closer to the display region AA.

[0075] For example, at least a portion of the edge of the first insulating layer 31 extends beyond the edge of the second insulating layer 32 to form a step structure.

[0076] For example, "at least a portion of the edge of the first insulating layer 31 extends beyond the edge of the second insulating layer 32" means that at least a portion of the edge of the first insulating layer 31 located in the peripheral region AN extends beyond the edge of the second insulating layer 32, and as shown in Figure 2, in region H in Figure 2, the edge of the first insulating layer 31 extends beyond the edge of the second insulating layer 32.

[0077] Note that the above phrase "at least a portion of the edge of the first insulating layer 31 extends beyond the edge of the second insulating layer 32" includes two scenarios: either a portion of the edge of the first insulating layer 31 extends beyond the edge of the second insulating layer 32, or all of the edges of the first insulating layer 31 extend beyond the edge of the second insulating layer 32.

[0078] The edge here refers to the boundary of the film layer. For example, the edge of the first insulating layer 31, i.e., boundary a of the first insulating layer, and the edge of the second insulating layer 32, i.e., boundary b of the second insulating layer 32. As shown in FIG. 2, boundary a of the first insulating layer exceeds boundary b of the second insulating layer 32.

[0079] In the light-emitting substrate 10 provided in some embodiments of the present disclosure, the insulating layer 3 includes a first insulating layer 31 and a second insulating layer 32, thereby ensuring that the insulating layer 3 has a consistent thickness and reducing the probability of DGS failure between the first conductive layer 2 and the second conductive layer 4. Furthermore, at least a portion of the edge of the first insulating layer 31 extends beyond the edge of the second insulating layer 32, thereby reducing the step height of some edges of the insulating layer 3 and the inclination angle of some edges of the insulating layer 3. This reduces the likelihood of insufficient etching of the metal film and the generation of metal residues during the subsequent manufacturing of the second conductive layer 4, which is advantageous for improving the yield, safety, and stability of the light-emitting substrate 10 and extending the service life of the light-emitting substrate 10.

[0080] In some embodiments, at least between the first peripheral region BN and the display region AA, the inclination angles of at least a portion of the edges of the first insulating layer 31 and the second insulating layer 32 are both 45° or less.

[0081] Exemplarily, the inclination angle of at least a portion of the edge of the first insulating layer 31 may be 45°, 44°, 43°, 42°, 40°, etc., and the embodiments of the present disclosure are not limited thereto.

[0082] Illustratively, the inclination angle of the edge of the second insulating layer 32 may be 45°, 44°, 43°, 42°, 40°, etc., and the embodiments of the present disclosure are not limited thereto.

[0083] For example, the inclination angle of at least a portion of the edge of the first insulating layer 31 and the inclination angle of the edge of the second insulating layer 32 may be the same or different. The embodiment of the present disclosure is not limited thereto. For example, the inclination angle of at least a portion of the edge of the first insulating layer 31 and the inclination angle of the edge of the second insulating layer 32 may be the same, that is, 45°.

[0084] The inclination angle here refers to the included angle between the side of the film layer (i.e., the plane on which the edge of the film layer is located) and the bottom surface of the film layer. If the side of the film layer is not flat, the inclination angle of the film layer is the included angle between the side that contacts the bottom surface of the film layer and the bottom surface of the film layer. For example, the inclination angle of the first insulating layer 31 refers to the included angle α between the side of the first insulating layer 31 and the bottom surface of the first insulating layer 31, the inclination angle of the second insulating layer 32 refers to the included angle β between the side of the second insulating layer 32 and the bottom surface of the second insulating layer 32, and the inclination angle of the insulating layer 3 refers to the included angle α between the side that contacts the bottom surface of the insulating layer 3 and the bottom surface of the insulating layer 3. As shown in Figure 3, Figure 3 is an electron microscope photograph of the insulating layer 3.

[0085] In some examples, the slope angle of at least a portion of the edge of the first insulating layer 31 is α, and the slope angle of the edge of the second insulating layer 32 is β. When the slope angle of at least a portion of the edge of the first insulating layer 31, α, and the slope angle of the edge of the second insulating layer 32 are both 45° or less, problems such as insufficient etching of the metal film and the generation of metal residue are less likely to occur during the subsequent manufacturing of the second conductive layer 4.

[0086] In some embodiments, as shown in FIG. 3, at least a portion of the edge of the first insulating layer 31 includes a first bevel a, and the edge of the second insulating layer 32 includes a second bevel b.

[0087] In some examples, the first slope a and the second slope b are connected. For example, the first slope a and the second slope b are directly connected. In another example, the first slope a and the second slope b are indirectly connected. However, the embodiments of the present disclosure are not limited thereto.

[0088] For example, as shown in FIG. 3, the first slope a and the second slope b are connected by a first plane c of the first insulating layer 31.

[0089] If the second insulating layer 32 is an organic layer, a leveling trailing phenomenon occurs at the edge of the second insulating layer 32. In this case, the first plane c is not an absolute plane but an inclined plane with a certain gradient.

[0090] In this embodiment, the first inclined surface a of the first insulating layer 31 and the second inclined surface b of the second insulating layer 32 are connected by the first flat surface c of the first insulating layer 31, thereby further reducing the flatness of the edge of the insulating layer 3 and further improving the problem of insufficient etching of the metal film caused by the large inclination angle of the insulating layer 3.

[0091] In some embodiments, as shown in FIG. 4, a plurality of signal lines 21 and a plurality of pads 41 are located in the display area AA.

[0092] 1 and 4, the signal lines 21 extend along a first direction X and are spaced apart along a second direction Y.

[0093] Illustratively, the second direction Y intersects with the first direction X.

[0094] Here, the angle between the first direction X and the second direction Y can be selected and set according to actual needs, for example, the angle between the first direction X and the second direction Y can be 85°, 88°, or 90°.

[0095] In some examples, as shown in FIG. 4, the light emitting substrate 10 includes a plurality of conductive portions 42.

[0096] Exemplarily, the plurality of conductive portions 42 are located on the second conductive layer 4 .

[0097] For example, the plurality of conductive portions 42 are used to connect the first peripheral area BN and the display area AA.

[0098] For example, as shown in Figure 5, which is a cross-sectional structure diagram along the cross-sectional line D-D' in Figure 4, the end of the conductive portion 42 close to the display area AA is stacked on the edges of the first insulating layer 31 and the second insulating layer 32 and extends to the display area AA, and passes through the insulating layer 3 to be connected to the signal line 21.

[0099] In some examples, the first peripheral region BN may be a detection region.

[0100] For example, the multiple conductive parts 42 are used to perform a signal transmission test on the light emitting substrate 10 to detect whether the multiple signal lines 21 and multiple pads 41 in the light emitting substrate 10 can transmit data signals normally.

[0101] In addition, when the first peripheral region BN is the detection region, the region between the first peripheral region BN and the display region AA may be a scribe region, which connects the display region AA and the first peripheral region BN, and the first peripheral region BN and a portion of the scribe region are cut off after the detection of the light-emitting substrate 10 is completed. In some other embodiments, as shown in FIG. 1, the first peripheral region BN is reserved after the detection of the light-emitting substrate 10 is completed, and the embodiments of the present disclosure are not limited thereto.

[0102] In this embodiment, between the first peripheral region BN and the display region AA, the edge of the first insulating layer 31 extends beyond the edge of the second insulating layer 32, thereby reducing the inclination angle of the edge of the insulating layer 3 located between the first peripheral region BN and the display region AA. This reduces the likelihood of insufficient etching of the metal film during subsequent fabrication of the second conductive layer 4, and also reduces the likelihood of metal residues and short circuits between the fabricated conductive portions 42. This is advantageous for improving the accuracy of signal transmission detection and the reliability of the light emitting substrate 10. Based on this, the conductive portions 42 for performing signal transmission tests on the signal lines 21 and pads 41 in the light emitting substrate 10 are located on the second conductive layer 4, and the thickness of the second conductive layer 4 is typically smaller than the thickness of the first conductive layer 2, facilitating subsequent removal of the first peripheral region BN.

[0103] In some embodiments, as shown in FIG. 5, the second insulating layer 32 is further located in the first peripheral region BN and between the base 1 and the conductive portion 42.

[0104] Exemplarily, as shown in FIG. 5, the edge of the second insulating layer 32 away from the display area AA is closer to the display area AA than the edge of the base 1 away from the display area AA.

[0105] For example, the portion of the first insulating layer 31 located between the first peripheral region BN and the display region AA has a first edge 3101, and the portion of the second insulating layer 32 located between the detection region BN and the display region AA has a second edge 3201 and a third edge 3202.

[0106] Exemplarily, as shown in FIG. 5, the first edge 3101 of the first insulating layer 31 exceeds the second edge 3201 of the second insulating layer 32, forming a step structure.

[0107] Illustratively, as shown in FIG. 5, there is a gap between the second edge 3201 of the second insulating layer 32 and the third edge 3202 of the second insulating layer 32. As shown in FIG.

[0108] For example, if the first peripheral region BN needs to be removed, the region between the first peripheral region BN and the display region AA is a division region, and the projection of the second insulating layer 32 on the base 1 is offset from the division region. In this case, the film layer in the division region is thin and easy to divide.

[0109] In this embodiment, the second insulating layer 32 is further positioned between the conductive portion 42 and the base 1, which avoids problems such as the conductive portion 42 affecting the base 1 and causing cracks in the base 1, compared to when the conductive portion 42 is placed directly on the base 1.

[0110] By using the above-mentioned arrangement, the inclination angle of the edge portion of the insulating layer 3 located between the first peripheral region BN and the display region AA can be reduced, and the problem of short circuits occurring between the ends of the multiple second conductive portions 42 close to the display region AA and the adjacent second conductive portions 42 can be improved, and the problem of short circuits occurring between the ends of the multiple second conductive portions 42 close to the first peripheral region BN and the adjacent second conductive portions 42 can also be improved, which is advantageous for further improving the accuracy of signal transmission detection of the light-emitting substrate 10 and further improving the reliability of the light-emitting substrate 10.

[0111] In some embodiments, the distance by which at least a portion of the edge of the first insulating layer 31 extends beyond the edge of the second insulating layer 32 ranges from 20 μm to 40 μm. For example, the distance by which at least a portion of the edge of the first insulating layer 31 extends beyond the edge of the second insulating layer 32 may be 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, etc., and embodiments of the present disclosure are not limited thereto.

[0112] Illustratively, the range of the distance that first edge 3101 of first insulating layer 31 extends beyond second edge 3201 of second insulating layer 32 is 20 μm to 40 μm. For example, the distance that first edge 3101 of first insulating layer 31 extends beyond second edge 3201 of second insulating layer 32 is 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, etc.

[0113] The distance by which at least a portion of the edge of the first insulating layer 31 exceeds the edge of the second insulating layer 32 can depend on the size of the dimensions of the peripheral region of the light emitting substrate 10. Those skilled in the art will understand that in addition to the need to consider the size of the peripheral region of the light emitting substrate 10, the gentler the slope of the step structure formed by at least a portion of the edge of the first insulating layer 31 exceeding the edge of the second insulating layer 32, the better.

[0114] In this embodiment, the distance range of at least a portion of the edge of the first insulating layer 31 exceeding the edge of the second insulating layer 32 is 20 μm to 40 μm, which makes it less likely that the metal film will be insufficiently etched when manufacturing the second conductive layer 4, and also makes it less likely that metal residue will be generated, thereby ensuring an improved yield of the light-emitting substrate 10 and ensuring that the peripheral area of ​​the light-emitting substrate 10 is narrow, which is advantageous for realizing a narrow bezel design for the light-emitting substrate 10 and improving the screen occupancy rate.

[0115] In some embodiments, the insulating layer 3 has a thickness h1, the first conductive layer 2 has a thickness h2, and h1 and h2 satisfy the following formula:

[0116]

number

[0117] Illustratively, the value of h2 / h1 may be, for example, 1 / 4, 3 / 8, 1 / 2, 5 / 8, 3 / 4, etc.

[0118] Exemplarily, the thickness h1 of the insulating layer 3 refers to the maximum thickness of the insulating layer 3 in the direction perpendicular to the base. The thickness h2 of the first conductive layer 2 refers to the thickness of the first conductive layer 2 in the direction perpendicular to the base. Exemplarily, the thickness h1 of the insulating layer 3 may be 10 μm, and the thickness h2 of the first conductive layer 2 may be 7 μm.

[0119] The above-mentioned installation ensures that the thickness of the insulating layer 3 between the first conductive layer 2 and the second conductive layer 4 is thick, thereby reducing the probability of DGS defects occurring between the first conductive layer 2 and the second conductive layer 4 and improving the yield of the light-emitting substrate 10.

[0120] In some embodiments, the ratio of the thickness of the first insulating layer 31 to the second insulating layer 32 is greater than 0.9 and less than 1.1.

[0121] Illustratively, the ratio of the thickness of the first insulating layer 31 to the thickness of the second insulating layer 32 may be, for example, 0.93, 0.96, 0.99, 1.02, 1.05, and the like.

[0122] For example, the thickness of the first insulating layer 31 may be 4 μm, and the thickness of the second insulating layer 32 may be 4.2 μm.

[0123] This ensures that the insulating layer 3 has a consistent thickness, reducing the likelihood of DGS defects occurring between the first conductive layer 2 and the second conductive layer 4. Furthermore, because the difference in thickness between the first insulating layer 31 and the second insulating layer 32 is small, the step at some edges of the insulating layer 3 can be further reduced, and the inclination angle at some edges of the insulating layer 3 can be made smaller. This reduces the likelihood of insufficient etching of the metal film and the generation of metal residue when manufacturing the second conductive layer 4, which is advantageous for improving the yield of the light emitting substrate 10.

[0124] In some embodiments, as shown in FIG. 2, the thickness of the first insulating layer 31 is less than the thickness of the first conductive layer 2, and the first insulating layer 31 surrounds each signal line 21 of the first conductive layer 2.

[0125] Exemplarily, the orthogonal projection of the first insulating layer 31 on the base 1 is complementary to the orthogonal projection of each signal line 21 on the base 1 .

[0126] For example, the first conductive layer 2 may be fabricated as follows: First, a conductive film layer is formed by electroplating or sputtering. Here, the conductive film layer is made of a metal material with good conductivity, such as copper. Next, photoresist is applied to the first conductive layer 2, a mask plate is placed, and the photoresist is exposed and developed to form multiple photoresist patterns. Then, the conductive film layer is etched using the multiple photoresist patterns as a mask to form the first conductive layer 2. The first insulating layer 31 may be fabricated as follows: An organic insulating film is formed on the first conductive layer 2, with portions of the organic insulating film covering the first conductive layer 2 and surrounding each signal line of the first conductive layer 2. A mask plate is placed, and photoresist is exposed and developed to remove the portions of the organic insulating film covering the first conductive layer 2, leaving the portions of the organic insulating film surrounding each signal line of the first conductive layer 2. This forms the first insulating layer 31.

[0127] The first insulating layer 31 surrounds each signal line 21 of the first conductive layer 2. By rationally selecting the properties of the photoresist used in the manufacturing process of the first conductive layer 2 and the properties of the organic insulating film used in the manufacturing process of the first insulating layer 31, the first conductive layer 2 and the first insulating layer 31 can be manufactured using the same mask plate, simplifying the manufacturing process of the light emitting substrate 10 and significantly reducing production costs. For example, when etching the conductive film layer using a photolithography process in the manufacturing process of the first conductive layer 2, the photoresist may be, for example, a photocurable material. The light-transmitting areas of the mask plate used in the photolithography process correspond one-to-one to the positions of the signal lines 21 to be formed. After exposure and development, the photoresist in the positions corresponding to the signal lines 21 to be formed is retained, and the photoresist in the positions corresponding to the conductive film layer that needs to be removed by etching is removed. In the manufacturing process of the first insulating layer 31, the organic insulating film may be, for example, a photodegradable material. In this case, the light-transmitting areas of the mask plate used correspond one-to-one to the positions of the signal lines 21, and after exposure and development, the portions of the organic insulating film surrounding each signal line 21 are retained, and the portions covering each signal line 21 are removed.

[0128] In some embodiments, the thickness of the second conductive layer 4 is less than the thickness of the first conductive layer 2 .

[0129] For example, the first conductive layer 2 is used to arrange various signal lines. If the thickness of the first conductive layer 2 is too thin, it will cause an increase in the resistance of the various signal lines. In order to reduce the resistance of the various signal lines, the thickness of the first conductive layer 2 is generally thick.

[0130] For example, the thickness of the first conductive layer 2 is about 1.5 μm to 7 μm.

[0131] For example, the second conductive layer 4 is used to provide various pads or connection leads, and generally has a small thickness.

[0132] Illustratively, the thickness of the second conductive layer 4 is about 6000 Å.

[0133] In some embodiments, the thickness of the second insulating layer 32 is 7.5 μm or more. For example, the thickness of the second insulating layer 32 may be 7.5 μm, 8 μm, 8.5 μm, etc., and embodiments of the present disclosure are not limited thereto.

[0134] In addition, since some of the pads 41 included in the second conductive layer 4 need to penetrate the insulating layer 3 and be connected to the signal line 21, it is necessary to etch the insulating layer 3 to make holes before manufacturing the second conductive layer 4.

[0135] 2, when the thickness of the first insulating layer 31 is smaller than the thickness of the first conductive layer 2, only the second insulating layer 32 exists between the first conductive layer 2 and the second conductive layer 4. A portion of the pad 41 included in the second conductive layer 4 needs to penetrate the second insulating layer 32 and connect to the signal line 21.

[0136] For example, when the thickness of the first insulating layer 31 is smaller than that of the first conductive layer 2 and the thickness of the second insulating layer 32 is 7.5 μm, holes are formed on the second insulating layer 32 by exposure and development.

[0137] For example, when drilling a hole on the second insulating layer 32, the inventors of the present disclosure examined the inclination angle of the edge of the second insulating layer 32, the size of the hole diameter when drilling the hole in the second insulating layer 32, and whether or not material remains at the opening position of the second insulating layer 32.

[0138] The test results are shown in Table 1. [Table 1]

[0139] Here, Exp.Gap is the distance between the mask plate used during exposure and the second insulating layer 32, and Dev is developing The distance between the mask plate and the second insulating layer 32 is constant. developingWhen the time is constant, the inventors of the present disclosure select 12 test points, measure the tilt angle of the second insulating layer 32 at each test point, and calculate that the distance between the mask plate and the second insulating layer 32 is constant, developing When the time is constant, the average value Ave of the tilt angles of the 12 test points, the maximum value Max of the tilt angles of the 12 test points, and the minimum value Min of the tilt angles of the 12 test points are obtained.

[0140] Based on this, the distance between the mask plate and the second insulating layer 32 is constant, developing When the time was constant, the inventors of the present disclosure further measured the via width (via CD) of the second insulating layer 32, and further recorded whether or not there was any material remaining at the opening position of the second insulating layer 32.

[0141] Table 1 shows that the tilt angle decreases by approximately 10° for every 50 μm increase in the distance between the mask plate and the second insulating layer 32. When the distance between the mask plate and the second insulating layer 32 is 150 μm and the development time is less than 90 seconds, residual material remains at the openings in the second insulating layer 32, causing poor contact between the first conductive layer 2 and the second conductive layer 4. When the distance between the mask plate and the second insulating layer 32 is 250 μm and the development time is 120 seconds, the tilt angle of the second insulating layer 32 is approximately 56°, and no residual material remains at the openings in the second insulating layer 32, ensuring good contact between the first conductive layer 2 and the second conductive layer 4. In other words, increasing the thickness of the second insulating layer 32 to a certain extent increases the distance between the first conductive layer 2 and the second conductive layer 4. This further reduces the probability of a short circuit occurring between the first conductive layer 2 and the second conductive layer 4. Based on this, by changing the distance between the mask plate and the second insulating layer 32 and the development time, it is possible to ensure a small inclination angle of the second insulating layer 32. This in turn makes it possible to ensure that the problem of insufficient etching of the metal film is less likely to occur when manufacturing the second conductive layer 4, and furthermore, that metal residue is less likely to be generated.

[0142] In some embodiments, as shown in FIG. 6, the light emitting substrate 10 further comprises a first passivation layer 5 disposed between the first insulating layer 31 and the second insulating layer 32 .

[0143] Illustratively, some of the pads 41 further pass through the first passivation layer 5 and are connected to the signal lines 21 .

[0144] Illustratively, the material of the first passivation layer 5 is an inorganic material, such as silicon nitride, silicon oxide, and the like.

[0145] Those skilled in the art will understand that if the materials of the first conductive layer 2 and the second conductive layer 4 both contain copper, copper ions are likely to migrate and grow under the influence of external environments such as foreign particles and voltage, resulting in a short circuit between the first conductive layer 2 and the second conductive layer 4.

[0146] In this embodiment, a first passivation layer 5 is provided between the first insulating layer 31 and the second insulating layer 32. Due to the high density of the inorganic material itself, the provision of the first passivation layer 5 can effectively prevent the migration and growth of metal ions in the first conductive layer 2 and the second conductive layer 4 toward each other. This effectively reduces the probability of a short circuit occurring between the first conductive layer 2 and the second conductive layer 4, further reducing the risk of defects in the light emitting substrate 10, improving the yield, safety, and stability of the light emitting substrate 10, and extending the service life of the light emitting substrate 10.

[0147] In some embodiments, as shown in FIG. 6, at least a portion of the edge of the first insulating layer 31 extends beyond the edge of the first passivation layer 5, and at least a portion of the edge of the first passivation layer 5 extends beyond the edge of the second insulating layer 32.

[0148] For example, "at least some edges of the first insulating layer 31 extend beyond the edges of the first passivation layer 5, and at least some edges of the first passivation layer 5 extend beyond the edges of the second insulating layer 32" means that at least some edges of the first insulating layer 31 located in the peripheral region AN extend beyond the edges of the first passivation layer 5 located in the peripheral region AN, and at least some edges of the first passivation layer 5 located in the peripheral region AN extend beyond the edges of the second insulating layer 32 located in the peripheral region AN. Note that the above phrase "at least some edges of the first insulating layer 31 extend beyond the edges of the first passivation layer 5, and at least some edges of the first passivation layer 5 extend beyond the edges of the second insulating layer 32" includes multiple scenarios, such as some edges of the first insulating layer 31 extending beyond the edges of the first passivation layer 5, and some edges of the first passivation layer 5 extending beyond the edges of the second insulating layer 32, or all edges of the first insulating layer 31 extending beyond the edges of the first passivation layer 5, and all edges of the first passivation layer 5 extending beyond the edges of the second insulating layer 32.

[0149] For example, at least a portion of the edge of the first insulating layer 31 extends beyond the edge of the first passivation layer 5, and at least a portion of the edge of the first passivation layer 5 extends beyond the edge of the second insulating layer, forming a step structure. Note that, in the above description, "at least a portion of the edge of the first insulating layer 31 extends beyond the edge of the second insulating layer, forming a step structure," the step structure is formed by the first insulating layer 31 and the second insulating layer 32. On the other hand, in this embodiment, the step structure is formed by the first insulating layer 31, the first passivation layer 5, and the second insulating layer 32.

[0150] By providing the first passivation layer 5 between the first insulating layer 31 and the second insulating layer 32, the metal ions in the first conductive layer 2 and the second conductive layer 4 can be effectively prevented from migrating and growing toward each other, effectively reducing the likelihood of a short circuit occurring between the first conductive layer 2 and the second conductive layer 4. Meanwhile, the step structure in which at least a portion of the edge of the first insulating layer 31 extends beyond the edge of the first passivation layer 5 and at least a portion of the edge of the first passivation layer 5 extends beyond the edge of the second insulating layer can reduce the inclination angle of the edges of the first insulating layer 31, the first passivation layer 5, and the second insulating layer 32. This reduces the risk of insufficient etching of the metal film during the manufacture of the second conductive layer 4, and also reduces the risk of metal residue, further improving the yield of the light emitting substrate 10.

[0151] In some embodiments, as shown in FIG. 7, the second insulating layer 32 includes a first sub-insulating layer 321 and a second sub-insulating layer 322 that are stacked in order along the direction away from the base 1.

[0152] For example, the thickness of the first insulating sub-layer 321 and the second insulating sub-layer 322 may be the same. Yo The embodiments of the present disclosure are not limited thereto.

[0153] For example, the first insulating sub-layer 321 and the second insulating sub-layer 322 may be made of the same material. Yo However, the embodiments of the present disclosure are not limited thereto. For example, the first insulating sub-layer 321 and the second insulating sub-layer 322 may be made of the same material, and both the first insulating sub-layer 321 and the second insulating sub-layer 322 may be overcoating (OC) adhesive layers.

[0154] In some examples, as shown in FIG. 7, the light emitting substrate 10 further includes a second passivation layer 6 disposed between the first insulating sub-layer 321 and the second insulating sub-layer 322.

[0155] Illustratively, the material of the second passivation layer 6 is an inorganic material, for example silicon nitride.

[0156] In this embodiment, the second insulating layer 32 includes a first sub-insulating layer 321 and a second sub-insulating layer 322, and a second passivation layer 6 is disposed between the first sub-insulating layer 321 and the second sub-insulating layer 322. Increasing the number of film layers between the first conductive layer 2 and the second conductive layer 4 increases the distance between the first conductive layer 2 and the second conductive layer 4, effectively reducing the probability of a short circuit occurring between the first conductive layer 2 and the second conductive layer 4. Meanwhile, the second passivation layer 6 effectively prevents metal ions in the first conductive layer 2 and the second conductive layer 4 from migrating and growing toward each other. This further effectively reduces the probability of a short circuit occurring between the first conductive layer 2 and the second conductive layer 4, improves the yield, safety, and stability of the light emitting substrate 10, and extends the service life of the light emitting substrate 10.

[0157] In some embodiments, as shown in FIG. 7, at least a portion of the edge of the first insulating sublayer 321 extends beyond the edge of the second passivation layer 6, and at least a portion of the edge of the second passivation layer 6 extends beyond the edge of the second insulating sublayer 322.

[0158] For example, "at least some edges of the first sub-insulating layer 321 extend beyond the edges of the second passivation layer 6, and at least some edges of the second passivation layer 6 extend beyond the edges of the second sub-insulating layer 322" means that at least some edges of the first sub-insulating layer 321 located in the peripheral region AN extend beyond the edges of the second passivation layer 6 located in the peripheral region AN, and at least some edges of the second passivation layer 6 located in the peripheral region AN extend beyond the edges of the second sub-insulating layer 322 located in the peripheral region AN.

[0159] Note that the above phrase "at least some edges of the first sub-insulating layer 321 extend beyond the edges of the second passivation layer 6, and at least some edges of the second passivation layer 6 extend beyond the edges of the second sub-insulating layer 322" includes multiple scenarios, such as some edges of the first sub-insulating layer 321 extending beyond the edges of the second passivation layer 6, and some edges of the second passivation layer 6 extending beyond the edges of the second sub-insulating layer 322, or all edges of the first sub-insulating layer 321 extending beyond the edges of the second passivation layer 6, and all edges of the second passivation layer 6 extending beyond the edges of the second sub-insulating layer 322.

[0160] Illustratively, at least a portion of the edge of the first sub-insulating layer 321 extends beyond the edge of the second passivation layer 6, and at least a portion of the edge of the second passivation layer extends beyond the edge of the second sub-insulating layer 322, forming a step structure.

[0161] The "step structure" is formed by the first insulating sub-layer 321, the second passivation layer 6, and the second insulating sub-layer 322. Exemplarily, as shown in Fig. 7, the first insulating layer 31, the first insulating sub-layer 321, the second passivation layer 6, and the second insulating sub-layer 322 form a staircase structure.

[0162] In this embodiment, the second passivation layer 6 effectively prevents the metal ions in the first conductive layer 2 and the second conductive layer 4 from migrating and growing toward each other, thereby further effectively reducing the probability of a short circuit occurring between the first conductive layer 2 and the second conductive layer 4. Meanwhile, at least a portion of the edge of the first sub-insulating layer 321 extends beyond the edge of the second passivation layer 6, and at least a portion of the edge of the second sub-insulating layer 6 extends beyond the edge of the second sub-insulating layer 322, forming a stepped structure, which reduces the inclination angle of some edges of the first insulating layer 31, the first sub-insulating layer 321, the second passivation layer 6, and the second sub-insulating layer 322. This reduces the risk of insufficient etching of the metal film and the generation of metal residue during the manufacturing of the second conductive layer 4, thereby further improving the yield of the light emitting substrate 10.

[0163] In some embodiments, the surrounding region AN comprises a binding region BB.

[0164] In some examples, the number of binding regions BB may be 1. In some other examples, the number of binding regions BB may be multiple, as shown in Figure 1. Illustratively, the number of binding regions BB may be 2, 3, or 4.

[0165] As shown in FIG. 1, when there are a plurality of binding areas BB, it is understood that the binding areas BB are located on the same side of the display area AA.

[0166] Exemplarily, the binding area BB and the display area AA are spaced apart along the first direction X. Exemplarily, when the peripheral area AN includes both the detection area BN and the binding area BB, the detection area BN and the binding area BB are located on opposite sides of the display area AA.

[0167] In some examples, the light emitting substrate 10 includes a plurality of binding pins 22 located in the binding region BB.

[0168] Exemplarily, a plurality of binding pins 22 located in the binding area BB are used to connect an external driving chip with the signal lines 21 located in the display area AA.

[0169] Exemplarily, a plurality of binding pins 22 located in the binding area BB are electrically connected to an external driving chip by a flexible circuit board.

[0170] For example, one signal line 21 is electrically connected to one binding pin 22. An external driving chip transmits driving signals to the multiple binding pins 22 via a flexible circuit board, and the multiple binding pins 22 further transmit driving signals to the multiple signal lines 21.

[0171] Illustratively, a plurality of binding pins 22 are located on the first conductive layer 2 .

[0172] In this embodiment, by positioning multiple binding pins 22 in the binding area BB on the first conductive layer 2, the number of film layers in the binding area BB can be reduced, and the film layer structure of the binding area BB is relatively simple, which reduces the probability of detachment occurring between the film layers in the binding area BB and further improves the yield of the light-emitting substrate 10.

[0173] In some embodiments, as shown in FIGS. 1 and 8, the display area AA includes multiple display unit areas A1.

[0174] In some examples, the light emitting substrate 10 further includes at least one light emitting element 7 and a driving chip 8 located in the display unit area A1 and on the second conductive layer 4.

[0175] The number of light-emitting elements 7 located in the same display unit area A1 may be one or more, and the embodiments of the present disclosure are not limited thereto. For example, as shown in FIG. 8, the number of light-emitting elements 7 located in the same display unit area A1 may be three.

[0176] For example, when there are multiple light-emitting elements 7 located in the same display unit area A1, the multiple light-emitting elements 7 may be used to emit light of the same color, or the multiple light-emitting elements 7 may be used to emit light of multiple different colors.

[0177] For example, multiple light-emitting elements 7 located in the same display unit area A1 can all be used to emit white light, or multiple light-emitting elements 7 located in the same display unit area A1 can all be used to emit blue light, thereby allowing the light-emitting substrate 10 to emit light of a specific color.

[0178] As another example, the light-emitting elements 7 located in the same display unit area A1 include light-emitting elements of at least three colors, and the light-emitting elements of the multiple colors include at least a first color, a second color, and a third color, and the first color, the second color, and the third color are three basic colors (e.g., red, green, and blue).

[0179] In some examples, the light-emitting elements 7 located in the same display unit region A1 have the same luminance. The light-emitting elements 7 located in different display unit regions A1 may have the same or different luminance. By controlling the luminance of the light-emitting elements 7 in different display unit regions A1, the luminance of different regions of the light-emitting substrate 10 can be controlled to meet different usage requirements.

[0180] For example, the light-emitting element 7 can emit light of different brightness under the control of the driving chip 8. When Mini LED or Micro LED is used as the light-emitting element, the size of the light-emitting element 7 is small, so that the human eye can see the display screen from one side of the light-emitting substrate 10.

[0181] Compared with using normal LEDs, using Mini LEDs or Micro LEDs as light-emitting elements allows for smaller light-emitting element dimensions, higher density, finer image display, shorter visible distance, and larger visible angle, with the viewing angle reaching 160° or more.

[0182] 8, the second conductive layer 4 includes a plurality of pad pairs 40 located in each display unit area A1. For example, six pad pairs 40 are provided in each display unit area A1.

[0183] Illustratively, each pad pair 40 includes two pads 41, which are a first pad 411 and a second pad 412, respectively.

[0184] Illustratively, the first pad 411 of each pad pair 40 is connected to the signal line 21 .

[0185] For example, among multiple pad pairs 40 located in the same display unit area A1, the second pad 412 of the pad pair 40 connected to the light-emitting element 7 is connected to the second pad 412 of the pad pair 40 connected to the driving chip 8.

[0186] In this embodiment, the second pad 412 of the pad pair 40 connected to the light-emitting element 7 is connected to the second pad 412 of the pad pair 40 connected to the driver chip 8, thereby realizing electrical connection between the light-emitting element 7 and the driver chip 8. This allows the driver chip 8 to control the light emission of the light-emitting element 7 electrically connected thereto.

[0187] In some embodiments, the light emitting substrate 10 further comprises a third passivation layer 9 and at least one raised portion 20 .

[0188] In some examples, as shown in FIG. 9, a third passivation layer 9 is disposed between the insulating layer 3 and the second conductive layer 4.

[0189] Illustratively, the material of the third passivation layer 9 is an inorganic material, such as silicon nitride, silicon oxide, and the like.

[0190] In some examples, at least one of the raising portions 20 is located in the display unit area A1.

[0191] The raised portion 20 is disposed between the insulating layer 3 and the third passivation layer 9 .

[0192] The raised portion 20 may have a variety of structures, and may be selected and installed according to the actual situation. The number of layers of the raised portion 20 may be one or more. For example, as shown in Figure 9, the raised portion 20 has two layers.

[0193] In some examples, the orthogonal projection of the pad 41 on the base 1 partially overlaps with the orthogonal projection of the raised portion 20 on the base 1. By using the above-mentioned arrangement, the pad 41 is raised, which is advantageous for good contact between the light emitting element 7 or the driving chip 8 and the pad 41 when the bottom of the light emitting element 7 or the driving chip 8 and the pad 41 are welded with flux in the die bonding stage, and effectively improves the yield of die bonding of the light emitting substrate 10.

[0194] In some embodiments, as shown in FIG. 10, the first pad 411 includes a first sub-portion 4111 and a second sub-portion 4112 that are connected together.

[0195] For example, the first sub-section 4111 is connected to the signal line 21.

[0196] For example, the orthogonal projection of the second sub-portion 4112 on the base 1 is located within the range of the orthogonal projection of the raised portion 20 on the base 1.

[0197] Exemplarily, the second sub-part 4112 is used to connect with the light emitting element 7 or the driving chip 8 .

[0198] By using the above-mentioned arrangement, the second sub-part 4112 is raised, which is advantageous for good contact between the light-emitting element 7 or the driving chip 8 and the second sub-part 4112 when the bottom of the light-emitting element 7 or the driving chip 8 and the second sub-part 4112 are welded with flux during the die bonding stage, thereby effectively improving the yield of die bonding of the light-emitting substrate 10.

[0199] In some embodiments, the light emitting substrate 10 further comprises a reflective layer 30, as shown in FIGS.

[0200] In some examples, the reflective layer 30 is disposed on the side of the third passivation layer 9 away from the insulating layer 3 .

[0201] For example, the material of the reflective layer 30 is one or more of silver, aluminum, white oil, and white glue, all of which have high reflectivity and can improve the light reflection efficiency.

[0202] For example, as shown in Figures 9 and 10, the reflective layer 30 includes a plurality of third openings 301, at least one pad 41 is located in the third opening 301, and the raised portion 20 is located in the third opening 301.

[0203] Exemplarily, the number of pads 41 located in one third opening 301 may be one or more. For example, as shown in Figures 8 and 9, the number of pads 41 located in one third opening 301 may be two.

[0204] Note that when the number of pads 41 located within one third opening 301 is two, both pads 41 may be first pads 411, or both pads 41 may be second pads 412. Alternatively, as shown in FIG. 9 , the two pads 41 may be the first pad 411 and the second pad 412, respectively. The embodiments of the present disclosure are not limited thereto. In this embodiment, the reflective layer 30 is provided to reflect light, improve the utilization rate of light to the light-emitting element 7, and increase the optical efficiency. For example, when light emitted downward from the light-emitting element 7 passes through the reflective layer 30, the reflective layer 30 can reflect the light and change it to an upward emission without passing through the base 1. As a result, the light emitted downward from the light-emitting element 7 is reflected by the reflective layer 30 and utilized, thereby improving the utilization rate of light of the light-emitting element 7 and increasing the optical efficiency.

[0205] Based on this, when the light emitting substrate 10 includes the reflective layer 30, the light emitting substrate 10 can be used as a backlight. Module and is used to provide backlighting.

[0206] In some embodiments, the thickness of the raised portion 20 is h3, the thickness of the reflective layer 30 is h4, and h3 and h4 satisfy the following formula:

[0207]

number

[0208] Illustratively, the values ​​of h3 / h4 may be, for example, 0.1, 0.2, 0.3, 0.4, etc.

[0209] In this embodiment, the reflective layer 30 improves the utilization rate of light rays to the light-emitting element 7, while the pad 41 is raised by the raising portion 20, which is advantageous for good contact between the light-emitting element 7 or the driving chip 8 and the pad 41, and effectively improves the yield of die bonding of the light-emitting substrate 10.

[0210] In some embodiments, as shown in FIG. 8, the signal lines 21 include a plurality of device power signal lines 211, a plurality of data signal lines 212, a plurality of first chip power signal lines 213, and a plurality of ground signal lines 214.

[0211] In some examples, the first pad 411 of the pad pair 40 connected to the light emitting element 7 is connected to the element power supply signal line 211 .

[0212] For example, the element power supply signal line 211 supplies a large constant current voltage to the light emitting element 7 and forms a circuit with the ground signal line 214 .

[0213] In some examples, each first pad 411 of at least two pad pairs 40 connected to the driver chip 8 is connected to a data signal line 212, a first chip power signal line 213, and a ground signal line 214, respectively.

[0214] For example, the first chip power signal line 213 is used to input a voltage signal for supplying the operating power to the driver chip 8 .

[0215] Illustratively, the ground signal line 214 is used to ground the driver chip 8 .

[0216] For example, the light emitting substrate 10 includes a plurality of second chip power signal lines located on the second conductive layer, and the plurality of second chip power signal lines extend along the second direction Y.

[0217] One first pad 411 of at least two pad pairs 40 connected to the driver chip 8 is connected to the second chip power supply signal line by the first chip power supply signal line 213 .

[0218] In some examples, a plurality of display unit regions P arranged in a line along the first direction X are electrically connected to a set of signal lines 21.

[0219] Exemplarily, the set of signal lines 21 includes two device power signal lines 211 , one data signal line 212 , one first chip power signal line 213 , and one ground signal line 214 .

[0220] In some embodiments, as shown in FIG. 8, the number of light-emitting elements 7 located in the same display unit area A1 is plural, and the plural light-emitting elements 7 include a red light-emitting element 71, a green light-emitting element 72, and a blue light-emitting element 73.

[0221] In some examples, the first pad 411 of the pad pair 40 connected to the green light emitting element 72 and the first pad 411 of the pad pair 40 connected to the blue light emitting element 73 are connected and form a unitary structure.

[0222] For example, the term "integral structure" refers to two connected patterns being located on the same layer and being continuous and not separated. That is, in the present disclosure, the first pad 411 of the pad pair 40 connected to the green light-emitting element 72 and the first pad 411 of the pad pair 40 connected to the blue light-emitting element 73 are located on the same film layer, and the two first pads 411 are connected to each other.

[0223] Since the conversion efficiency of the red light-emitting element 71 is significantly different from the conversion efficiency of the blue light-emitting element 73 and the green light-emitting element 72, in this embodiment, the red light-emitting element 71 is connected to one element power supply signal line 211, and the blue light-emitting element 73 and the green light-emitting element 72 are connected to one element power supply signal line 211. In other words, the power supply signal of the red light-emitting element 71 is supplied separately from the power supply signals of the blue light-emitting element 73 and the green light-emitting element 72, thereby effectively reducing the power consumption of the light-emitting substrate 10.

[0224] In some embodiments, as shown in FIGS. 2, 6, and 7, the light emitting substrate 10 further comprises a buffer layer 50, a first insulating barrier layer 60, a second insulating barrier layer 70, a light-shielding layer 80, and a third insulating layer 90.

[0225] In some examples, a buffer layer 50 is disposed between the first conductive layer 2 and the base 1 .

[0226] Illustratively, the buffer layer 50 is made of an inorganic material such as silicon nitride, silicon oxide, etc. The buffer layer 50 is located between the base 1 and the first conductive layer 2 and can protect the base 1, making the base 1 less likely to break under the stress generated by the first conductive layer 2.

[0227] In some examples, as shown in Figures 2, 6, and 7, the first insulating barrier layer 60 is located between the buffer layer 50 and the insulating layer 3, and between the first conductive layer 2 and the insulating layer 3.

[0228] Illustratively, the material of the first insulating barrier layer 60 is an inorganic material, such as silicon nitride, silicon oxide, or the like.

[0229] Illustratively, the first insulating barrier layer 60 can shield the first conductive layer 2 from water and oxygen.

[0230] In some examples, the second insulating barrier layer 70 is disposed on the side of the second conductive layer 4 away from the base 1 .

[0231] Illustratively, the material of the second insulating barrier layer 70 is an inorganic material, such as silicon nitride, silicon oxide, or the like.

[0232] Illustratively, the second insulating barrier layer 70 can shield the second conductive layer 4 from water and oxygen.

[0233] In some examples, the light-shielding layer 80 is disposed on the side of the second insulating barrier layer 70 away from the base 1 .

[0234] For example, the material of the light-shielding layer 80 may be a light-shielding insulating material, such as black resin, or may be a metal or a metal alloy, such as aluminum, silver, magnesium, or a magnesium-silver alloy, but the embodiments of the present disclosure are not limited thereto.

[0235] Illustratively, the light-shielding layer 80 includes a plurality of light-shielding patterns 801, and the orthogonal projections of the plurality of light-shielding patterns 801 on the base 1 at least partially overlap with the orthogonal projections of the first conductive layer 2 and the second conductive layer 4 on the base 1.

[0236] For example, the light-shielding layer 80 is used to block light rays and reduce the overall reflectance of the light-emitting substrate 10. For example, ambient light irradiates the signal lines 21 and the pads 41, causing the signal lines 21 and the pads 41 to reflect light rays. When a viewer watches a video, the reflected light rays enter the viewer's eyes, affecting the viewer's viewing experience. On the other hand, in the present disclosure, by providing the light-shielding layer 80 for blocking light rays, the reflectance of the entire light-emitting substrate 10 can be reduced, and when the light-emitting substrate 10 is used to display image information, the display effect of the light-emitting substrate 10 can be improved, thereby improving the viewer's viewing experience.

[0237] Based on this, when the light emitting substrate 10 includes the light blocking layer 80, the light emitting substrate 10 can directly display a screen as a display panel.

[0238] In some examples, the third insulating layer 90 is disposed on the side of the light-shielding layer 80 away from the base 1 .

[0239] Exemplarily, the third insulating layer 90 may be an OC (Over Coating) adhesive layer.

[0240] For example, the third insulating layer 90 is used to cover the side of the second conductive layer 4 away from the base 1 and to protect the second conductive layer 4. This makes the surface of the portion of the second conductive layer 4 covered by the third insulating layer 90 less susceptible to oxidation, and serves to slow down the corrosion rate of the second conductive layer 4.

[0241] In some examples, the light emitting element 7 is connected to one pad pair 40 through the third insulating layer 90, the light shielding layer 80, and the second insulating barrier layer 70. The driver chip 8 is connected to at least two pad pairs 40 through the third insulating layer 90, the light shielding layer 80, and the second insulating barrier layer 70.

[0242] In some examples, the light emitting substrate 10 further comprises a plurality of alignment patterns 100 .

[0243] Exemplarily, as shown in FIGS. 2, 6 and 7, a plurality of alignment patterns 100 are located between the base 1 and the buffer layer 50. As shown in FIG.

[0244] For example, the alignment patterns 100 can be used as alignment marks when depositing a mask plate. For example, the alignment patterns can be used as alignment marks for the first conductive layer 2.

[0245] In some examples, the light emitting substrate 10 further comprises a fourth passivation layer 110 .

[0246] Exemplarily, as shown in FIGS. 2, 6 and 7, the fourth passivation layer 110 is disposed between the second conductive layer 4 and the insulating layer 3. As shown in FIGS.

[0247] Illustratively, the material of the fourth passivation layer 110 is an inorganic material, such as silicon nitride, silicon oxide, and the like.

[0248] For example, the fourth passivation layer 110 can be provided to increase the number of film layers between the first conductive layer 2 and the second conductive layer 4. This increases the thickness of the insulating layer between the first conductive layer 2 and the second conductive layer 4, further reducing the probability of a short circuit occurring between the first conductive layer 2 and the second conductive layer 4.

[0249] As shown in FIG. 11, some embodiments of the present disclosure further provide a method for manufacturing a light emitting substrate, which can be used to manufacture the light emitting substrate 10 provided by some of the above embodiments.

[0250] 11 is a flowchart of a method for manufacturing a light emitting substrate according to some embodiments, which includes steps S1 to S6.

[0251] S1, as shown in FIG. 12A, provides base 1.

[0252] Here, for the material of the base 1, the explanations in the above several embodiments may be referred to, and will not be repeated here.

[0253] In some examples, after step S1, the method further includes forming a plurality of alignment patterns 100 on the base 1.

[0254] In some examples, as shown in FIG. 12B, after forming the alignment patterns 100 on the base 1, a step of forming a buffer layer 50 on the alignment patterns 100 may be further included.

[0255] For example, the buffer layer 50 may be formed using chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0256] In some examples, as shown in FIG. 12C, after forming the buffer layer 50 on the plurality of alignment patterns 100, a step of forming a seed layer 01 on the plurality of alignment patterns may be further included.

[0257] For example, the seed layer 01 may be formed by a sputtering process, which can ensure the uniformity of the thickness of the film layer.

[0258] S2, as shown in FIG. 12D, a first conductive layer 2 is formed on the base 1, and the first conductive layer 2 includes a plurality of signal lines 21.

[0259] For example, the first conductive layer 2 may be manufactured as follows: First, a conductive film layer is formed by electroplating or sputtering, and the conductive film layer is made of a metal material with good conductivity, such as copper. Then, the conductive film layer is etched by photolithography to form a conductive pattern on the conductive film layer.

[0260] Here, the conductor pattern refers to the plurality of signal lines 21 and the plurality of binding pins 22 included in the first conductive layer 2.

[0261] The electroplating process, sputtering process, and photolithography process are merely examples of processes used in the manufacturing method, and are not limited to those used in the actual manufacturing process.

[0262] In S3, a first insulating layer 31 is formed on the first conductive layer 2, as shown in FIG. 12E.

[0263] Here, the material and thickness of the first insulating layer 31 may be referred to in the descriptions of the above-mentioned several embodiments, and will not be repeated here.

[0264] For example, the insulating layer may be formed using a magnetron sputtering process, or may be formed using chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0265] In some examples, the method further includes a step of forming a first insulating barrier layer 60 on the first conductive layer 2 before step S3, as shown in FIG. 12E.

[0266] Here, the first insulating barrier layer 60 is used to block the first conductive layer 2 from water and oxygen.

[0267] S4: As shown in FIG. 12F, a first mask plate 001 is placed on the side of the first insulating layer 31 away from the base 1.

[0268] Illustratively, the first mask plate 001 has a frame a, and the frame a blocks at least a part of the edge of the first insulating layer 31 .

[0269] S5, as shown in FIG. 12F, the second insulating layer 32 is formed through the fourth opening 0010 surrounded by the frame of the first mask plate 001, and an insulating layer 3 including the first insulating layer 31 and the second insulating layer 32 is obtained.

[0270] Illustratively, at least a portion of the edge of the first insulating layer 31 exceeds an edge of the second insulating layer 32, forming a step structure. In some examples, after forming the second insulating layer 32, a step of etching the second insulating layer 32 to open a hole and expose a portion of the signal line 21 may be further included.

[0271] In some examples, as shown in FIG. 12G, after forming the second insulating layer 32 through a fourth opening surrounded by the frame of the first mask plate 001, the method may further include forming a fourth passivation layer 110 on the second insulating layer 32.

[0272] S6: A second conductive layer 4 is formed on the side of the second insulating layer 32 away from the base 1, as shown in FIG. 12H.

[0273] Illustratively, the second conductive layer 4 includes a plurality of pads 41. Illustratively, at least some of the pads 41 penetrate the insulating layer 3 and are connected to the signal lines 21.

[0274] For example, the method for manufacturing the second conductive layer is as follows: First, a conductive film layer is formed by electroplating or sputtering, where the conductive film layer is made of a metal material with good conductivity, such as copper, and then the conductive film layer is etched by photolithography to form a conductive pattern on the conductive film layer.

[0275] Here, the conductive pattern refers to a plurality of pads included in the second conductive layer.

[0276] In some examples, the method further includes forming a second insulating barrier layer 70 on the second conductive layer 4 after step S6, as shown in FIG. 12I.

[0277] Here, for the material of the second insulating barrier layer 70, the explanations in the above several embodiments may be referred to, and will not be repeated here.

[0278] In some examples, as shown in FIG. 12J, after forming a second insulating barrier layer 70 on the second conductive layer 4, the method further includes a step of sequentially forming a light-shielding layer 80 and a third insulating layer 90 on the second insulating barrier layer 70.

[0279] For example, both the light-shielding layer 80 and the third insulating layer 90 may be formed using chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0280] The manufacturing method in the above embodiments of the present disclosure is the same as the light-emitting substrate 10 provided in some of the above embodiments. Jiyu This has beneficial effects and will not be repeated here. In some embodiments, the step of forming the first conductive layer 2 on the base 1 includes steps S21 to S25.

[0281] S21, as shown in FIG. 13A, a first conductive film layer 02 is formed on one side of the base 1.

[0282] S22, as shown in FIG. 13B, apply photoresist 03 to the side of the first conductive film layer away from the base 1.

[0283] S23: As shown in FIG. 13B, a second mask plate 002 is placed on the side of the first conductive film layer 02 away from the base 1.

[0284] In step S24, as shown in FIG. 13C, the photoresist is exposed and developed using a second mask plate to form a plurality of photoresist patterns 031.

[0285] For example, the orthogonal projections of the multiple photoresist patterns 031 on the base 1 may overlap with the orthogonal projections of the multiple signal lines 21 to be formed on the base 1.

[0286] S25, as shown in FIG. 13D, using a plurality of photoresist patterns 031 as a mask, the first conductive film layer 02 is etched to form a first conductive layer 2, and the first conductive layer 2 includes a plurality of signal lines 21 located in the display area AA.

[0287] For example, after step S25, the method further includes a step of stripping the photoresist patterns 031.

[0288] The step of forming the first insulating layer 31 on the first conductive layer 2 includes steps S31 to S34.

[0289] In step S31, an organic insulating film 030 is formed on the first conductive layer 2, as shown in FIG. 13E.

[0290] For example, a first portion 0301 of the organic insulating film 030 covers the signal lines 21 , and a second portion 0302 of the organic insulating film surrounds the signal lines 21 .

[0291] In step S32, as shown in FIG. 13E, a second mask plate 002 is placed on the side of the organic insulating film 030 away from the base 1.

[0292] In step S33, as shown in FIG. 13F, the organic insulating film 030 is exposed and developed using the second mask plate 002 to remove the first portion 0301 and leave the second portion 0302, thereby forming the first insulating layer 31.

[0293] Illustratively, one of the material of the organic insulating film 030 and the photoresist 03 is a photodecomposable material, and the other is a photocurable material.

[0294] For example, the material of the photoresist 03 is a photocurable material, and the photoresist 03 at positions corresponding to the plurality of signal lines 21 to be formed is retained after being irradiated with ultraviolet light. The material of the organic insulating film 030 is a photodecomposable material, and the photoresist 03 at positions corresponding to the plurality of signal lines 21 is soluble in an organic or inorganic alkaline aqueous solution and removed after being irradiated with ultraviolet light. That is, because the positions that need to be exposed are the same when forming the first conductive layer 2 and the first insulating layer 31, the same mask plate (i.e., the second mask plate 002) may be used when forming the first conductive layer 2 and the first insulating layer 31.

[0295] In addition, a photodegradable material means a material in which, after being irradiated with ultraviolet light, the photodegrading agent in the irradiated area is decomposed and can be dissolved in an organic or inorganic alkaline aqueous solution, and the unexposed area is retained, forming the same pattern as the master plate.

[0296] Photocurable materials are those that are exposed to ultraviolet light, and the radicals generated in the exposed area form crosslinks between rubber molecules, making them insoluble in the developer. In other words, the exposed area is retained after exposure and development.

[0297] In this embodiment, the first conductive layer 2 and the first insulating layer 31 are both manufactured using a single mask plate (i.e., the second mask plate 002), which simplifies the manufacturing process of the light-emitting substrate 10 and significantly reduces manufacturing costs.

[0298] As shown in FIG. 14, some embodiments of the present disclosure further provide a display device 1000 including the light emitting substrate 10 according to any of the above embodiments.

[0299] In some embodiments, the light-emitting substrate 10 is used for display, i.e., the light-emitting substrate 10 can directly function as a display panel to display a screen, and the display device 1000 is an active light-emitting display device. In this case, the light-emitting substrate 10 itself can emit light, eliminating the need for a separate backlight module, and the light-emitting substrate 10 can directly function as a display panel to display the screen to be displayed.

[0300] In some examples, the display target screen is the target display screen of the display device 1000, and may be an all-black screen, an all-white screen, a color screen, or the like.

[0301] For example, when the display target screen is a color screen, the plurality of light-emitting elements located in the same display unit region include light-emitting elements of at least three colors, and by controlling the light-emitting intensities of the light-emitting elements in different display unit regions, red light, green light, and blue light of different intensities can be obtained, so that the display device 1000 can realize full-color image display.

[0302] For example, the display device 1000 is a transparent display device, and the base 1 is made of a transparent material, such as glass. Using glass for the base 1 allows for two-way light transmission, making it suitable for applications such as indoor partitions and transparent display screens.

[0303] In some other embodiments, the light-emitting substrate 10 is applied to a backlight, and the display device 1000 is a liquid crystal display device. In this case, the display device 1000 further includes a liquid crystal display panel, and the light-emitting substrate 10 serves as a light source in a backlight module to provide backlight for the display panel, which is used to display the target screen.

[0304] The light-emitting element 7 includes, but is not limited to, a Mini LED (Mini Light-Emitting Diode), a Micro LED (Micro Light-Emitting Diode), and the like.

[0305] The use of miniature or micro LEDs as light emitting elements 7 has the advantages of a smaller occupied volume, smaller particles, a higher light source density per unit area for the same screen size, and a better light source unit size compared to conventional LEDs. Small Therefore, more precise local control can be achieved for the light emitting elements 7, and the problem of uneven brightness of the light emitting elements 7 is less likely to occur. That is, the light emitting substrate 10 serves as a backlight module to provide a backlight for the display panel, thereby ensuring uniform brightness of the backlight and ensuring the display quality of the display device 1000.

[0306] The above are merely specific embodiments of the present disclosure, and the scope of protection of the present disclosure is not limited thereto. Any modifications or replacements that can be easily thought of by a person skilled in the art within the technical scope of the present disclosure are intended to be embraced within the technical scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be governed by the scope described in the claims.

Claims

1. a light-emitting substrate having a display area and a peripheral area located on at least one side of the display area, the peripheral area including a first peripheral area, the first peripheral area and the display area being spaced apart along a first direction; The light emitting substrate is With the base, a first conductive layer disposed on the base, the first conductive layer including a plurality of signal lines located in the display area; an insulating layer covering the plurality of signal lines; a second conductive layer disposed on the insulating layer; Equipped with the insulating layer includes a first insulating layer and a second insulating layer sequentially stacked along a direction away from the base, and at least a part of an edge of the first insulating layer extends beyond an edge of the second insulating layer at least between the first peripheral region and the display region; Light-emitting substrate.

2. At least between the first peripheral region and the display region, an inclination angle of at least a part of an edge of the first insulating layer and an inclination angle of an edge of the second insulating layer are both 45° or less. The light-emitting substrate according to claim 1 .

3. an edge of at least a portion of the first insulating layer includes a first slope; an edge of the second insulating layer includes a second slope; the first slope and the second slope are connected by a first plane on the first insulating layer; The light-emitting substrate according to claim 2 .

4. the second conductive layer includes a plurality of pads located in the display area, the plurality of signal lines and the plurality of pads are located in the display area, the plurality of signal lines extend along a first direction and are spaced apart along a second direction, the second direction intersecting the first direction; The light emitting substrate is a plurality of conductive portions located in the first peripheral region, the plurality of conductive portions being located in the second conductive layer; an end of the conductive portion close to the display area is stacked on edges of the first insulating layer and the second insulating layer, extends to the display area, and penetrates the insulating layer to be connected to the signal line; The light emitting substrate according to any one of claims 1 to 3.

5. the second insulating layer is located in the first peripheral region and between the base and the conductive portion; The light-emitting substrate according to claim 4 .

6. the distance by which at least a portion of the edge of the first insulating layer extends beyond the edge of the second insulating layer is in the range of 20 μm to 40 μm; and / or The light-emitting substrate according to any one of claims 1 to 3, wherein the insulating layer has a thickness h1, the first conductive layer has a thickness h2, and h1 and h2 satisfy the following formula (1):

7. the ratio of the thickness of the first insulating layer to the thickness of the second insulating layer is greater than 0.9 and less than 1.1; and / or the thickness of the first insulating layer is equal to or less than the thickness of the first conductive layer; the first insulating layer surrounds each of the signal lines; The light emitting substrate according to any one of claims 1 to 3.

8. the thickness of the second conductive layer is less than the thickness of the first conductive layer; and / or The thickness of the second insulating layer is 7.5 μm or more. The light emitting substrate according to any one of claims 1 to 3.

9. The display device further includes a first passivation layer disposed between the first insulating layer and the second insulating layer, the second conductive layer including a plurality of pads located in the display area, and at least some of the pads are connected to the signal lines through the insulating layer and the first passivation layer; or The display device further includes a first passivation layer disposed between the first insulating layer and the second insulating layer, the second conductive layer including a plurality of pads located in the display area, at least some of the pads passing through the insulating layer and the first passivation layer and connected to the signal lines, and at least some edges of the first insulating layer extend beyond edges of the first passivation layer, and at least some edges of the first passivation layer extend beyond edges of the second insulating layer. The light emitting substrate according to any one of claims 1 to 3.

10. the second insulating layer includes a first sub-insulating layer and a second sub-insulating layer stacked in sequence along a direction away from the base, and the second conductive layer includes a plurality of pads located in a display unit area; The light emitting substrate further includes a second passivation layer disposed between the first sub-insulation layer and the second sub-insulation layer; The pad further passes through the second passivation layer and is connected to the signal line; or The pad is further connected to the signal line through the second passivation layer, and at least a portion of an edge of the first sub-insulating layer extends beyond an edge of the second passivation layer, and at least a portion of an edge of the second passivation layer extends beyond an edge of the second sub-insulating layer. The light emitting substrate according to any one of claims 1 to 3.

11. The display area includes a plurality of display unit areas, the second conductive layer includes a plurality of pad pairs located in each display unit area, each pad pair includes two pads, the two pads being a first pad and a second pad, respectively; the light emitting substrate is located in the display unit area, and further includes at least one light emitting element and a driving chip located on the second conductive layer, the light emitting element being connected to one pad pair, and the driving chip being connected to at least two pad pairs; a first pad of each of the pad pairs is connected to a signal line; Among a plurality of pad pairs located in the same display unit area, a second pad of the pad pair connected to the light emitting element is connected to a second pad of the pad pair connected to the driving chip; The light emitting substrate according to any one of claims 1 to 3.

12. a third passivation layer disposed between the insulating layer and the second conductive layer; At least one raised portion located in the display unit area, the raised portion being disposed between the insulating layer and the third passivation layer; Furthermore, An orthogonal projection of the pad on the base partially overlaps with an orthogonal projection of the raised portion on the base; or an orthogonal projection of the pad on the base partially overlaps with an orthogonal projection of the raised portion on the base, the first pad includes a first sub-portion and a second sub-portion that are connected together, the first sub-portion is connected to the signal line, and the orthogonal projection of the second sub-portion on the base is located within a range of the orthogonal projection of the raised portion on the base; The light-emitting substrate according to claim 11 .

13. A method for manufacturing a light emitting substrate, the light-emitting substrate has a display area and a peripheral area located on at least one side of the display area; The manufacturing method includes: providing a base; forming a first conductive layer on the base, the first conductive layer including a plurality of signal lines; forming a first insulating layer on the first conductive layer; placing a first mask plate on a side of the first insulating layer away from the base, the first mask plate having a frame, and the frame blocking at least a portion of an edge of the first insulating layer; forming a second insulating layer through a fourth opening surrounded by a frame of the first mask plate, to obtain an insulating layer including the first insulating layer and the second insulating layer, wherein at least a portion of an edge of the first insulating layer extends beyond an edge of the second insulating layer; forming a second conductive layer on a side of the second insulating layer away from the base, the second conductive layer including a plurality of pads, at least some of the pads being connected to signal lines through the insulating layer; Including, A method for manufacturing a light-emitting substrate.

14. forming a first conductive layer on one side of the base; forming a first conductive film layer on one side of the base; applying a photoresist to a side of the first conductive film layer away from the base; placing a second mask plate on a side of the first conductive film layer away from the base; exposing and developing the photoresist using the second mask plate to form a plurality of photoresist patterns; etching the first conductive film layer using the plurality of photoresist patterns as a mask to form a first conductive layer, the first conductive layer including a plurality of signal lines located in the display area; Including, forming a first insulating layer on one side of the base; forming an organic insulating film on the first conductive layer, a first portion of the organic insulating film covering the plurality of signal lines and a second portion of the organic insulating film surrounding the signal lines; placing the second mask plate on a side of the organic insulating film away from the base; exposing and developing the organic insulating film using the second mask plate to remove the first portion and retain the second portion, thereby forming the first insulating layer; Including, one of the organic insulating film material and the photoresist is a photodecomposable material, and the other is a photocurable material; The method for manufacturing the light emitting substrate according to claim 13 .

15. A light emitting substrate according to any one of claims 1 to 3, Display device.

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