Techniques for hybrid digital / analog processors for quantum computers

Abstract

Techniques for hybrid digital / analog processors for quantum computers are disclosed. In exemplary embodiments, the hybrid digital / analog processor may be capable of processing digital instructions as well as analog instructions. Digital instructions may, for example, read from or write to memory or registers, perform arithmetic operations, perform branches, etc. Analog instructions may, for example, provide an analog voltage to a particular electrode of a qubit, provide an analog pulse to a qubit, measure the reflection of an analog signal from the qubit, etc. The integration of analog operations in a hybrid digital / analog processor may improve performance, for example, through reduced latency and reduced power consumption.

Description

[Background technology]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims the benefit of and priority to U.S. Utility Patent Application No. 17 / 954,131, entitled TECHNOLOGIES FOR HYBRID DIGITAL / ANALOG PROCESSORS FOR A QUANTUM COMPUTER, filed September 27, 2022. The disclosure of the prior application is hereby incorporated by reference in its entirety and is hereby deemed part of the disclosure of this application.

[0002] Quantum computers promise computational capabilities not possible with classical computation. One of the many challenges in quantum computing is high-speed, low-latency communication with large numbers of qubits. Techniques such as finite state machines can manage relatively small numbers of qubits, but are infeasible for large numbers of qubits. The circuitry managing the qubits must be close to the qubits to reduce latency. However, circuits close to the qubits, for example in dilution refrigerators, [Brief explanation of the drawings]

[0003] [Figure 1A] 1A-1C illustrate various views of an exemplary quantum dot device according to one embodiment. [Figure 1B] 1A-1C illustrate various views of an exemplary quantum dot device according to one embodiment. [Figure 1C] 1A-1C illustrate various views of an exemplary quantum dot device according to one embodiment. [Figure 1D] 1A-1C illustrate various views of an exemplary quantum dot device according to one embodiment. [Figure 1E] 1A-1C illustrate various views of an exemplary quantum dot device according to one embodiment. [Figure 1F] 1A-1C illustrate various views of an exemplary quantum dot device according to one embodiment.

[0004] [Figure 2]FIG. 1 is a simplified block diagram of at least one embodiment of a quantum compute device.

[0005] [Figure 3] FIG. 3 is a simplified block diagram of at least one embodiment of a portion of the quantum compute device of FIG. 2.

[0006] [Figure 4] FIG. 1C is a simplified block diagram of at least one embodiment of a hybrid digital / analog processor of the quantum compute device of FIGS. 1A-1F.

[0007] [Figure 5] FIG. 1B is a simplified block diagram of at least one embodiment of a multi-core hybrid digital / analog processor of the quantum compute device of FIGS. 1A-1F.

[0008] [Figure 6] FIG. 3 is a simplified block diagram of at least one embodiment of a portion of the quantum compute device of FIG. 2 having multiple hybrid digital / analog processors.

[0009] [Figure 7] FIG. 3 is a simplified block diagram of at least one embodiment of an environment that may be established by the quantum compute device of FIG. 2.

[0010] [Figure 8] 5 is a simplified flow diagram of at least one embodiment of a method for executing a program on the hybrid digital / analog processor of FIG. 4.

[0011] [Figure 9] 3 is a simplified flow diagram of at least one embodiment of a method for executing a program by the quantum compute device of FIG. 2.

[0012] [Figure 10]FIG. 2 is a top view of a wafer and die according to any of the embodiments disclosed herein.

[0013] [Figure 11] 1 is a cross-sectional side view of an integrated circuit according to any of the embodiments disclosed herein.

[0014] [Figure 12A] 1A and 1B are perspective views of exemplary planar gate-all-around and stacked gate-all-around transistors; [Figure 12B] 1A and 1B are perspective views of exemplary planar gate-all-around and stacked gate-all-around transistors; [Figure 12C] 1A and 1B are perspective views of exemplary planar gate-all-around and stacked gate-all-around transistors; [Figure 12D] 1A and 1B are perspective views of exemplary planar gate-all-around and stacked gate-all-around transistors;

[0015] [Figure 13] 1 is a cross-sectional side view of an integrated circuit device assembly according to any of the embodiments disclosed herein.

[0016] [Figure 14] FIG. 1 is a block diagram of an exemplary electrical device according to any of the embodiments disclosed herein. DETAILED DESCRIPTION OF THE INVENTION

[0017] Aspects of the present disclosure include a quantum compute device having a hybrid digital / analog processor. In an exemplary embodiment, the hybrid digital / analog processor is located within a dilution refrigerator close to the qubits of the quantum compute device. During use, the processor of the quantum compute device sends instructions to the hybrid digital / analog processor. The processor may send digital instructions as well as analog instructions. Digital instructions may include, for example, reading from and writing to memory, arithmetic operations, conditional branching, reading from and writing to registers, etc. Analog instructions may include instructions for generating or reading analog pulses that are sent to and received from the qubits. The hybrid digital / analog processor may be able to coordinate operations on the qubits with lower latency, lower power, and better synchronization than using a digital processor with separate analog signal processing circuitry.

[0018] In the following description, specific details are set forth; however, embodiments of the technology described herein may be practiced without these specific details. Well-known circuits, structures, and techniques have not been shown in detail to avoid obscuring an understanding of this specification. Phrases such as "one embodiment," "various embodiments," "some embodiments," etc. may include a feature, structure, or characteristic, but not all embodiments necessarily include the particular feature, structure, or characteristic.

[0019] In the following description, for purposes of explanation, numerical and specific details are set forth to provide an understanding thereof. However, it will be apparent that these novel embodiments may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form to facilitate their description. It is intended to cover all modifications, equivalents, and alternatives within the scope of the claims.

[0020] Some embodiments may have some, all, or none of the features described for other embodiments. "First," "second," "third," etc., describe a common object and indicate that different instances of the same object are being referred to. Such adjectives do not imply that the objects so described need be in a given order, sequence, or any other manner, either temporally or spatially. "Connected" can indicate that elements are in direct physical or electrical contact, and "coupled" can indicate that elements cooperate or interact, but they may or may not be in direct physical or electrical contact. Furthermore, terms such as "comprises," "includes," and "has," as used with respect to embodiments of the present disclosure, are synonymous. Terms modified by "substantially" include arrangements, orientations, spacing, or positions that differ slightly from the meaning of the unmodified term. For example, a feature of a substrate assembly, such as a through-width, described as having substantially a recited dimension may vary within a few percent of the recited dimension.

[0021] As used herein, the phrase "communicatively coupled" refers to the ability of a component to transmit signals to or receive signals from another component. The signal may be any type of signal, such as an input signal, an output signal, or a power signal. A component may transmit signals to or receive signals from another component to which it is communicatively coupled via a wired or wireless communication medium (e.g., conductive traces, conductive contacts, air). Examples of communicatively coupled components may include integrated circuit dies located in the same package that communicate via embedded bridges in the package substrate, and integrated circuit components mounted on a printed circuit board that transmit signals to or receive signals from other integrated circuit components or electronic devices mounted on the printed circuit board.

[0022] In the examples shown and further described below, it is understood that the figures may not be drawn to scale and may not include all possible layers and / or circuit components. Additionally, while particular figures show transistor designs having source / drain regions, electrodes, etc. with orthogonal (e.g., vertical) boundaries, it is understood that embodiments herein may implement such boundaries in a substantially orthogonal manner (e.g., + / - 5 or 10 degrees of orthogonality) due to the fabrication methods used to create such devices or for other reasons.

[0023] As used herein, the term "located" in the context of a first layer or component located on a second layer or component refers to the first layer or component being physically attached directly to the second part or component (with no layers or components between the first and second layers or components) or being physically attached to the second layer or component with one or more intervening layers or components.

[0024] As used herein, the term "adjacent" refers to layers or components that are in physical contact with one another. That is, there are no layers or components between the designated adjacent layers or components. For example, layer X adjacent to layer Y refers to the layer that is in physical contact with layer Y.

[0025] As used herein, the terms "top" / "bottom" or "above" / "below" may refer to the relative location of an object (e.g., the surfaces described above) rather than the absolute location of the object, particularly in light of the examples shown in the accompanying figures. For example, the top surface of a device may be on the opposite side of the device from the bottom surface of the object, and the top surface may generally face upward only when viewed in a particular way. As another example, a first object that is above a second object may be on or near the "top" surface of the second object but not near the "bottom" surface of the object, and the first object may only truly be above the second object when the two objects are viewed in a particular way.

[0026] Reference is made to the drawings, which are not necessarily drawn to scale, and like or identical numbers may be used to designate the same or similar parts in different figures. The use of like or identical numbers in different figures does not imply that all figures containing like or identical numbers constitute a single or the same embodiment. Like numbers with different letter suffixes may represent different instances of similar components. The drawings generally illustrate, by way of example, and not by way of limitation, various embodiments discussed herein.

[0027] Quantum computers use quantum mechanical phenomena such as superposition and entanglement to perform calculations, simulations, or other functions. In contrast to digital computers, which store data in one of two definite states (0 or 1), quantum computing uses quantum bits (qubits), which can be in a superposition of states. Qubits may be implemented using physically distinguishable quantum states of elementary particles such as electrons and photons. For example, the polarization of a photon may be used where the two states are vertical and horizontal polarization. Similarly, the spin of an electron may have distinguishable states such as "up spin" and "down spin." A qubit in a quantum mechanical system may be in a superposition of both states simultaneously, which is an inherent and fundamental feature of quantum computing.

[0028] Quantum computing systems execute algorithms that involve quantum logic operations performed on qubits. In some cases, the results of the algorithms are not deterministic. Quantum algorithms can be repeated multiple times to determine the statistical distribution of results or to increase the likelihood of finding the correct answer. In some cases, classical algorithms can be used to verify whether the quantum computer has determined the correct result.

[0029] Qubits have been implemented using a variety of different technologies capable of manipulating and reading quantum states. These include, but are not limited to, quantum dot devices (spin-based and spatially-based), ion trap devices, superconducting quantum computers, optical lattices, nuclear magnetic resonance computers, solid-state NMR Kane quantum devices, electron-on-helium quantum computers, cavity quantum electrodynamics (CQED) devices, molecular magnet computers, and fullerene-based ESR quantum computers, to name a few. Thus, although quantum dot devices are described below in connection with specific embodiments of the present invention, the underlying principles of the present invention may be used in combination with any type of quantum computer, including, but not limited to, those listed above. The particular physical implementation used for the qubits is not necessarily required for the embodiments of the invention described herein.

[0030] Quantum dots are small semiconductor particles, typically a few nanometers in size. Because of their small size, quantum dots behave according to the rules of quantum mechanics and have optical and electronic properties that differ from their macroscopic counterparts. Quantum dots are sometimes referred to as "artificial atoms," to allude to the fact that they are single objects with distinct, confined electronic states, as in the case of atoms or molecules.

[0031] 1A-1F are various views of a quantum dot device 100, which may be used in embodiments of the invention described below. FIG. 1A is a top view of a portion of quantum dot device 100 with some of the material removed so that a first gate line 102, a second gate line 104, and a third gate line 106 are visible. Many of the figures and descriptions herein may refer to a particular set of lines or gates as "barrier" or "quantum dot" lines or gates, respectively, but this is merely for ease of discussion; in other embodiments, the roles of the "barrier" and "quantum dot" lines and gates may be reversed (e.g., a barrier gate may instead act as a quantum dot gate, and vice versa). 1B to 1F are cross-sectional side views of the quantum dot device 100 of FIG. 1A. Specifically, FIG. 1B is a view through the BB section of FIG. 1A, FIG. 1C is a view through the CC section of FIG. 1A, FIG. 1D is a view through the DD section of FIG. 1A, FIG. 1E is a view through the EE section of FIG. 1A, and FIG. 1F is a view through the FF section of FIG. 1A.

[0032] 1A-1F may be operated in any of several ways. For example, in some embodiments, an electrical signal, such as a voltage, a current, a radio frequency (RF), and / or a microwave signal, may be provided to one or more of the first gate line 102, the second gate line 104, and / or the third gate line 106 to cause quantum dots (e.g., electron spin-based quantum dots or hole spin-based quantum dots) to form in the quantum well stack 146 beneath the third gate 166 of the third gate line 106. An electrical signal provided to the third gate line 106 may control the potential of the quantum well under the third gate 166 of that third gate line 106, while an electrical signal provided to the first gate line 102 (and / or the second gate line 104) may control the potential energy barrier between adjacent quantum wells under the first gate 162 of that first gate line 102 (and / or the second gate 164 of that second gate line 104). Quantum interactions between quantum dots in different quantum wells in the quantum well stack 146 (e.g., under different quantum dot gates) may be controlled in part by the potential energy barrier provided by a barrier potential imposed between them (e.g., by intervening barrier gates).

[0033] Generally, the quantum dot device 100 disclosed herein may further include a magnetic field source (not shown) that can be used to create an energy difference in a normally decaying quantum dot state (e.g., the spin state of an electron spin-based quantum dot), and the quantum dot state (e.g., the spin state) may be manipulated by applying electromagnetic energy to the gate line to create a computationally capable qubit. The magnetic field source may be one or more magnet lines. Thus, the quantum dot device 100 disclosed herein may be capable of manipulating the position, number, and quantum state (e.g., spin) of quantum dots in the quantum well stack 146 through the controlled application of electromagnetic energy.

[0034] In the quantum dot device 100 of FIGS. 1A-1F, a gate dielectric 114 may be disposed on a quantum well stack 146. The quantum well stack 146 may include at least one quantum well layer (not shown in FIG. 1A) in which quantum dots may be localized during operation of the quantum dot device 100. The gate dielectric 114 may be any suitable material, such as a high-k material. Multiple parallel first gate lines 102 may be disposed on the gate dielectric 114, and spacer material 118 may be disposed on the sides of the first gate lines 102. In some embodiments, a patterned hard mask 110 may be disposed on the first gate lines 102 (in a pattern corresponding to the pattern of the first gate lines 102), and the spacer material 118 may extend to the sides of the hard mask 110, as shown. Each of the first gate lines 102 may be a first gate 162. Different ones of the first gate lines 102 may be electrically controlled in any desired combination (e.g., each first gate line 102 may be electrically controlled separately, or some or all of the first gate lines 102 may be shorted together in one or more groups, as desired).

[0035] Multiple parallel second gate lines 104 may be disposed over and between the first gate lines 102. As illustrated in FIG. 1A, the second gate lines 104 may be aligned perpendicular to the first gate lines 102. The second gate lines 104 may extend over the hard mask 110, as illustrated in FIG. 1D, and may include second gates 164 that extend down toward the quantum well stack 146 and contact the gate dielectric 114 between adjacent ones of the first gate lines 102. In some embodiments, the second gates 164 may fill the areas between adjacent ones of the first gate line 102 / spacer material 118 structures; in other embodiments, an insulating material (not shown) may be present between the first gate line 102 / spacer material 118 structure and adjacent second gates 164. In some embodiments, spacer material 118 may be disposed on the sides of the second gate lines 104. In other embodiments, spacer material 118 may not be disposed on the sides of the second gate lines 104. In some embodiments, a hard mask 115 may be disposed above the second gate lines 104. The multiple gates of the second gates 164 of the second gate lines 104 are electrically continuous (due to the shared conductive material of the second gate lines 104 on the hard mask 110). Different ones of the second gate lines 104 may be electrically controlled in any desired combination (e.g., each second gate line 104 may be electrically controlled separately, or some or all of the second gate lines 104 may be shorted together in one or more groups, as desired). The first gate lines 102 and the second gate lines 104 together may form a grid, as depicted in FIG. 1A.

[0036] Multiple parallel third gate lines 106 may be disposed over and between the first gate lines 102 and the second gate lines 104. As shown in FIG. 1A , the third gate lines 106 may be arranged diagonally relative to the first gate lines 102 and diagonally relative to the second gate lines 104. In particular, the third gate lines 106 may be arranged diagonally over openings in the grid formed by the first gate lines 102 and the second gate lines 104. The third gate lines 106 may include third gates 166 that extend down to the gate dielectric 114 within openings in the grid formed by the first gate lines 102 and the second gate lines 104, such that each third gate 166 may be bounded by two different first gate lines 102 and two different second gate lines 104. In some embodiments, the third gates 166 may be bounded by insulating material 128, while in other embodiments, the third gates 166 may fill openings in the grid (e.g., in contact with spacer material 118 flanking adjacent first and second gate lines 102 and 104, not shown). Additional insulating material 117 may be disposed over and / or around the third gate lines 106. The multiple gates of the third gates 166 of the third gate lines 106 are electrically continuous (due to the shared conductive material of the third gate lines 106 over the first and second gate lines 102 and 104). Different ones of the third gate lines 106 may be electrically controlled in any desired combination (e.g., each third gate line 106 may be electrically controlled separately, or some or all of the third gate lines 106 may be shorted together in one or more groups, as desired).

[0037] 1A-1F illustrate a particular number of first gate lines 102, second gate lines 104, and third gate lines 106, this is for illustrative purposes only, and any number of first gate lines 102, second gate lines 104, and third gate lines 106 may be included in the quantum dot device 100. Other example arrangements of the first gate lines 102, second gate lines 104, and third gate lines 106 are possible. Electrical interconnects (e.g., vias and conductive lines) may contact the first gate lines 102, second gate lines 104, and third gate lines 106 in any desired manner.

[0038] Although not shown in FIG. 1A , there is an accumulation region that can be electrically coupled to the quantum well layer of the quantum well stack 146 (e.g., laterally adjacent to the quantum well layer). The accumulation region may be separated from the gate line by a thin layer of intervening dielectric material. The accumulation region may be a region where carriers accumulate (e.g., by doping or by the presence of a large electrode that draws carriers into the quantum well layer) and may serve as a reservoir of carriers that can be selectively drawn into the area of ​​the quantum well layer under the third gate 166 (e.g., by controlling the voltages on the quantum dot gate, first gate 162, and second gate 164) to form a carrier-based quantum dot (e.g., an electron or hole quantum dot, including a single charge carrier, a plurality of charge carriers, or no charge carriers at all). In other embodiments, the quantum dot device 100 may not include a lateral accumulation region but instead include a doped layer within the quantum well stack 146. Such a doped layer may provide carriers to the quantum well layer. Any combination of accumulation regions or doped layers (eg, doped or undoped) within the quantum well stack 146 may be used in any of the embodiments of the quantum dot device 100 disclosed herein.

[0039] Referring now to FIG. 2, a simplified block diagram of a quantum compute device 200 is shown. In some embodiments, quantum compute device 200 may include quantum dot device 100 described above with respect to FIGS. 1A-1F. Quantum compute device 200 may be embodied as or included in any type of compute device. For example, quantum compute device 200 may include or otherwise be included in, without limitation, a server computer, an embedded computing system, a system-on-a-chip (SoC), a multiprocessor system, a processor-based system, a consumer electronic device, a desktop computer, a laptop computer, a network device, a networked computer, a distributed computing system, and / or any other computing device. The exemplary quantum compute device 200 includes a processor 202, a memory 204, an input / output (I / O) subsystem 206, a quantum / classical interface circuit 208, and a quantum processor 210. In some embodiments, one or more of the illustrated components of quantum compute device 200 may be incorporated into or otherwise form a part of another component. For example, memory 204, or a portion thereof, may be incorporated into processor 202 in some embodiments. In some embodiments, quantum compute device 200 may be embodied as, or include any suitable components of, electrical device 1400, described below with respect to FIG. 14 .

[0040] In some embodiments, quantum compute device 200 may be located in a datacenter with other compute devices, such as an enterprise datacenter (e.g., a datacenter owned and operated by a company and typically located on the company's premises), a managed service datacenter (e.g., a datacenter managed by a third party on behalf of a company), a co-located datacenter (e.g., a datacenter where the datacenter infrastructure is provided by a datacenter host and the company provides and manages their own datacenter components (e.g., servers)), a cloud datacenter (e.g., a datacenter operated by a cloud service that hosts a company's applications and data), and an edge datacenter (e.g., a datacenter with a smaller footprint than other datacenter types, typically located near the geographic area it serves), a micro datacenter, etc. In some embodiments, quantum compute device 200 may receive a job for execution on quantum processor 210 over a network (e.g., the Internet). Quantum compute device 200 may execute the job on quantum processor 210 and send the result back to the requesting device.

[0041] Processor 202 may be embodied as any type of processor capable of performing the functions described herein. For example, processor 202 may be embodied as a single or multi-core processor, a single or multi-socket processor, a digital signal processor, a graphics processor, a neural network computation engine, an image processor, a microcontroller, or other processor or processing / control circuitry. Processor 202 may include multiple processor cores. In some embodiments, processor 202 may support quantum extensions to the existing ISA of processor core 202, thereby enabling instructions to interface with quantum / classical interface circuit 208 and quantum processor 210.

[0042] Memory 204 may be embodied as any type of volatile or non-volatile memory or data storage capable of performing the functions described herein. During operation, memory 204 may store various data and software used during operation of quantum compute device 200, such as an operating system, applications, programs, libraries, and drivers. Memory 204 is communicatively coupled to processor 202 via I / O subsystem 206, which may be embodied as circuits and / or components for facilitating I / O operations with processor 202, memory 204, and other components of quantum compute device 200. For example, I / O subsystem 206 may be embodied as or otherwise include a memory controller hub, an I / O control hub, a firmware device, a communication link (e.g., a point-to-point link, a bus link, a wire, a cable, a light guide, a printed circuit board trace, etc.), and / or other components and subsystems for facilitating I / O operations. I / O subsystem 206 may connect various internal and external components of quantum compute device 200 to one another using any suitable connectors, interconnects, buses, protocols, etc., such as SoC fabric, PCIe®, USB2, USB3, USB4, NVMe®, Thunderbolt®, Compute Express Link (CXL), and / or the like. In some embodiments, I / O subsystem 206 may form part of a system-on-chip (SoC) and may be integrated onto a single integrated circuit chip with processor 202 and memory 204 and other components of quantum compute device 200.

[0043] Quantum / classical interface circuit 208 is configured to interface with both classical components of quantum compute device 200, such as processor 202 and memory 204, as well as quantum processor 210. Quantum / classical interface circuit 208 may include a variety of analog or digital circuits, such as analog-to-digital converters, digital-to-analog converters, high-gain amplifiers, low-noise amplifiers, cryogenic amplifiers, field-programmable gate arrays (FPGAs), classical processors, application-specific integrated circuits (ASICs), signal conditioning circuits, etc. In some embodiments, some or all of quantum / classical interface circuit 208 may be inside a refrigerator, such as a dilution refrigerator, a magnetic refrigerator, a helium-4 and / or helium-3 refrigerator, etc. Some or all of the components of quantum / classical interface circuit 208 may be at any suitable temperature, such as 10 millikelvin, 100 millikelvin, 4 Kelvin, 20 Kelvin, 77 Kelvin, room temperature, or higher, or anywhere in between.

[0044] Quantum processor 210 is configured to operate on one or more qubits. The qubits may be any suitable type of qubit, for example, the quantum dot spin qubits described above with respect to FIGS. 1A-1F. In other embodiments, the qubits may be, for example, charge qubits, transmon qubits, microwave qubits, superconducting qubits, or any other suitable type of qubit. Quantum processor 210 may operate on any suitable number of physical or logical qubits, for example, 1 to 10 6 In an exemplary embodiment, some or all of quantum processor 210 is located within a refrigerator, such as a dilution refrigerator. In particular, in an exemplary embodiment, the qubits are held at a temperature of about 10 millikelvin. In other embodiments, the qubits may be held at any suitable temperature, for example, 1-100 millikelvin or higher, depending on the temperature sensitivity of the particular qubit being used.

[0045] Quantum processor 210 may be able to control the various qubits in various ways, such as by performing two-qubit gates, three-qubit gates, error correction operations, transferring states from one type of qubit to another, measuring some, any, or all of the qubits, initializing some, any, or all of the qubits, etc.

[0046] Quantum compute device 200 may include additional components not shown in FIG. 2, such as one or more data storage devices, a network interface controller, one or more peripheral devices, etc.

[0047] 3, in one embodiment, quantum processor 210 and some or all of quantum / classical interface circuit 208 may be within a cryogenic refrigerator 300. Quantum / classical interface circuit 208 includes a hybrid digital / analog processor 302 that may interface with a companion chip 308. Hybrid digital / analog processor 302 may also be referred to as an auxiliary processor, an adjunct processor, or simply a processor. Hybrid digital / analog processor 302 may be connected to companion chip 308 by one or more wires 310. Wires 310 may be embodied as one or more cables, buses, twisted wire pairs, etc.

[0048] In an exemplary embodiment, the hybrid digital / analog processor 302 may be in a first stage 316 of the cryogenic refrigerator 300, and the companion chip 308 and quantum processor 210 may be in a second stage 318 of the cryogenic refrigerator 300. In an exemplary embodiment, the first stage 316 is maintained at a temperature of approximately 4 Kelvin, and the second stage 318 is maintained at a temperature of approximately 20 milliKelvin. In other embodiments, the first stage 316 may be maintained at, for example, 1-77 Kelvin, and the second stage 318 may be maintained at, for example, 10-100 milliKelvin. In some embodiments, various components of FIG. 3 may be in different stages than those shown in FIG. 3, and / or the refrigerator 300 may include additional stages, for example, one or more stages at a higher or lower temperature than the first stage 316 and / or the second stage 318. Cryogenic refrigerator 300 can be any suitable refrigerator with active or passive cooling, such as a dilution refrigerator, a magnetic refrigerator, a Helium-4 and / or Helium-3 refrigerator, or the like.

[0049] In use, and as described in more detail below with respect to FIGS. 4-6 , hybrid digital / analog processor 302 receives instructions from another component of quantum compute device 200 (e.g., from processor 202 or memory 204). The instructions may be digital instructions, such as those read from or written to memory, those read from or written to registers, conditional branches, etc. The instructions may also be analog instructions, such as instructions to generate or receive an analog pulse, set an analog voltage on a qubit, set a digital voltage on a multiplexer that selects a qubit, etc. Hybrid digital / analog processor 302 may send and receive digital and / or analog signals to companion chip 308. Signals for multiple qubits may be sent over wires 310 from hybrid digital / analog processor 302 to companion chip 308, and companion chip 308 may demultiplex the signals from hybrid digital / analog processor 302, for example, by using frequency multiplexing, time multiplexing, etc. As such, hybrid digital / analog processor 302 may send and receive analog signals to and from a relatively large number of qubits over a relatively few wires 310. For example, for each wire 310 that carries an analog signal to / from hybrid digital / analog processor 302, hybrid digital / analog processor 302 may control between 2 and 100 qubits. Additionally or alternatively, in some embodiments, hybrid digital / analog processor 302 may send and receive analog and / or digital signals directly to or from quantum processor 210, without necessarily going through companion chip 308.

[0050] Referring now to FIG. 4 , in one embodiment, hybrid digital / analog processor 302 includes a processor core 402, memory 404, input / output (I / O) 406, interconnect 408, and debug access port (DAP) 410. Processor core 402 includes instruction management circuitry 412, digital execution circuitry 414, and analog execution circuitry 416. In an exemplary embodiment, hybrid digital / analog processor 302 is based on a von Neumann architecture. In an exemplary embodiment, hybrid digital / analog processor 302 is embodied as an integrated circuit having one or more semiconductor dies, one or more circuit boards having interconnect layers, or the like. Hybrid digital / analog processor 302 may be embodied as a system-on-chip. Hybrid digital / analog processor 302 may use an architecture having any suitable number of bits, for example, a 32-bit or 64-bit architecture. The instruction set of the hybrid digital / analog processor 302 includes both digital and analog instructions and may be an extension or modification of an existing instruction set, such as x86, or may be a different instruction set.

[0051] The memory 404 may be embodied as any suitable type or amount of memory, for example, one or more levels of SRAM cache. The I / O 406 allows digital input and output to and from the hybrid digital / analog processor 302. The interconnect 408 allows communication between the various components of the hybrid digital / analog processor 302. The DAP 410 allows debugging of operations on the hybrid digital / analog processor 302.

[0052] The instruction management circuit 412 includes a fetch / stream module 418, a decode module 422, and a distribution module 424. The fetch / stream module 418 retrieves or streams the next instruction or set of instructions. The fetch / stream module 418 may receive instructions from on-processor memory 404 or from another component of the quantum compute device 200, such as the processor 202 or memory 204. The decode module 422 is configured to decode the instruction and determine what the instruction is, and in particular whether it should be executed by the digital execution circuit 414 or the analog execution circuit 416. The distribution module 424 sends the instruction to the digital execution circuit 414 or the analog execution circuit 416, as appropriate.

[0053] Digital execution circuitry 414 executes digital instructions. Digital instructions may, for example, be read from or written to a memory (e.g., memory 404 or memory 204), read from or written to a register (e.g., a register in core 402), a conditional branch, etc. Digital instructions may be arithmetic operations that may be performed by arithmetic logic unit (ALU) 426. For instructions that transfer data to one or more memories, address generation unit (AGU) 428 may be used to calculate addresses used to access memory 204. In some cases, digital instructions may be used to write parameters to registers used to generate analog pulses as part of the execution of an analog instruction.

[0054] The analog execution circuit 416 executes the analog instructions. The analog execution circuit includes one or more signal processing blocks (SPBs) 430. The SPBs 430 may also be referred to as digital signal processors (DSPs) 430. In an exemplary embodiment, each SPB 430 may send or receive signals to or from the companion chip 308 and quantum processor using wires 310. The signals sent to the companion chip 308 may be, for example, analog pulses to perform operations on qubits, analog voltages to control DC voltages applied to qubits, digital voltages to select qubits through multiplexing, etc. The signals received from the companion chip 308 may be, for example, reflections of signals sent to the qubits indicating the state of the qubits. In some embodiments, each SPB 430 may send or receive signals for several qubits, such as between 2 and 100. The SPB 430 may transmit or receive signals for more than one qubit over a single wire 310 or set of wires 310 using multiplexing, such as frequency and / or time multiplexing. The analog instruction may, for example, be to create or measure an analog pulse. In some embodiments, the instruction may cause the SPB 430 to first create an analog pulse that is sent to a qubit on a quantum processor and then measure the reflected or returned signal. In some embodiments, parameters of the pulse may be loaded into registers using digital instructions before the analog instruction is executed. For example, in one embodiment, the digital instruction may load values ​​for the pulse frequency, pulse amplitude, pulse phase, pulse envelope, etc. into registers. The analog instruction may then instruct the SPB 430 to generate a pulse based on the parameters stored in the registers. In an exemplary embodiment, the SPB 430 has direct access to the analog input and output channels of the hybrid digital / analog processor 302.

[0055] The SPB 430 may create a voltage or pulse with any suitable wavelength, bandwidth, envelope (e.g., rectangular or Gaussian), amplitude, etc. The SPB 430 may generate a rectangular voltage pulse, for example, having a duration of 1 nanosecond to 100 microseconds. The SPB 430 may generate a microwave pulse, for example, having a duration of 1 to 100 nanoseconds. The microwave pulse may be modulated on a carrier frequency, for example, 11 to 20 gigahertz, with a bandwidth of, for example, 1 to 100 megahertz. To measure the state of a qubit, the SPB 430 may generate one or more pulses with a center frequency of 50 to 1,000 MHz and a bandwidth of 2 to 20 MHz. The SPB 430 generating the pulses, or a different SPB, may measure the reflection of such a signal from the qubit and infer the state of the qubit based on the reflection.

[0056] It should be understood that the timing of analog signals is important, so in some embodiments, some or all of the hybrid digital / analog processor 302 may operate in a timing-aware or real-time mode to ensure that signals sent to the quantum processor 210 are sent at the appropriate times.

[0057] In an exemplary embodiment, the analog execution circuit 416 may not operate at the same clock speed as other components of the processor core 402, such as the digital execution circuit 414. For example, the analog execution circuit 416 may operate in a different clock domain and / or at a different clock speed. In some embodiments, portions of the analog execution circuit 416 may be powered down to reduce power consumption.

[0058] In an exemplary embodiment, the processor core 402 of the hybrid digital / analog processor 302 may be able to control a number of qubits, such as between 2 and 1,000 qubits. To do so, the processor core 402 may include a number of SPBs 430, such as between 2 and 10. The SPBs 430 may perform operations on the qubits at a relatively slow rate, such as one operation per qubit every 20 nanoseconds. However, if the processor core 402 controls, for example, 100 qubits, the processor core 402 consumes one operation every 0.2 nanoseconds, or at a rate of 5 gigahertz. To provide sufficient instructions to the processor core 402, the front end of the hybrid digital / analog processor may be relatively wide. For example, the hybrid digital / analog processor may receive, for example, 5 to 20 instructions per clock cycle.

[0059] It should be understood that integrating the SPB 430 into the processor core 402 may provide several advantages. Because the SPB 430 is integrated into the same die or package as other components of the processor core 402, latency between the digital execution circuit 414 and the analog execution circuit 416 is reduced. For example, handover of data from the digital and analog backends may occur within a few clock cycles or in less than one nanosecond. Additionally, the digital execution circuit 414 and the analog execution circuit 416 may share memory 404 and registers, further reducing the latency required for copying data as well as reducing the power used for memory storage. Any digital circuitry required to manage the SPB 430 may be integrated with other digital circuitry within the processor core 402, reducing the components in the SPB 430. Because the front end for both digital and analog instructions is the same, a compiler may optimize the program at compile time to execute more efficiently on the hybrid digital / analog processor 302. Feedback from quantum processor 210, such as condition readouts, error correction readouts, etc., can be used to feed forward further operations on quantum processor 210 with low latency, improving the performance of algorithms running on quantum processor 210.

[0060] It should be understood that the description of hybrid digital / analog processor 302 is simplified and that hybrid digital / analog processor 302 may include additional components or circuitry typically found in a processor. For example, hybrid digital / analog processor 302 may include a memory management unit (MMU), may use techniques such as pipelining, may execute instructions out of order, etc.

[0061] Referring now to FIG. 5 , in some embodiments, it may be difficult for a single processor core 402 to perform all of the desired functions of the hybrid digital / analog processor 302. For example, the hybrid digital / analog processor 302 may manage a large number of qubits, such as 100 to 1,000 qubits, and a single processor core 402 may not be able to add more SPBs 430 without incurring performance loss. In such an embodiment, the hybrid digital / analog processor 302 may include more than one processor core 402 as shown in FIG. 5 . The hybrid digital / analog processor 302 may include any suitable number of processor cores 402, such as 1 to 20. The multi-core hybrid digital / analog processor 302 may include a core synchronization matrix 502 for synchronizing timing among the various processor cores 402, particularly among the various SPBs 430.

[0062] Referring now to FIG. 6 , in some embodiments, even in the case of a hybrid digital / analog processor 302 with multiple cores 402, it may be difficult for a single hybrid digital / analog processor 302 to control the desired number of qubits of the quantum processor 210. For example, the hybrid digital / analog processor 302 may manage a large number of qubits, such as 1,000 to 10,000 qubits, and a single hybrid digital / analog processor 302 may not be able to add more processor cores 402 without suffering performance loss or lower yield. In such an embodiment, the quantum / classical interface circuit 208 may include more than one hybrid digital / analog processor 302 as shown in FIG. 6 . The quantum / classical interface circuit 208 may include any suitable number of hybrid digital / analog processors 302, such as 1 to 20. A core synchronization matrix 502 in each hybrid digital / analog processor 302 may provide synchronization between the hybrid digital / analog processors as well as between the processor cores 402. In the exemplary embodiment, each hybrid digital / analog processor 302 has a corresponding companion chip 308 , and the various companion chips 308 interface with different qubits on the same quantum processor 210 .

[0063] 7, in an exemplary embodiment, quantum compute device 200 establishes environment 700 during operation. Exemplary environment 700 includes a compiler 702, an instruction scheduler 704, and a synchronizer 706. The various modules of environment 700 may be embodied as hardware, software, firmware, or a combination thereof. For example, the various modules, logic, and other components of environment 700 may form part of, or be otherwise established by, processor 202, memory 204, data storage, or other hardware components of quantum compute device 200. As such, in some embodiments, one or more of the modules of environment 700 may be embodied as a circuit or collection of electrical devices (e.g., compiler circuit 702, instruction scheduler circuit 704, synchronizer circuit 706, etc.). It should be understood that in such embodiments, one or more of the circuits (e.g., compiler circuit 702, instruction scheduler circuit 704, synchronizer circuit 706, etc.) may form part of one or more of processor 202, memory 204, data storage, and / or other components of quantum compute device 200. For example, in some embodiments, some or all of the modules may be embodied as processor 202, memory 204, and / or data storage that stores instructions executed by processor 202. Additionally, in some embodiments, one or more of the example modules may form part of another module, and / or one or more of the example modules may be independent of one another. Furthermore, in some embodiments, one or more of the modules of environment 700 may be embodied as a virtualized hardware component or emulation architecture, which may be established and maintained by processor 202 or other components of quantum compute device 200.It should be understood that some of the functionality of one or more of the modules of environment 700 may require hardware implementation, and in that case, an embodiment of a module that implements such functionality is at least partially embodied as hardware.

[0064] Compiler 702, which may be embodied as hardware, firmware, software, virtualization hardware, emulation architecture, and / or combinations thereof as discussed above, is configured to compile programs to be executed by processor 202, hybrid digital / analog processor 302, and quantum processor 210. In an exemplary embodiment, compiler 702 may optimize the compiled code based on the capabilities of hybrid digital / analog processor 302. The optimization may reduce or eliminate idle time of hybrid digital / analog processor 302, core 402, SPB 430, etc.

[0065] The instruction scheduler 704, which may be embodied as hardware, firmware, software, virtualization hardware, emulation architecture, and / or combinations thereof as discussed above, is configured to schedule instructions on one or more hybrid digital / analog processors 302. The instructions may be digital or analog instructions. The instructions may be, for example, to initialize some or all of the qubits in the quantum processor 210, perform one or more operations on the qubits, and read values ​​from one or more of the qubits. The instruction scheduler 704 may coordinate the scheduling of operations on different SPBs 430, different cores 402, and different hybrid digital / analog processors 302. The instruction scheduler 704 may have various options for channel allocation within a given hybrid digital / analog processor 302 and across various hybrid digital / analog processors 302.

[0066] Instruction scheduler 704 is configured to receive feedback data from hybrid digital / analog processor 302, such as readout data from qubits in quantum processor 210. Because computational and cooling power may be limited on hybrid digital / analog processor 302, particularly if latency is not critical, some of the algorithms for controlling the qubits of quantum processor 210 may be performed on processor 202. Instruction scheduler 704 may determine which operations should be performed on quantum processor 210 based on the measurements on the qubits, and instruction scheduler 704 may send instructions and / or data to hybrid digital / analog processor 302 based on the measurements on the qubits.

[0067] The synchronizer 706 may manage synchronization between the various cores 402, SPBs 430, etc. of one or more hybrid digital / analog processors 302. The synchronizer 706 may communicate with the various core synchronization matrices 502 of the hybrid digital / analog processor 302.

[0068] 8, a flowchart of a method 800 is shown, in one embodiment, for executing instructions in the hybrid digital / analog processor 302. The method 800 begins at block 802, where the hybrid digital / analog processor 302 receives instructions. The hybrid digital / analog processor 302 may receive instructions from, for example, the processor 202, the memory 204, the memory 404, etc.

[0069] In block 804, the hybrid digital / analog processor 302 determines whether the instruction is a digital or analog instruction. The hybrid digital / analog processor 302 may examine the decoded microcode in the instruction to determine whether the instruction is a digital or analog instruction. For example, an instruction with a particular microcode may be assigned to the digital execution circuitry 414, and an instruction with a particular microcode may be assigned to the analog execution circuitry 416.

[0070] At block 806, if the instruction is a digital instruction, the method 800 proceeds to block 808, where the instruction is passed to the digital execution circuitry 414, which executes the instruction. The instruction may be, for example, a read or write operation to memory, a read or write operation to a register, an arithmetic operation, a conditional branch, etc. The method 800 then jumps to block 816, where the hybrid digital / analog processor 302 synchronizes among its cores 402, and in some embodiments, with other hybrid digital / analog processors 302. The method 800 then loops back to block 802 to receive another instruction.

[0071] Referring again to block 806, if the instruction is not a digital instruction, the method 800 jumps to block 810, where the instruction is passed to the analog execution circuit 416, which executes the instruction. At block 812, the analog execution circuit 416 may generate an analog signal, such as a radio frequency pulse. The analog execution circuit 416 may generate the analog signal using values ​​stored in a register, such as a register indicating amplitude, frequency, envelope, etc. At block 814, the analog execution circuit 416 may measure the analog signal, such as a reflection of an RF signal sent to the qubit. In some embodiments, the generation of the analog signal and the measurement of the reflection may be performed as a single instruction. The method 800 then proceeds to block 816 to synchronize with other cores 402 and / or other hybrid digital / analog processors 302.

[0072] It should be understood that method 800 shows a simplified flow of hybrid digital / analog processor 302, and that in some embodiments, the flow of hybrid digital / analog processor 302 may include additional stages, may perform stages out of order, etc. For example, in some embodiments, hybrid digital / analog processor 302 may use pipelining and / or may perform certain instructions out of order.

[0073] 9, a flowchart of a method 900 for executing a program on quantum processor 210 is shown in one embodiment. Method 900 may be performed by components of quantum compute device 200, such as processor 202, memory 204, compiler 702, instruction scheduler 704, synchronizer 706, etc. Method 900 begins at block 902, where quantum compute device 200 compiles a program to be executed by processor 202, hybrid digital / analog processor 302, and quantum processor 210. In an exemplary embodiment, the compiler may optimize the compiled code based on the capabilities of hybrid digital / analog processor 302. Optimization may reduce or eliminate idle time in hybrid digital / analog processor 302, core 402, SPB 430, etc.

[0074] In block 906, processor 202 sends one or more instructions to one or more hybrid digital / analog processors 302. The instructions may be digital or analog instructions. The instructions may, for example, be to initialize some or all of the qubits in quantum processor 210, perform one or more operations on the qubits, and read values ​​from one or more of the qubits. Processor 202 may coordinate the scheduling of operations on different SPBs 430, on different cores 402, and on different hybrid digital / analog processors 302. Processor 202 may have various options for channel allocation within a given hybrid digital / analog processor 302 and across various hybrid digital / analog processors 302.

[0075] At block 908, if processor 202 has not received data, such as measurement data for one or more qubits, from hybrid digital / analog processor 302, method 900 loops back to block 908 to continue waiting for results from hybrid digital / analog processor 302. If processor 202 has received data from hybrid digital / analog processor 302, method 900 proceeds to block 910.

[0076] At block 910, processor 202 determines which instructions to send to hybrid digital / analog processor 302. Because computing power and cooling capacity may be limited on hybrid digital / analog processor 302, particularly if latency is not critical, portions of the algorithms for controlling the qubits of quantum processor 210 may be performed on processor 202. Processor 202 may determine which operations to perform on quantum processor 210 based on measurements on the qubits, and processor 202 may send instructions and / or data to hybrid digital / analog processor 302 based on the measurements on the qubits. At block 912, processor 202 sends the instructions and / or data to hybrid digital / analog processor 302.

[0077] At block 914, the processor 202 may manage synchronization between the various cores 402 of the one or more hybrid digital / analog processors 302. The method 900 then loops back to block 908 to wait to receive more data from the hybrid digital / analog processor 302.

[0078] 10 is a top view of a wafer 1000 and dies 1002 that may be included in any of the processors disclosed herein (e.g., as any suitable one of the dies of processor 202, hybrid digital / analog processor 302, or quantum processor 210). Wafer 1000 may be constructed of semiconductor material and may include one or more dies 1002 having integrated circuit structures formed on the surface of wafer 1000. Individual dies 1002 may be repeating units of integrated circuit products, including any suitable integrated circuits. After fabrication of the semiconductor products is complete, wafer 1000 may undergo a singulation process in which dies 1002 are separated from one another to provide individual “chips” of integrated circuit products. Dies 1002 may be any of the dies of the processors disclosed herein, such as processor 202, hybrid digital / analog processor 302, or quantum processor 210. The die 1002 may include one or more transistors (e.g., some of the transistors 1140 in FIG. 11 , discussed below), support circuitry that routes electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other integrated circuit components. In some embodiments, the wafer 1000 or die 1002 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM®) devices, conductive-bridging RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 1002. For example, a memory array formed by multiple memory devices may be formed on the same die 1002 as a processor unit (e.g., processor unit 1402 of FIG. 14) or other logic configured to store information in the memory devices or execute instructions stored in the memory array.Various of the processors disclosed herein (e.g., processor 202, hybrid digital / analog processor 302, or quantum processor 210) may be manufactured using die-to-wafer assembly techniques in which some dies are attached to a wafer 1000 containing other dies, and then the wafer 1000 is singulated.

[0079] FIG. 11 is a cross-sectional side view of an integrated circuit device 1100 that may be included in any of the processors disclosed herein (e.g., processor 202, hybrid digital / analog processor 302, or quantum processor 210). One or more of the integrated circuit devices 1100 may be included in one or more dies 1002 (FIG. 10). The integrated circuit devices 1100 may be formed on a die substrate 1102 (e.g., wafer 1000 of FIG. 10) and included in a die (e.g., die 1002 of FIG. 10). The die substrate 1102 may be a semiconductor substrate constructed of a semiconductor material system, including, for example, an n-type or p-type material system (or a combination of both). The die substrate 1102 may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate 1102 may be formed using alternative materials, which may or may not be combined with silicon, including, but not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Additional materials classified as II-VI, III-V, or IV may also be used to form the die substrate 1102. While only a few examples of materials from which the die substrate 1102 may be formed are described here, any material that can serve as the foundation for the integrated circuit device 1100 may be used. The die substrate 1102 may be part of a singulated die (e.g., die 1002 of FIG. 10 ) or a wafer (e.g., wafer 1000 of FIG. 10 ).

[0080] The integrated circuit device 1100 may include one or more device layers 1104 disposed on a die substrate 1102. The device layer 1104 may include features of one or more transistors 1140 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1102. The transistor 1140 may include, for example, one or more source and / or drain (S / D) regions 1120, a gate 1122 that controls current flow between the S / D regions 1120, and one or more S / D contacts 1124 that route electrical signals to / from the S / D regions 1120. The transistor 1140 may include additional features, such as device isolation regions, gate contacts, etc., not depicted for clarity. The transistor 1140 is not limited to the types and configurations depicted in FIG. 11 and may include a variety of other types and configurations, such as planar transistors, non-planar transistors, or a combination of both. Non-planar transistors can include FinFET transistors, such as double-gate or tri-gate transistors, and wrap-around or all-around gate transistors, for example nanoribbon, nanosheet, or nanowire transistors.

[0081] 12A-12D are simplified perspective views of exemplary planar, FinFET, gate-all-around, and stacked gate-all-around transistors. The transistors shown in FIGS. 12A-12D are formed on a substrate 1216 having a surface 1208. Isolation regions 1214 separate the source and drain regions of the transistor from other transistors and from a bulk region 1218 of the substrate 1216.

[0082] 12A is a perspective view of an exemplary planar transistor 1200 that includes a gate 1202 that controls current flow between a source region 1204 and a drain region 1206. The transistor 1200 is planar in that the source region 1204 and the drain region 1206 are planar with respect to a surface 1208 of a substrate.

[0083] Figure 12B is a perspective view of an exemplary FinFET transistor 1220 that includes a gate 1222 that controls current flow between a source region 1224 and a drain region 1226. The transistor 1220 is non-planar in that the source region 1224 and the drain region 1226 include "fins" that extend upward from a surface 1228 of a substrate. Because the gate 1222 surrounds three sides of the semiconductor fin that extends from the source region 1224 to the drain region 1226, the transistor 1220 may be considered a tri-gate transistor. Although Figure 12B shows one S / D fin extending through the gate 1222, multiple S / D fins can extend through the gate of a FinFET transistor.

[0084] 12C is a perspective view of a gate-all-around (GAA) transistor 1240 that includes a gate 1242 that controls current flow between a source region 1244 and a drain region 1246. Transistor 1240 is non-planar in that source region 1244 and drain region 1246 are elevated above surface 1228 of the substrate.

[0085] 12D is a perspective view of a GAA transistor 1260 including a gate 1262 that controls current flow between multiple elevated source regions 1264 and multiple elevated drain regions 1266. Transistor 1260 is a stacked GAA transistor because the gate controls current flow between multiple elevated S / D regions stacked on top of each other. Transistors 1240 and 1260 are considered gate-all-around transistors because the gate surrounds all sides of the semiconductor portion extending from the source region to the drain region. Transistors 1240 and 1260 may alternatively be referred to as nanowire, nanosheet, or nanoribbon transistors, depending on the width of the semiconductor portion extending through the gate (e.g., widths 1248 and 1268 for transistors 1240 and 1260, respectively).

[0086] 11, transistor 1140 may include a gate 1122 formed by at least two layers, a gate dielectric and a gate electrode. The gate dielectric layer may include one layer or a stack of multiple layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or high-k dielectric materials.

[0087] High-k dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalate, and lead zinc niobate. In some embodiments, when a high-k material is used, an annealing process may be performed on the gate dielectric layer to improve its quality.

[0088] A gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal depending on whether the transistor 1140 is to be a p-type metal oxide semiconductor (PMOS) or n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Additional metal layers, such as barrier layers, may be included for other purposes.

[0089] For PMOS transistors, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to NMOS transistors (e.g., for work function tuning). For NMOS transistors, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to PMOS transistors (e.g., for work function tuning).

[0090] In some embodiments, when viewed as a cross-section of the transistor 1140 along the source-channel-drain direction, the gate electrode may comprise a U-shaped structure with a bottom portion substantially parallel to the surface of the die substrate 1102 and two sidewall portions substantially perpendicular to the top surface of the die substrate 1102. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the die substrate 1102 and does not include sidewall portions substantially perpendicular to the top surface of the die substrate 1102. In other embodiments, the gate electrode may comprise a planar combination of U-shaped and non-U-shaped structures. For example, the gate electrode may comprise one or more U-shaped metal layers formed on top of one or more planar, non-U-shaped layers.

[0091] In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack to surround the gate stack. These sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, multiple spacer pairs may be used. For example, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[0092] The S / D regions 1120 may be formed in the die substrate 1102 adjacent to the gates 1122 of the individual transistors 1140. The S / D regions 1120 may be formed using, for example, an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion-implanted into the die substrate 1102 to form the S / D regions 1120. An annealing process to activate the dopants and further diffuse them into the die substrate 1102 may follow the ion-implantation process. In the latter process, the die substrate 1102 may first be etched to form recesses at the locations of the S / D regions 1120. An epitaxial growth process may then be performed to fill the recesses with the material used to fabricate the S / D regions 1120. In some implementations, the S / D regions 1120 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorus. In some embodiments, the S / D regions 1120 are formed using one or more alternating semiconductor materials, such as germanium or III-V materials or alloys. In further embodiments, one or more layers of metal and / or metal alloys may be used to form the S / D regions 1120.

[0093] Electrical signals, such as power and / or input / output (I / O) signals, may be routed to and / or from devices (e.g., transistor 1140) in device layer 1104 through one or more interconnect layers (shown in FIG. 11 as interconnect layers 1106-1110) disposed on device layer 1104. For example, conductive features of device layer 1104 (e.g., gate 1122 and S / D contacts 1124) may be electrically coupled with interconnect structures 1128 in interconnect layers 1106-1110. One or more interconnect layers 1106-1110 may form a metallization stack (also referred to as an "ILD stack") 1119 of integrated circuit device 1100.

[0094] Interconnect structures 1128 may be arranged within interconnect layers 1106-1110 to route electrical signals according to a variety of designs, and in particular, the arrangement is not limited to the particular configuration of interconnect structures 1128 depicted in Figure 11. Although a particular number of interconnect layers 1106-1110 are depicted in Figure 11, embodiments of the present disclosure include integrated circuit devices having more or fewer interconnect layers than depicted.

[0095] In some embodiments, the interconnect structures 1128 may include lines 1128a and / or vias 1128b filled with a conductive material, such as metal. The lines 1128a may be arranged to route electrical signals in a plane substantially parallel to the surface of the die substrate 1102 on which the device layer 1104 is formed. For example, the lines 1128a may route electrical signals into and out of the page and / or across the page. The vias 1128b may be arranged to route electrical signals in a plane substantially perpendicular to the surface of the die substrate 1102 on which the device layer 1104 is formed. In some embodiments, the vias 1128b may electrically couple together the lines 1128a of different interconnect layers 1106-1110.

[0096] As shown in FIG. 11 , the interconnect layers 1106-1110 can include a dielectric material 1126 disposed between interconnect structures 1128. In some embodiments, the dielectric material 1126 disposed between the interconnect structures 1128 in different ones of the interconnect layers 1106-1110 can have different compositions. In other embodiments, the composition of the dielectric material 1126 between different interconnect layers 1106-1110 can be the same. The device layer 1104 can include a dielectric material 1126 disposed between the transistor 1140 and a bottom layer of the metallization stack. The dielectric material 1126 included in the device layer 1104 can have a different composition than the dielectric material 1126 included in the interconnect layers 1106-1110. In other embodiments, the composition of the dielectric material 1126 in the device layer 1104 can be the same as the dielectric material 1126 included in any one of the interconnect layers 1106-1110.

[0097] A first interconnect layer 1106 (referred to as metal 1 or "M1") may be formed directly on the device layer 1104. As shown, in some embodiments, the first interconnect layer 1106 may include a line 1128a and / or a via 1128b. The line 1128a of the first interconnect layer 1106 may be coupled to a contact (e.g., an S / D contact 1124) of the device layer 1104. The via 1128b of the first interconnect layer 1106 may be coupled to a line 1128a of the second interconnect layer 1108.

[0098] A second interconnect layer 1108 (referred to as metal 2 or "M2") may be formed directly on the first interconnect layer 1106. In some embodiments, the second interconnect layer 1108 may include vias 1128b for coupling lines 1128 of the second interconnect layer 1108 to lines 1128a of the third interconnect layer 1110. Although the lines 1128a and vias 1128b are structurally depicted with lines within individual interconnect layers for clarity, the lines 1128a and vias 1128b may be structurally and / or materially continuous in some embodiments (e.g., filled simultaneously during a dual damascene process).

[0099] The third interconnect layer 1110 (referred to as metal 3 or "M3") (and additional interconnect layers, as desired) may be formed successively on the second interconnect layer 1108 according to similar techniques and configurations described in connection with the second interconnect layer 1108 or the first interconnect layer 1106. In some embodiments, interconnect layers "higher" in the metallization stack 1119 (i.e., further from the device layer 1104) within the integrated circuit device 1100 may be thicker than interconnect layers lower in the metallization stack 1119, with lines 1128a and vias 1128b in the higher interconnect layers being thicker than those in the lower interconnect layers.

[0100] The integrated circuit device 1100 may include a solder resist material 1134 (e.g., polyimide or a similar material) and one or more conductive contacts 1136 formed on the interconnect layers 1106-1110. In FIG. 11, the conductive contacts 1136 are shown to take the form of bond pads. The conductive contacts 1136 may be electrically coupled to the interconnect structure 1128 and configured to route electrical signals from the transistor 1140 to an external device. For example, solder bonds may be formed on the one or more conductive contacts 1136 to mechanically and / or electrically couple an integrated circuit die including the integrated circuit device 1100 to another component (e.g., a printed circuit board). The integrated circuit device 1100 may include additional or alternate structures for routing electrical signals from the interconnect layers 1106-1110. For example, the conductive contacts 1136 may include other similar features (e.g., posts) that route electrical signals to external components.

[0101] In some embodiments in which integrated circuit device 1100 is a double-sided die, integrated circuit device 1100 may include another metallization stack (not shown) on the opposite side of device layer 1104. This metallization stack may include multiple interconnect layers as discussed above with reference to interconnect layers 1106-1110 to provide conductive paths (e.g., including conductive lines and vias) between device layer 1104 and additional conductive contacts (not shown) on the opposite side of integrated circuit device 1100 from conductive contact 1136.

[0102] In other embodiments in which integrated circuit device 1100 is a double-sided die, integrated circuit device 1100 may include one or more through silicon vias (TSVs) through die substrate 1102. These TSVs may contact device layer 1104 and provide a conductive path between device layer 1104 and additional conductive contacts (not shown) on the opposite side of integrated circuit device 1100 from conductive contact 1136. In some embodiments, the TSVs extending through the substrate may be used to route power and ground signals from the conductive contacts on the opposite side of integrated circuit device 1100 from conductive contact 1136 to transistor 1140 and any other components integrated on die 1100, and metallization stack 1119 may be used to route I / O signals from conductive contact 1136 to transistor 1140 and any other components integrated on die 1100.

[0103] In each stacked device, multiple integrated circuit devices 1100 may be stacked with one or more TSVs providing a connection between one of the devices and any of the other devices in the stack. For example, one or more high-bandwidth memory (HBM) integrated circuit dies may be stacked on top of a base integrated circuit die, with TSVs in the HBM die providing a connection between the individual HBM and base integrated circuit dies. Conductive contacts may provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts may be fine-pitch solder bumps (microbumps).

[0104] FIG. 13 is a cross-sectional side view of an integrated circuit device assembly 1300 that may include any of the processors disclosed herein (e.g., processor 202, hybrid digital / analog processor 302, or quantum processor 210). In some embodiments, integrated circuit device assembly 1300 may be processor 202, hybrid digital / analog processor 302, or quantum processor 210. Integrated circuit device assembly 1300 includes several components disposed on a circuit board 1302 (which may be a motherboard, system board, mainboard, etc.). Integrated circuit device assembly 1300 includes components disposed on a first side 1340 of circuit board 1302 and an opposing second side 1342 of circuit board 1302. Generally, components may be disposed on one or both sides 1340 and 1342. Any of the integrated circuit components discussed below with reference to integrated circuit device assembly 1300 may take the form of any suitable embodiment of a processor disclosed herein (e.g., processor 202, hybrid digital / analog processor 302, or quantum processor 210).

[0105] In some embodiments, the circuit board 1302 may be a printed circuit board (PCB) including multiple metal (or interconnect) layers separated from each other by layers of dielectric material and interconnected by conductive vias. Individual metal layers comprise conductive traces. Any one or more of the metal layers may be formed with a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between components coupled to the circuit board 1302. In other embodiments, the circuit board 1302 may be a non-PCB substrate. The integrated circuit device assembly 1300 shown in FIG. 13 includes a package-on-interposer structure 1336 coupled to a first surface 1340 of the circuit board 1302 by a coupling component 1316. The bonding components 1316 may electrically and mechanically couple the package-on-interposer structure 1336 to the circuit board 1302 and may include solder balls (as shown in FIG. 13), pins (e.g., as part of a pin grid array (PGA)), contacts (e.g., as part of a land grid array (LGA)), male and female portions of a socket, adhesive, underfill material, and / or any other suitable electrical and / or mechanical bonding structure.

[0106] Package-on-interposer structure 1336 may include an integrated circuit component 1320 coupled to interposer 1304 by a coupling component 1318. Coupling component 1318 may take any suitable form for the application, such as those discussed above with reference to coupling component 1316. While a single integrated circuit component 1320 is shown in FIG. 13, multiple integrated circuit components may be coupled to interposer 1304. In fact, additional interposers may be coupled to interposer 1304. Interposer 1304 may provide an intervening substrate used to bridge circuit board 1302 and integrated circuit component 1320.

[0107] Integrated circuit component 1320 may be a packaged or unpackaged integrated circuit product that includes one or more integrated circuit dies (e.g., die 1002 of FIG. 10 , integrated circuit device 1100 of FIG. 11 ) and / or one or more other suitable components. A packaged integrated circuit component comprises one or more integrated circuit dies mounted on a package substrate, with the integrated circuit dies and package substrate encapsulated in a casing material such as metal, plastic, glass, or ceramic. In one example of an unpackaged integrated circuit component 1320, a single monolithic integrated circuit die comprises solder bumps attached to contacts on the die. The solder bumps allow the die to be directly attached to interposer 1304. The integrated circuit component 1320 may comprise one or more computing system components, such as one or more processor units (e.g., a system on a chip (SoC), a processor core, a graphics processor unit (GPU)), an accelerator, a chipset processor, an I / O controller, a memory, or a network interface controller. In some embodiments, the integrated circuit component 1320 may comprise one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

[0108] In embodiments in which integrated circuit component 1320 comprises multiple integrated circuit dies, the dies may be of the same type (a homogeneous multi-die integrated circuit component) or two or more different types (a heterogeneous multi-die integrated circuit component). A multi-die integrated circuit component may be referred to as a multi-chip package (MCP) or a multi-chip module (MCM).

[0109] In addition to including one or more processor units, integrated circuit component 1320 may include additional components, such as embedded DRAM, stacked high-bandwidth memory (HBM), shared cache memory, input / output (I / O) controllers, or memory controllers. Any of these additional components may be located on the same integrated circuit die as the processor unit or on one or more integrated circuit dies separate from the integrated circuit die that includes the processor unit. These separate integrated circuit dies may be referred to as "chiplets." In embodiments in which the integrated circuit component includes multiple integrated circuit dies, interconnection between the dies may be provided by a package substrate, one or more silicon interposers, one or more silicon bridges embedded in the package substrate (e.g., an Intel® embedded multi-die interconnect bridge (EMIB)), or a combination thereof.

[0110] In general, interposer 1304 may spread connections to a wider pitch or reroute connections to different connections. For example, interposer 1304 may couple integrated circuit component 1320 to a set of ball grid array (BGA) conductive contacts of coupling component 1316 for coupling to circuit board 1302. In the embodiment shown in FIG. 13, integrated circuit component 1320 and circuit board 1302 are mounted on opposite sides of interposer 1304. In other embodiments, integrated circuit component 1320 and circuit board 1302 may be mounted on the same side of interposer 1304. In some embodiments, three or more components may be interconnected by interposer 1304.

[0111] In some embodiments, interposer 1304 may be formed as a PCB including multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. In some embodiments, interposer 1304 may be formed of a polymeric material, such as epoxy, glass-reinforced epoxy, epoxy with inorganic filler, ceramic material, or polyimide. In some embodiments, interposer 1304 may be formed of alternating rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other III-V and IV materials. The interposer 1304 may include metal interconnects 1308 and vias 1310, including, but not limited to, through-hole vias 1310-1 (extending from a first surface 1350 of the interposer 1304 to a second surface 1354 of the interposer 1304), blind vias 1310-2 (extending from the first or second surface 1350 or 1354 of the interposer 1304 to an internal metal layer), and buried vias 1310-3 (connecting internal metal layers).

[0112] In some embodiments, the interposer 1304 may comprise a silicon interposer. Through-silicon vias (TSVs) extending through the silicon interposer may connect connections from a first side of the silicon interposer to an opposing second side of the silicon interposer. In some embodiments, the interposer 1304 comprising a silicon interposer may further comprise one or more routing layers for routing connections from the first side of the interposer 1304 to the opposing second side of the interposer 1304.

[0113] The interposer 1304 may further include embedded devices 1314, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, may also be formed on the interposer 1304. The package-on-interposer structure 1336 may take the form of any package-on-interposer structure known in the art. In embodiments where the interposer is a printed circuit board,

[0114] Integrated circuit device assembly 1300 may include an integrated circuit component 1324 coupled to a first surface 1340 of circuit board 1302 by a coupling component 1322. Coupling component 1322 may take the form of any of the embodiments discussed above with reference to coupling component 1316, and integrated circuit component 1324 may take the form of any of the embodiments discussed above with reference to integrated circuit component 1320.

[0115] 13 includes a package-on-package structure 1334 coupled to a second surface 1342 of a circuit board 1302 by a coupling component 1328. The package-on-package structure 1334 may include an integrated circuit component 1326 and an integrated circuit component 1332 coupled together by a coupling component 1330 such that the integrated circuit component 1326 is disposed between the circuit board 1302 and the integrated circuit component 1332. The coupling components 1328 and 1330 may take the form of any of the embodiments of the coupling component 1316 discussed above, and the integrated circuit components 1326 and 1332 may take the form of any of the embodiments of the integrated circuit component 1320 discussed above. The package-on-package structure 1334 may be configured according to any of the package-on-package structures known in the art.

[0116] FIG. 14 is a block diagram of an exemplary electrical device 1400 that may include one or more of the processors disclosed herein (e.g., processor 202, hybrid digital / analog processor 302, or quantum processor 210). For example, any suitable components of electrical device 1400 may include one or more of integrated circuit device assembly 1300, integrated circuit component 1320, integrated circuit device 1100, or integrated circuit die 1002 disclosed herein and may be arranged in any of the processors disclosed herein (e.g., processor 202, hybrid digital / analog processor 302, or quantum processor 210). While numerous components are shown in FIG. 14 as being included in electrical device 1400, any one or more of these components may be omitted or duplicated if suitable for the application. In some embodiments, some or all of the components included in electrical device 1400 may be mounted on one or more motherboards, mainboards, or system boards. In some embodiments, one or more of these components are fabricated on a single system-on-chip (SoC) die.

[0117] 14 , but electrical device 1400 may include interface circuitry for coupling one or more components. For example, electrical device 1400 may not include display device 1406, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which display device 1406 may be coupled. In another set of examples, electrical device 1400 may not include audio input device 1424 or audio output device 1408, but may include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which audio input device 1424 or audio output device 1408 may be coupled.

[0118] The electrical device 1400 may include one or more processor units 1402 (e.g., one or more processor units). As used herein, the terms “processor unit,” “processing unit,” or “processor” may refer to any device or portion of a device that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that may be stored in registers and / or memory. The processor unit 1402 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller crypto-processors (dedicated processors that execute cryptographic algorithms in hardware), server processors, controllers, or any other suitable type of processor unit. As such, the processor unit may be referred to as an XPU (or xPU).

[0119] The electrical device 1400 may itself include memory 1404, which may include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM), static random-access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-voltage memory), solid-state memory, and / or a hard drive. In some embodiments, the memory 1404 may include memory located on the same integrated circuit die as the processor unit 1402. This memory may be used as cache memory (e.g., Level 1 (L1), Level 2 (L2), Level 3 (L3), Level 4 (L4), Last Level Cache (LLC)), and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0120] In some embodiments, electrical device 1400 may include one or more processor units 1402 that are heterogeneous or asymmetric with respect to other processor units 1402 in electrical device 1400. There may be a variety of differences between processing units 1402 in a system in terms of a spectrum of metrics of merit, including architectural, microarchitectural, thermal, power consumption characteristics, etc. These differences may effectively manifest themselves as asymmetric and heterogeneous between processor units 1402 in electrical device 1400.

[0121] In some embodiments, electrical device 1400 may include a communications component 1412 (e.g., one or more communications components). For example, communications component 1412 may manage wireless communications for data transfer to and from electrical device 1400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc. that may communicate data through the use of modulated electromagnetic radiation over a non-solid medium. The term "wireless" does not imply that the associated device does not include any wires, although in some embodiments this may not be the case.

[0122] The communications component 1412 may implement any of several wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), Institute of Electrical and Electronics Engineers (IEEE) standards, including the IEEE 802.16 standard (e.g., the IEEE 802.16-2005 amendment), and any amendments, updates, and / or revisions (e.g., the Long-Term Evolution (LTE) project, including the Advanced LTE project, the Ultra Mobile Broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 802.16-compatible broadband wireless access (BWA) networks are commonly referred to as WiMAX networks. The acronym stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed IEEE 802.16 standard compliance and interoperability testing. The communications component 1412 may operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communications component 1412 may operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communications component 1412 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and their derivatives, as well as any other wireless protocols designated as 3G, 4G, 5G, and beyond. In other embodiments, the communications component 1412 may operate according to multiple other wireless protocols.Electrical device 1400 may include an antenna 1422 to facilitate wireless communication and / or receive other wireless communications (such as AM or FM radio transmissions).

[0123] In some embodiments, the communications component 1412 may manage wired communications, such as electrical, optical, or any other suitable communications protocol (e.g., the IEEE 802.3 Ethernet standard). As noted above, the communications component 1412 may include multiple communications components. For example, a first communications component 1412 may be dedicated to shorter-range wireless communications, such as Wi-Fi or Bluetooth, and a second communications component 1412 may be dedicated to longer-range wireless communications, such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communications component 1412 may be dedicated to wireless communications, and the second communications component 1412 may be dedicated to wired communications.

[0124] Electric device 1400 may include battery / power circuitry 1414. Battery / power circuitry 1414 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of electric device 1400 to an energy source separate from electric device 1400 (e.g., AC line power).

[0125] Electrical device 1400 may include a display device 1406 (or corresponding interface circuitry, as discussed above), which may include one or more embedded or wired or wirelessly connected external visual indicators, such as, for example, a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0126] Electrical device 1400 may include audio output device 1408 (or corresponding interface circuitry, as discussed above), which may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such as, for example, a speaker, a headset, or an earbud.

[0127] Electrical device 1400 may include audio input device 1424 (or corresponding interface circuitry, as discussed above). Audio input device 1424 may include any embedded, wired, or wirelessly connected device that generates a signal representing sound, such as a microphone, a microphone array, or a digital device (e.g., a device with a musical instrument digital interface (MIDI) output). Electrical device 1400 may include a Global Navigation Satellite System (GNSS) device 1418 (or corresponding interface circuitry, as discussed above), such as a Global Positioning System (GPS) device. GNSS device 1418 may communicate with a satellite-based system and may determine the geographic location of electrical device 1400 based on information received from one or more GNSS satellites, as known in the art.

[0128] Electrical device 1400 may include other output devices 1410 (or corresponding interface circuitry, as discussed above). Examples of other output devices 1410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage devices.

[0129] The electrical device 1400 may include other input devices 1420 (or corresponding interface circuitry, as discussed above). Examples of other input devices 1420 may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., a monoscopic or stereoscopic camera), a trackball, a trackpad, a touchpad, a keyboard, a cursor control device such as a mouse, a stylus, a touchscreen, a proximity sensor, a microphone, a barcode reader, a Quick Response (QR) code reader, an electrocardiogram (ECG) sensor, a PPG (photoplethysmogram) sensor, a galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader.

[0130] Electrical device 1400 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a mobile phone, a smartphone, a mobile internet device, a music player, a tablet computer, a laptop computer, a 2-in-1 convertible computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, a portable gaming console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., a blade, tray, or sled computing system), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a stationary gaming console, a smart television, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device, or an embedded computing system (e.g., a computing system that is part of a vehicle, a smart appliance, a home appliance or device, a manufacturing facility), etc. In some embodiments, electrical device 1400 may be any other electronic device that processes data. In some embodiments, electrical device 1400 may comprise multiple separate physical components. Given the range of devices that electrical device 1400 may represent in various embodiments, in some embodiments electrical device 1400 may be referred to as a computing device or a computing system. [Example]

[0131] Illustrative examples of the technology disclosed herein are provided below. Embodiments of the technology may include any one or more, and any combination, of the examples described below.

[0132] Example 1 includes an apparatus comprising a processor having a processor core, the processor core including an instruction management circuit, a digital instruction execution circuit, and an analog instruction execution circuit, the instruction management circuit receiving a plurality of instructions, determining whether each instruction of the plurality of instructions is a digital instruction or an analog instruction, sending each digital instruction of the plurality of instructions to the digital instruction execution circuit in response to determining that the corresponding each instruction is a digital instruction, and sending each analog instruction of the plurality of instructions to the analog instruction execution circuit in response to determining that the corresponding each instruction is an analog instruction, the analog instruction execution circuit executing analog instructions received from the instruction management circuit, and executing the analog instructions includes generating or measuring analog signals at an input / output of the processor.

[0133] Example 2 includes the subject matter of example 1, wherein the digital instruction execution circuitry executes instructions to load one or more parameters into one or more registers, and the analog instruction execution circuitry executes instructions to generate an analog pulse based on the one or more parameters in the one or more registers.

[0134] Example 3 includes the subject matter of any of examples 1 and 2, wherein the one or more parameters in the one or more registers are used to control the amplitude and frequency of the analog pulses.

[0135] Example 4 includes the subject matter of any of Examples 1-3, wherein the analog instruction execution circuitry executes instructions to generate analog pulses and measure reflections of the generated analog pulses.

[0136] Example 5 includes the subject matter of any of Examples 1 to 4, wherein the analog instruction execution circuitry operates in a first clock domain, and the digital instruction execution circuitry operates in a second clock domain different from the first clock domain.

[0137] Example 6 includes the subject matter of any of Examples 1 to 5, wherein the processor has a plurality of processor cores, each of which receives a plurality of instructions, determines whether each of the plurality of instructions is a digital instruction or an analog instruction, and, in response to determining that the corresponding instruction is a digital instruction, sends each of the plurality of instructions to the digital instruction execution circuit; an instruction management circuit that executes the digital instructions received from the instruction management circuit; and an analog instruction execution circuit that executes the analog instructions received from the instruction management circuit, wherein executing the analog instructions includes generating or measuring an analog signal at an input / output of the processor.

[0138] Example 7 includes the subject matter of any of Examples 1 to 6, wherein the processor further includes a core synchronization matrix that synchronizes between processor cores of the plurality of processor cores.

[0139] Example 8 includes the subject matter of any of Examples 1-7, further including a plurality of processors, each processor in a separate package, each processor of the plurality of processors having a plurality of processor cores, each processor core of the plurality of processors of each processor of the plurality of processors receiving a plurality of instructions; determining whether each instruction of the plurality of instructions is a digital instruction or an analog instruction; an instruction management circuit responsive to determining that the corresponding instruction is a digital instruction, sending each digital instruction of the plurality of instructions to a digital instruction execution circuit; and an instruction management circuit responsive to determining that the corresponding instruction is an analog instruction, sending each analog instruction of the plurality of instructions to an analog instruction execution circuit; the digital instruction execution circuit executing the digital instructions received from the instruction management circuit; and an analog instruction execution circuit executing the analog instructions received from the instruction management circuit, wherein executing the analog instructions includes generating or measuring an analog signal at an input / output of the processor.

[0140] Example 9 includes the subject matter of any of Examples 1 to 8, wherein each processor of the plurality of processors comprises a core synchronization matrix for synchronizing with other processors of the plurality of processors.

[0141] A tenth example includes the subject matter of any one of the first to ninth examples, wherein the analog instruction execution circuitry includes a plurality of digital signal processors, and the plurality of digital signal processors execute a plurality of analog instructions in parallel.

[0142] Example 11 includes the subject matter of any of Examples 1-10, further including a plurality of qubits, wherein each digital signal processor of the plurality of digital signal processors controls two or more qubits of the plurality of qubits.

[0143] Example 12 includes the subject matter of any of Examples 1-11, wherein the instruction management circuitry receives the multiple instructions in a single clock cycle.

[0144] Example 13 includes the subject matter of any of Examples 1-12, wherein a latency of transmission of each analog instruction of the plurality of instructions to the analog instruction execution circuitry is less than 1 nanosecond.

[0145] Example 14 includes the subject matter of any of examples 1-13, wherein the processor has a von Neumann architecture.

[0146] Example 15 includes an apparatus comprising: a plurality of qubits; and a processor, wherein the processor executes digital instructions and analog instructions, and executing the analog instructions includes transmitting an analog signal to a qubit of the plurality of qubits or measuring an analog signal from a qubit of the plurality of qubits.

[0147] Example 16 includes the subject matter of example 15, further including a plurality of processors, each processor in a separate package, each processor of the plurality of processors executing digital instructions and analog instructions, and executing the analog instructions comprising transmitting an analog signal to a qubit of the plurality of qubits or measuring an analog signal from a qubit of the plurality of qubits.

[0148] Example 17 includes the subject matter of any of examples 15 and 16, wherein the processor executes instructions to load one or more parameters into one or more registers; and the processor executes instructions to generate an analog pulse based on the one or more parameters in the one or more registers.

[0149] Example 18 includes the subject matter of any of Examples 15-17, wherein the one or more parameters in the one or more registers are used to control the amplitude and frequency of the analog pulses.

[0150] Example 19 includes the subject matter of any of examples 15-18, wherein the processor executes instructions to generate analog pulses and measure reflections of the generated analog pulses.

[0151] Example 20 includes the subject matter of any of Examples 15-19, wherein the processor has a plurality of processor cores, each processor core of the plurality of processor cores executes digital instructions and analog instructions, and executing the analog instructions includes transmitting an analog signal to a qubit of the plurality of qubits or measuring an analog signal from a qubit of the plurality of qubits.

[0152] Example 21 includes the subject matter of any of Examples 15 to 20, wherein the processor further includes a core synchronization matrix that synchronizes between processor cores of the plurality of processor cores.

[0153] Example 22 includes the subject matter of any of Examples 15-21, further including a plurality of processors, each processor in a separate package, each processor of the plurality of processors having a plurality of processor cores, each processor core of the plurality of processors of each processor of the plurality of processors executing digital instructions and analog instructions, and executing the analog instructions includes transmitting an analog signal to a qubit of the plurality of qubits or measuring an analog signal from a qubit of the plurality of qubits.

[0154] Example 23 includes the subject matter of any of Examples 15-22, wherein each processor of the plurality of processors comprises a core synchronization matrix for synchronizing with other processors of the plurality of processors.

[0155] Example 24 includes the subject matter of any of Examples 15-23, wherein the processor comprises a plurality of digital signal processors, and the plurality of digital signal processors execute a plurality of analog instructions in parallel.

[0156] Example 25 includes the subject matter of any of Examples 15-24, wherein each digital signal processor of the plurality of digital signal processors controls two or more qubits of the plurality of qubits.

[0157] Example 26 includes the subject matter of any of examples 15-25, wherein the processor receives the instructions in a single clock cycle.

[0158] Example 27 includes the subject matter of any of examples 15-26, wherein the processor has a von Neumann architecture.

[0159] Example 28 includes a quantum compute device comprising: a first processor; a plurality of qubits; a second processor; and one or more computer-readable media storing a plurality of instructions for the first processor that, when executed by the first processor, cause the first processor to send a plurality of instructions for the second processor to the second processor, wherein the plurality of instructions for the second processor comprises one or more digital instructions and one or more analog instructions, and the one or more analog instructions, when executed by the second processor, cause the second processor to generate or measure an analog signal at an input / output of the second processor.

[0160] Example 29 further includes the subject matter of example 28, wherein the plurality of instructions for the first processor causes the first processor to compile code into the plurality of instructions for the second processor, where compiling code into the plurality of instructions for the second processor comprises optimizing the one or more digital instructions and the one or more analog instructions of the plurality of instructions for the second processor.

[0161] Example 30 includes the subject matter of any of Examples 28 and 29, wherein the second processor has multiple cores, and wherein optimizing the one or more digital instructions and the one or more analog instructions of the multiple instructions for the second processor includes optimizing the one or more digital instructions and the one or more analog instructions of the multiple instructions for the multiple cores.

[0162] Example 31 includes the subject matter of any of Examples 28-30, wherein optimizing the one or more digital instructions and the one or more analog instructions of the plurality of instructions for the second processor comprises optimizing the one or more digital instructions and the one or more analog instructions of the plurality of instructions for a plurality of second processors.

[0163] Example 32 includes the subject matter of any of Examples 28-31, wherein the one or more digital instructions, when executed by the second processor, cause the second processor to load one or more parameters into one or more registers; and the one or more analog instructions, when executed by the second processor, cause the second processor to generate an analog pulse based on the one or more parameters in the one or more registers.

[0164] Example 33 includes the subject matter of any of Examples 28-32, wherein the one or more parameters in the one or more registers are used to control the amplitude and frequency of the analog pulses.

[0165] Example 34 includes the subject matter of any of Examples 28-33, wherein the one or more digital instructions, when executed by the second processor, cause the second processor to generate an analog pulse and measure a reflection of the generated analog pulse.

[0166] Example 35 includes the subject matter of any of Examples 28 to 34, wherein the second processor has multiple processor cores.

[0167] Example 36 includes the subject matter of any of Examples 28 to 35, wherein the second processor further includes a core synchronization matrix that synchronizes between processor cores of the plurality of processor cores.

[0168] Example 37 includes the subject matter of any of Examples 28-36, wherein the quantum compute device has a plurality of second processors, and further includes scheduling instructions on individual second processors of the plurality of digital / analog processors.

[0169] Example 38 includes the subject matter of any of Examples 28 to 37, wherein each second processor among the plurality of second processors has a core synchronization matrix for synchronizing with other second processors of the plurality of second processors.

[0170] Example 39 includes the subject matter of any of Examples 28 to 38, wherein the instructions for the first processor further cause the first processor to communicate with a core synchronization matrix of each of the plurality of second processors by the first processor to synchronize the plurality of second processors.

[0171] Example 40 includes the subject matter of any of Examples 28-39, wherein the second processor comprises a plurality of digital signal processors, and the plurality of digital signal processors execute a plurality of analog instructions in parallel.

[0172] Example 41 includes the subject matter of any of Examples 28-40, wherein each digital signal processor of the plurality of digital signal processors controls two or more qubits of the plurality of qubits.

[0173] Example 42 includes the subject matter of any of examples 28-41, wherein the second processor has a von Neumann architecture.

[0174] Example 43 includes a method comprising: sending, by a first processor of a quantum compute device, a plurality of instructions for a second processor of the quantum compute device to the second processor, wherein the plurality of instructions for the second processor comprises one or more digital instructions and one or more analog instructions, the one or more analog instructions, when executed by the second processor, cause the second processor to generate or measure an analog signal at an input / output of the second processor.

[0175] Example 44 includes the subject matter of example 43, and further includes compiling, by the first processor, code into the plurality of instructions for the second processor, wherein compiling the code into the plurality of instructions for the second processor includes optimizing the one or more digital instructions and the one or more analog instructions of the plurality of instructions for the second processor.

[0176] Example 45 includes the subject matter of any of Examples 43 and 44, wherein the second processor has multiple cores, and wherein optimizing the one or more digital instructions and the one or more analog instructions of the multiple instructions for the second processor includes optimizing the one or more digital instructions and the one or more analog instructions of the multiple instructions for the multiple cores.

[0177] Example 46 includes the subject matter of any of Examples 43-45, wherein optimizing the one or more digital instructions and the one or more analog instructions of the plurality of instructions for the second processor comprises optimizing the one or more digital instructions and the one or more analog instructions of the plurality of instructions for a plurality of second processors.

[0178] Example 47 includes the subject matter of any of Examples 43-46, wherein the one or more digital instructions, when executed by the second processor, cause the second processor to load one or more parameters into one or more registers; and the one or more analog instructions, when executed by the second processor, cause the second processor to generate an analog pulse based on the one or more parameters in the one or more registers.

[0179] Example 48 includes the subject matter of any of Examples 43-47, wherein the one or more parameters in the one or more registers are used to control the amplitude and frequency of the analog pulses.

[0180] Example 49 includes the subject matter of any of Examples 43-48, wherein the one or more digital instructions, when executed by the second processor, cause the second processor to generate an analog pulse and measure a reflection of the generated analog pulse.

[0181] Example 50 includes the subject matter of any of Examples 43 to 49, wherein the second processor has multiple processor cores.

[0182] Example 51 includes the subject matter of any of Examples 43 to 50, wherein the second processor further includes a core synchronization matrix that synchronizes between processor cores of the plurality of processor cores.

[0183] Example 52 includes the subject matter of any of Examples 43 to 51, wherein the quantum compute device has a plurality of second processors, and further includes scheduling instructions on individual second processors of the plurality of digital / analog processors.

[0184] Example 53 includes the subject matter of any of Examples 43 to 52, wherein each second processor among the plurality of second processors has a core synchronization matrix for synchronizing with other second processors of the plurality of second processors.

[0185] Example 54 includes the subject matter of any of Examples 43 to 53, and further includes communicating, by the first processor, with core synchronization matrices of individual ones of the plurality of second processors to synchronize the plurality of second processors.

[0186] Example 55 includes the subject matter of any of Examples 43-54, wherein the second processor comprises a plurality of digital signal processors, and the plurality of digital signal processors execute a plurality of analog instructions in parallel.

[0187] Example 56 includes the subject matter of any of Examples 43-55, wherein the quantum compute device has a plurality of qubits, and wherein each digital signal processor of the plurality of digital signal processors controls two or more qubits of the plurality of qubits.

[0188] Example 57 includes the subject matter of any of examples 43-56, wherein the second processor has a von Neumann architecture.

[0189] Example 58 includes a quantum compute device comprising: a first processor comprising a plurality of qubits; a second processor; and means for transmitting a plurality of instructions for the second processor of the quantum compute device to the second processor, the plurality of instructions for the second processor comprising one or more digital instructions and one or more analog instructions, the one or more analog instructions, when executed by the second processor, causing the second processor to generate or measure an analog signal at an input / output of the second processor.

[0190] Example 59 includes the subject matter of example 58, and further includes means for compiling, by the first processor, code into the plurality of instructions for the second processor, wherein the means for compiling the code into the plurality of instructions for the second processor includes means for optimizing the one or more digital instructions and the one or more analog instructions of the plurality of instructions for the second processor.

[0191] Example 60 includes the subject matter of any of Examples 58 and 59, wherein the second processor has multiple cores, and wherein the means for optimizing the one or more digital instructions and the one or more analog instructions of the multiple instructions for the second processor comprises means for optimizing the one or more digital instructions and the one or more analog instructions of the multiple instructions for the multiple cores.

[0192] Example 61 includes the subject matter of any of Examples 58-60, wherein the means for optimizing the one or more digital instructions and the one or more analog instructions of the plurality of instructions for the second processor comprises means for optimizing the one or more digital instructions and the one or more analog instructions of the plurality of instructions for a plurality of second processors.

[0193] Example 62 includes the subject matter of any of Examples 58-61, wherein the one or more digital instructions, when executed by the second processor, cause the second processor to load one or more parameters into one or more registers, and the one or more analog instructions, when executed by the second processor, cause the second processor to generate an analog pulse based on the one or more parameters in the one or more registers.

[0194] Example 63 includes the subject matter of any of Examples 58-62, wherein the one or more parameters in the one or more registers are used to control the amplitude and frequency of the analog pulses.

[0195] Example 64 includes the subject matter of any of Examples 58-63, wherein the one or more digital instructions, when executed by the second processor, cause the second processor to generate an analog pulse and measure a reflection of the generated analog pulse.

[0196] Example 65 includes the subject matter of any of Examples 58 to 64, wherein the second processor has multiple processor cores.

[0197] Example 66 includes the subject matter of any of Examples 58 to 65, wherein the second processor further includes a core synchronization matrix that synchronizes between processor cores of the plurality of processor cores.

[0198] Example 67 includes the subject matter of any of Examples 58 to 66, wherein the quantum compute device has a plurality of second processors and further has means for scheduling instructions on individual second processors of the plurality of digital / analog processors.

[0199] Example 68 includes the subject matter of any of Examples 58 to 67, and further includes a core synchronization matrix for each second processor among the plurality of second processors to synchronize with other second processors among the plurality of second processors.

[0200] Example 69 includes the subject matter of any of Examples 58 to 68, further including means for the first processor to communicate with a core synchronization matrix of each of the plurality of second processors to synchronize the plurality of second processors.

[0201] Example 70 includes the subject matter of any of Examples 58-69, wherein the second processor comprises a plurality of digital signal processors, and the plurality of digital signal processors execute a plurality of analog instructions in parallel.

[0202] Example 71 includes the subject matter of any of Examples 58-70, wherein each digital signal processor of the plurality of digital signal processors controls two or more qubits of the plurality of qubits.

[0203] Example 72 includes the subject matter of any of Examples 58-71, wherein the second processor has a von Neumann architecture.

[0204] Example 73 includes one or more computer-readable media having stored thereon a plurality of instructions for a first processor of a quantum compute device that, when executed, causes the first processor to send a plurality of instructions for the second processor to the second processor, wherein the plurality of instructions for the second processor comprises one or more digital instructions and one or more analog instructions, and the one or more analog instructions, when executed by the second processor, cause the second processor to generate or measure an analog signal at an input / output of the second processor.

[0205] Example 74 further includes the subject matter of Example 73, wherein the plurality of instructions for the first processor causes the first processor to compile code into the plurality of instructions for the second processor, wherein compiling code into the plurality of instructions for the second processor includes optimizing the one or more digital instructions and the one or more analog instructions of the plurality of instructions for the second processor.

[0206] Example 75 includes the subject matter of any of Examples 73 and 74, wherein the second processor has multiple cores, and optimizing the one or more digital instructions and the one or more analog instructions of the multiple instructions for the second processor includes optimizing the one or more digital instructions and the one or more analog instructions of the multiple instructions for the multiple cores.

[0207] Example 76 includes the subject matter of any of Examples 73-75, wherein optimizing the one or more digital instructions and the one or more analog instructions of the plurality of instructions for the second processor comprises optimizing the one or more digital instructions and the one or more analog instructions of the plurality of instructions for a plurality of second processors.

[0208] Example 77 includes the subject matter of any of Examples 73-76, wherein the one or more digital instructions, when executed by the second processor, cause the second processor to load one or more parameters into one or more registers, and the one or more analog instructions, when executed by the second processor, cause the second processor to generate an analog pulse based on the one or more parameters in the one or more registers.

[0209] Example 78 includes the subject matter of any of Examples 73-77, wherein the one or more parameters in the one or more registers are used to control the amplitude and frequency of the analog pulses.

[0210] Example 79 includes the subject matter of any of Examples 73-78, wherein the one or more digital instructions, when executed by the second processor, cause the second processor to generate an analog pulse and measure a reflection of the generated analog pulse.

[0211] Example 80 includes the subject matter of any of Examples 73 to 79, wherein the second processor has multiple processor cores.

[0212] Example 81 includes the subject matter of any of Examples 73 to 80, wherein the second processor further includes a core synchronization matrix that synchronizes between processor cores of the plurality of processor cores.

[0213] Example 82 includes the subject matter of any of Examples 73 to 81, wherein the quantum compute device has a plurality of second processors, and further includes scheduling instructions on individual second processors of the plurality of digital / analog processors.

[0214] Example 83 includes the subject matter of any of Examples 73 to 82, and further includes a core synchronization matrix for each second processor among the plurality of second processors to synchronize with other second processors among the plurality of second processors.

[0215] Example 84 includes the subject matter of any of Examples 73 to 83, wherein the instructions for the first processor further cause the first processor to communicate with a core synchronization matrix of each of the plurality of second processors by the first processor to synchronize the plurality of second processors.

[0216] Example 85 includes the subject matter of any of Examples 73-84, wherein the second processor comprises a plurality of digital signal processors, and the plurality of digital signal processors execute a plurality of analog instructions in parallel.

[0217] Example 86 includes the subject matter of any of Examples 73-85, wherein each digital signal processor of the plurality of digital signal processors controls two or more qubits of the plurality of qubits.

[0218] Example 87 includes the subject matter of any of Examples 73 to 86, wherein the second processor has a von Neumann architecture.

[0219] Example 88 includes a quantum compute device comprising a processor, the processor receiving an instruction; determining whether the instruction is a digital instruction or an analog instruction; and executing the instruction as an analog instruction in response to determining that the instruction is an analog instruction, wherein executing the instruction includes generating an analog signal or measuring an analog signal.

[0220] Example 89 includes the quantum compute device of Example 88, wherein the processor further receives, by the processor, a second instruction; determines, by the processor, whether the second instruction is a digital instruction or an analog instruction; and executes, by the processor, the second instruction as a digital instruction in response to determining that the second instruction is a digital instruction.

[0221] Example 90 includes the subject matter of any of Examples 88 and 89, wherein executing the second instruction includes loading one or more parameters into one or more registers, and executing the instruction includes generating an analog pulse based on the one or more parameters in the one or more registers.

[0222] Example 91 includes the subject matter of any of Examples 88-90, wherein the one or more parameters in the one or more registers are used to control the amplitude and frequency of the analog pulses.

[0223] Example 92 includes the subject matter of any of Examples 88-91, wherein executing the instructions includes generating an analog pulse and measuring a reflection of the generated analog pulse.

[0224] Example 93 includes the subject matter of any of Examples 88 to 92, wherein the processor has multiple processor cores.

[0225] Example 94 includes the subject matter of any of Examples 88 to 93, wherein the processor further includes a core synchronization matrix that synchronizes between processor cores of the plurality of processor cores.

[0226] Example 95 includes the subject matter of any of Examples 88-94, wherein the processor comprises a plurality of digital signal processors, and the plurality of digital signal processors execute a plurality of analog instructions in parallel.

[0227] Example 96 includes the subject matter of any of Examples 88-95, wherein each digital signal processor of the plurality of digital signal processors controls two or more qubits of the plurality of qubits.

[0228] Example 97 includes the subject matter of any of Examples 88-96, wherein the processor further receives the instructions in a single clock cycle.

[0229] Example 98 includes the subject matter of any of Examples 88-97, wherein the processor has a von Neumann architecture.

[0230] Example 99 includes a method comprising: receiving an instruction by a processor; determining, by the processor, whether the instruction is a digital instruction or an analog instruction; and, in response to a determination that the instruction is an analog instruction, executing, by the processor, the instruction as an analog instruction, wherein executing the instruction includes generating an analog signal or measuring an analog signal.

[0231] Example 100 includes the method of example 99, further including receiving, by the processor, a second instruction; determining, by the processor, whether the second instruction is a digital instruction or an analog instruction; and, in response to determining that the second instruction is a digital instruction, executing, by the processor, the second instruction as a digital instruction.

[0232] Example 101 includes the subject matter of any of Examples 99 and 100, wherein executing the second instruction includes loading one or more parameters into one or more registers, and executing the instruction includes generating an analog pulse based on the one or more parameters in the one or more registers.

[0233] Example 102 includes the subject matter of any of Examples 99-101, wherein the one or more parameters in the one or more registers are used to control the amplitude and frequency of the analog pulses.

[0234] Example 103 includes the subject matter of any of Examples 99-102, wherein executing the instructions includes generating an analog pulse and measuring a reflection of the generated analog pulse.

[0235] Example 104 includes the subject matter of any of Examples 99 to 103, wherein the processor has multiple processor cores.

[0236] Example 105 includes the subject matter of any of Examples 99 to 104, wherein the processor further includes a core synchronization matrix that synchronizes between processor cores of the plurality of processor cores.

[0237] Example 106 includes the subject matter of any of Examples 99 to 105, wherein the processor comprises a plurality of digital signal processors, and the plurality of digital signal processors execute a plurality of analog instructions in parallel.

[0238] Example 107 includes the subject matter of any of Examples 99-106, wherein each digital signal processor of the plurality of digital signal processors controls two or more qubits of the plurality of qubits.

[0239] Example 108 includes the subject matter of any of Examples 99-107, further including receiving, by the processor, multiple instructions in a single clock cycle.

[0240] Example 109 includes the subject matter of any of Examples 99-108, wherein the processor has a von Neumann architecture.

[0241] Example 110 includes a quantum compute device comprising: means for receiving an instruction; means for determining whether the instruction is a digital instruction or an analog instruction; and means for executing the instruction as an analog instruction in response to determining that the instruction is an analog instruction, wherein the means for executing the instruction comprises means for generating or measuring an analog signal.

[0242] Example 111 includes the subject matter of example 110, and further includes means for receiving a second instruction; means for determining whether the second instruction is a digital instruction or an analog instruction; and means for executing the second instruction as a digital instruction in response to determining that the second instruction is a digital instruction.

[0243] Example 112 includes the subject matter of any of Examples 110 and 111, wherein the means for executing the second instructions comprises loading one or more parameters into one or more registers, and the means for executing the instructions comprises means for generating an analog pulse based on the one or more parameters in the one or more registers.

[0244] Example 113 includes the subject matter of any of Examples 110-112, wherein the one or more parameters in the one or more registers are used to control the amplitude and frequency of the analog pulses.

[0245] Example 114 includes the subject matter of any of Examples 110-113, wherein the means for executing the instructions comprises means for generating an analog pulse and measuring a reflection of the generated analog pulse.

[0246] Example 115 includes the subject matter of any of Examples 110 to 114, wherein the means for executing the instructions as analog instructions comprises a plurality of digital signal processors, and the plurality of digital signal processors execute a plurality of analog instructions in parallel.

[0247] Example 116 includes the subject matter of any of Examples 110-115, wherein each digital signal processor of the plurality of digital signal processors controls two or more qubits of the plurality of qubits.

[0248] Example 117 includes the subject matter of any of Examples 110-116, further including means for receiving multiple instructions in a single clock cycle.

[0249] Example 118 includes the subject matter of any of Examples 110-117, wherein the means for executing the instructions as analog instructions has a Von Neumann architecture. [Item 1] a processor having a processor core, the processor core comprising: an instruction management circuit, a digital instruction execution circuit, and an analog instruction execution circuit, said instruction management circuit: Receive multiple orders; determining whether each instruction of the plurality of instructions is a digital instruction or an analog instruction; transmitting a respective digital instruction of the plurality of instructions to the digital instruction execution circuitry in response to determining that the corresponding respective instruction is a digital instruction; and transmitting a respective analog instruction of the plurality of instructions to the analog instruction execution circuitry in response to determining that the corresponding respective instruction is an analog instruction; the analog instruction execution circuitry executes analog instructions received from the instruction management circuitry, and executing the analog instructions includes generating or measuring analog signals at input / outputs of the processor. Device. [Item 2] Item 10. The apparatus of item 1, wherein the digital instruction execution circuitry executes instructions to load one or more parameters into one or more registers, and the analog instruction execution circuitry executes instructions to generate an analog pulse based on the one or more parameters in the one or more registers. [Item 3] 3. The apparatus of claim 2, wherein the one or more parameters in the one or more registers are used to control the amplitude and frequency of the analog pulses. [Item 4] 4. The apparatus of any one of items 1 to 3, wherein the analog instruction execution circuitry executes instructions to generate an analog pulse and measure reflections of the generated analog pulse. [Item 5] 5. The device according to any one of items 1 to 4, wherein the analog instruction execution circuitry operates in a first clock domain and the digital instruction execution circuitry operates in a second clock domain different from the first clock domain. [Item 6] 6. The device according to any one of items 1 to 5, wherein the analog instruction execution circuitry has a plurality of digital signal processors, and the plurality of digital signal processors execute a plurality of analog instructions in parallel. [Item 7] Item 7. The apparatus of item 6, further comprising a plurality of qubits, wherein each digital signal processor of the plurality of digital signal processors controls two or more qubits of the plurality of qubits. [Item 8] 8. The apparatus of claim 1, wherein the instruction management circuitry receives the plurality of instructions in a single clock cycle. [Item 9] 9. The apparatus according to any one of items 1 to 8, wherein the latency of transmission of an individual analog instruction of the plurality of instructions to the analog instruction execution circuitry is less than 1 nanosecond. [Item 10] a plurality of qubits; and a processor; the processor executes digital instructions and analog instructions, and executing the analog instructions comprises transmitting an analog signal to a qubit of the plurality of qubits or measuring an analog signal from a qubit of the plurality of qubits. Device. [Item 11] further comprising a plurality of processors, each processor in a separate package; Each processor of the plurality of processors executes digital instructions and analog instructions, and executing an analog instruction comprises transmitting an analog signal to a qubit of the plurality of qubits or measuring an analog signal from a qubit of the plurality of qubits. Item 11. The device according to item 10. [Item 12] 12. The apparatus of any one of items 10 to 11, wherein the processor executes instructions to load one or more parameters into one or more registers, and the processor executes instructions to generate an analog pulse based on the one or more parameters in the one or more registers. [Item 13] Item 13. The apparatus of item 12, wherein the one or more parameters in the one or more registers are used to control the amplitude and frequency of the analog pulses. [Item 14] 14. The apparatus of any of items 10 to 13, wherein the processor executes instructions to generate an analog pulse and measure reflections of the generated analog pulse. [Item 15] the processor has multiple processor cores; each processor core of the plurality of processor cores executes digital instructions and analog instructions, and executing an analog instruction includes transmitting an analog signal to a qubit of the plurality of qubits or measuring an analog signal from a qubit of the plurality of qubits; The device according to any one of items 10 to 14. [Item 16] Item 16. The apparatus of item 15, wherein the processor further includes a core synchronization matrix for synchronizing between processor cores of the plurality of processor cores. [Item 17] 17. The apparatus of any of items 10 to 16, further comprising a plurality of processors, each processor in a separate package, each processor of the plurality of processors having a plurality of processor cores, each processor core of the plurality of processors of each processor of the plurality of processors executing digital instructions and analog instructions, and executing the analog instructions includes transmitting an analog signal to a qubit of the plurality of qubits or measuring an analog signal from a qubit of the plurality of qubits. [Item 18] Item 18. The apparatus of item 17, wherein each processor of the plurality of processors has a core synchronization matrix for synchronizing with other processors of the plurality of processors. [Item 19] 19. The apparatus according to any one of items 10 to 18, wherein the processor comprises a plurality of digital signal processors, the plurality of digital signal processors executing a plurality of analog instructions in parallel. [Item 20] 20. The apparatus of claim 19, wherein each digital signal processor of the plurality of digital signal processors controls two or more qubits of the plurality of qubits. [Item 21] 21. The apparatus according to any one of items 10 to 20, wherein the processor receives multiple instructions in a single clock cycle. [Item 22] First processor; Multiple cubits; a second processor; and The program is stored therein and, when executed by the first processor, causes the first processor to: sending a plurality of instructions for the second processor to the second processor, wherein the plurality of instructions for the second processor comprises one or more digital instructions and one or more analog instructions, the one or more analog instructions, when executed by the second processor, causing the second processor to generate or measure an analog signal at an input / output of the second processor; one or more computer-readable media having a plurality of instructions for the first processor to perform A quantum computing device comprising: [Item 23] The instructions for the first processor include: Compiling code into the plurality of instructions for the second processor, where compiling code into the plurality of instructions for the second processor comprises optimizing the one or more digital instructions and the one or more analog instructions of the plurality of instructions for the second processor. 23. The quantum computing device of claim 22, further comprising: [Item 24] 24. The quantum compute device of claim 23, wherein the second processor has a plurality of cores, and wherein optimizing the one or more digital instructions and the one or more analog instructions of the plurality of instructions for the second processor comprises optimizing the one or more digital instructions and the one or more analog instructions of the plurality of instructions for the plurality of cores. [Item 25] 25. The quantum compute device of claim 23, wherein optimizing the one or more digital instructions and the one or more analog instructions of the plurality of instructions for the second processor comprises optimizing the one or more digital instructions and the one or more analog instructions of the plurality of instructions for a plurality of second processors.

Claims

1. a processor having a processor core, the processor core comprising: an instruction management circuit, a digital instruction execution circuit, and an analog instruction execution circuit, said instruction management circuit: Receive multiple commands; determining whether each instruction of said plurality of instructions is a digital instruction or an analog instruction; transmitting each digital instruction of the plurality of instructions to the digital instruction execution circuitry in response to determining that the corresponding individual instruction is a digital instruction; and transmitting a respective analog instruction of the plurality of instructions to the analog instruction execution circuitry in response to determining that the corresponding respective instruction is an analog instruction; the analog instruction execution circuitry executes analog instructions received from the instruction management circuitry, and executing analog instructions includes generating or measuring analog signals at input / outputs of the processor. Device.

2. 2. The apparatus of claim 1, wherein the digital instruction execution circuitry executes instructions to load one or more parameters into one or more registers, and the analog instruction execution circuitry executes instructions to generate an analog pulse based on the one or more parameters in the one or more registers.

3. The apparatus of claim 2 , wherein the one or more parameters in the one or more registers are used to control the amplitude and frequency of the analog pulses.

4. 4. Apparatus according to any one of claims 1 to 3, wherein the analogue instruction execution circuitry executes instructions to generate analogue pulses and measure reflections of the generated analogue pulses.

5. 4. The apparatus of claim 1, wherein the analog instruction execution circuitry operates in a first clock domain and the digital instruction execution circuitry operates in a second clock domain different from the first clock domain.

6. 4. Apparatus according to any one of claims 1 to 3, wherein the analogue instruction execution circuitry comprises a plurality of digital signal processors, the plurality of digital signal processors executing a plurality of analogue instructions in parallel.

7. 7. The apparatus of claim 6, further comprising a plurality of qubits, wherein each digital signal processor of the plurality of digital signal processors controls two or more qubits of the plurality of qubits.

8. The apparatus of any one of claims 1 to 3, wherein the instruction management circuitry receives the instructions in a single clock cycle.

9. 4. Apparatus according to any one of claims 1 to 3, wherein the latency of transmission of an individual analog instruction of said plurality of instructions to said analog instruction execution circuitry is less than 1 nanosecond.

10. a plurality of qubits; and a processor; the processor executes digital instructions and analog instructions, and executing the analog instructions comprises transmitting an analog signal to a qubit of the plurality of qubits or measuring an analog signal from a qubit of the plurality of qubits. Device.

11. further comprising a plurality of processors, each processor in a separate package; Each processor of the plurality of processors executes digital instructions and analog instructions, and executing an analog instruction comprises transmitting an analog signal to a qubit of the plurality of qubits or measuring an analog signal from a qubit of the plurality of qubits.

11. The apparatus of claim 10.

12. 12. The apparatus of claim 10 or 11, wherein the processor executes instructions to load one or more parameters into one or more registers, and wherein the processor executes instructions to generate an analog pulse based on the one or more parameters in the one or more registers.

13. 13. The apparatus of claim 12, wherein the one or more parameters in the one or more registers are used to control the amplitude and frequency of the analog pulses.

14. 12. Apparatus according to claim 10 or 11, wherein the processor executes instructions for generating an analog pulse and measuring reflections of the generated analog pulse.

15. the processor has multiple processor cores; each processor core of the plurality of processor cores executes digital instructions and analog instructions, and executing an analog instruction includes transmitting an analog signal to a qubit of the plurality of qubits or measuring an analog signal from a qubit of the plurality of qubits; 12. Apparatus according to claim 10 or 11.

16. The apparatus of claim 15 , wherein the processor further comprises a core synchronization matrix for providing synchronization between processor cores of the plurality of processor cores.

17. 12. The apparatus of claim 10 or 11, further comprising a plurality of processors, each processor in a separate package, each processor of the plurality of processors having a plurality of processor cores, each processor core of the plurality of processor cores of each processor of the plurality of processors executing digital instructions and analog instructions, and executing the analog instructions includes transmitting an analog signal to a qubit of the plurality of qubits or measuring an analog signal from a qubit of the plurality of qubits.

18. 20. The apparatus of claim 17, wherein each processor of the plurality of processors has a core synchronization matrix for synchronizing with other processors of the plurality of processors.

19. a first processor; Multiple cubits; a second processor; and stored therein and, when executed by the first processor, causing the first processor to: sending a plurality of instructions for the second processor to the second processor, wherein the plurality of instructions for the second processor comprises one or more digital instructions and one or more analog instructions, the one or more analog instructions, when executed by the second processor, causing the second processor to generate or measure an analog signal at an input / output of the second processor; one or more computer-readable media having a plurality of instructions for the first processor to perform A quantum computing device comprising:

20. The instructions for the first processor include instructions for the first processor: Compiling code into the plurality of instructions for the second processor, where compiling code into the plurality of instructions for the second processor comprises optimizing the one or more digital instructions and the one or more analog instructions of the plurality of instructions for the second processor.

20. The quantum compute device of claim 19, further comprising:

21. 1. A quantum compute device, comprising: a first processor; Multiple cubits; a second processor; and means for transmitting a plurality of instructions for the second processor of the quantum compute device to the second processor, wherein the plurality of instructions for the second processor comprises one or more digital instructions and one or more analog instructions, the one or more analog instructions, when executed by the second processor, causing the second processor to generate or measure an analog signal at an input / output of the second processor; A quantum computing device comprising:

22. means for compiling, by the first processor, code into the plurality of instructions for the second processor, wherein the means for compiling code into the plurality of instructions for the second processor comprises means for optimizing the one or more digital instructions and the one or more analog instructions of the plurality of instructions for the second processor; 22. The quantum compute device of claim 21 further comprising:

23. 23. The quantum compute device of claim 22, wherein the second processor has a plurality of cores, and wherein the means for optimizing the one or more digital instructions and the one or more analog instructions of the plurality of instructions for the second processor comprises means for optimizing the one or more digital instructions and the one or more analog instructions of the plurality of instructions for the plurality of cores.

24. 24. The quantum compute device of claim 22 or 23, wherein the means for optimizing the one or more digital instructions and the one or more analog instructions of the plurality of instructions for the second processor comprises means for optimizing the one or more digital instructions and the one or more analog instructions of the plurality of instructions for a plurality of second processors.

25. 24. The quantum compute device of any one of claims 21 to 23, wherein the one or more digital instructions, when executed by the second processor, cause the second processor to load one or more parameters into one or more registers, and the one or more analog instructions, when executed by the second processor, cause the second processor to generate an analog pulse based on the one or more parameters in the one or more registers.

Images