Orthogonal Circuit Interconnect Architecture with Clock Forwarding

Abstract

An integrated circuit communication architecture is provided, comprising a clock lane, a clock divider, and a first deskew circuit. The clock lane is configured to transmit a clock signal from a first chip to a second chip at a first rate. The clock divider is on the second chip and configured to receive the clock signal transmitted via the clock lane and to create and transmit a first divided clock signal and a second divided clock signal from the received clock signal. The divided clock signals are transmitted at a reduced rate compared to the first rate. The clock divider maintains current-mode logic characteristics for the divided clock signal. The first deskew circuit is configured to receive and process the divided clock signal to enable sampling of data transmitted from the first chip to the second chip.

Description

[Background technology]

[0001] The present invention relates generally to processors used in computer systems such as personal computers, servers, and / or other computing devices that have computer chips.

[0002] The demand for faster, more powerful, and more energy-efficient computers has led to improved computer chip and computer chip package designs. Improved designs have been attempted to allow for expanded processor core counts and improved memory bandwidth. Chip designs have been implemented using smaller dies.

[0003] Embedded multi-die interconnect bridges (EMIBs) have been created, complex multi-layer slivers of silicon that allow large amounts of data to be sent back and forth between adjacent chips at high speeds. High Bandwidth Memory (HBM) has been adopted as the industry standard and is a high-speed memory interface for 3D-stacked synchronous dynamic random access memories. EMIB and HBM designs transmit many signals between chips but can suffer from performance impacts, especially when the two chips are not positioned closely adjacent to each other. For slightly longer interconnects, such as those with lengths in the high single digits to tens of millimeters, standard connections such as personal component interconnect express (PCIe) or double data rate (DDR) have been used. However, these standard connections consume a lot of power for short interfaces.

[0004] The new interconnects typically use shorter pitches between chips, formatted with controlled collapse chip protection, so area constraints are much tighter and they don't work with standard serializer / deserializers (SerDes).

[0005] Ali et al., US 8,116,420 B2, provides a clock forwarding technique for high-speed links. The clock forwarding technique involves the use of a repeater circuit, such as a clock recovery and multiplication circuit. In the repeater circuit, a clock multiplier unit (CMU) generates an internal clock signal based on the forwarded clock signal, which is received on the link.

[0006] Other interfaces, such as Bunch of Wires (BoW), have attempted to simplify the interconnect, preserving the terminating SerDes aspects of the complex interface but removing much of the complexity. However, BoW designs suffer from performance limitations due to receiver clock requirements.

[0007] A clock data recovery (CDR) circuit determines the clock signal by interpreting the transmitted data without any additional clock signal lanes. However, the CDR circuit requires significant overhead to re-establish the clock from the transmitted data. The overhead can consume significant power.

[0008] The prior art has the disadvantage of lacking the combination of improved bandwidth, low latency, and reduced power requirements for the chip and chip package, and may require high-power consumption structures such as a clock data recovery (CDR) circuit in the receiver macro, a phase-locked loop (PLL) on the receiver side, and / or forward error correction (FEC) redundancy. Summary of the Invention

[0009] According to one exemplary embodiment, an integrated circuit communication architecture is provided, comprising a clock lane, a clock divider, and a first deskew circuit. The clock lane is configured to transmit a clock signal from a first chip to a second chip at a first rate. The clock divider is on the second chip and configured to receive the clock signal transmitted via the clock lane and generate and transmit a first divided clock signal and a second divided clock signal from the received clock signal. The first divided clock signal and the second divided clock signal are transmitted at a reduced rate compared to the first rate. The clock divider maintains current-mode logic characteristics for the first and second divided clock signals. The first deskew circuit is configured to receive and process the first divided clock signal and the second divided clock signal to enable sampling of data transmitted from the first chip to the second chip. A method corresponding to the integrated circuit communication architecture described above is also disclosed herein.

[0010] Using this embodiment, data transmission between chips is achieved with high bandwidth, low latency, low power requirements compared to other SerDes structures, and while avoiding forward error correction (FEC) structures.

[0011] According to another exemplary embodiment, another integrated circuit communication architecture is provided, comprising a clock lane, a clock divider, and first and second receivers on a second chip. The clock lane is configured to transmit a clock signal from a first chip to a second chip at a first rate. The clock divider is on the second chip and configured to receive the clock signal transmitted via the clock lane and to create and transmit first and second divided clock signals from the received clock signal. The first and second divided clock signals are transmitted at a reduced rate compared to the first rate. The clock divider is configured to provide each of the first and second divided clock signals to both the first and second receivers.

[0012] Using this embodiment, data transmission between chips is achieved with reduced power requirements for handling the clock signal on the receiver side: multiple clock lanes for a single chip receiver can be avoided.

[0013] According to additional embodiments, the first divided clock signal may be an in-phase clock signal running at one-quarter the data rate, the second divided clock signal may be a quadrature clock signal running at one-quarter the data rate, and the quadrature clock signals may be shifted by 90 degrees.

[0014] Using this embodiment, high bandwidth and low latency data transmission is achieved over the interconnect between chips, the performance requirements for the clock path circuitry are lowered, and the need for an IQ generator per lane is eliminated. [Brief explanation of the drawings]

[0015] These and other objects, features, and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. The illustrations are for clarity purposes to facilitate understanding of the invention by those skilled in the art, and together with the detailed description, various features of the drawings are not to scale. In the drawings, the following is shown:

[0016] [Figure 1] FIG. 1 is a block diagram illustrating a chip package having a clock signal splitting feature according to at least one embodiment.

[0017] [Figure 2] FIG. 10 is a graphical comparison of signal frequencies for various signals implemented with a clock signal splitting feature in accordance with at least one embodiment.

[0018] [Figure 3] FIG. 10 is another block diagram illustrating another chip package having a clock signal splitting feature according to at least one embodiment.

[0019] [Figure 4] 1 is an operational flowchart illustrating a clock signal splitting process according to at least one embodiment.

[0020] [Figure 5] FIG. 1 is a block diagram of the internal and external components of a computer system in which one or more of the chip packages described herein may be implemented. DETAILED DESCRIPTION OF THE INVENTION

[0021] Detailed embodiments of the claimed structures and methods are disclosed herein; however, it should be understood that the disclosed embodiments are merely exemplary of the claimed structures and methods, which may be embodied in various forms. The present invention may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0022] Exemplary embodiments described below provide an integrated circuit communication architecture including improved interconnects between computer chips on a package. With the improved interconnects, processor core counts and memory bandwidth can be expanded for a package. Packages with the improved interconnects can achieve high bandwidth with low latency, enable lower power consumption, and avoid fabricated evaluation chip structures. Thus, computer systems with the improved circuit communication architectures for processors described herein achieve enhanced computing performance. The improved interconnects can be achieved by implementing clock signal forwarding and clock signal splitting to generate reduced-frequency split clock signals. The clock signal forwarding can be performed via a clock signal lane that is physically separate from one or more data lanes. The improved interconnects can also be achieved by removing clock dividers from within the chip receiver so that they are external to any particular receiver on the receiving chip, allowing the clock divider to split the clock signal to have a reduced-frequency split signal that can be served to multiple receivers on the chip in the package. With these features, the improved interconnect also reduces space requirements by requiring a single clock lane instead of multiple clock lanes between transmitter / receiver pairs of chips on a chip package.

[0023] 1 shows a block diagram illustrating a first chip package 100 with improved interconnects according to at least one embodiment. The first chip package 100 implements protective features to protect the circuitry, wiring, and / or processing components carried by the first chip package 100. The first chip package 100 may be formed from a support material that may include a plastic and / or ceramic material. The first chip package 100 has material strength and may be connected to a larger computer substrate such as a printed circuit board and / or a motherboard.

[0024] 1 shows a first chip 102 and a second chip 104 both connected to a first chip package 100. The first chip 102 and the second chip 104 may be directly connected to the first chip package 100. In the depicted embodiment, the first chip 102 and the second chip 104 have controlled collapse chip connections to the first chip package 100. Other embodiments may include individual chips connected to the chip package via other connection implementations. The chips are computer chips and may be formed from a variety of materials, including semiconductor materials such as silicon.

[0025] Each of the chips may include various components, such as cores, cache, and input / output (I / O). FIG. 1 illustrates a transmitter 106 of the first chip 102 and a receiver 108 of the second chip 104 to help illustrate aspects of the interconnect between the first chip 102 and the second chip 104. The transmitter 106 may transmit data to the receiver 108 via the interconnect. The receiver 108 may receive and process the transmitted data and send the received and processed data to other components on the second chip, such as cores, cache, and I / O, and / or to other chips or off-chip memory. In practice, the first chip 102 and the second chip 104 may each include multiple transmitters and multiple receivers for communicating with other chips, memories, and / or other chip components.

[0026] 1 shows that the interconnect between the first chip 102 and the second chip 104 may include multiple lanes, including a data lane 116 and a clock signal lane 124. Data in the form of bits having respective binary values ​​may be transmitted over the data lane 116. A clock signal may be transmitted over the clock signal lane 124 and may be used to coordinate processing of data received over the data lane 116.

[0027] FIG. 1 indicates that differential signaling is implemented using the symbol " / " within the connections / lines. With differential signaling, two complementary voltage signals may be generated and transmitted. Upon receiving them, the signals may be combined to create one information signal. In other embodiments, lanes with enhanced interconnects may implement other signaling types instead of differential signaling. For example, in other embodiments, single-ended signaling may be performed using each of the lanes of the interconnect.

[0028] 1 shows that the transmitter 106 may include a serializer block 110 and a data lane driver 114 to generate a data flow over the data lanes 116. The receiver 108 may include an equalizer 118, one or more sampling latches, and a deserializer 130 to receive data to be transmitted over the data lanes 116. The equalizer 118 may perform termination and equalization of the received data. The depicted embodiment includes multiple sampling latches: a first sampling latch 6a, a second sampling latch 6b, a third sampling latch 6c, and a fourth sampling latch 6d. The sampling latches use a clock signal generated by a deskew circuit 128 to accurately sample the data transmitted over the data lanes 116. Using the four sampling latches depicted, data can be sampled via the first sampling latch 6a, the second sampling latch 6b, the third sampling latch 6c, and the fourth sampling latch 6d at C4 clock intervals of 0, 90, 180, and 270 degrees, respectively.

[0029] Clock generator 120 may generate a clock signal for transmission along clock signal lane 124. Clock generator 120 may include current-mode logic and may feed the generated clock signal to clock lane driver 122 and to serializer block 110. The clock signal in the depicted embodiment may be in the form of a square wave with a fixed constant frequency that oscillates between the values ​​1 and 0. Clock generator 120 may generate a full-rate clock signal. A full-rate clock signal is typically half the rate of data transmission occurring within data lane 116. The clock signal may be used for synchronization on the rising edge, falling edge, and / or both the rising and falling edges of the clock signal. Clock lane driver 122, in some embodiments, may be of the same structure as data lane driver 114, but for driving a clock signal instead of data.

[0030] The clock generator 120 may feed the generated clock signal to the serializer block 110 inside the transmitter 106. The serializer block 110 serializes the data according to the clock signal. The serialized data is then driven by the data lane driver 114. This data may be driven by both the rising and falling edges of the clock, resulting in data having twice the rate of that of the clock signal, i.e., double the data rate.

[0031] The data lanes 116 and the clock signal lanes 124 may each be formed through respective metal traces on the protective material of the chip package 100. The metal traces physically connect the first chip 102 to the second chip 104. Signals may be transmitted through the metal traces.

[0032] As shown in FIG. 1 , the second chip 104 includes a clock divider 126 disposed outside the receiver 108. In at least some embodiments, the location of a deskew circuit, such as the deskew circuit 128, may be considered a physical boundary of the receiver 108. The clock divider 126 is configured to receive a clock signal transmitted via the clock signal lane 124 and create and transmit a first divided clock signal and a second divided clock signal from the received clock signal. The first divided clock signal and the second divided clock signal may each have a reduced rate compared to the first rate at which the original clock signal was generated. In the depicted embodiment, the first divided clock signal may be an in-phase signal. The second divided clock signal may be a quadrature clock signal. In the depicted embodiment, these two divided clock signals run at half the rate of the original clock signal, i.e., one-quarter of the data rate. The in-phase signals may maintain the same phase as the original clock signal. The quadrature clock signal may have a phase shifted compared to the phase of the original clock signal. This shift is the basis for the use of the name "quadrature" for the divided clock signal. This shift may be by as much as 90 degrees, at least in some embodiments.

[0033] Clock divider 126 can generate these reduced frequency clock signals while maintaining the current mode logic (CML) characteristics of the clock signal. CML circuits have lower output voltage swings compared to static CMOS circuits and are well known to those skilled in the art. CML circuits have improved performance due to the lower voltage swings and the differential nature of the signals. Being differential helps the clock signal to be more resistant to power supply noise and more resilient to potential corruption. Clock divider 126 receives the clock signal from clock lane 124 without any intervening signal buffering or any intervening voltage swing level adjustment of the clock signal. For example, in at least one embodiment, the clock signal is received by clock divider 126 without buffering the clock signal to CMOS swing levels. Higher bandwidths can be achieved by maintaining the CML characteristics and not buffering to CMOS levels.

[0034] FIG. 2 shows a graphical comparison of signal frequencies for various signals implemented with a clock signal splitting feature, according to at least one embodiment. The data signal transmitted over the data lane 116 is shown as a differential signaling pair oscillating at a first rate or frequency. The fundamental frequency refers to the time between two immediately following corresponding edges in the signal, for example, the two nearest rising edges in the signal or the two nearest falling edges in the signal. The C2 clock signal refers to the original clock signal generated via clock generator 120 and transmitted over the clock signal lane 124. The graph in FIG. 2 shows that the clock signal oscillating frequency is one-half the data rate. If the data signal travels over the data lane 116 at 20 gigabits per second (50 ps per bit), the clock signal will oscillate over the clock signal lane 124 at 10 gigahertz (100 ps cycles). The C4 clock in-phase and C4 clock quadrature lines shown in Figure 2 are examples of first and second divided clock signals produced via clock divider 126, which receives the clock signal from clock signal lane 124, and which cycle at a reduced rate compared to the clock signal. Figure 2 shows that these two signals cycle at half the rate of the C2 clock signal, i.e., one-quarter the rate of the data signal. Figure 2 shows that the in-phase clock signal maintains the phase of the C2 clock signal, but the quadrature clock signal is shifted by 90 degrees so that it is out of phase with respect to the C2 clock signal.

[0035] By distributing these lower frequency clock signals, the power requirements for these clock signals are reduced throughout the chip. The circuits distributing these clock signals can be powered down due to the reduced frequency. However, the deskew circuit 128 still successfully corrects the phase of the reduced frequency clock signals so that data from the data lanes 116 can be sampled correctly.

[0036] The clock divider 126 may further include a CML (Current Mode Logic) circuit to correct for jitter in the received clock signal. Such jitter may be a variation in the timing of a set of signal edges from an ideal value, and may be caused by noise or other disturbances within the second chip 104 or within the chip package 100.

[0037] The divided clock signal is transmitted to the receiver 108, and in particular to a deskew circuit 128 of the receiver 108. The deskew circuit 128 corrects the phase of the divided clock signal so that data received over the data lane 116 can be sampled. The deskew circuit 128 mixes the two divided clock signals to generate a final clock signal that can have any phase with edges different from the phases of the individual divided clock signals. Sampling can be based on the phase of the mixed signal. In at least one embodiment, the deskew circuit 128 includes a first phase rotator to generate the first sampling clock signal. The deskew circuit 128 may also include a second phase rotator to generate a second quadrature sampling clock signal that is shifted 90 degrees from the first sampling clock signal. In other embodiments, the deskew circuit 128 may include a delay line or delay-locked loop instead of a phase rotator to correct the phase of the divided clock signal. The deskew circuit 128 synchronizes the divided clock signal with the data.

[0038] FIG. 3 is another block diagram illustrating another chip package 300 with a clock signal splitting feature according to at least one embodiment. The another chip package 300 includes substantially similar clock forwarding, clock signal splitting, and frequency reduction concepts as those occurring with respect to the chip package 100 shown in FIG. 1. FIG. 3 illustrates the concept that another clock divider 326 on the other, second chip 304 can create divided clock signals that are provided to multiple receivers on the other, second chip. In particular, in the example shown in FIG. 3, the other clock divider 326 receives a clock signal via another clock signal lane 324, generates first and second reduced-frequency divided clock signals, e.g., an in-phase clock signal and a quadrature clock signal based on the received clock signal, and then transmits the two reduced-frequency divided clock signals to a first receiver 308a and a second receiver 308b, both of which are on the other, second chip 304. 3 shows the other clock divider 326 serving two receivers, in other embodiments, the reduced frequency split signal may be generated by the clock divider to serve more than two receivers. In this embodiment, the other clock divider 326 may generate the reduced frequency clock signal as a CMOS or CML clock signal.

[0039] Thus, Figure 3 illustrates structural aspects of the interconnect architecture to achieve the additional power and space saving requirement that each receiver not require its own clock divider lane. Figure 3 also includes a particular advantage of the architecture depicted in Figure 1, that with the distribution of a lower frequency clock signal on the receiving chip, the power requirements for the receiving chip can be reduced.

[0040] For this interconnect architecture depicted in FIG. 3, each of the first and second receivers 308a and 308b includes its own deskew circuitry equivalent to the deskew circuitry 128 of FIG. 1. The first and second receivers 308a, 308b may receive data signals via first and second data lanes 316a, 316b, respectively. The data signals may be transmitted via first and second transmitters 306a, 306b, respectively, on another first chip 302. Another clock generator 320 may generate a first half-rate clock signal for another clock signal lane 324. The other clock generator 320 may pass the clock signal to another driver 322, which drives the clock-rate signal across the other clock signal lane 324.

[0041] For simplicity, the internal components of the first and second transmitters 306a, 306b and the first and second receivers 308a, 308b are not shown in FIG. 3 but may be equivalent to the internal components of the corresponding transmitters 106 and receivers 108, respectively, shown in FIG. 1 and described above.

[0042] FIG. 3 uses the symbol " / " in the connections / lines to indicate that differential signaling is implemented. With differential signaling, two complementary voltage signals may be generated and transmitted. Upon receiving them, the signals may be combined to create one information signal. In other embodiments, where a clock divider on a receiving chip serves multiple receivers on a receiver chip, lanes with enhanced interconnects may implement other signaling types instead of differential signaling. For example, in other embodiments, single-ended signaling may be performed with each of the lanes of the interconnect.

[0043] FIG. 4 is an operational flowchart illustrating a clock signal splitting process 400 that may be performed using the improved interconnect architecture depicted in FIG. 1 and / or FIG. 3, according to at least one embodiment.

[0044] In step 402 of the clock signal splitting process 400, data is transmitted from a first chip to a second chip via a data lane. Figure 1 illustrates an example in which data is transmitted from a transmitter 106 of a first chip 102 to a receiver 108 of a second chip 104 via a data lane 116. Figure 3 illustrates an example in which data is transmitted from another first chip 302 to another second chip 304 via multiple data lanes, i.e., a first other data lane 316a and a second other data lane 316b. Both the first chip and the second chip may be physically part of a single chip package.

[0045] In step 404 of the clock signal splitting process 400, the clock signal is transmitted from the first chip to the second chip via a clock signal lane. The clock signal lane may be physically separate from the data lanes or lanes involved in step 402. Figure 1 shows an example in which a clock generator 120 generates a clock signal that is transmitted from a first chip 102 to a second chip 104 via a clock signal lane 116. Figure 3 shows an example in which a separate clock signal lane 316 is used to transmit a clock signal from another first chip 302 to another second chip 304.

[0046] In step 406 of the clock signal splitting process 400, the clock signal is divided via a clock divider in the second chip. This clock signal refers to the clock signal transmitted in step 404. FIG. 1 shows an example of a clock divider 126 that divides and splits the clock signal into a first divided clock signal and a second divided clock signal. FIG. 3 shows an example of another clock divider 326 that divides and splits the clock signal into a first divided clock signal and a second divided clock signal. The divided clock signals may have a reduced frequency compared to the frequency of the original clock signal. The divided clock signals may include an in-phase clock signal and a quadrature clock signal, each running at half the frequency of the original clock signal. The quadrature clock signals may have a phase shifted by 90 degrees compared to the original clock signal. The clock divider may be disposed outside any receiver on the second chip.

[0047] In step 408 of the clock signal splitting process 400, the split / divided clock signal is sent to deskew circuits in one or more receivers on the second chip. The split / divided clock signal refers to the signal produced in step 406. FIG. 1 shows an example in which the divided clock signal from the clock divider 126 is input to the deskew circuit 128 in the receiver 108 on the second chip. In the embodiment shown in FIG. 3, the divided signal from the other clock divider 326 is input to a deskew circuit in the first other receiver 308a and to another deskew circuit in the second other receiver 308b. The deskew circuit may include one or more phase rotators, delay lines, and / or delay-locked loops to correct the phase of the divided signal.

[0048] In step 410 of the clock signal splitting process 400, the split clock signals are mixed to create a modified final clock signal. The deskew circuitry involved in step 408 may create these modified final clock signals from the divided clock signals. The modified final clock signal may have any phase with edges that are different from the phases of the individual divided clock signals. For example, if a 0-degree phase and a 90-degree phase are received for the split clock signals, the modified final clock signal may have a phase of 45 degrees or any combination of the divided clock signals. The deskew circuitry may send a separate clock signal to each sampling latch, for example, a total of four separate clock signals to a total of four sampling latches.

[0049] In step 412 of the clock signal splitting process 400, the mixed signal is fed to a sampling latch to sample the received data. The mixed signal refers to the modified final clock signal created in step 410. FIG. 1 shows an exemplary embodiment with four sampling latches, namely, a first sampling latch 6a, a second sampling latch 6b, a third sampling latch 6c, and a fourth sampling latch 6d, which are involved in step 412. FIG. 3 shows a first other receiver 308a and a second other receiver 308b. Each of these other receivers 308a, 308b includes a sampling latch that receives the mixed signal from a deskew circuit within the other receiver 308a, 308b, respectively.

[0050] In step 414 of the clock signal splitting process 400, received data is sampled according to the clock signal. Received data refers to the data transmitted in step 402. The data is received by the same receiver that maintains the deskew circuits involved in steps 408 and 410 and the sampling latches involved in step 412. Figure 1 shows that the data is sampled in multiple sampling latches and then fed to the deserializer 130. In the embodiment shown in Figure 3, data from the first other data lane 316a and the second other data lane 316b may be sampled according to the clock signal as part of step 414.

[0051] 1-4 provide merely illustrative examples of some embodiments and do not imply any limitations with respect to how different embodiments may be implemented. Many modifications to the depicted embodiments, such as the depicted structures, process flows, and / or sequence of steps, may be made based on design and implementation requirements.

[0052] 5 is a block diagram of the internal and external components of a computer system in which one or more of the chip packages described herein may be implemented. Computing environment 500 illustrates an example of one or more computers having processors in which the enhanced circuitry interconnect architecture described above may be implemented. Computing environment 500 includes, for example, computer 501, wide area network (WAN) 502, end user device (EUD) 503, remote server 504, public cloud 505, and private cloud 506. In this embodiment, computer 501 includes a set of processors 510 (including processing circuitry 520 and cache 521), a communications fabric 511, volatile memory 512, persistent storage 513 (including an operating system 522 and software programs 516), a set of peripheral devices 514 (including a set of user interface (UI) devices 523, storage 524, and a set of Internet of Things (IoT) sensors 525), and a network module 515. Remote server 504 includes a remote database 530. Public cloud 505 includes a gateway 540, a cloud orchestration module 541, a set of host physical machines 542, a set of virtual machines 543, and a set of containers 544. The processing circuitry 520 of computer 501 and the processing circuitry of remote server 504 may each include the hardened interconnect architecture described above.

[0053] Computer 501 may take the form of a desktop computer, laptop computer, tablet computer, smartphone, smartwatch or other wearable computer, mainframe computer, quantum computer, or any other form of computer or mobile device now known or later developed that is capable of executing programs, accessing a network, or querying a database such as remote database 530. As is well understood and in accordance with the art of computer technology, execution of a computer-implemented method may be distributed among multiple computers and / or among multiple locations. While in this presentation of computing environment 500, to keep the presentation as simple as possible, the detailed discussion focuses on a single computer, specifically computer 501. Computer 501 may be located in a cloud, although it is not shown in FIG. 1 . However, computer 501 need not be located in a cloud.

[0054] The processor set 510 includes one or more computer processors of any type now known or to be developed in the future. The processing circuitry 520 may be distributed across multiple packages, e.g., multiple tailored integrated circuit chips. The processing circuitry 520 may implement multiple processor threads and / or multiple processor cores. The cache 521 is memory located within the processor chip package and is typically used for data or code that should be available for fast access by threads or cores executing on the processor set 510. Cache memory is typically organized into multiple levels depending on relative proximity to the processing circuitry. Alternatively, some or all of the cache for a processor set may be located “off-chip.” In some computing environments, the processor set 510 may be designed for operation with qubits and for performing quantum computing.

[0055] Computer-readable program instructions are typically loaded onto computer 501 and cause processor set 510 of computer 501 to perform a series of operational steps. These computer-readable program instructions are stored in various types of computer-readable storage media, such as cache 521 and other storage media discussed below. The program instructions and associated data are accessed by processor set 510 to control and direct the execution of the methods of the invention.

[0056] Communications fabric 511 is the signal-conducting pathway that allows the several components of computer 501 to communicate with each other. Typically, this fabric is made up of switches and conductive pathways, such as those that make up buses, bridges, physical input / output ports, and the like. Other types of signal communication pathways, such as fiber optic and / or wireless communication pathways, may be used.

[0057] Volatile memory 512 may be any type of volatile memory, now known or later developed. Examples include dynamic random access memory (RAM) or static RAM. Typically, volatile memory 512 is characterized by random access, although this is not required unless affirmatively indicated. In computer 501, volatile memory 512 is located in a single package and is internal to computer 501, although alternatively or additionally, volatile memory may be distributed across multiple packages and / or located external to computer 501.

[0058] Persistent storage 513 is any form of non-volatile storage for a computer, now known or later developed. The non-volatility of this storage means that stored data remains regardless of whether power is supplied to computer 101 and / or to persistent storage 513 directly. Persistent storage 513 can be read-only memory (ROM), but is typically at least a portion of persistent storage that allows data to be written, data to be erased, and data to be rewritten. Some well-known forms of persistent storage include magnetic disks and solid-state storage devices. Operating system 522 can take multiple forms, such as various known proprietary operating systems or open-source Portable Operating System Interface-type operating systems that employ a kernel.

[0059] Peripheral device set 514 includes a set of peripheral devices of computer 501. Data communication connections between peripheral devices and other components of computer 501 may be implemented in various ways, such as Bluetooth connections, near field communication (NFC) connections, connections made by cable (such as a universal serial bus (USB)-type cable), insertable connections (e.g., a Secure Digital (SD) card), connections made by a local area communication network, and even connections made by a wide area network such as the Internet. In various embodiments, UI device set 523 may include components such as a display screen, speakers, microphones, wearable devices (such as goggles and smartwatches), keyboards, mice, printers, touchpads, game controllers, and haptic devices. Storage 524 may be external storage, such as an external hard drive, or insertable storage, such as an SD card. Storage 524 may be persistent and / or volatile. In some embodiments, storage 524 may take the form of a quantum computing storage device for storing data in the form of qubits. In embodiments where computer 501 is required to have a large amount of storage (e.g., computer 501 stores and manages a large database locally), this storage may be provided by a peripheral storage device designed to store very large amounts of data, such as a storage area network (SAN) shared by multiple geographically distributed computers. IoT sensor set 525 consists of sensors that can be used in Internet of Things applications. For example, one sensor may be a thermometer and another may be a motion detector. Various sensors and / or UI devices may each include separate packages with the enhanced interconnect architecture described herein.

[0060] Network module 515 is a collection of computer software, hardware, and firmware that enables computer 501 to communicate with other computers over WAN 502. Network module 515 may include hardware such as a modem or Wi-Fi® signal transceiver, software for packetizing and / or depacketizing data for communication network transmission, and / or web browser software for communicating data over the Internet. In some embodiments, the network control and network forwarding functions of network module 515 are performed on the same physical hardware device. In other embodiments (e.g., embodiments utilizing Software-Defined Networking (SDN)), the control and forwarding functions of network module 515 are performed on physically separate devices, such that the control function manages multiple different network hardware devices. Computer-readable program instructions for implementing the methods of the invention can be downloaded to computer 501 from an external computer or external storage device, typically via a network adapter card or network interface included in network module 515.

[0061] WAN 502 is any wide area network (e.g., the Internet) capable of communicating computer data over non-local distances by any now known or later developed technology for communicating computer data. In some embodiments, WAN 502 may be replaced and / or supplemented by a local area network (LAN) designed to communicate data between devices located in a local area, such as a Wi-Fi network. WANs and / or LANs typically include copper transmission cables, optical fiber transmissions, wireless transmissions, and computer hardware such as routers, firewalls, switches, gateway computers, and edge servers.

[0062] End-user device (EUD) 503 is any computer system used and controlled by an end user (e.g., a customer of the enterprise operating computer 501) and may take any of the forms discussed above in connection with computer 501. EUD 503 typically receives useful and actionable data from the operation of computer 501. For example, in a hypothetical case in which computer 501 is designed to provide recommendations to the end user, the recommendations would typically be communicated from computer 501's network module 515 over WAN 502 to EUD 503. In this manner, EUD 503 can display or otherwise present the recommendations to the end user. In some embodiments, EUD 503 may be a client device such as a thin client, a heavy client, a mainframe computer, a desktop computer, etc. Each EUD 503 may include a package with the enhanced interconnection architecture described herein.

[0063] Remote server 504 is any computer system that provides at least some data and / or functionality to computer 501. Remote server 504 may be controlled and used by the same entity that operates computer 501. Remote server 504 represents a machine that collects and stores useful and useful data for use by other computers, such as computer 501. For example, in the hypothetical case where computer 501 is designed and programmed to provide recommendations based on historical data, this historical data may be provided to computer 501 from a remote database 530 of remote server 504. Remote server 504 may include packages with the enhanced interconnection architecture described herein.

[0064] A public cloud 505 is any computer system available for use by multiple entities that provides on-demand availability of computer system resources and / or other computer functionality, particularly data storage (cloud storage) and computing power, without direct, active management by users. Cloud computing typically leverages resource sharing to achieve coherence and economies of scale. Direct, active management of the computing resources of the public cloud 505 is performed by computer hardware and / or software in a cloud orchestration module 541. The computing resources provided by the public cloud 505 are typically implemented by virtual computing environments running on various computers that make up a host physical machine set 542, which is the universe of physical computers within and / or available in the public cloud 505. Each of these physical computers may include a respective package with the enhanced interconnection architecture described herein.

[0065] A virtual computing environment (VCE) typically takes the form of a virtual machine from virtual machine set 543 and / or a container from container set 544. It should be understood that these VCEs may be stored as images and transferred among and between various physical machine hosts either as images or after instantiation of the VCE. Cloud orchestration module 541 manages the transfer and storage of images, deploys new instantiations of VCEs, and manages active instantiations of VCE deployments. Gateway 540 is a collection of computer software, hardware, and firmware that enables communication over WAN 502 to public cloud 505.

[0066] Some further description of virtualized computing environments (VCEs) is now provided. A VCE can be stored as an "image." A new, active instance of a VCE can be instantiated from an image. Two well-known types of VCEs are virtual machines and containers. A container is a VCE that uses operating system-level virtualization. This refers to a feature of an operating system in which the kernel allows the existence of multiple isolated user space instances, called containers. These isolated user space instances typically behave as actual computers from the perspective of programs running within them. A computer program running on a typical operating system can utilize all of the computer's resources, such as connected devices, files and folders, network shares, CPU power, and quantifiable hardware capabilities. However, a program running inside a container can only use the contents of the container and the devices assigned to the container, a feature known as containerization.

[0067] Private cloud 506 is similar to public cloud 505, except that the computing resources are available only for use by a single enterprise. While private cloud 506 is shown in communication with WAN 502, in other embodiments, the private cloud may be entirely disconnected from the Internet and accessible only through a local / private network. A hybrid cloud is a composite of multiple clouds of different types (e.g., private, community, or public cloud types), often each implemented by a different vendor. While each of the multiple clouds remains a separate, discrete entity, the larger hybrid cloud architecture is bound together by standardized or proprietary technologies that enable orchestration, management, and / or data / application portability between the constituent clouds. In this embodiment, both public cloud 505 and private cloud 506 are part of a larger hybrid cloud.

[0068] In computing environment 500, computer 501 is shown as connected to the Internet (see WAN 502). However, in many embodiments, computer 501 is isolated from communications over a communications network, is not connected to the Internet, and operates as a stand-alone computer. In these embodiments, network module 515 of computer 501 may not be necessary or even desirable to ensure isolation and prevent external communications from entering computer 501. Stand-alone computer embodiments are potentially advantageous because they are typically more secure in at least some applications of the present invention. In other embodiments, computer 501 is connected to a secure WAN or secure LAN instead of WAN 502 and / or the Internet. In these networked (i.e., non-stand-alone) embodiments, system designers may wish to take appropriate security measures, now known or developed in the future, to reduce the risk that incoming network communications will not cause a security breach.

[0069] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems and methods according to various embodiments of the present invention. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may actually be implemented as a single step, executed concurrently, substantially concurrently, partially, or fully in a time-overlapping manner, or the blocks may possibly be executed in the reverse order, depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a dedicated hardware-based system that performs the specified functions or acts or executes a combination of dedicated hardware and computer instructions.

[0070] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," "including," "has," "have," "having," "with," and similar terms, when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0071] The description of various embodiments of the present invention has been presented for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein have been selected to best explain the principles, practical applications, or technical improvements of the embodiments over techniques found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. a clock lane configured to transmit a clock signal at a first rate from the first chip to the second chip; a clock divider on the second chip, the clock divider configured to receive the clock signal transmitted via the clock lane and to create and transmit a first divided clock signal and a second divided clock signal from the received clock signal, the first divided clock signal and the second divided clock signal being transmitted at a reduced rate compared to the first rate, and the clock divider maintaining current mode logic characteristics with respect to the first and second divided clock signals; and a first deskew circuit configured to receive and process the first divided clock signal and the second divided clock signal to enable sampling of data transmitted from the first chip to the second chip; 1. An integrated circuit communication architecture comprising:

2. 2. The integrated circuit communication architecture of claim 1, wherein the first rate is half-rate compared to a data rate.

3. 2. The integrated circuit communication architecture of claim 1, wherein said first divided clock signal is an in-phase clock signal and runs at one-quarter the data rate.

4. 2. The integrated circuit communication architecture of claim 1, wherein the second divided clock signal is a quadrature clock signal and runs at one-quarter the data rate.

5. 10. The integrated circuit communication architecture of claim 1, wherein the clock divider comprises one or more current mode logic circuits for low clock jitter.

6. 2. The integrated circuit communication architecture of claim 1, wherein the first deskew circuit comprises one or more phase rotators for rotating the first divided clock signal and the second divided clock signal.

7. 2. The integrated circuit communication architecture of claim 1, wherein the reduced rate of the first divided clock signal is half the first rate.

8. 2. The integrated circuit communication architecture of claim 1, wherein the reduced rate of the second divided clock signal is half the first rate.

9. 2. The integrated circuit communication architecture of claim 1, further comprising a driver on said first chip for driving said clock signal across said clock lane.

10. The integrated circuit communication architecture of claim 1 further comprising a data lane configured to transmit data from the first chip to the second chip.

11. 2. The integrated circuit communication architecture of claim 1, wherein the first deskew circuit is disposed within a first receiver of the second chip, and the clock divider serves multiple receivers on the second chip.

12. 1. A method of integrated circuit communication, said method comprising: transmitting a clock signal from a first chip to a second chip via a clock lane at a first rate; dividing the transmitted clock signal via a clock divider in the second chip to form a first divided clock signal and a second divided clock signal having a reduced rate compared to the first rate; maintaining a current mode logic characteristic for the first and second divided clock signals via the clock divider; and inputting the first divided clock signal and the second divided clock signal into a deskew circuit of a receiver of the first chip; A method comprising:

13. The method of claim 12 , wherein the first rate is a half rate.

14. 13. The method of claim 12, wherein the first divided clock signal is an in-phase clock signal and runs at one-quarter the data rate.

15. 13. The method of claim 12, wherein the second divided clock signal is a quadrature clock signal and runs at one-quarter the data rate.

16. 13. The method of claim 12, wherein the clock divider comprises one or more current-mode logic circuits for low clock jitter.

17. 13. The method of claim 12, wherein the first deskew circuit comprises one or more phase rotators for rotating the first divided clock signal and the second divided clock signal.

18. a clock lane configured to transmit a clock signal at a first rate from the first chip to the second chip; a clock divider on the second chip, the clock divider configured to receive the clock signal transmitted via the clock lane and to create and transmit a first divided clock signal and a second divided clock signal from the received clock signal, the first divided clock signal and the second divided clock signal being transmitted at a reduced rate compared to the first rate; and a first and second receiver on the second chip; the clock divider is configured to provide each of the first and second divided clock signals to both the first and second receivers; Integrated Circuit Communication Architecture.

19. 20. The integrated circuit communication architecture of claim 18, wherein the first divided clock signal is an in-phase clock signal and runs at one-quarter the data rate.

20. 20. The integrated circuit communication architecture of claim 18, wherein the second divided clock signal is a quadrature clock signal and runs at one-quarter the data rate.

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