Fast memory clear of system memory

Abstract

Various embodiments are provided herein for compressing data in a latency-critical processor link of a computing system within a computing environment, wherein one or more cache lines may be dynamically compressed at a lowest level of a networking stack based on one or more of a plurality of parameters prior to transferring the single cache line, the networking stack including a framer and a data link layer.

Description

[Background technology]

[0001] The present invention relates generally to computing systems, and more particularly to various embodiments for compressing data in latency-critical processor links of a computing system within a computing environment using a computing processor. Summary of the Invention

[0002] According to one embodiment of the present invention, a method is presented for compressing data in a latency-critical processor link of a computing system within a computing environment using a computing processor, wherein one or more cache lines can be dynamically compressed at a lowest level of a networking stack based on one or more of a plurality of parameters prior to transferring the single cache line, the networking stack including a framer and a data link layer.

[0003] One embodiment includes a computer usable program product comprising a computer readable storage device and program instructions stored on the storage device.

[0004] One embodiment includes a computer system comprising a processor, a computer-readable memory, and a computer-readable storage device, and program instructions stored on the storage device for execution by the processor via the memory.

[0005] Thus, in addition to the exemplary method embodiments described above, other exemplary system and computer product embodiments are provided. [Brief explanation of the drawings]

[0006] [Figure 1]1 is a block diagram illustrating an exemplary cloud computing node, according to one embodiment of the present invention.

[0007] [Figure 2] 1 is a diagram of a cloud computing environment, according to one embodiment of the present invention.

[0008] [Figure 3] FIG. 2 is a diagram of abstraction model layers according to one embodiment of the present invention.

[0009] [Figure 4] 10 is an additional block diagram illustrating exemplary functional relationships between various aspects of the present invention.

[0010] [Figure 5] FIG. 1 is a block diagram illustrating operations for compressing data in a latency-critical processor link of a computing system within a computing environment, according to one embodiment of the present invention.

[0011] [Figure 6] FIG. 10 is an additional block diagram illustrating operations for compressing data in a latency-critical processor link of a computing system within a computing environment, according to one embodiment of the present invention.

[0012] [Figure 7] FIG. 10 is an additional block diagram illustrating operations for compressing data in a latency-critical processor link of a computing system within a computing environment, according to one embodiment of the present invention.

[0013] [Figure 8] FIG. 10 is an additional block diagram illustrating operations for compressing data in a latency-critical processor link of a computing system using compression in a framer and decompression in a parser within a computing environment in accordance with one embodiment of the present invention.

[0014] [Figure 9] FIG. 10 is a flowchart diagram illustrating an additional exemplary method for compressing data in a latency-critical processor link of a computing system within a computing environment, according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0015] In modern computer systems, multiprocessor systems include multi-core central processing units (CPUs) within a single module. Communication between processors in a multiprocessor system is typically via inter-processor buses (also referred to as processor links). Processors coupled via a processor link (i.e., a driver processor and a destination processor) are typically associated with I / O parameters that govern the analog characteristics of signals transmitted from the driver processor and corresponding signals received at the destination processor. Characterizing the processor link during the test / verification phase can help identify the best I / O parameters to reliably achieve the desired performance level.

[0016] Furthermore, a computer hardware cache is a temporary holding storage for fast access to frequently used memory data. Stated differently, to reduce or avoid the time delay (or "latency") in accessing data stored in a computer's main memory, modern computer processors include cache memory (or "cache") that stores recently accessed data so that it can be quickly accessed again by the processor. Data stored in the cache can be quickly accessed by the processor without having to access the main memory (or "memory"), thereby increasing the performance of the processor and the computer as a whole. Caches have shorter access times than computer system memory (e.g., often referred to as dynamic random-access memory (DRAM)). Caches are typically built using static random-access memory (SRAM), which is faster than DRAM. However, cache capacities are smaller than DRAM. Cache / memory access speed and capacity are inversely proportional.

[0017] Several different layers of cache may be provided within a computer system. Level 1 (or primary) cache, for example, is used to store data instead of system memory (which comprises random access memory, or RAM) for access by the processor. Level 1 ("L1") cache may be directly integrated into the processor, run at the same speed as the processor, and provide the fastest possible access times. Level 2 (or secondary) ("L2") cache is also used to store a portion of system memory and may be included within the chip package but separate from the processor. Level 2 cache has a larger capacity than the level 1 cache but is slower. Some systems may even include a level 3 ("L3") cache, which has an even larger capacity than the level 2 cache. However, while level 3 cache is typically slower than the level 2 cache, it is still faster than the primary storage device and may be located away from the chip package.

[0018] Data in a cache is stored in "lines", which are contiguous chunks of data (i.e., a power of two number of bytes long and aligned on a boundary corresponding to this size). That is, data is typically transferred and accessed in groupings known as cache lines, which can contain more than one item of data.

[0019] In a typical computing architecture, a processor core may be connected to a cache (e.g., an on-chip cache or "nest"), which is further connected to a processor link ("link"). The nest and link are designed to operate at much slower speeds than the processor core. The nest may be the computing infrastructure that handles the transfer of data between a core and other cores, main memory, and input / output ("I / O") devices. The nest is responsible for maintaining the degree of coherence of data lines throughout the system. It is not an industry standard term, so perhaps we should define it better before using it. Within a computing system, there are many data links, such as processor-to-IO links (PCIe, Ethernet), processor-to-memory links, and processor-to-processor links. The nest includes all the infrastructure that handles these links. Thus, a link may be the connection that facilitates data transfer to and from a processor. In other words, in a computer system configuration in which a cache is shared across different processors connected together with inter-processor links, coherent transfer of cache data lines between processors is possible.

[0020] A typical computing system has a handshake protocol for cache line transfers, and only a limited number of requests can be outstanding over a link. Requests for cache line transfers are satisfied but limited by the link speed. This results in computer system performance with reasonable power consumption, since not all processor core computations require nesting or link interaction. However, when a processor core requests a cache line over a processor link, a speed mismatch adversely affects computer system performance. For example, physical limitations constrain the link speed, which is a combination of the number of serial lanes per link and the speed of operation.

[0021] The present invention therefore provides for improving and optimizing the effective bandwidth and latency of such constrained processor links while reducing computing processor overhead, resulting in improved and increased computing efficiency.

[0022] In this manner, the present invention provides improved computing system performance by reducing the latency of single cache line transfers through lossless compression.

[0023] Accordingly, various embodiments are provided herein for compressing data in a latency-critical processor link of a computing system within a computing environment using a computing processor. One or more cache lines may be dynamically compressed at the lowest level of a networking stack, where the networking stack includes a framer and a data link layer, based on one or more of a plurality of parameters before transferring the single cache line. In some examples, a data packet prepared for transfer over a link may consist of header information, cache line data, and some control information. The cache line data may be compressed, while other parts of the data pack (e.g., header, control flags) are not compressed. Thus, in practice, more of the cache line data may fit into a single data packet when compressed. That is, the cache line may be dynamically compressed at the lowest level of the networking stack (framer / DLL) rather than at the application layer.

[0024] It should be noted that as used herein, a networking stack may consist of the following layers: 1) application layer (the application layer may be the core and any software that runs), 2) transport layer (the layer that handles data transfer coherency, creates packets from cache line data for transmission, and processes and delivers received packets to the application layer), 3) data link layer (the layer that is responsible for ensuring error-free and in-order delivery of data packets), and 4) physical layer (the actual electrical circuitry). Thus, the core may be the application layer, the nest may be the transport layer, and the link may be the link layer and the physical layer.

[0025] So, the compression at a lower level is that it is a purely hardware ("HW") driven mechanism without any intervention from the core or software application.

[0026] In one example, a framer may be defined as a component / module that frames data for transmission over a link by adding some additional information in a predefined organization, allowing the data to be processed at the receiving end. A DLL may be a data link layer.

[0027] In some examples, various embodiments provide for compressing data in the data link layer using framer feedforward. In some examples, various embodiments provide for compressing data in the framer using bus feedback. In some examples, various embodiments provide dynamic compression toggling based on cache line contention. For example, an attacker may attempt to create frequent transfers of cache lines between processors to gain information about their compressibility. If large transfers are observed in a particular address space, i.e., if there is high contention for some cache lines, it is safer to disable compression to prevent any information leakage.

[0028] In this manner, various embodiments provide pipelined compression at the data link layer, enabling compression in a computing system without any performance penalty. That is, the present invention provides low-latency compression over the data link without compromising security via a side channel, compared to always compressing only over the cache. By enabling dynamic compression operation over the data link, any real-time impact (good or bad) on compression performance can be evaluated, which in turn can enable corrective action / selection to adjust compression and reduce latency.

[0029] In some examples, various embodiments provide for compressing data at the data link level by using control signals at the link layer, i.e., data can be dynamically compressed by dynamically adapting to data link layer conditions, improving compression efficiency in terms of latency to equal or higher than the data link rate without compression.

[0030] In some examples, various embodiments provide for implementing compression at the link level to reduce link latency without increasing the complexity of the cache implementation and while keeping overall cache data access latency equal to or better than systems without compression. A cache line is considered the smallest entity to operate on and therefore can be implemented on top of linked data.

[0031] It should be noted that the calculation(s) may be performed using various mathematical operations or functions that may include one or more mathematical operations (e.g., addition, subtraction, division, multiplication, standard deviation, median, mean, percentages, statistical modeling using statistical distributions, analytically or computationally solving differential equations or partial differential equations by finding minimum, maximum, or similar thresholds for combined variables, etc.).

[0032] Generally, as used herein, "optimization" may refer to and / or be defined as "maximizing," "minimizing," "best," or achieving one or more particular targets, objectives, goals, or intentions. Optimization may also refer to maximizing benefits to a user (e.g., maximizing the benefits of a trained machine learning scheduling agent). Optimization may also refer to making the most effective or functional use of a situation, opportunity, or resource.

[0033] Furthermore, optimizing need not refer to the best solution or result, but may refer, for example, to a solution or result that is “good enough” for a particular application. In some implementations, the goal is to recommend the “best” combination of operations, schedules, compression / decompression operations, and / or framer / DLL manager options, but there may be a variety of factors that may result in a different recommendation of a combination of operations, schedules, compression / decompression operations, and / or framer / DLL manager options that produces a better result. As used herein, the term “optimization” may refer to such a result based on a minimum (or maximum, depending on the parameters considered in the optimization problem). In additional aspects, the terms “optimize” and / or “optimizing” may refer to operations performed to achieve improved results, such as reduced execution costs or increased resource utilization, regardless of whether an optimal result is actually achieved. Similarly, the term “optimize” may refer to a component for performing such an improvement operation, and the term “optimized” may be used to describe the result of such an improvement operation.

[0034] Although this disclosure includes detailed descriptions of cloud computing, it is understood that implementation of the teachings recited herein is not limited to a cloud computing environment. Rather, embodiments of the present invention can be implemented in conjunction with any other type of computing environment now known or later developed.

[0035] Cloud computing is a service delivery model for enabling convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) that can be rapidly provisioned and released with minimal management effort or interaction with a service provider. The cloud model may include at least five characteristics, at least three service models, and at least four deployment models.

[0036] The characteristics are as follows:

[0037] On-Demand Self-Service: Cloud consumers can unilaterally provision computing capacity, such as server time and network storage, automatically as needed without requiring human interaction with the service provider.

[0038] Broad Network Access: Capabilities are available over the network and accessed through standard mechanisms that facilitate use by heterogeneous thin or thick client platforms (e.g., cell phones, laptops, and PDAs).

[0039] Resource Pooling: Provider computing resources are pooled to serve multiple consumers using a multi-tenant model, with various physical and virtual resources dynamically allocated and reallocated according to demand. Consumers generally have no control or knowledge of the exact location of the resources provided, although there is some location independence in that they may be able to specify location at a higher level of abstraction (e.g., country, state, or data center).

[0040] Rapid Elasticity: Capacity is provisioned quickly and elastically, sometimes automatically, and can be quickly scaled out or quickly released and quickly scaled in. To the consumer, the capacity available for provisioning often appears unlimited, and any amount can be purchased at any time.

[0041] Metering Services: Cloud systems automatically control and optimize resource usage by leveraging metering capabilities appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts) at a certain level of abstraction. Resource usage may be monitored, controlled, and reported, providing transparency to both providers and consumers of utilized services.

[0042] The service model is as follows:

[0043] Software as a Service (SaaS): The consumer is offered the ability to use a provider's applications running on a cloud infrastructure. The applications are accessible from a variety of client devices through a thin-client interface such as a web browser (e.g., web-based email). The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, storage, or even individual application capabilities, with the possible exception of limited user-specific application configuration settings.

[0044] Platform as a Service (PaaS): The ability offered to consumers is to deploy applications they create or acquire, written using programming languages ​​and tools supported by the provider, onto a cloud infrastructure. The consumer does not manage or control the underlying cloud infrastructure, including networks, servers, operating systems, or storage, but does control the deployed applications and, in some cases, the configuration of the application hosting environment.

[0045] Infrastructure as a Service (IaaS): The ability provided to consumers is to provision processing, storage, network, and other basic computing resources onto which they can deploy and run any software, which may include operating systems and applications. The consumer does not manage or control the underlying cloud infrastructure, but rather controls the operating systems, storage, deployed applications, and possibly limited control over selected networking components (e.g., host firewalls).

[0046] The deployment model is as follows:

[0047] Private Cloud: Cloud infrastructure is operated exclusively for one organization. It may be managed by that organization or a third party and may reside on-premise or off-premise.

[0048] Community Cloud: Cloud infrastructure is shared by multiple organizations and supports a specific community with shared interests (e.g., roles, security requirements, policies, and compliance considerations). It may be managed by the organization or a third party and may reside on-premises or off-premises.

[0049] Public Cloud: Cloud infrastructure is made available to the general public or large industry organizations and is owned by organizations that sell cloud services.

[0050] Hybrid Cloud: This cloud infrastructure is a composite of two or more clouds (private, community, or public) that remain unique entities but are bound together by standardized or proprietary technologies that allow for data and application portability (e.g., cloud bursting for load balancing between clouds).

[0051] Cloud computing environments are service-oriented with an emphasis on statelessness, low coupling, modularity, and semantic interoperability. At the heart of cloud computing is an infrastructure consisting of a network of interconnected nodes.

[0052] 1, a schematic diagram of an example cloud computing node is shown. Cloud computing node 10 is merely one example of a suitable cloud computing node and is not intended to suggest any limitation as to the scope of use or functionality of the embodiments of the present invention described herein. Nevertheless, cloud computing node 10 is capable of implementing and / or performing any of the functions described above.

[0053] Within cloud computing node 10 resides computer system / server 12, which operates in conjunction with numerous other general-purpose or special-purpose computing system environments or configurations. Examples of well-known computing systems, environments, and / or configurations that may be suitable for use with computer system / server 12 include, but are not limited to, personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics devices, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of the above systems or devices, and the like.

[0054] The computer system / server 12 may be described in the general context of computer system-executable instructions, such as program modules, being executed by a computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, etc. that perform particular tasks or implement particular abstract data types. The computer system / server 12 may be practiced in a distributed cloud computing environment where tasks are performed by remote processing devices that are linked through a communications network. In a distributed cloud computing environment, program modules may be located in both local and remote computer system storage media, including memory storage devices.

[0055] 1, computer system / server 12 of cloud computing node 10 is shown in the form of a general-purpose computing device. Components of computer system / server 12 may include, but are not limited to, one or more processors or processing units 16, system memory 28, and a bus 18 that couples various system components including system memory 28 to processor 16.

[0056] Bus 18 represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures. By way of example and not limitation, such architectures include an Industry Standard Architecture (ISA) bus, a Micro Channel Architecture (MCA) bus, an Enhanced ISA (EISA) bus, a Video Electronics Standards Association (VESA) local bus, and a Peripheral Component Interconnect (PCI) bus.

[0057] Computer system / server 12 typically includes a variety of computer system-readable media. Such media may be any available media that can be accessed by computer system / server 12 and includes both volatile and nonvolatile media, removable and non-removable media.

[0058] The system memory 28 may include computer system-readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. The computer system / server 12 may further include other computer system storage media, removable / non-removable, volatile / non-volatile. By way of example only, a storage system 34 may be provided for reading from and writing to a non-removable, non-volatile magnetic medium (not shown, but typically referred to as a "hard drive"). Although not shown, a magnetic disk drive may be provided for reading from and writing to a removable, non-volatile magnetic disk (e.g., a "floppy disk"), and an optical disk drive may be provided for reading from or writing to a removable, non-volatile optical disk, such as a CD-ROM, DVD-ROM, or other optical media. In such cases, one or more data medium interfaces may each be connected to the bus 18. As further shown and described below, the system memory 28 may include at least one program product having a set of program modules (e.g., at least one of which) configured to perform the functions of embodiments of the present invention.

[0059] A program / utility 40 having a set of program modules 42 (at least one of which) may be stored in system memory 28, by way of example and not limitation, as well as an operating system, one or more application programs, other program modules, and program data. Each of the operating system, one or more application programs, other program modules, and program data, or any combination thereof, may comprise an implementation of a networking environment. The program modules 42 generally perform the functions and / or methodologies of embodiments of the present invention described herein.

[0060] The computer system / server 12 may also communicate with one or more external devices 14, such as a keyboard, pointing device, display 24, etc.; one or more devices that allow a user to interact with the computer system / server 12; and / or any device (e.g., a network card, modem, etc.) that allows the computer system / server 12 to communicate with one or more other computing devices. Such communication may occur via an input / output (I / O) interface 22. Additionally, the computer system / server 12 may communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), and / or a public network (e.g., the Internet), via a network adapter 20. As shown, the network adapter 20 communicates with other components of the computer system / server 12 via a bus 18. Although not shown, it should be understood that other hardware and / or software components may be used in conjunction with the computer system / server 12. Examples include, but are not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archive storage systems.

[0061] Referring now to FIG. 2 , an exemplary cloud computing environment 50 is shown. As shown, the cloud computing environment 50 includes one or more cloud computing nodes 10 with which local computing devices used by cloud consumers, such as a personal digital assistant (PDA) or cellular phone 54A, a desktop computer 54B, a laptop computer 54C, and / or an automotive computer system 54N, can communicate. The nodes 10 may communicate with each other. They may be physically or virtually grouped in one or more networks (not shown), such as the private cloud, community cloud, public cloud, or hybrid cloud described above, or a combination thereof. This enables the cloud computing environment 50 to provide infrastructure, platforms, and / or software as a service without the cloud consumer having to maintain resources on the local computing device. It should be understood that the types of computing devices 54A-N shown in FIG. 2 are intended to be exemplary only, and that computing node 10 and cloud computing environment 50 can communicate with any type of computerized device via any type of network and / or network-addressable connection (e.g., using a web browser).

[0062] Referring now to Figure 3, a set of functional abstraction layers provided by cloud computing environment 50 (Figure 2) is shown. It should be understood in advance that the components, layers, and functions shown in Figure 3 are intended to be illustrative only, and embodiments of the present invention are not limited thereto. As shown, the following layers and corresponding functions are provided:

[0063] The device layer 55 includes physical and / or virtual devices, embedded and / or standalone electronic devices, sensors, actuators, and other objects for performing various tasks in the cloud computing environment 50. Each of the devices in the device layer 55 incorporates networking functionality to the other functional abstraction layers so that information obtained from the devices can be provided to them and / or information from the other abstraction layers can be provided to the devices. In one embodiment, the various devices comprising the device layer 55 may incorporate a network of entities collectively known as the "Internet of Things" (IoT). Such a network of entities enables intercommunication, collection, and dissemination of data to accomplish a wide variety of purposes, as will be appreciated by those skilled in the art.

[0064] The device layer 55 as shown includes, as shown, sensors 52, actuators 53, a "learning" thermostat 56 with integrated processing, sensor, and networking electronics, a camera 57, a controllable household outlet / receptacle 58, and a controllable light switch 59. Other possible devices may include, but are not limited to, various additional sensor devices, networking devices, electronic devices (such as remote control devices), additional actuator devices, so-called "smart" appliances such as refrigerators or washer / dryers, and a wide range of other possible interconnected objects.

[0065] Hardware and software layer 60 comprises hardware and software components. Examples of hardware components include mainframe 61; RISC (reduced instruction set computer) architecture-based servers 62; servers 63; blade servers 64; storage devices 65; and networks and networking components 66. In some embodiments, software components include network application server software 67 and database software 68.

[0066] The virtualization layer 70 provides an abstraction layer over which the following examples of virtual entities can be provided: virtual servers 71; virtual storage 72; virtual networks, including virtual private networks 73; virtual applications and operating systems 74; and virtual clients 75.

[0067] In one example, management layer 80 may provide the functions described below. Resource provisioning 81 provides dynamic procurement of computing and other resources utilized to execute tasks within the cloud computing environment. Metering and pricing 82 provides cost tracking as resources are utilized within the cloud computing environment and charging or billing for the consumption of these resources. In one example, these resources may include application software licenses. Security provides identity verification of cloud consumers and tasks, as well as protection of data and other resources. User portal 83 provides access to the cloud computing environment to consumers and system administrators. Service level management 84 provides allocation and management of cloud computing resources so that required service levels are met. Service level agreement (SLA) planning and fulfillment 85 provides advance arrangements for and procurement of cloud computing resources for anticipated future requirements in accordance with SLAs.

[0068] The workload layer 90 provides examples of functionality for which a cloud computing environment may be utilized. Examples of workloads and functions that may be provided from this layer include: mapping and navigation 91; software development and lifecycle management 92; virtual classroom instruction provision 93; data analytics processing 94; transaction processing 95; and, in the context of the illustrated embodiment of the present invention, various workloads and functions for compressing data in latency-critical processor links of computing systems within a computing environment 96. Additionally, the workloads and functions for compressing data in latency-critical processor links of computing systems within a computing environment 96 may include operations such as interleaving, and user and device management functions, as further described. Those skilled in the art will appreciate that the workloads and functions for compressing data in latency-critical processor links of computing systems within a computing environment 96 may also function in conjunction with other portions of the various abstraction layers, such as hardware and software 60, virtualization 70, management 80, and other workloads 90 (e.g., data analytics processing 94) to achieve various objectives of the illustrated embodiment of the present invention.

[0069] As previously mentioned, the present invention provides a novel solution for improving and optimizing the effective bandwidth and latency of such constrained processor links while reducing computing processor overhead, resulting in improved and increased computing efficiency. Accordingly, various embodiments may be provided herein for compressing data in a latency-critical processor link of a computing system within a computing environment using a computing processor. One or more cache lines may be dynamically compressed at the lowest level of a networking stack, where the networking stack includes a framer and a data link layer, based on one or more of a plurality of parameters prior to transferring a single cache line. That is, the cache lines may be dynamically compressed at the lowest level of the networking stack (framer / DLL) rather than at the application layer.

[0070] In some examples, various embodiments are provided herein for dynamic compression of cache lines at the lowest level of the networking stack (framer / DLL) rather than the application layer, performed via pipelined compression as described herein. In some examples, data is fed from the framer to the DLL, and the feed data is used to determine the amount of compression to attempt. One or more queue levels within the framer may be monitored.

[0071] In some examples, various embodiments are provided herein for dynamic compression by dynamically toggling dynamic compression on or off, as described herein, which may be based on rate matching. Various embodiments use rate matching to provide compression operations designed with awareness of clocking differences between links and nests. In some examples, various embodiments are provided herein for dynamic compression by dynamically controlling compression on hot cache lines (e.g., cache lines that are frequently transferred, e.g., transferred more than other cache lines, transferred above a predefined threshold, transferred at or above a specified percentage, and / or transferred n times within a specified period, where n is a positive integer), as described herein, to prevent timing side channel attacks. That is, attacks that can exploit the time spent performing a particular operation to gain additional information about the operation itself. Thus, if a certain amount of data is observed to be transferred quickly between processors, it indicates that the data has low entropy, and an attacker can attempt to gain further information based on this low entropy.

[0072] Referring now to Figure 4, a block diagram illustrating example functional components of a cache system 400 for use in compressing data in a latency-critical processor link of a computing system within a computing environment, in accordance with various mechanisms of the illustrated embodiment, is shown. In one aspect, one or more of the components, modules, services, applications, and / or functions described in Figures 1-3 may be used in Figure 4. As will be appreciated, many of the functional blocks may also be considered functional "modules" or "components" in the same descriptive sense as previously described in Figures 1-3.

[0073] The system 400 includes a memory 410 , a cache 420 (eg, a cache data array), and a cache directory 430 , all of which may be in communication with a processor 450 .

[0074] Data in cache 420 is stored in "lines," such as memory lines 422, which are contiguous chunks of data (i.e., a power-of-two number of bytes long and aligned on a boundary corresponding to this size). Cache lines 422 of memory data are typically 64 to 256 bytes long and stored in data array locations, with their respective memory addresses stored in a directory as shown in FIG. 4. Processor 450 provides memory addresses to the cache, such as cache data array 420. If the address is found in cache directory 430, processor 450 can access the respective line of data in cache 420. If the address is not found in cache directory 430, processor 450 can access the respective line of data in memory 410.

[0075] Referring now to Figure 5, a block diagram illustrating example functional components of a system 500 for compressing data in a latency-critical processor link of a computing system within a computing environment, according to various mechanisms of the illustrated embodiment, is shown. In one aspect, one or more of the components, modules, services, applications, and / or functions described in Figures 1-4 may be used in Figure 5. As will be appreciated, many of the functional blocks may also be considered functional "modules" or "components" in the same descriptive sense as previously described in Figures 1-4.

[0076] According to various aspects of the present invention, a data compression service 510 is shown incorporating a processing unit 520 ("processor") to perform various calculations, data processing, and other functions. In one aspect, the processor 520 and memory 530 may be internal and / or external to the interleaving service 510 and internal and / or external to the computing system / server 12. The interleaving service 510 may be included in and / or external to the computer system / server 12, as described in FIG. 1 . The processing unit 520 may be in communication with the memory 530. The data compression service 510 may include a compression component 540, a framer / data link layer ("DLL") component 550, a determination component 560, and a decompression component 570.

[0077] In one aspect, system 400 may provide virtualized computing services (i.e., virtualized computing, virtualized storage, virtualized networking, etc.). More specifically, system 500 may provide virtualized computing, virtualized storage, virtualized networking, and other virtualized services running on a hardware board.

[0078] The data compression service 510 may use a compression component 540, a framer / DLL component 550, a determination component 560, and a decompression component 570 to determine to compress one or more cache lines based on one or more of a plurality of parameters, where the plurality of parameters include the number of pending data packets, quality of service (QoS), and a current packet type, where the current packet type is either a data packet or a control packet.

[0079] The data compression service 510 may use a compression component 540, a framer / DLL component 550, a determination component 560, and a decompression component 570 to dynamically compress one or more cache lines at the lowest level of the networking stack, where the networking stack includes the framer and data link layers, based on one or more of a plurality of parameters before transferring the single cache line.

[0080] The data compression service 510 may use a compression component 540, a framer / DLL component 550, a determination component 560, and a decompression component 570 to enable compression of one or more cache lines based on data in the queue above a specified threshold, or to disable compression of one or more cache lines based on data in the queue below a specified threshold.

[0081] The data compression service 510 may use a compression component 540, a framer / DLL component 550, a determination component 560, and a decompression component 570 to feed data from the framer to the data link layer and determine the amount of data to compress based on one or more of several parameters.

[0082] The data compression service 510 may use a compression component 540, a framer / DLL component 550, a determination component 560, and a decompression component 570 to dynamically toggle the compression of one or more cache lines using a Bloom filter on a set of previously forwarded cache line addresses.

[0083] The data compression service 510 may use a compression component 540, a framer / DLL component 550, a determination component 560, and a decompression component 570 to dynamically compress one or more cache lines to match the data input rate.

[0084] The data compression service 510 may use a compression component 540, a framer / DLL component 550, a determination component 560, and a decompression component 570 to dynamically control the compression of one or more cache lines based on the number of hot cache lines.

[0085] For further explanation, FIG. 6 is a block diagram illustrating operations for compressing data in a latency-critical processor link of a computing system within a computing environment, according to one embodiment of the present invention. In one aspect, one or more of the components, modules, services, applications, and / or functions described in FIGS. 1-5 may be used in FIG. 6. As shown, various blocks of functionality are depicted with arrows indicating the relationship of the blocks of system 600 to one another to illustrate process flow (e.g., steps or operations). Additionally, descriptive information is also referenced with respect to each of the functional blocks of system 600. As will be appreciated, many of the functional blocks may also be considered functional "modules," in the same descriptive sense as previously described in FIGS. 1-5. Repeated descriptions of similar elements employed in other embodiments described herein are omitted for the sake of brevity.

[0086] With the foregoing in mind, the modular blocks of system 600 may be incorporated into various hardware and software components of a computing system, or even within a cloud computing environment in accordance with the present invention. Many of the functional blocks of system 600 may run as background processes on various components, either within a distributed computing component or elsewhere.

[0087] As shown, in the first example of system 600, a framer 610A at the data link layer is shown for receiving data packets (e.g., receiving data from a processor core, not shown for ease of illustration). A queue 612A may reside within framer 610A, where queue 612A may be monitored. A decision operation may be performed within queue 612A to determine whether the data (e.g., the number of data packets in queue 612A) is below a threshold for disabling compression. If so, a decision to disable compression is made, and compressor 614A bypasses compression of data 610A in the queue and forwards data 616A to parser 618A, which receives uncompressed data, e.g., 620A and 622A. In one example, the threshold may be dynamically set as the average compressibility of previous packets multiplied by the number of clocks it took to compress a single packet.

[0088] In a second example of system 600, a framer 610B at the data link layer is shown for receiving data packets (e.g., receiving data from a processor core, not shown for ease of illustration). A queue 612B may reside within framer 610B, where queue 612B may be monitored. A decision operation may be performed within queue 612B to determine whether the data (e.g., the number of data packets in queue 612B) exceeds a threshold for enabling compression. If so, a decision to enable compression may be made, and the data may be sent to compressor 614B, where the cache line may be dynamically compressed. Compressed cache line 616B may be forwarded to parser 618B for decompressing one or more cache lines, such as 620B and 622B.

[0089] In this way, embodiments enable scaling of computing system performance by dynamically determining how much (if at all) the next data should be compressed, using the same link bandwidth but still transferring more data without compromising on latency. While this variation may add certain side channels, one or more safeguards may be provided against side channel attacks.

[0090] Figure 7 is an additional block diagram illustrating operations for compressing data in a latency-critical processor link of a computing system within a computing environment, according to one embodiment of the present invention. In one aspect, one or more of the components, modules, services, applications, and / or functions described in Figures 1-6 may be used in Figure 7. Repetitive descriptions of similar elements employed in other embodiments described herein are omitted for the sake of brevity.

[0091] A network stack 700 is shown, including a framer 710, a compressor 720, and a data link layer (e.g., also referred to as a data link adaptor ("DLA") 730 or DLL), which may be associated with a processor core. Note that "DLA" may be used interchangeably with "DLL." DLA 730A may be in communication with additional DLAs, such as DLA 730B, which is associated with decompressor 740 and parser 750. In some implementations, framer 710 and DLA 730A may be in communication with one or more compression ("CMP") controls.

[0092] In operation, framer 710 may receive incoming data (e.g., from a processor core), i.e., an incoming packet, which may be 30 bytes and may include a packet identifier (“ID”) that may indicate the packet type.

[0093] The framer 710 may indicate various parameters to the DLL (e.g., DLA 730A) regarding compressing or not compressing data. In one example, the framer 710 indicates at least three parameters to the DLA 730A: 1) the number of pending data packets (e.g., pending data), 2) the quality of service ("QoS"), and 3) the current packet type, where the current packet type is either a data packet or a control packet. In some examples, a stall signal from the link layer to the framer may be used to allow the DLL to control the flow rate of data. In one example, the link may not be ready to accept new packets due to certain error conditions within the link, causing the DLL to stall the framer. In some implementations, a modified version of the stall signal may be used to indicate that the compression engine is busy processing a packet and that new packets should not be driven in. The modified stall signal is thus the original DLL stall, along with any reason the compression engine may have.

[0094] Based on these parameters, the compressor 720 may perform at least two stages: 1) a compression stage, or 2) a decompression stage. That is, in the decompression stage, the compressor does not attempt compression on the current packet type, which is designated as a control packet. That is, cache lines, which are designated as control, are not compressed. Rather, the compressor 720 passes the data (e.g., cache lines) to the DLA 730A based on the assumption that control packets are difficult to compress.

[0095] Alternatively, in the compression stage, the compressor 720 attempts to compress data depending on the amount of data pending (e.g., pending data in a queue in the framer 710). For example, if the amount of pending data is greater than a threshold, the compressor 720 will attempt to compress more cache lines. Alternatively, if the amount of pending data is less than a threshold, the compressor 720 will compress and zero-pad to the packet size. For example, consider a situation where there are three packets P0, P1, and P2. Ideally, if all three packets can be compressed together, only one packet would then be forwarded out. After compressing P0 and P1, it can be observed that P2 cannot be compressed into the same packet and that it overflows. At this point, a compressed form of P0 and P1 (e.g., P0 + P1) can be transmitted and forwarded out, with zeros appended to reach a fixed packet size. Then, P2 can be transmitted and forwarded out separately.

[0096] The compressor 720 also takes into account the quality of service ("QoS") required for compression. QoS is a measure of how much additional latency can be added to that particular data packet (e.g., a cache line) without adversely affecting the system. A higher latency indicates that the compressor 720 will attempt to pack more data into the packet (e.g., pack more cache lines); otherwise, the compressor 720 will compress, zero-pad to the packet size, and flush sooner.

[0097] For example, as described in the P0, P1, P2 scenario above, another option for the compression engine is to combine P0, P1, and P2 together to attempt improved compression rather than processing them separately. Compressing packets individually is ideal with respect to latency since there is no need to buffer multiple packets. However, combining packets together can increase efficiency and result in better compression at the expense of latency. QoS factors indicate whether the data can afford to be delayed even slightly in order to identify a more efficient compression format. If latency is critical, a decision can be made to simply send the packets out without processing.

[0098] For example, as an example of the operation of FIG. 7 , the transmitting core (e.g., Tx side) bus may be released faster than the normal number of processor clock signals (“pclk”) early, such as by 28 pclk. Similarly, the operation of FIG. 7 can complete a cache line transfer (256 bytes) n pclks early / faster (e.g., complete a cache line transfer 24 pclks early). Similarly, bandwidth may be increased on average, such as by 20% bandwidth increase. On average, each oct-word (“OW”) (32 bytes) arrives several pclks early, such as each OW arriving 10 pclks early. In one aspect, the first OW is delayed by 2 pclk, while all others arrive several pclks early.

[0099] 8 is an additional block diagram illustrating operations for compressing data in a latency-critical processor link of a computing system using compression in the framer with bus feedback (e.g., compression in the framer and decompression in the parser) within a computing environment, according to one embodiment of the present invention. In one aspect, one or more of the components, modules, services, applications, and / or functions described in FIGS. 1-7 may be used in FIG. 8. Repeated descriptions of similar elements employed in other embodiments described herein are omitted for brevity.

[0100] As shown, a compressor 810 in the framer may receive an input flow of data having tag (n+1) and data (n). The compressor may tag buffers and an 8-deep data buffer. The nest clock is equal to the processor core clock divided by 2 for the input flow rate (e.g., nest clock = processor core clock / 2 input flow rate), and the link clock is equal to the processor core clock divided by 3 for the output flow rate (e.g., link clock = processor core clock / 3 output flow rate). That is, the cache (e.g., nest) is running at one-half the speed of the processor core, and the link is running at one-third the speed of the processor core.

[0101] Note that the threshold calculation can be similar to the previous case, and the maximum compression attempted (eg, 2x, 4x, 8x) can be determined as the fill level divided by the output flow rate.

[0102] So, given a packet that can be received with 37 bytes, only twenty (20) bytes can be flushed. That is, the DLL framer fill rate is equal to 37 bytes ("B") per nest clock (37B / nest clock). The DLL framer flush rate is equal to 20 bytes per nest clock (e.g., 20B / nest clock).

[0103] The framer compressor (e.g., DLL compression) attempts compression based on rate matching. That is, in some examples, the framer compressor 810 attempts dynamic compression of cache lines at a compression rate (e.g., eight times "8x") if the fill level is equal to or greater than 180 bytes. In some examples, the framer compressor 810 attempts dynamic compression of cache lines at a compression rate (e.g., four times "4x") if the fill level is equal to or greater than 100 bytes. In some examples, the framer compressor 810 attempts dynamic compression of cache lines at a compression rate (e.g., two times "2x") if the fill level is equal to or greater than 60 bytes.

[0104] In some instances, the framer's compressor 810 does not compress the data and allows the data to pass through. In this manner, various embodiments provide dynamic compression without increasing latency for cache line transmissions.

[0105] The framer 810 may send compressed or uncompressed data to the parser 820, which may decompress the data.

[0106] For further example, various embodiments provide dynamic compression, where transmit ("Tx") is released 9 pclk sooner per cache line. Receive ("Rx") completes cache line transfer 4 pclk sooner (plus the nominal latency for one cache line assuming everything else is idle). Also, transmits of OWs 0-2 incur no additional latency relative to parser 820 output. The third OW may be delayed by only 2 pclk. Transmits of OWs 4-7 may arrive 1, 2, 3, and 4 pclk earlier, respectively. Thus, on average over isolated cache lines, each OW arrives 1 pclk earlier. On average over multiple transactions, each OW arrives at least 7 pclk earlier.

[0107] Furthermore, due to cache line compression, an attacker can launch an attack that constantly flushes and reloads sensitive lines. Based on the time taken for flushing and reloading, the attacker can determine the compressibility of the line, which leaks entropy. To overcome this vulnerability, the present invention can implement a Bloom filter on a set of previously forwarded cache line addresses. If the same cache line moves back and forth too many times (a programmable limit), compression can be turned off (e.g., dynamic compression is toggled off). Dynamic compression can be turned back on if the computing system does not have hot cache lines that are being flushed / reloaded too many times. Compression can also be turned back on (e.g., dynamic compression is toggled on) after a specified period of time.

[0108] 9, a method 900 for compressing data in a latency-critical processor link of a computing system within a computing environment using a processor is illustrated, in which various aspects of the illustrated embodiments may be implemented. The function 900 may be implemented as a method (e.g., a computer-implemented method) executed as instructions on a machine, where the instructions are contained on at least one computer-readable medium or one non-transitory machine-readable storage medium. The function 900 may begin at block 902.

[0109] As in block 904, one or more cache lines may be dynamically compressed at a lowest level of a networking stack, where the networking stack includes a framer and a data link layer, based on one or more of a plurality of parameters before transferring the single cache line. As in block 906, function 900 may end.

[0110] 9, the operations of method 900 may include each of the following: enabling compression of one or more cache lines based on data in the queue above a specified threshold; or disabling compression of one or more cache lines based on data in the queue below a specified threshold.

[0111] The operations of method 900 may determine to compress one or more cache lines based on one or more of a plurality of parameters, where the plurality of parameters include a number of pending data packets, a quality of service (“QoS”), and a current packet type, where the current packet type is either a data packet or a control packet.

[0112] The operations of method 900 may feed data from a framer to a data link layer and determine an amount of data to compress based on one or more of a plurality of parameters. The operations of method 900 may dynamically toggle compression of one or more cache lines using a Bloom filter on a set of previously forwarded cache line addresses. The operations of method 900 may dynamically compress one or more cache lines to match a data input rate. The operations of method 900 may dynamically control compression of one or more cache lines based on the number of hot cache lines.

[0113] The present invention may be a system, a method, and / or a computer program product, which may include a computer-readable storage medium (or media) having computer-readable program instructions for causing a processor to perform aspects of the present invention.

[0114] A computer-readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. The computer-readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or ridge structures in grooves in which instructions are recorded, and any suitable combination of the foregoing. Computer-readable storage medium, as used herein, should not be construed as a transitory signal per se, such as an electric wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse passing through a fiber optic cable), or an electrical signal transmitted over an electrical wire.

[0115] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may comprise copper transmission cables, optical transmission fiber, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and transfers the computer-readable program instructions to a computer-readable storage medium in the respective computing / processing device for storage.

[0116] The computer-readable program instructions for carrying out the operations of the present invention may be either source code or object code written in any combination of one or more programming languages, including assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or conventional procedural programming languages ​​such as Smalltalk®, C++, or similar object-oriented programming languages, and the “C” programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be to an external computer (e.g., through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, a field programmable gate array (FPGA), or a programmable logic array (PLA) may execute computer readable program instructions to personalize the electronic circuitry by utilizing state information of the computer readable program instructions to perform aspects of the present invention.

[0117] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0118] These computer-readable program instructions may be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, executed by the processor of the computer or other programmable data processing apparatus, create means for implementing the function(s) / act(s) specified in the block(s) of the flowcharts and / or block diagrams. These computer-readable program instructions may also be stored on a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and / or other device to function in a particular manner, such that the computer-readable storage medium having instructions stored therein comprises an article of manufacture containing instructions that implement aspects of the function(s) / act(s) specified in the block(s) of the flowcharts and / or block diagrams.

[0119] The computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be executed on the computer, other programmable apparatus, or other device to generate a computer-implemented process, such that the instructions executing on the computer, other programmable apparatus, or other device implement the function / act specified in a block or blocks of the flowcharts and / or block diagrams.

[0120] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions described in the blocks may occur in a different order than that described in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a dedicated hardware-based system that performs the specified functions or operations, or a combination of dedicated hardware and computer instructions.

[0121] While the descriptions of various embodiments of the present invention have been presented for illustrative purposes, they are not intended to be exhaustive or limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein have been selected to best explain the principles, practical applications, or technical improvements of the embodiments over technologies found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for compressing data in a latency-critical processor link of a computing system in a computing environment by one or more processors, comprising: dynamically compressing one or more cache lines at a lowest level of a networking stack based on one or more of a plurality of parameters before transferring the single cache line, wherein the networking stack includes a framer and a data link layer.

2. enabling compression of the one or more cache lines based on data in the queue exceeding a defined threshold; or Disabling compression of the one or more cache lines based on data in the queue falling below a defined threshold. The method of claim 1 further comprising:

3. 2. The method of claim 1, further comprising: determining to compress the one or more cache lines based on the one or more of the plurality of parameters, wherein the plurality of parameters include a number of pending data packets, a quality of service ("QoS"), and a current packet type, wherein the current packet type is either a data packet or a control packet.

4. 4. The method of claim 3, further comprising feeding data from said framer to said data link layer to determine an amount of data to compress based on said one or more of said plurality of parameters.

5. 2. The method of claim 1, further comprising dynamically toggling the compression of the one or more cache lines using a Bloom filter on a set of previously forwarded cache line addresses.

6. 2. The method of claim 1, further comprising dynamically compressing the one or more cache lines to match a data input rate.

7. 10. The method of claim 1, further comprising dynamically controlling the compaction of the one or more cache lines based on a number of hot cache lines.

8. 1. A system for compressing data in a latency-critical processor link of a computing system in a computing environment, comprising: When executed, the system: before transferring the single cache line, dynamically compressing one or more cache lines at a lowest level of a networking stack based on one or more of a plurality of parameters, wherein the networking stack includes a framer and a data link layer; One or more computers with executable instructions A system comprising:

9. The executable instructions, when executed, cause the system to: enabling compression of the one or more cache lines based on data in the queue exceeding a defined threshold; or Disabling compression of the one or more cache lines based on data in the queue falling below a defined threshold. The system of claim 8.

10. 9. The system of claim 8, wherein the executable instructions, when executed, cause the system to determine to compress the one or more cache lines based on the one or more of the plurality of parameters, wherein the plurality of parameters include a number of pending data packets, a quality of service ("QoS"), and a current packet type, wherein the current packet type is either a data packet or a control packet.

11. 11. The system of claim 10, wherein the executable instructions, when executed, cause the system to feed data from the framer to the data link layer and determine an amount of data to compress based on the one or more of the plurality of parameters.

12. 10. The system of claim 8, wherein the executable instructions, when executed, cause the system to dynamically toggle the compression of the one or more cache lines using a Bloom filter on a set of previously forwarded cache line addresses.

13. 9. The system of claim 8, wherein the executable instructions, when executed, cause the system to dynamically compress the one or more cache lines to match a data input rate.

14. 9. The system of claim 8, wherein the executable instructions, when executed, cause the system to dynamically control the compaction of the one or more cache lines based on a number of hot cache lines.

15. 1. A computer program product for compressing data in a latency-critical processor link of a computing system in a computing environment, the computer program product comprising: One or more computer-readable storage media and program instructions collectively stored on the one or more computer-readable storage media, the program instructions comprising: and program instructions for dynamically compressing one or more cache lines at a lowest level of a networking stack based on one or more of a plurality of parameters before transferring the single cache line, wherein the networking stack includes a framer and a data link layer. Computer program products.

16. enabling compression of the one or more cache lines based on data in the queue exceeding a defined threshold; or Disabling compression of the one or more cache lines based on data in the queue falling below a defined threshold.

16. The computer program product of claim 15, further comprising program instructions.

17. compressing the one or more cache lines based on the one or more of the plurality of parameters, wherein the plurality of parameters include a number of pending data packets, a quality of service ("QoS"), and a current packet type, wherein the current packet type is either a data packet or a control packet; and feeding data from said framer to said data link layer to determine an amount of data to compress based on said one or more of said plurality of parameters; 16. The computer program product of claim 15, further comprising program instructions for determining:

18. 16. The computer program product of claim 15, further comprising program instructions for dynamically toggling the compression of the one or more cache lines using a Bloom filter on a set of previously forwarded cache line addresses.

19. 16. The computer program product of claim 15, further comprising program instructions for dynamically compressing the one or more cache lines to match a data input rate.

20. 16. The computer program product of claim 15, further comprising program instructions for dynamically controlling the compaction of the one or more cache lines based on a number of hot cache lines.

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