Vertical transistor cell structure utilizing top-side and back-side resources

Abstract

Various structures are disclosed that implement topside metal routing and backside metal routing in combination with vertical transistors. The various structures include cells that form inverter, NAND, and MUX (multiplexer) devices. The disclosed cells include two or four vertical transistors with various connections made to the transistors, including either connected gate logic for inverter and NAND devices, or disconnected gate logic for MUX devices.

Description

[Technical Field]

[0001] FIELD OF THE INVENTION The embodiments described herein relate to power and signal routing for semiconductor devices. More particularly, the embodiments described herein relate to power and signal routing for vertical transistors. [Background technology]

[0002] A standard cell is a group of transistors, passive structures, and interconnect structures that can provide logic functions, memory functions, etc. The current trend in standard cell methodology is to reduce the size of the standard cell while increasing the complexity within the standard cell (e.g., circuit density and number of components or transistors). However, as standard cell designs become smaller, it becomes more difficult to provide access (e.g., connections) to the components within the standard cell within the design / manufacturing constraints of the standard cell.

[0003] The features and advantages of the method and apparatus of the embodiments described in this disclosure will be more fully understood by reference to the following detailed description of presently preferred, but nevertheless exemplary, embodiments in accordance with the embodiments described in this disclosure, taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0004] [Figure 1] 1 illustrates a perspective view of a contemplated vertical transistor device according to some embodiments.

[0005] [Figure 2] 1 illustrates a perspective view of another contemplated vertical transistor device, according to some embodiments.

[0006] [Figure 3] 1 illustrates a perspective view of an inverter cell structure according to some embodiments.

[0007] [Figure 4]1 illustrates a top plan view of an inverter cell structure according to some embodiments.

[0008] [Figure 5] 1 illustrates a backside plan view of an inverter cell structure according to some embodiments.

[0009] [Figure 6] 6 illustrates a cross-sectional view of an inverter cell structure taken along line 6-6 shown in FIG. 4, according to some embodiments.

[0010] [Figure 7] 7 illustrates a cross-sectional view of an inverter cell structure taken along line 7-7 shown in FIG. 4, according to some embodiments.

[0011] [Figure 8] 1 illustrates a perspective view of a NAND cell structure, according to some embodiments.

[0012] [Figure 9] 1 illustrates a top plan view of a NAND cell structure, according to some embodiments.

[0013] [Figure 10] 1 illustrates a backside plan view of a NAND cell structure, according to some embodiments.

[0014] [Figure 11] 11 illustrates a cross-sectional view of a NAND cell structure taken along line 11-11 shown in FIG. 9, according to some embodiments.

[0015] [Figure 12] 12 illustrates a cross-sectional view of a NAND cell structure taken along line 12-12 shown in FIG. 9, according to some embodiments.

[0016] [Figure 13] 1 illustrates a perspective view of a MUX cell structure, according to some embodiments.

[0017] [Figure 14] 1 illustrates a top plan view of a MUX cell structure according to some embodiments.

[0018] [Figure 15] 1 illustrates a backside plan view of a MUX cell structure according to some embodiments.

[0019] [Figure 16] 16 illustrates a cross-sectional view of a MUX cell structure taken along line 16-16 shown in FIG. 14, according to some embodiments.

[0020] [Figure 17] 17 illustrates a cross-sectional view of a MUX cell structure taken along line 17-17 shown in FIG. 14, according to some embodiments.

[0021] [Figure 18] 1 shows a perspective view of a device according to some embodiments.

[0022] [Figure 19] 52 illustrates a cross-sectional view of a device taken along line 19-19 shown in FIG. 51, according to some embodiments.

[0023] [Figure 20] 1 illustrates a perspective view of an inverter cell structure according to some embodiments.

[0024] [Figure 21] 1 illustrates a top plan view of an inverter cell structure according to some embodiments.

[0025] [Figure 22] 1 illustrates a backside plan view of an inverter cell structure according to some embodiments.

[0026] [Figure 23] 1 illustrates a cross-sectional view of an inverter cell structure according to some embodiments.

[0027] [Figure 24]1 illustrates a cross-sectional view of an inverter cell structure according to some embodiments.

[0028] [Figure 25] 1 illustrates a perspective view of a NAND cell structure, according to some embodiments.

[0029] [Figure 26] 1 illustrates a top plan view of a NAND cell structure, according to some embodiments.

[0030] [Figure 27] 1 illustrates a backside plan view of a NAND cell structure, according to some embodiments.

[0031] [Figure 28] 1 illustrates a cross-sectional view of a NAND cell structure, according to some embodiments.

[0032] [Figure 29] 1 illustrates a cross-sectional view of a NAND cell structure, according to some embodiments.

[0033] [Figure 30] 1 illustrates a perspective view of a MUX cell structure, according to some embodiments.

[0034] [Figure 31] 1 illustrates a top plan view of a MUX cell structure according to some embodiments.

[0035] [Figure 32] 1 illustrates a backside plan view of a MUX cell structure according to some embodiments.

[0036] [Figure 33] 1 illustrates a cross-sectional view of a MUX cell structure according to some embodiments.

[0037] [Figure 34] FIG. 1 is a block diagram of one embodiment of an exemplary system.

[0038] While the embodiments disclosed herein are susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the drawings and detailed description are not intended to limit the scope of the claims to the particular forms disclosed. On the contrary, the present application is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure, as defined by the appended claims. DETAILED DESCRIPTION OF THE INVENTION

[0039] The present disclosure is directed to implementations of vertical transistors within integrated circuit cells (e.g., standard cells) that utilize connections to both top and bottom metal layers. The top and bottom metal layers may provide routing (e.g., paths) for control and / or power signals. The disclosed embodiments provide connections for vertical transistors within integrated circuit cells to either control signal routing or power signal routing in either the top or bottom metal layers. As used herein, the term “standard cell” refers to a group of transistor structures, passive structures, and interconnect structures formed on a substrate to provide logic or memory functions that are standard for various implementations. For example, an individual standard cell may be one cell in a library of cells from which various appropriate cells may be selected to implement a particular cell design. Integrated circuit cells may also include custom circuit design cells individually designed for a particular implementation. The circuit design cell embodiments described herein may be implemented in various implementations of logic or memory integrated circuits.

[0040] Many current designs of cells provide connections and routing for power or signals to transistors or other structures in the area above the transistors. For example, connections and routing for power or signals may be provided on an upper layer of the device. As used herein, the term "upper side" refers to an area in the device that is vertically above the active layer of the device (e.g., above the transistor region of the device when viewed in a typical cross-sectional view). For example, upper side may refer to components such as contacts or layers that are vertically above the transistor region, as shown in the figures and described herein. In some cases, the term "front side" may be used interchangeably with the term "upper side."

[0041] Some recent developments for standard cell design have moved the connections and routing for power connections to metal layers below the transistors. For example, the connections and routing for power may be provided in the backside layer of the device. As used herein, the term “backside” refers to an area within a device that is vertically below the active layer of the device (e.g., below the transistor region of the device when viewed in a typical cross-sectional view). For example, the backside may refer to components such as contacts or layers that are vertically below the transistor region, as shown in the figures and described herein. Note that, as used herein, backside elements located below the active layer may be above, within, or below the silicon substrate on which the active layer is fabricated. That is, as used herein, “backside” refers to the active layer, not the silicon substrate. As used herein, the term “routing” refers to any combination of metal vias, metal wires, metal traces, etc., that provide a path / route between two structures. Additional embodiments may be contemplated in which the metal in “routing” is replaced with an alternative conductive material. For example, the metal in “routing” may be replaced with a superconducting material, a semiconductor material, or a non-metallic conductor.

[0042] A recent development in transistor design is the implementation of vertical transistors, in which the cell has vertical transport through vertically displaced source / drain regions, with the gate located vertically between the source / drain regions. Current vertical transistor designs typically include wide front (e.g., top) power rails at the cell boundary for power delivery. However, these wide power rails result in increased, larger standard cell heights. The increased standard cell height reduces the area efficiency of the vertical transistor while also reducing the transistor's available connectivity and performance.

[0043] The present disclosure contemplates various embodiments that utilize backside power routing in vertical transistor designs to reduce scaling, provide better connectivity, and provide better transistor performance. Particular embodiments disclosed herein have four broad elements: 1) a pair of vertical transistors in an integrated circuit cell; 2) a top metal layer above the transistor region of the vertical transistor with signal routing; 3) a backside metal layer below the transistor region with power routing; and 4) a metal contact layer between the backside metal layer and the source / drain regions of the transistor. In particular embodiments, the transistors are complementary transistors. In some embodiments, vias couple the power routing in the backside metal layer to the metal contact layer. In some embodiments, a second pair of vertical transistors may be included in the cell. Additional implementations of gate vias, fins, contact vias, and various other connections and routing may also be contemplated in various embodiments.

[0044] The present disclosure further contemplates various embodiments of vertical transistor designs that utilize backside power routing in combination with cell-height (e.g., vertical cell) signal routing in upper layers to reduce scaling, provide better connectivity, and provide better transistor performance. Particular embodiments disclosed herein have four broad elements: 1) a pair of vertical transistors; 2) an upper metal layer above the transistor region of the vertical transistor with parallel signal routing in a first direction; 3) gate vias coupling the signal routing in the upper metal layer to at least one of the transistor gates; and 4) parallel power routing in the backside metal layer in a second direction perpendicular to the first direction. In particular embodiments, at least one of the transistors is coupled to the power routing. In some embodiments, a gate bridge connects the gates of the transistors. The gate bridge may be connected to the signal routing by a gate via. The signal routing may include both input and output signal routing, with the input signal routing coupled to the gates and the output signal routing coupled to the source / drain regions of the transistors. In some embodiments, a second pair of vertical transistors may be included in the cell. Additional implementations of gate vias, fins, contact vias, and various other connections and routing may also be contemplated in various embodiments.

[0045] In various embodiments, various contacts or vias are used to form connections for control signals and power signals to implement logic associated with a particular integrated circuit device having multiple vertical transistors for the cell structures described herein. For example, examples of inverter devices, NAND devices, and MUX devices that may be implemented based on the vertical transistor cell structures are described below. Various possible connection embodiments for control signals and voltage signals to the vertical transistors within the cell structures are also described. Those skilled in the art will understand that based on the vertical transistor structures within the cell structures disclosed herein, combinations of these various possible connections can be implemented to generate many different desired circuits.

[0046] In summary, the inventors have recognized that implementing backside routing for power connections in combination with vertical transistors provides various opportunities for building specific transistor designs with reduced scaling. Additionally, various techniques are implemented to provide specific routing for control signals and power routing within cell structures having vertical transistors as described herein. Implementation of the various disclosed techniques contemplates vertical transistor cell structures that provide improved performance at small scale factors.

[0047] Figure 1 shows a perspective view of a contemplated vertical transistor device according to some embodiments. Figure 2 shows a perspective view of another contemplated vertical transistor device according to some embodiments. It should be noted that device 3400 shown in Figure 1 and device 3500 shown in Figure 2 are general representations of vertical transistor-based device structures and do not show the various connections that can be made to the structure. Exemplary embodiments of connected structures are further disclosed herein below with respect to Figures 3-19.

[0048] In the illustrated embodiment of FIG. 1 , device 3400 includes two vertical transistors 3410, 3420. In particular embodiments, transistors 3410, 3420 are complementary transistors. For example, transistor 3410 is a PMOS transistor and transistor 3420 is an NMOS transistor. Transistor 3410 includes a lower source / drain region 3412, a gate 3414, and an upper source / drain region 3416. Similarly, transistor 3420 includes a lower source / drain region 3422, a gate 3424, and an upper source / drain region 3426. In some embodiments, gate 3414 and gate 3424 are fin gates. In various embodiments, gate 3414 includes a gate spacer 3415, and gate 3424 includes a gate spacer 3425. To simplify the drawings, gate spacers 3415, 3425 are not labeled in the remaining figures.

[0049] 1, the lower source / drain region, the gate, and the upper source / drain region are stacked vertically through the transistor. As further shown, transistor 3410 and transistor 3420 are parallel and have a spacing (e.g., distance) between them in the horizontal (e.g., horizontal) direction of device 3400.

[0050] In particular embodiments, transistor 3410 includes a top contact 3418 coupled to top source / drain region 3416, and transistor 3420 includes a top contact 3428 coupled to top source / drain region 3426. Contact 3418 and contact 3428 may be, for example, metal contacts for contacting various resources in a first metal layer disposed above transistors 3410 and 3420. For example, as shown in FIG. 1 , contact 3418 may be routed to a resource by route 3430 (e.g., routing shown by a dotted line). Route 3430 may be, for example, a metal layer route path in the first metal layer above transistors 3410 and 3420. It should be noted that the dotted depiction of route 3430 is provided as an example of one resource (e.g., routing) in a metal layer, and that a metal layer may include multiple resources (e.g., multiple routings). Furthermore, only the first metal layer above transistor 3410 and transistor 3420 is shown; there may be multiple additional metal routings above route 3430.

[0051] In various embodiments, transistor 3410 includes a bottom contact 3419 coupled to bottom source / drain region 3412, and transistor 3420 includes a bottom contact 3429 coupled to bottom source / drain region 3422. Contacts 3419, 3429 may be, for example, metal contacts. Contacts 3419, 3429 may be utilized to route to a backside power routing layer (e.g., backside power routing 3440A or backside power routing 3440B as shown in FIG. 1 and described herein) or to various other resources within device 3400.

[0052] 1, the backside power layer includes backside power routing 3440A and backside power routing 3440B. Routing 3440A and routing 3440B may, for example, provide routing to and from power (e.g., Vdd) and ground (e.g., Vss) resources for device 3400.

[0053] In various embodiments, gate 3414 and gate 3424 are interconnected by gate bridge 3450. Gate bridge 3450 may be formed, for example, by extending the gate material of gate 3414 and gate 3424 to join the gates together. In some embodiments, gate bridge 3450 may be formed by a single extension of gate material extending from either gate 3414 or gate 3424 to the other gate. Gate bridge 3450 may also include an extension of material for a gate spacer. Gate bridge 3450 merges gate 3414 and gate 3424 for implementation of transistor 3410 and transistor 3420 in various embodiments of CMOS devices, some examples of which are described herein. Various embodiments in which gate 3414 and / or gate 3424 extend in other directions may also be contemplated. For example, the gate may include an extension that extends toward the outer boundary of the device 3400 (eg, in the opposite direction from the gate bridge 3450, toward the outer boundary of the cell structure).

[0054] In the illustrated embodiment of FIG. 2 , device 3500 does not have a gate bridge connecting gate 3414 in transistor 3410 and gate 3424 in transistor 3420. Various techniques for connecting transistors 3410 and 3420 without a gate bridge are contemplated. For example, in one contemplated embodiment, contact 3418 and contact 3428 may be connected by strap 3510. Strap 3510 may be, for example, a metal strap. In some embodiments, contact 3418, contact 3428, and strap 3510 may be formed as a single contact (e.g., a single strap connecting upper source / drain region 3416 and upper source / drain region 3426). Various embodiments are also contemplated in which strap 3510 extends in another direction from one of contacts 3418, 3428. For example, strap 3510 may extend orthogonally to the illustrated embodiment toward another vertical transistor or resource within device 3500.

[0055] In another contemplated embodiment, contact 3419 and contact 3429 may be connected by strap 3520. Strap 3520 may also be a metal strap. In some embodiments, strap 3520 is formed with contact 3419 and contact 3429 as a single contact. For example, strap 3520, contact 3419, and contact 3429 may be part of a single metal contact plate formed in a contact layer. Various embodiments may also be contemplated in which contact 3419 and / or contact 3429 extend outward from the bottom of transistor 3410, 3420. For example, the contact may have a portion that extends toward an outer boundary of device 3500 (e.g., toward an outer boundary of the cell structure).

[0056] While various connection structures are shown separately in device 3400 shown in FIG. 1 and device 3500 shown in FIG. 2, it should be understood that embodiments may be contemplated in which structures from device 3400 are combined with structures from device 3500 in a cell design. For example, a device may be contemplated that includes both gate bridge 3450 and one or both of strap 3510 and strap 3520. Various exemplary device cell configurations based on device 3400 and / or device 3500 will now be described by way of example. It should be noted that the various device cell structures are provided as examples, and that various additional device cell structures may be implemented based on the description herein.

[0057] 3-7 show diagrams of inverter cell structures, according to some embodiments. FIG. 3 shows a perspective view of an inverter cell structure, according to some embodiments. FIG. 4 shows a top plan view of an inverter cell structure, according to some embodiments. FIG. 5 shows a back plan view of an inverter cell structure, according to some embodiments. FIG. 6 shows a cross-sectional view of an inverter cell structure along line 6-6 (e.g., along the gate bridge) shown in FIG. 4, according to some embodiments. FIG. 7 shows a cross-sectional view of an inverter cell structure along line 7-7 (e.g., perpendicular to the gate fin of transistor 3410) shown in FIG. 4, according to some embodiments.

[0058] Inverter cell device 3600 can be derived from the structure of device 3400 shown in Figure 1. In the illustrated embodiment of Figures 3-7, device 3600 includes vertical transistor 3410 and vertical transistor 3420. Transistor 3410 includes a lower source / drain region 3412, a gate 3414, an upper source / drain region 3416, an upper contact 3418, and a lower contact 3419. Transistor 3420 includes a lower source / drain region 3422, a gate 3424, an upper source / drain region 3426, an upper contact 3428, and a lower contact 3429. In the illustrated embodiment of device 3600, transistor 3410 is a PMOS transistor and transistor 3420 is an NMOS transistor.

[0059] In a particular embodiment, device 3600 includes backside vias 3610A, 3610B. Backside via 3610A is coupled to lower source / drain region 3412 via bottom contact 3419. Backside via 3610A couples lower source / drain region 3412 to backside power routing 3440A. For device 3600, backside power routing 3440A provides power (e.g., Vdd) to lower source / drain region 3412 and transistor 3410. Backside via 3610B is coupled to lower source / drain region 3422 via bottom contact 3429. Backside via 3610B couples lower source / drain region 3422 to backside power routing 3440B. For device 3600, backside power routing 3440B provides ground (e.g., Vss) to lower source / drain region 3422 and transistor 3420.

[0060] In various embodiments, device 3600 includes upper vias 3620A, 3620B. Upper via 3620A may be coupled to upper source / drain region 3416 via top contact 3418, and upper via 3620B may be coupled to upper source / drain region 3426 via top contact 3428. Upper vias 3620A, 3620B may provide connections to signal routing resources (e.g., routes 3430A-E) in the first metal layer above transistors 3410 and 3420. For example, in the illustrated embodiment, upper via 3620A is coupled to route 3430B, and upper via 3620B is coupled to route 3430D. Routes 3430B and 3430D may provide routes for output signals from transistors 3410 and 3420, respectively.

[0061] In particular embodiments, a route for an input signal to transistor 3410 and transistor 3420 is provided by route 3430C. As shown in FIGS. 3 and 4 , route 3430C is coupled to gate via 3630, which is coupled to gate bridge 3450. Thus, gate via 3630 provides a connection between route 3430C (e.g., an input signal route) and both gate 3414 of transistor 3410 and gate 3424 of transistor 3420. By connecting to the input signal route, the output signal route, and the power / ground route, transistor 3410 and transistor 3420 are connected to form inverter cell device 3600.

[0062] 3 and 4 show five routes 3430A-E in the first metal layer above transistors 3410 and 3420, it should be noted that the first metal layer may include additional routes. Furthermore, additional metal layers may be disposed above the first metal layer to provide various connections to either the first metal layer or device 3600. For example, in one embodiment, the metal layer above the first metal layer may include a strap (or other connector) that couples route 3430B and route 3430D such that the outputs of transistors 3410 and 3420 are merged together into a single output. Additionally, while two backside power routings (e.g., routing 3440A and routing 3440B) are shown, the backside power layer may include additional routings (e.g., routings for other power and signal resources).

[0063] The top and back plan views of device 3600 shown in Figures 4 and 5 further show gate fins that may be present on the gates of the transistor. For example, gate fin 3415 is the gate fin for gate 3414, and gate fin 3425 is the gate fin for gate 3424. Gate fin 3415 and gate fin 3425 are also shown in the cross-sectional view of device 3600 in Figure 6, and gate fin 3415 is shown in the cross-sectional view of transistor 3410 in Figure 7. Note that the cross-sectional view in Figure 7 is perpendicular to the gate fins of transistor 3410, which is in the direction of route 3430B shown in Figures 3 and 4.

[0064] 8-12 show diagrams of NAND cell structures, according to some embodiments. FIG. 8 shows a perspective view of a NAND cell structure, according to some embodiments. FIG. 9 shows a top plan view of a NAND cell structure, according to some embodiments. FIG. 10 shows a back plan view of a NAND cell structure, according to some embodiments. FIG. 11 shows a cross-sectional view of a NAND cell structure along line 11-11 shown in FIG. 9 (e.g., along gate bridge 3450′), according to some embodiments. FIG. 12 shows a cross-sectional view of a NAND cell structure along line 12-12 shown in FIG. 9 (e.g., perpendicular to the gate fins of transistor 3410 and transistor 3410′), according to some embodiments.

[0065] The NAND cell device 4100 can be derived from the structure of the device 3400 shown in FIG. 1. In the illustrated embodiment of FIGS. 8-12, the device 4100 includes a vertical transistor 3410, a vertical transistor 3420, a vertical transistor 3410', and a vertical transistor 3420'. Transistor 3410 includes a lower source / drain region 3412, a gate 3414, and an upper source / drain region 3416. Transistor 3420 includes a lower source / drain region 3422, a gate 3424, and an upper source / drain region 3426. Transistor 3410' includes a lower source / drain region 3412', a gate 3414', and an upper source / drain region 3416'. Transistor 3420' includes a lower source / drain region 3422', a gate 3424', and an upper source / drain region 3426'. In the illustrated embodiment of device 4100, transistor 3410 and transistor 3410' are PMOS transistors, and transistor 3420 and transistor 3420' are NMOS transistors.

[0066] In particular embodiments, a route for an input signal to transistor 3410, transistor 3410′, transistor 3420, and transistor 3420′ is provided by route 3430C. As shown in FIGS. 8 and 9 , route 3430C is coupled to gate via 3630A, which is coupled to gate bridge 3450, and gate via 3630B, which is coupled to gate bridge 3450′. Thus, gate via 3630A provides a connection between route 3430C (e.g., an input signal route) and both gate 3414 of transistor 3410 and gate 3424 of transistor 3420. Gate via 3630B provides a connection between route 3430C (e.g., an input signal route) and both gate 3414′ in transistor 3410′ and gate 3424′ in transistor 3420′.

[0067] In particular embodiments, upper source / drain region 3416 of transistor 3410 and upper source / drain region 3416' of transistor 3410' are connected by contact 3418. Similarly, upper source / drain region 3426 of transistor 3420 and upper source / drain region 3426' of transistor 3420' are connected by contact 3428. In various embodiments, device 4100 includes an upper via 3620 connected to contact 3418. Upper via 3620 can provide a connection to route 3430B in the first metal layer above the transistor region of device 4100. In the illustrated embodiment, route 3430B provides a route for output signals from transistor 3410 and transistor 3410'.

[0068] In the illustrated embodiment, only transistor 3410, transistor 3410', and transistor 3420 are connected to the backside layer. For example, as shown in Figures 7 and 10, transistor 3410 is connected to backside power routing 3440A by contact 3419 and backside via 3610A, transistor 3410' is connected to backside power routing 3440A by contact 3419' and backside via 3610A', and transistor 3420 is connected to backside power routing 3440B by contact 3429 and backside via 3610B. In various embodiments of device 4100, backside power routing 3440A provides power (e.g., Vdd) to lower source / drain region 3412 and transistor 3410, and lower source / drain region 3412' and transistor 3410', while backside power routing 3440B provides ground (e.g., Vss) to lower source / drain region 3422 and transistor 3420.

[0069] In a particular embodiment, the lower source / drain region 3422′ in the transistor 3420′ is connected to a contact 3429′ that is not connected to the backside power routing layer. The contact 3429′ extends away from the lower source / drain region 3422′ toward the boundary of the cell, as shown in FIGS. 8, 10, and 11. The contact 3429′ is then coupled to a route 3430E by a contact via 4110. The route 3430E is a route in the first metal layer above the transistor region. The contact via 4110 is a via that belongs to the cell structure of the device 4100 and is not shared with any adjacent cells along the cell boundary. In a particular embodiment, the route 3430E is a signal route in the first metal layer for signal output from the transistor 3420′. Thus, signals in the NMOS transistors (e.g., transistor 3420 and transistor 3420') are routed from the lower source / drain region 3422 (connected to ground by backside power routing 3440B), through the transistor, and through contact via 4110 to route 3430E.

[0070] In the illustrated embodiment, route 3430E provides a route for the output signals from transistor 3420 and transistor 3420′. The output signal routed through route 3430E may be combined with the output signal from route 3430B. For example, a metal layer above the first metal layer may include a strap (or other connector) that couples route 3430B and route 3430E so that the outputs of the transistors are merged together into a single output.

[0071] The various routings and connections within device 4100 form a NAND cell device. Figures 9 and 10 show gate fins 3415, 3415', 3425, and 3425' within gates 3414, 3414', 3424, and 3424', respectively. Gate fins 3415' and 3425' are also shown in the cross-sectional view of device 4100 in Figure 11, and gate fins 3415 and 3415' are shown in the cross-sectional view of device 4100 in Figure 12. Note that the cross-sectional view in Figure 12 is perpendicular to the gate fins of transistor 3410 and transistor 3410', which is in the direction of route 3430B shown in Figure 9.

[0072] 13-17 show diagrams of MUX (multiplexer) cell structures, according to some embodiments. FIG. 13 shows a perspective view of a MUX cell structure, according to some embodiments. FIG. 14 shows a top plan view of a MUX cell structure, according to some embodiments. FIG. 15 shows a back plan view of a MUX cell structure, according to some embodiments. FIG. 16 shows a cross-sectional view of a MUX cell structure along line 16-16 shown in FIG. 14 (e.g., along gate fin 3415′ and gate fin 3425″), according to some embodiments. FIG. 17 shows a cross-sectional view of a MUX cell structure along line 17-17 shown in FIG. 14 (e.g., perpendicular to the gate fins of transistor 3410 and transistor 3410″), according to some embodiments.

[0073] MUX cell device 4600 can be derived from the structure of device 3500 shown in FIG. 2. In the illustrated embodiment of FIGS. 13-17, device 4600 includes vertical transistor 3410, vertical transistor 3420, vertical transistor 3410", and vertical transistor 3420". As in device 3500, there are no gate bridges between the gates of the transistors in device 4600, and as a result, there is no common gate between complementary transistors. Transistor 3410 includes a lower source / drain region 3412, a gate 3414, and an upper source / drain region 3416. Transistor 3420 includes a lower source / drain region 3422, a gate 3424, and an upper source / drain region 3426. Transistor 3410" includes a lower source / drain region 3412", a gate 3414", and an upper source / drain region 3416". Transistor 3420'' includes a lower source / drain region 3422'', a gate 3424'', and an upper source / drain region 3426''. In the illustrated embodiment of device 4600, transistors 3410 and 3410'' are PMOS transistors, and transistors 3420 and 3420'' are NMOS transistors.

[0074] Because MUX cell device 4600 is a transfer device, neither transistor 3410 nor transistor 3410" nor transistor 3420 nor transistor 3420" is connected to any power sources within the MUX cell structure. In various embodiments of MUX cell device 4600, the lower source / drain regions of the transistors are connected together (e.g., merged together). For example, in the illustrated embodiment, contact plate 4620 is connected to lower source / drain region 3412 of transistor 3410, lower source / drain region 3412" of transistor 3410", lower source / drain region 3422 of transistor 3420, and lower source / drain region 3422" of transistor 3420".

[0075] In particular embodiments, contact via 4630 is coupled to contact plate 4620. Contact via 4630 may be connected to contact plate 4620 at or near the center of the contact plate. Contact via 4630 then connects to route 3430C in the first metal layer above the transistor region. In various embodiments, route 3430C provides output routing for MUX cell device 4600. Thus, contact via 4630 can be referred to as an output pin of MUX cell device 4600.

[0076] In various embodiments, gates 3414, 3414", 3424, 3424" extend toward the cell boundary to provide a surface for direct vertical connection from a route in the upper first metal layer to the gate. For example, as shown in FIGS. 13-17, gate 3414 includes gate extension 4640A that extends toward the cell boundary (e.g., extends horizontally toward the cell boundary). Similarly, gate 3414" includes gate extension 4640B, gate 3424 includes gate extension 4640C, and gate 3424" includes gate extension 4640D. Gate extensions 4640A-D are then connected to a route in the upper first metal layer by gate vias 3630A-D, respectively. 13 and 14, gate via 3630A connects gate extension 4640A to route 3430A, gate via 3630B connects gate extension 4640B to route 3430A, gate via 3630C connects gate extension 4640C to route 3430E, and gate via 3630D connects gate extension 4640D to route 3430E. One or both of route 3430A and route 3430E are located at the boundary of the cell and are not shared with adjacent cells. Route 3430A and route 3430E may provide input routes to device 4600.

[0077] In a particular embodiment, upper source / drain region 3416 in transistor 3410 is connected to upper source / drain region 3426 in transistor 3420 by contact 4610A. This connection merges upper source / drain region 3416 into upper source / drain region 3426. Similarly, upper source / drain region 3416" in transistor 3410" is connected to upper source / drain region 3426" in transistor 3420" by contact 4610B. These merging of upper source / drain regions and the common connection between the lower source / drain regions (and single output through contact via 4630) allow device 4600 to operate as a MUX (multiplexer), with signals input through gate vias 3630A-D and output through contact via 4630.

[0078] 14 and 15 show gate fins 3415, 3415'', 3425, and 3425'' in gates 3414, 3414'', 3424, and 3424'', respectively. Gate fins 3415 and 3425 are also shown in the cross-sectional view of device 4600 in FIG. 16, and gate fins 3415 and 3415'' are shown in the cross-sectional view of device 4600 in FIG. 17. Note that the cross-sectional view in FIG. 17 is perpendicular to the gate fins of transistor 3410 and transistor 3410'', which is in the direction of route 3430B shown in FIG. 14.

[0079] Figures 18 and 19 show diagrams of cell devices with dielectric walls, according to some embodiments. Figure 18 shows a perspective view of device 5100, according to some embodiments. Figure 19 shows a cross-sectional view of device 5100 along line 19-19 shown in Figure 51 (e.g., along gate bridge 3450'), according to some embodiments.

[0080] Device 5100 can be derived from the structure of device 3400 shown in FIG. 1. In some embodiments, device 5100 can be similar to inverter cell device 4100 shown in FIGS. 8-12. In the illustrated embodiment of FIGS. 18 and 19, device 5100 includes vertical transistor 3410 and vertical transistor 3420. Transistor 3410 includes a lower source / drain region 3412, a gate 3414, and an upper source / drain region 3416. Transistor 3420 includes a lower source / drain region 3422, a gate 3424, and an upper source / drain region 3426. In particular embodiments, transistor 3410 is a PMOS transistor and transistor 3420 is an NMOS transistor.

[0081] In various embodiments, as shown in Figures 18 and 19, wall 5100A may be disposed on a first side of the cell (e.g., the side of transistor 3410) and wall 5100B may be disposed on a second side of the cell (e.g., the side of transistor 3420 opposite transistor 3410). In particular embodiments, wall 5100A and wall 5100B are dielectric walls. By disposing a dielectric wall on one or both sides of device 5100, the space required between device 5100 and another adjacent cell may be reduced. Thus, wall 5100A and wall 5100B may be implemented when device scaling needs to be reduced.

[0082] 20-33 illustrate various exemplary device cell structures for integrated circuit cell devices having vertical transistors. In these exemplary device cell structures, the device has a first metal layer along the cell height (e.g., along the cell height direction) that is utilized for signal input / output connections to the vertical transistors. It should be noted that the various device cell structures are provided as examples, and various additional device cell structures can be implemented based on the description herein. For example, the illustrated device cell structures include an inverter cell structure, a NAND cell structure, and a MUX (multiplexer) cell structure. These cell structures can provide basic cell structures that can be implemented in various types of integrated circuit devices.

[0083] 20-24 show diagrams of inverter cell structures, according to some embodiments. FIG. 20 shows a perspective view of an inverter cell structure, according to some embodiments. FIG. 21 shows a top plan view of an inverter cell structure, according to some embodiments. FIG. 22 shows a back plan view of an inverter cell structure, according to some embodiments. FIG. 23 shows a cross-sectional view of an inverter cell structure along line 23-23 shown in FIG. 21 (e.g., in the cell height direction, along the gate bridge) according to some embodiments. FIG. 24 shows a cross-sectional view of an inverter cell structure along line 24-24 shown in FIG. 21 (e.g., perpendicular to the gate bridge in the gate pitch direction) according to some embodiments.

[0084] Inverter cell device 5300 can be derived from the structures of device 3400 shown in Figure 1 and device 3600 shown in Figure 3. In the illustrated embodiment of Figures 20-24, device 5300 includes four vertical transistors 5310, 5320, 5330, and 5340. Transistor 5310 includes a lower source / drain region 5312, a gate 5314, a gate spacer 5315, and an upper source / drain region 5316. Transistor 5320 includes a lower source / drain region 5322, a gate 5324, a gate spacer 5325, an upper source / drain region 5326, an upper contact 5328, and a lower contact 5329. Similarly, transistor 5330 includes lower source / drain region 5332, gate 5334, gate spacer 5335, upper source / drain region 5336, upper contact 5338, and lower contact 5339, and transistor 5340 includes lower source / drain region 5342, gate 5344, gate spacer 5345, upper source / drain region 5346, upper contact 5348, and lower contact 5349. In the illustrated embodiment of device 5300, transistors 5310 and 5330 are PMOS transistors, and transistors 5320 and 5340 are NMOS transistors. Note that some components may be hidden in some views of Figures 20-24.

[0085] Device 5300 may include various contacts to the transistors (e.g., transistors 5310, 5320, 5330, 5340) for signal routing or power routing. For example, device 5300 may include an upper contact 5318 connected to upper source / drain region 5316 and a lower contact 5319 connected to lower source / drain region 5312 for transistor 5310, an upper contact 5328 connected to upper source / drain region 5326 and a lower contact 5329 connected to lower source / drain region 5322 for transistor 5320, an upper contact 5338 connected to upper source / drain region 5336 and a lower contact 5339 connected to lower source / drain region 5332 for transistor 5330, and an upper contact 5348 connected to upper source / drain region 5346 and a lower contact 5349 connected to lower source / drain region 5342 for transistor 5340. In various embodiments, device 5300 includes backside vias 5350A, 5350B, 5350C, 5350D to transistors 5310, 5320, 5330, 5340. Backside via 5350A is coupled to lower source / drain region 5312 via bottom contact 5319. Backside via 5350B is coupled to lower source / drain region 5322 via bottom contact 5329. Backside via 5350C is coupled to lower source / drain region 5332 via bottom contact 5339. Backside via 5350D is coupled to lower source / drain region 5342 via bottom contact 5349.

[0086] In the illustrated embodiment, backside vias 5350A, 5350C couple the lower source / drain regions 5312, 5332 of transistors 5310, 5330, respectively, to backside power routing 5360A. Backside vias 5350B, 5350D couple the lower source / drain regions 5322, 5342 of transistors 5320, 5340 to backside power routing 5360B. For device 5300, backside power routing 5360A provides power (e.g., Vdd) to the lower source / drain regions 5312, 5332 and transistors 5310, 5330, while backside power routing 5360B provides ground (e.g., Vss) to the lower source / drain regions 5322, 5342 and transistors 5320, 5340. However, backside power routing 5360A can be switched to backside power routing 5360B to provide power, and backside power routing 5360B can be switched to backside power routing 5360A to provide ground.

[0087] The top and back plan views of device 5300 shown in Figures 21 and 22, respectively, further show gate fins that may be present on the gates of the transistor. For example, gate fin 5313 is a gate fin for gate 5314, gate fin 5323 is a gate fin for gate 5324, gate fin 5333 is a gate fin for gate 5334, and gate fin 5343 is a gate fin for gate 5345. Gate fins 5313 and 5323 are shown in the cross-sectional view of device 5300 in Figure 23, and gate fins 5323 and 5343 are shown in the cross-sectional view of device 5300 in Figure 24.

[0088] In various embodiments, gate pairs (e.g., gate pair 5314 and gate 5324, or gate pair 5334 and gate 5344) are interconnected by a gate bridge. For example, in the illustrated embodiment, gates 5314 and 5324 are interconnected by gate bridge 5380A, and gates 5334 and 5344 are interconnected by gate bridge 5380B. Gate bridges 5380A, 5380B may be formed by extending gate material across the space between the gates, as shown in Figures 20-23, for example. To implement transistors 5310, 5320, 5330, and 5340 in an inverter device, gate bridge 5380A merges gate 5314 and gate 5324, while gate bridge 5380B merges gate 5334 and gate 5344. In some embodiments, gate bridges 5380A, 5380B may also include extensions of material for gate spacers between transistors, for example, gate bridge 5380A includes extensions of material for gate spacers 5315 and 5325, and gate bridge 5380B includes extensions of material for gate spacers 5335 and 5345.

[0089] In particular embodiments, gate vias 5390A, 5390B are connected to gate bridges 5380A, 5380B, respectively. Gate vias 5390A, 5390B may be vias utilized to connect gate bridges 5380A, 5380B to routing within the first metal layer, as described below. Connecting gate via 5390A to gate bridge 5380A allows for the implementation of a single signal input connection for the pair of gates 5314 and 5324 merged by the bridge. Similarly, a single signal input for gates 5334 and 5344 is provided by gain via 5390B connected to gate bridge 5380B.

[0090] In various embodiments, the device 5300 includes upper vias 5392A, 5392B, 5392C, 5392D. The upper vias 5392A, 5392B, 5392C, 5392D can be coupled to the upper source / drain regions 5316, 5326, 5336, 5346 via top contacts 5318, 5328, 5338, 5348, respectively. As shown in the illustrated embodiment, the top contacts 5318, 5328, 5338, 5348 can include portions that extend from where the top contacts connect to the upper source / drain regions 5316, 5326, 5336, 5346 to where the top contacts connect to the upper vias 5392A, 5392B, 5392C, 5392D. Thus, the top contacts 5318, 5328, 5338, 5348 redistribute the horizontal locations for connections to the top source / drain regions 5316, 5326, 5336, 5346 from the horizontal locations of the top source / drain regions to the horizontal locations of the top vias 5392A, 5392B, 5392C, 5392D. The top vias 5392A, 5392B, 5392C, 5392D may provide connections to signal routing resources (e.g., routes 5370B,D) in the first upper metal layer above transistors in the device 5300, as described below.

[0091] In a particular embodiment, device 5300 includes a first upper metal layer having signal routing with routes that extend in the cell height direction (e.g., along the vertical direction of the integrated circuit cell, as shown in FIGS. 21 and 22). In the illustrated embodiment, the signal routing in the first upper metal layer includes four signal routes 5370A, 5370B, 5370C, and 5370D (shown by dashed lines) that extend in the cell height direction. Because these signal routes 5370A-D extend in the cell height direction, the signal routes may have a pitch (e.g., metal pitch) that has a 1:2 ratio to the gate pitch (e.g., contact poly pitch) in device 5300.

[0092] Because the pitch of signal routes 5370A-D is narrow compared to the pitch of gates 5314, 5324, 5334, and 5344, the signal routes can be used for both input and output signal routing to transistors 5310, 5320, 5330, and 5340. For example, in the illustrated embodiment, signal route 5370A and signal route 5370C are input signal routes connected to gate via 5390A and gate via 5390B, respectively. Thus, signal route 5370A provides an input signal to merged transistors 5310 and 5320 (e.g., the transistor having gates 5314 and 5324 merged by gate bridge 5380A and coupled to gate via 5390A). Similarly, signal route 5370C provides an input signal to merged transistors 5330 and 5340 (eg, transistors having gates 5334 and 5344 merged by gate bridge 5380B and coupled to gate via 5390B).

[0093] Further, in the illustrated embodiment, signal route 5370B and signal route 5370D are output signal routes. Signal route 5370B is connected to the outputs of transistors 5310 and 5320 via upper source / drain regions 5316, 5326, upper contacts 5318, 5328, and upper vias 5392A, 5392B. Signal route 5370D is connected to the outputs of transistors 5330 and 5340 via upper source / drain regions 5336, 5346, upper contacts 5338, 5348, and upper vias 5392C, 5392D. In device 5300, both input and output signal routes can be in the same upper metal layer due to the metal pitch being half the gate pitch in the device. This pitch difference allows signal routes 5370A, 5370C to be above the gates (e.g., above the gate fins) and signal routes 5370B, 5370D to be between the gates (e.g., between the gate fins). The metal pitch described above therefore allows device 5300 to have connected gate logic through a single upper metal layer for an inverter device with four vertical transistors.

[0094] While Figures 20-22 (and additional figures herein) show four routes 5370A-D in the first upper metal layer above transistors 5310, 5320, 5330, and 5340, it should be noted that the first upper metal layer may include additional routes. Furthermore, additional metal layers may be disposed above the first upper metal layer to provide various connections to either the first upper metal layer or device 5300. For example, in one embodiment, another upper metal layer above the first upper metal layer may include a strap (or other connector) that couples route 5370B and route 5370D so that the transistor outputs are merged together into a single output. An example of routing in the second upper metal layer is shown in Figure 21 by routes 5410A-G. Note that the routing in the second upper metal layer is orthogonal to the routing in the first upper metal layer. Additionally, although two backside power routings (eg, routing 5360A and routing 5360B) are shown, the backside power layer may include additional routings (eg, routings for other power resources).

[0095] 25-29 show diagrams of NAND cell structures, according to some embodiments. FIG. 25 shows a perspective view of a NAND cell structure, according to some embodiments. FIG. 26 shows a top plan view of a NAND cell structure, according to some embodiments. FIG. 27 shows a back plan view of a NAND cell structure, according to some embodiments. FIG. 28 shows a cross-sectional view of a NAND cell structure along line 28-28 shown in FIG. 26 (e.g., across gate fin 5313 and gate fin 5333), according to some embodiments. FIG. 29 shows a cross-sectional view of a NAND cell structure along line 29-29 shown in FIG. 26 (e.g., across gate fin 5323 and gate fin 5343), according to some embodiments.

[0096] NAND cell device 5800 can be derived from the structures of device 3400 shown in Figure 1 and device 4100 shown in Figure 8. In the illustrated embodiment of Figures 25-29, NAND cell device 5800 includes vertical transistor 5310, vertical transistor 5320, vertical transistor 5330, and vertical transistor 5340. Transistors 5310, 5320, 5330, and 5340 are similar to the corresponding transistors shown in Figures 20-24. For example, transistor 5310 includes lower source / drain region 5312, gate 5314, gate spacer 5315, and upper source / drain region 5316; transistor 5320 includes lower source / drain region 5322, gate 5324, gate spacer 5325, and upper source / drain region 5326; transistor 5330 includes lower source / drain region 5332, gate 5334, gate spacer 5335, and upper source / drain region 5336; and transistor 5340 includes lower source / drain region 5342, gate 5344, gate spacer 5345, and upper source / drain region 5346. In the illustrated embodiment of device 5800, transistors 5310 and 5330 are PMOS transistors, and transistors 5320 and 5340 are NMOS transistors. Note that some components may be hidden in some of the views of FIGS. 25-29.

[0097] Device 5800 may include various contacts to the transistors (e.g., transistors 5310, 5320, 5330, 5340) for signal routing or power routing. For example, device 5800 may include a top contact 5810 connected to both the upper source / drain region 5316 of transistor 5310 and the upper source / drain region 5336 of transistor 5330. Top contact 5810 also includes an extension 5812 that extends (e.g., extends horizontally) beyond the upper source / drain region 5336 of transistor 5330 toward the cell boundary. An upper via 5392C then provides a connection between top contact 5810 and route 5370D. Device 5800 further includes a top contact 5820 connected to both the upper source / drain region 5326 of transistor 5320 and the upper source / drain region 5346 of transistor 5340. Note that there is no extension of top contact 5820.

[0098] 25 , device 5800 includes bottom contacts to power for transistors 5310, 5320, and 5330, but not for transistor 5340. Thus, device 5800 includes bottom contact 5319 connected to bottom source / drain region 5312 of transistor 5310, bottom contact 5329 connected to bottom source / drain region 5322 of transistor 5320, and bottom contact 5339 connected to bottom source / drain region 5332 of transistor 5330. For power connections, device 5800 includes backside vias 5350A, 5350B, and 5350C to transistors 5310, 5320, and 5330. Backside via 5350A is coupled to lower source / drain region 5312 via bottom contact 5319, backside via 5350B is coupled to lower source / drain region 5322 via bottom contact 5329, and backside via 5350C is coupled to lower source / drain region 5332 via bottom contact 5339. In a particular embodiment of device 5800, backside power routing 5360A supplies power (e.g., Vdd) to lower source / drain region 5312 and transistor 5310, and lower source / drain region 5332 and transistor 5330, while backside power routing 5360B supplies ground (e.g., Vss) to lower source / drain region 5322 and transistor 5320.

[0099] For transistor 5340 in device 5800, bottom contact 5830 is coupled to bottom source / drain region 5342. Bottom contact 5830 includes extension 5832 that extends (e.g., extends horizontally) toward the boundary of the cell, away from bottom source / drain region 5342 of transistor 5340, as shown in FIG. 25 . As shown, there is no connection between transistor 5340 and backside power routing 5360B. For connected gate logic associated with a NAND device, device 5800 includes an upper backside via 5840 that connects extension 5832 of bottom contact 5830 to route 5370D.

[0100] 25-27, route 5370A provides signal input routing to gate via 5390A, and route 5370C provides signal input routing to gate via 5390B. Thus, device 5800 can receive two separate input signals, one for transistors 5310 and 5320 merged by gate bridge 5380A, and one for transistors 5330 and 5340 merged by gate bridge 5380B. Route 5370B is not used for NAND cell device 5800 (e.g., is not connected to any transistors).

[0101] Output signal routing of device 5800 is provided by route 5370D. As shown in the illustrated embodiment, route 5370D is connected to upper source / drain regions 5316, 5336 of transistors 5310, 5330, respectively, by top contact 5810, extension 5812, and upper via 5392C. Route 5370D is also connected to lower source / drain region 5342 of transistor 5340 by bottom contact 5830, extension 5832, and upper backside via 5840. Thus, the transistor outputs are merged together at route 5370D. Due to the 1:2 ratio between metal pitch and gate pitch mentioned above, connection to route 5370D through extension 5812 and extension 5832, and subsequently through top via 5392C and upper backside via 5840, respectively, is possible in device 5800.

[0102] The connections within device 5800 establish connected gate logic for a NAND cell device, with inputs through gate vias 5390A, 5390B and outputs through top via 5392C and top backside via 5840. Similar to device 5300, both the input and output signal routes of device 5800 can be in the same upper metal layer due to the metal pitch being half the gate pitch within the device. This pitch difference allows signal routes 5370A, 5370C to be above the gates (e.g., above the gate fins) and signal routes 5370B, 5370D to be between the gates (e.g., between the gate fins). The metal pitch described above therefore enables device 5800 to have connected gate logic through a single upper metal layer for a NAND device with four vertical transistors.

[0103] 20-24 illustrate device 5300 with connected gate logic for an inverter device, and FIGS. 25-29 illustrate device 5800 with connected gate logic for a NAND device, it should be understood that various additional embodiments may be contemplated for other connected gate logic for other devices utilizing four vertical transistors and signal routes extending along the cell height in the first upper metal layer. For example, various other gate extensions, bridges, vias, etc. may be implemented to provide any of a variety of connected gate logic to the vertical transistors, independently or in combination.

[0104] 30-33 show diagrams of a MUX (multiplexer) cell structure, according to some embodiments. FIG. 30 shows a perspective view of a MUX cell structure, according to some embodiments. FIG. 31 shows a top plan view of a MUX cell structure, according to some embodiments. FIG. 32 shows a back plan view of a MUX cell structure, according to some embodiments. FIG. 33 shows a cross-sectional view of a MUX cell structure along line 33-33 shown in FIG. 31 (e.g., across gate fin 5313 and gate fin 5333), according to some embodiments.

[0105] MUX cell device 6300 can be derived from the structures of device 3500 shown in Figure 2 and device 4600 shown in Figure 13. In the illustrated embodiment of Figures 30-33, device 6300 includes vertical transistor 5310, vertical transistor 5320, vertical transistor 5330, and vertical transistor 5340. Transistors 5310, 5320, 5330, and 5340 are similar to the corresponding transistors shown in Figures 20-24. For example, transistor 5310 includes lower source / drain region 5312, gate 5314, gate spacer 5315, and upper source / drain region 5316; transistor 5320 includes lower source / drain region 5322, gate 5324, gate spacer 5325, and upper source / drain region 5326; transistor 5330 includes lower source / drain region 5332, gate 5334, gate spacer 5335, and upper source / drain region 5336; and transistor 5340 includes lower source / drain region 5342, gate 5344, gate spacer 5345, and upper source / drain region 5346. In the illustrated embodiment of device 5800, transistors 5310 and 5330 are PMOS transistors, and transistors 5320 and 5340 are NMOS transistors. Note that some components may be hidden in some of the views of FIGS. 25-29.

[0106] Device 6300 may include various contacts to the transistors (e.g., transistors 5310, 5320, 5330, 5340) for signal routing. In a particular embodiment, device 6300 includes contact 6310, where upper source / drain region 5316 in transistor 5310 is connected to upper source / drain region 5326 in transistor 5320 by top contact 6310. Thus, top contact 6310 merges upper source / drain region 5316 with upper source / drain region 5326. Similarly, upper source / drain region 5336 in transistor 5330 is connected to upper source / drain region 5346 in transistor 5340 by contact 6320. Thus, top contact 6320 merges upper source / drain region 5336 with upper source / drain region 5346.

[0107] In various embodiments, gates 5314, 5324, 5334, 5344 are extended to provide a surface for direct vertical connection to the gate from routes 5370B, 5370D in the first upper metal layer. For example, as shown in FIGS. 30-33, gate 5314 includes a gate extension 6330A that extends (e.g., extends horizontally) toward gate 5334. Similarly, gate 5324 includes a gate extension 6330B that extends (e.g., extends horizontally) toward gate 5344. Connection to route 5370B is then provided by gate via 6332A connected to gate extension 6330A and gate via 6332B connected to gate extension 6330B. Due to the 1:2 ratio between metal pitch and gate pitch mentioned above, gate extensions 6330A, 6330B and subsequent connection to route 5370B through gate vias 6332A, 6332B, respectively, are possible in device 6300. Note that gate extensions 6330A-D may include both gate material and gate spacer material.

[0108] The ratio between the metal pitch and the gate pitch further allows gate extension 6330C from gate 5334 and gate extension 6330D from gate 5344 to extend toward the boundary of the cell (e.g., extend horizontally) without increasing the size of the cell beyond the standard cell size. Gate extension 6330C and gate extension 6330D are connected to route 5370D by gate via 6332C and gate via 6332D, respectively. Route 5370B and route 5370D may provide input signal routes to device 6300 via connections to gates of transistors within the device.

[0109] Because MUX cell device 6300 is a transfer device, none of transistors 5310, 5320, 5330, 5340 are connected to any power routing within the MUX cell configuration (e.g., backside power routing 5360A or backside power routing 5360B). In various embodiments of MUX cell device 6300, the lower source / drain regions of the transistors (e.g., lower source / drain regions 5312, 5322, 5332, 5342) are connected together to provide a transfer device. For example, in the illustrated embodiment, device 6300 includes a contact plate 6340 connected to lower source / drain region 5312 of transistor 5310, lower source / drain region 5322 of transistor 5320, lower source / drain region 5332 of transistor 5330, and lower source / drain region 5342 of transistor 5340.

[0110] In particular embodiments, upper backside via 6350 is coupled to contact plate 6340. In particular embodiments, via 6350 connects to contact plate 6340 at or near the center of contact plate 6340. Via 6350 then connects to route 5370B in the first metal layer above the transistor. In various embodiments, route 5370B provides output routing for device 6300. Thus, via 6350 can be referred to as an output pin of device 6300. By merging pairs of upper source / drain regions in device 6300 with a common connection between top contact 6310 and top contact 6320 and the lower source / drain regions (and a single output through contact via 6350), device 6300 can operate as a MUX (multiplexer) where signals are input through gate vias 6332A-D and output through contact via 6350. Thus, the upper metal layer routing and metal pitch to gate pitch described herein allows device 6300 to have disconnected gate logic through a single upper metal layer for a MUX device with four vertical transistors.

[0111] 30-33 illustrate device 6300 with truncated gate logic for a MUX device, it should be understood that various additional embodiments may be contemplated for other truncated gate logic for other devices utilizing four vertical transistors and signal routes extending along the cell height in the first upper metal layer. For example, various other gate extensions, bridges, vias, etc. may be implemented to provide any of a variety of truncated gate logic for the vertical transistors, independently or in combination. Exemplary Computer System

[0112] Referring now to FIG. 34 , a block diagram of one embodiment of a system 6700 is shown, which may incorporate and / or otherwise utilize the methods and mechanisms described herein. In the illustrated embodiment, the system 6700 includes at least one instance of a system on chip (SoC) 6706, which may include multiple types of processing units, such as a central processing unit (CPU), a graphics processing unit (GPU), or other types of processing units, a communications fabric, and interfaces to memory and input / output devices. In some embodiments, one or more processors in the SoC 6706 include multiple execution lanes and instruction issue queues. In various embodiments, the SoC 6706 is coupled to an external memory 6702, peripheral devices 6704, and a power supply 6708.

[0113] A power supply 6708 is also provided to provide a supply voltage to the SoC 6706 and to provide one or more supply voltages to the memory 6702 and / or peripherals 6704. In various embodiments, the power supply 6708 represents a battery (e.g., a rechargeable battery in a smartphone, laptop or tablet computer, or other device). In some embodiments, two or more instances of the SoC 6706 are included (and two or more external memories 6702 are included as well).

[0114] The memory 6702 may be any type of memory, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM, such as mDDR3, and / or low-power versions of SDRAM, such as LPDDR2), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices may be coupled to a circuit board to form a memory module, such as a single inline memory module (SIMM), a dual inline memory module (DIMM), etc. Alternatively, the devices may be mounted on an SoC or integrated circuit in a chip-on-chip, package-on-package, or multi-chip module configuration.

[0115] The peripherals 6704 may include any desired circuitry depending on the type of system 6700. For example, in one embodiment, the peripherals 6704 may include devices for various wireless communications, such as Wi-Fi, Bluetooth, cellular, global positioning systems, etc. In some embodiments, the peripherals 6704 may also include additional storage, including RAM storage, solid-state storage, or disk storage. The peripherals 6704 may include user interface devices, such as a display screen, including a touch or multi-touch display screen, a keyboard or other input device, a microphone, a speaker, etc.

[0116] As shown, the system 6700 is shown to have broad application. For example, the system 6700 may be utilized as part of a chip, circuit, component, etc. in a desktop computer 6710, a laptop computer 6720, a tablet computer 6730, a cellular or mobile phone 6740, or a television 6750 (or a set-top box coupled to a television). Also illustrated is a smartwatch and a health monitoring device 6760. In some embodiments, a smartwatch may include various general-purpose computing-related functions. For example, a smartwatch may provide access to email, mobile phone service, a user calendar, etc. In various embodiments, a health monitoring device may be a dedicated medical device or may otherwise include dedicated health-related functions. For example, a health monitoring device may monitor a user's vital signs, track a user's proximity to other users for epidemiological social distancing, perform contact tracing, and provide communication to emergency services in the event of a health crisis. In various embodiments, the smartwatch described above may or may not include some or any health monitoring-related functions. Other wearable devices are also contemplated, such as devices worn around the neck, devices implantable in the human body, and glasses designed to provide an augmented and / or virtual reality experience.

[0117] The system 6700 may further be used as part of cloud-based service(s) 6770. For example, the aforementioned devices and / or other devices may access computing resources (i.e., remotely located hardware and / or software resources) in the cloud. Furthermore, the system 6700 may be utilized in one or more devices in a home 6780 other than those described above. For example, appliances in the home may monitor and detect noteworthy conditions. For example, various devices in the home (e.g., refrigerators, cooling systems, etc.) may monitor the device status and alert the homeowner (or a repair facility) if a particular event is detected. Alternatively, a thermostat may monitor the home's temperature and automate adjustments to the heating / cooling system based on the homeowner's historical responses to various conditions. FIG. 34 also illustrates the application of the system 6700 to various transportation modes 6790. For example, the system 6700 may be used in control and / or entertainment systems for airplanes, trains, buses, rental cars, private automobiles, watercraft ranging from private boats to cruise ships, scooters (rented or owned), etc. In various cases, system 6700 can be used to provide automated guidance (e.g., for autonomous vehicles), general system control, and other methods. Many other embodiments of any of these are possible and contemplated. Note that the devices and applications illustrated in Figure 34 are merely exemplary and are not intended to be limiting. Other devices are possible and contemplated. ***

[0118] The present disclosure includes references to "one embodiment" or groups of "embodiments" (e.g., "some embodiments" or "various embodiments"). Embodiments are different implementations or examples of the disclosed concepts. References to "one embodiment," "one embodiment," "particular embodiment," etc. do not necessarily refer to the same embodiment. Numerous possible embodiments, including those specifically disclosed, as well as modifications or alternatives that are within the spirit or scope of the present disclosure, are contemplated.

[0119] This disclosure may discuss potential advantages that may result from the disclosed embodiments. Not all implementations of these embodiments necessarily exhibit any or all of the potential advantages. Whether advantages are realized for a particular implementation depends on many factors, some of which are outside the scope of this disclosure. Indeed, there are many reasons why an implementation within the scope of the claims may not exhibit some or all of any disclosed advantages. For example, a particular implementation may include other circuitry outside the scope of this disclosure that, in conjunction with one of the disclosed embodiments, negates or reduces one or more of the disclosed advantages. Furthermore, suboptimal design practices of a particular implementation (e.g., implementation techniques or tools) may also negate or reduce a disclosed advantage. Even assuming skilled practice, realization of advantages may still depend on other factors, such as the environmental conditions in which the implementation is deployed. For example, inputs provided to a particular implementation may prevent one or more problems addressed in this disclosure from occurring on a particular occasion, resulting in the benefits of that solution not being realized. Given the existence of factors external to the present disclosure that may arise, it is expressly intended that any potential advantages described herein should not be construed as claim limitations that must be met in order to demonstrate infringement. Rather, the identification of such potential advantages is intended to illustrate the type(s) of improvement available to a designer having the benefit of the present disclosure. The fact that such advantages are permissibly described (e.g., a statement that a particular advantage "may result") is not intended to convey any doubt as to whether such advantage can actually be realized, but rather to recognize the technological reality that realization of such advantages often depends on additional factors.

[0120] Unless otherwise specified, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of claims made based on this disclosure, even if only a single example is described with respect to a particular feature. The disclosed embodiments are intended to be illustrative, not limiting, unless a statement to the contrary is present in the present disclosure. The above description is intended to enable claims that cover not only the disclosed embodiments, but also alternatives, modifications, and equivalents that will be apparent to those skilled in the art having the benefit of this disclosure.

[0121] For example, features of the present application may be combined in any suitable manner. Accordingly, new claims may be formulated during prosecution of this application (or an application claiming priority to this application) to any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with features of other dependent claims as appropriate, including claims that are dependent on other independent claims. Similarly, features from each independent claim may be combined as appropriate.

[0122] Thus, the accompanying dependent claims may each be drafted to depend on a single other claim, although additional dependencies are also contemplated. Any combination of features in the dependent claims consistent with this disclosure is contemplated and may be claimed in this or another application. In short, combinations are not limited to those specifically recited in the accompanying claims.

[0123] Where appropriate, it is contemplated that a claim drafted in one format or statutory type (e.g., apparatus) is also intended to support a corresponding claim in another format or statutory type (e.g., method). ***

[0124] Because this disclosure is a legal document, various terms and phrases may be subject to administrative and judicial interpretation. The public is hereby notified that the definitions provided in the following paragraphs, as well as throughout this disclosure, will be used in interpreting the claims made based on this disclosure.

[0125] Reference to a singular item (i.e., a noun or noun phrase preceded by "a," "an," or "the") is intended to mean "one or more" unless the context clearly indicates otherwise. Thus, a reference to an "item" in a claim does not exclude additional instances of the item without context. A "plurality" of an item refers to a set of two or more items.

[0126] The word "may" is used herein in a permissive sense (i.e., having the possibility, being able to do), not in an obligatory sense (i.e., not required).

[0127] The terms "comprising" and "including" and their variations are open-ended and mean "including, but not limited to."

[0128] When the term "or" is used in this disclosure in reference to a list of alternatives, it will generally be understood to be used in an inclusive sense unless the context clearly indicates otherwise. Thus, a list of "x or y" is equivalent to "x or y, or both," and thus encompasses 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, the phrase "either x or y, but not both" makes clear that "or" is used in an exclusive sense.

[0129] The enumeration of "w, x, y, z, or any combination thereof," or "...at least one of w, x, y, and z" is intended to encompass all possibilities, including single elements, up to the total number of elements in the set. For example, for the set [w, x, y, z], these expressions encompass any single element of the set (e.g., w but not x, y, or z), any two elements (e.g., w and x but not y or z), any three elements (e.g., w, x, and y but not z), and all four elements. Thus, the phrase "...at least one of w, x, y, and z" refers to at least one element of the set [w, x, y, z], thereby encompassing all possible combinations of this list of elements. This phrase should not be interpreted as requiring that there be at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0130] In this disclosure, various "labels" may precede nouns or noun phrases. Unless the context clearly indicates otherwise, various labels used for a feature (e.g., "first circuit," "second circuit," "particular circuit," "given circuit," etc.) refer to different instances of the feature. Furthermore, when applied to features, the labels "first," "second," and "third" do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) unless otherwise specified.

[0131] The phrase "based on" is used to describe one or more factors that influence a determination. This term does not exclude the possibility that additional factors may influence the decision. That is, the decision may be based only on the specified factors, or on the specified factors as well as other unspecified factors. Consider the phrase "determining A based on B." This phrase identifies B as a factor used to determine A or that influences the determination of A. This phrase does not exclude that the determination of A may also be based on some other factor, such as C. This phrase is intended to cover an embodiment in which A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0132] The phrases "in response to" and "in response to" describe one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, either together with the particular factor or independently of the specified factor. That is, the effect may depend only on these factors, or on the specified factor as well as other unspecified factors. Consider the phrase "performing A in response to B." By this phrase, B is a factor that triggers the execution of A or triggers a particular result for A. This phrase does not exclude that the execution of A may also be in response to other factors, such as C. This phrase also does not exclude that performing A may be in response to both B and C. This phrase is intended to cover embodiments in which A is performed only in response to B. As used herein, the phrase "in response to" is synonymous with the phrase "at least partially in response to." Similarly, the phrase "in response to" is synonymous with the phrase "at least partially in response to." ***

[0133] Within this disclosure, various entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed as being "configured" to perform one or more tasks or operations. This phrase "entity" configured to perform one or more tasks is used herein to refer to a structure (i.e., a physical thing). More specifically, this phrase is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be said to be "configured to" perform a task even if the structure is not currently operating. In this manner, an entity described or explained as being "configured" to perform a task refers to a physical thing, such as a device, a circuit, a system having a processor unit and a memory storing executable program instructions to perform the task. This phrase is not used herein to refer to an intangible thing.

[0134] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations, and even if not specifically described, it will be understood that those entities are "configured to" perform those tasks / operations.

[0135] The term "configured to" is not intended to mean "configurable to." For example, an unprogrammed FPGA is not considered to be "configured" to perform a particular function. However, this unprogrammed FPGA may be "configurable" to perform that function. After appropriate programming, the FPGA can then be said to be "configured" to perform a particular function.

[0136] For purposes of U.S. patent applications based on this disclosure, reciting in a claim that a structure is "configured to" perform one or more tasks is expressly intended to invoke 35 U.S.C. §112(f) for that claim element. not present If an applicant, based on this disclosure, wishes to invoke Section 112(f) during prosecution of a U.S. patent application, it would use "means for" to recite claim elements.

[0137] Various "circuits" may be described in this disclosure. These circuits or "circuitry" comprise hardware that includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuits may be custom designed or obtained from standard libraries. In various implementations, circuitry may include digital components, analog components, or a combination of both, as appropriate. Particular types of circuits may be generally referred to as "units" (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such units are also referred to as circuits or circuitry.

[0138] The disclosed circuits / units / components and other elements shown in the drawings and described herein include hardware elements such as those described in the preceding paragraphs. Often, the internal arrangement of hardware elements within a particular circuit can be specified by describing the function of that circuit. For example, a particular "decode unit" may be described as performing the function of "processing the opcode of an instruction and routing the instruction to one or more of a plurality of functional units," meaning that the decode unit is "configured to" perform this function. This specification of this function is sufficient to suggest a set of possible configurations of the circuit to one skilled in the computer arts.

[0139] In various embodiments, as described in the previous paragraph, circuits, units, and other elements are defined by the functions or operations they are configured to implement. The arrangement of such circuits / units / components relative to one another and the way they interact form a microarchitecture definition of the hardware that is ultimately fabricated in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Thus, a microarchitecture definition is recognized by those skilled in the art as a structure from which many physical implementations can be derived, all of which belong to the broader structure described by the microarchitecture definition. That is, a person skilled in the art presented with a microarchitecture definition provided in accordance with this disclosure can, without undue experimentation, implement the structure by coding the circuit / unit / component description into a hardware description language (HDL), such as Verilog or VHDL, using ordinary techniques. HDL descriptions are often expressed in a manner that appears to be functional. However, to those skilled in the art, this HDL description is the method used to translate the structure of a circuit, unit, or component into the next level of implementation detail. Such HDL descriptions may take the form of behavioral-level code (which is typically not synthesizable), register transfer language (RTL) code (which, in contrast to behavioral-level code, is typically synthesizable), or structural code (e.g., a netlist specifying logic gates and their connections). The HDL description may be synthesized against a library of cells designed for a given integrated circuit manufacturing technology and modified for timing, power, and other reasons, resulting in a final design database that can be sent to a foundry to generate masks and ultimately manufacture the integrated circuit. Some hardware circuits, or portions thereof, may also be custom designed in a schematic editor and incorporated into the integrated circuit design along with the synthesized circuit.An integrated circuit may further include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.), as well as interconnects between the transistors and circuit elements. Some embodiments may implement multiple integrated circuits connected together to realize a hardware circuit, and / or some embodiments may use discrete elements. Alternatively, the HDL design may be integrated into or implemented in a programmable logic array, such as a field programmable gate array (FPGA). This decoupling between the design of a group of circuits and the subsequent lower-level implementation of those circuits generally results in a scenario where the circuit or logic designer does not specify any particular set of structures for the lower-level implementation other than describing how the circuit is configured, since this process is performed at a different stage in the circuit implementation process.

[0140] The fact that many different low-level combinations of circuit elements can be used to implement the same specification for a circuit results in numerous equivalent structures for that circuit. As noted above, these low-level circuit implementations may vary depending on variations in manufacturing technology, the foundry selected to manufacture the integrated circuit, the library of cells provided for a particular project, etc. In many cases, the choices made by different design tools or methods to generate these different implementations may be arbitrary.

[0141] Furthermore, for a given embodiment, it is common for a single implementation of a circuit's particular functional specifications to include a large number of devices (e.g., millions of transistors). Thus, this absolute amount of information makes it impractical to exhaustively enumerate the low-level structures used to implement a single embodiment, let alone the vast number of equivalent possible implementations. For this reason, this disclosure describes the structure of a circuit using functional abbreviations used in the industry.

Claims

1. a first vertical transistor formed in a transistor region of the integrated circuit cell structure, the first vertical transistor having a vertically stacked lower source / drain region, a first gate, and an upper source / drain region; a second vertical transistor formed in the transistor region, the second vertical transistor having a lower source / drain region, a second gate, and an upper source / drain region stacked in the vertical direction, the second vertical transistor being parallel to the first vertical transistor along a first horizontal direction, with at least some spacing between the vertical transistors in the first direction; a first metal layer positioned in the vertical direction above the transistor region, the first metal layer including parallel signal routing in the first direction; at least one gate via coupled between the signal routing in the first metal layer and at least one of the first gate and the second gate; a second metal layer positioned in the vertical direction below the transistor region, the second metal layer including parallel power routing in a second direction perpendicular to the first horizontal direction.

2. The device of claim 1 , wherein the first vertical transistor and the second vertical transistor are complementary transistor types.

3. 2. The apparatus of claim 1, wherein the first vertical transistor is a PMOS transistor and the second vertical transistor is an NMOS transistor.

4. 2. The device of claim 1, further comprising a gate bridge extending in the first direction across the at least some of the spacing between the vertical transistors, the gate bridge being coupled between the first gate and the second gate.

5. 5. The device of claim 4, wherein the at least one gate via is coupled between the signal routing in the first metal layer and a portion of the gate bridge within the at least some spacing between the vertical transistors.

6. 6. The apparatus of claim 5, wherein the at least one gate via is coupled between the gate bridge and a signal input route of the signal routing in the first metal layer.

7. 10. The device of claim 1, further comprising: a third metal layer disposed below the lower source / drain regions and above the second metal layer, the third metal layer including at least one metal portion contacting at least one of the lower source / drain regions.

8. The apparatus of claim 7 , further comprising a bottom via coupled between the at least one metal portion in the third metal layer and the power routing in the second metal layer.

9. a fourth metal layer disposed above the upper source / drain regions and below the first metal layer, the fourth metal layer including at least one metal portion in contact with at least one of the upper source / drain regions; The apparatus of claim 4 further comprising:

10. The fourth metal layer comprises: a first contact coupled to the upper source / drain region of the first transistor, the first contact having a portion extending in the second direction away from the upper source / drain region; a second contact coupled to the upper source / drain region of the second transistor, the second contact having a portion extending in the second direction away from the upper source / drain region.

11. a first contact via coupled between an end of the first contact distal from the upper source / drain region of the first transistor and a signal output route of the signal routing in the first metal layer; a second contact via coupled between an end of the second contact distal from the upper source / drain region of the second transistor and the signal output route; The apparatus of claim 10 further comprising:

12. a third vertical transistor formed in the transistor region, the third vertical transistor having a lower source / drain region, a third gate, and an upper source / drain region stacked in the vertical direction, the third vertical transistor being parallel to the first vertical transistor along the second direction; a fourth vertical transistor formed in the transistor region, the fourth vertical transistor having a lower source / drain region, a fourth gate, and an upper source / drain region stacked in the vertical direction, the fourth vertical transistor being parallel to the third vertical transistor along the first horizontal direction, and having at least some spacing in the first direction between the third vertical transistor and the fourth vertical transistor; a first contact in the fourth metal layer coupled between the upper source / drain region of the first transistor and the upper source / drain region of the third transistor, the first contact having a portion extending in the second direction beyond the upper source / drain region of the third transistor; a second contact in the fourth metal layer, the second contact coupled between the upper source / drain region of the second transistor and the upper source / drain region of the fourth transistor; The apparatus of claim 9 further comprising:

13. a first contact via coupled between the portion of the first contact extending in the second direction beyond the upper source / drain region of the third transistor and a signal output route of the signal routing in the first metal layer; a metal extension coupled to a bottom of the lower source / drain region of the fourth transistor, the metal extension extending in the second direction from the bottom of the lower source / drain region toward a boundary of the integrated circuit cell; a second contact via coupled between the metal extension portion and the signal output route; The apparatus of claim 12 further comprising:

14. The fourth metal layer comprises:

10. The device of claim 9, further comprising a first contact coupled between the upper source / drain region of the first transistor and the upper source / drain region of the second transistor.

15. a third vertical transistor formed in the transistor region, the third vertical transistor having a lower source / drain region, a third gate, and an upper source / drain region stacked in the vertical direction, the third vertical transistor being parallel to the first vertical transistor along the second direction; a fourth vertical transistor formed in the transistor region, the fourth vertical transistor having a lower source / drain region, a fourth gate, and an upper source / drain region stacked in the vertical direction, the fourth vertical transistor being parallel to the third vertical transistor along the first horizontal direction, and having at least some spacing in the first direction between the third vertical transistor and the fourth vertical transistor; a second contact in the fourth metal layer, the second contact coupled between the upper source / drain region of the third transistor and the upper source / drain region of the fourth transistor; The apparatus of claim 14 further comprising:

16. and a third contact coupled between the lower source / drain regions of the first vertical transistor, the second vertical transistor, the third vertical transistor, and the fourth vertical transistor, wherein the first gate, the second gate, the third gate, and the fourth gate include a first gate extension, a second gate extension, a third gate extension, and a fourth gate extension, respectively, each gate extension extending horizontally from its respective gate in the second direction at least some distance, and the device: a first gate via coupled between the first gate extension and a first signal input route of the signal routing in the first metal layer, the first gate via being the at least one gate via; a second gate via coupled between the second gate extension and the first signal input route of the signal routing in the first metal layer; a third gate via coupled between the third gate extension and a second signal input route of the signal routing in the first metal layer; a fourth gate via coupled between the fourth gate extension and the second signal input route of the signal routing in the first metal layer; 16. The apparatus of claim 15, further comprising: a contact via coupled between the third contact and the first signal input route.

17. 1. An apparatus comprising: a first vertical transistor formed in a transistor region of the integrated circuit cell structure, the first vertical transistor having a vertically stacked lower source / drain region, a first gate, and an upper source / drain region; a second vertical transistor formed in the transistor region, the second vertical transistor having a lower source / drain region, a second gate, and an upper source / drain region stacked in the vertical direction, the second vertical transistor being parallel to the first vertical transistor along a first horizontal direction, and having at least some spacing in the first direction between the first vertical transistor and the second vertical transistor; a first metal layer positioned in the vertical direction above the transistor region, the first metal layer including parallel signal routing in the first direction; a first gate bridge extending in the first direction across at least some of the spacing between the first vertical transistor and the second vertical transistor, the first gate bridge being coupled between the first gate and the second gate; a first gate via coupled between a first signal input route of the signal routing in the first metal layer and the first gate bridge; a second metal layer positioned in the vertical direction below the transistor region, the second metal layer including parallel power routing in a second direction perpendicular to the first horizontal direction; a third metal layer disposed below the lower source / drain regions and above the second metal layer, the third metal layer including a lower metal contact coupled to the lower source / drain regions; a bottom contact via between the bottom metal contact and the power routing in the second metal layer; a fourth metal layer disposed above the upper source / drain region and below the first metal layer, the fourth metal layer including an upper metal contact coupled to the upper source / drain region, the upper metal contact having a portion extending in the second direction away from the upper source / drain region; a first set of top contact vias coupled between a first signal output route of the signal routing in the first metal layer and the top metal contacts coupled to the first vertical transistor and the second vertical transistor.

18. The bottom contact via is a first set of bottom contact vias coupled between a first power route of the power routing in the second metal layer and a bottom metal contact coupled to the first vertical transistor; 20. The apparatus of claim 17, further comprising: a second set of bottom contact vias coupled between a second power route of the power routing in the second metal layer and a bottom metal contact coupled to the second vertical transistor.

19. 1. An apparatus comprising: a first vertical transistor formed in a transistor region of the integrated circuit cell structure, the first vertical transistor having a vertically stacked lower source / drain region, a first gate, and an upper source / drain region; a second vertical transistor formed in the transistor region, the second vertical transistor having a lower source / drain region, a second gate, and an upper source / drain region stacked in the vertical direction, the second vertical transistor being parallel to the first vertical transistor along a first horizontal direction, and having at least some spacing in the first direction between the first vertical transistor and the second vertical transistor; a third vertical transistor formed in the transistor region, the third vertical transistor having a lower source / drain region, a third gate, and an upper source / drain region stacked in the vertical direction, the third vertical transistor being parallel to the first vertical transistor along a second direction perpendicular to the first horizontal direction, and having at least some spacing in the second direction between the first vertical transistor and the third vertical transistor; a fourth vertical transistor formed in the transistor region, the fourth vertical transistor having a lower source / drain region, a fourth gate, and an upper source / drain region stacked in the vertical direction, the fourth vertical transistor being parallel to the third vertical transistor along the first direction, with at least some spacing between the third vertical transistor and the fourth vertical transistor in the first direction, and the fourth vertical transistor being parallel to the second vertical transistor along the second direction, with at least some spacing between the second vertical transistor and the fourth vertical transistor in the second direction; a first metal layer positioned in the vertical direction above the transistor region, the first metal layer including parallel signal routing in the first direction; a first gate bridge extending in the first direction across at least some of the spacing between the first vertical transistor and the second vertical transistor, the first gate bridge being coupled between the first gate and the second gate; a second gate bridge extending in the first direction across at least some of the spacing between the third vertical transistor and the fourth vertical transistor, the second gate bridge being coupled between the third gate and the fourth gate; a first gate via coupled between a first signal input route of the signal routing in the first metal layer and the first gate bridge; a second gate via coupled between a second signal input route of the signal routing in the first metal layer and the second gate bridge; a second metal layer positioned in the vertical direction below the transistor region, the second metal layer including parallel power routing in a second direction perpendicular to the first horizontal direction; a third metal layer disposed below the lower source / drain region and above the second metal layer, a first lower metal contact coupled to the lower source / drain region of the first vertical transistor; a second lower metal contact coupled to the lower source / drain region of the second vertical transistor; a third lower metal contact coupled to the lower source / drain region of the third vertical transistor; and a third metal layer including a fourth lower metal contact coupled to the lower source / drain region of the fourth vertical transistor, the fourth lower metal contact including a metal extension extending from the lower source / drain region toward a boundary of the integrated circuit cell in the second direction; a fourth metal layer disposed above the upper source / drain regions and below the first metal layer, a first upper contact coupled between the upper source / drain region of the first transistor and the upper source / drain region of the third transistor, the first upper contact having a portion extending in the second direction beyond the upper source / drain region of the third transistor; and a fourth metal layer including a second top contact in the fourth metal layer, the second top contact coupled between the upper source / drain region of the second transistor and the upper source / drain region of the fourth transistor; a first contact via coupled between the portion of the first upper contact that extends in the second direction beyond the upper source / drain region of the third transistor and a signal output route of the signal routing in the first metal layer; a second contact via coupled between the metal extension portion of the fourth lower metal contact and the signal output route.

20. a first vertical transistor formed in a transistor region of the integrated circuit cell structure, the first vertical transistor having a vertically stacked lower source / drain region, a first gate, and an upper source / drain region; a second vertical transistor formed in the transistor region, the second vertical transistor having a lower source / drain region, a second gate, and an upper source / drain region stacked in the vertical direction, the second vertical transistor being parallel to the first vertical transistor along a first horizontal direction, and having at least some spacing in the first direction between the first vertical transistor and the second vertical transistor; a third vertical transistor formed in the transistor region, the third vertical transistor having a lower source / drain region, a third gate, and an upper source / drain region stacked in the vertical direction, the third vertical transistor being parallel to the first vertical transistor along a second direction perpendicular to the first horizontal direction, and having at least some spacing in the second direction between the first vertical transistor and the third vertical transistor; a fourth vertical transistor formed in the transistor region, the fourth vertical transistor having a lower source / drain region, a fourth gate, and an upper source / drain region stacked in the vertical direction, the fourth vertical transistor being parallel to the third vertical transistor along the first direction, with at least some spacing between the third vertical transistor and the fourth vertical transistor in the first direction, and the fourth vertical transistor being parallel to the second vertical transistor along the second direction, with at least some spacing between the second vertical transistor and the fourth vertical transistor in the second direction; a first metal layer positioned in the vertical direction above the transistor region, the first metal layer including parallel signal routing in the first direction; a second metal layer positioned in the vertical direction below the transistor region, the second metal layer including parallel power routing in a second direction perpendicular to the first horizontal direction; a third metal layer disposed below the lower source / drain regions and above the second metal layer, the third metal layer including lower metal contacts coupled between the lower source / drain regions of the first vertical transistor, the second vertical transistor, the third vertical transistor, and the fourth vertical transistor; a fourth metal layer disposed above the upper source / drain regions and below the first metal layer, a first upper contact coupled between the upper source / drain region of the first transistor and the upper source / drain region of the second transistor; and a fourth metal layer including a second upper contact coupled between the upper source / drain region of the third transistor and the upper source / drain region of the fourth transistor; a first gate extension extending horizontally from the first gate in the second direction at least some distance; a second gate extension extending horizontally from the second gate in the second direction at least some distance; a third gate extension extending horizontally from the third gate in the second direction at least some distance; a fourth gate extension extending horizontally from the fourth gate in the second direction at least some distance; a first gate via coupled between the first gate extension and a first signal input route of the signal routing in the first metal layer; a second gate via coupled between the second gate extension and the first signal input route of the signal routing in the first metal layer; a third gate via coupled between the third gate extension and a second signal input route of the signal routing in the first metal layer; a fourth gate via coupled between the fourth gate extension and the second signal input route of the signal routing in the first metal layer; a contact via coupled between the bottom metal contact and the first signal input route.

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