Multistate ferroelectric RAM with stacked capacitors.

Abstract

The memory device includes a substrate and vertically stacked ferroelectric capacitors formed on the substrate. A first ferroelectric capacitor has a different capacitance output than a second ferroelectric capacitor when a certain voltage is applied. First and second electrodes are in electrical contact with the vertically stacked ferroelectric capacitors. In some cases, a first capacitor plate in the first ferroelectric capacitor and a second capacitor plate in the second ferroelectric capacitor have different thicknesses. The different thicknesses enable the capacitance output of each capacitor to generate different electric field outputs. Accordingly, different output signal combinations can be generated based on the different threshold voltage levels of each capacitor contributing to the output.

Description

[Technical Field]

[0001] The present disclosure relates generally to electrical devices, and more particularly to multi-state ferroelectric RAM devices with stacked capacitors. 2. Description of Related Art

[0002] Ferroelectric RAM (FRAM) is a random access memory similar in construction to DRAM, but using a ferroelectric layer instead of a dielectric layer. FRAM typically uses two terminals with an intermediate element. For example, a typical FRAM includes a top electrode, a bottom electrode, and a ferroelectric film disposed between these vertically arranged electrodes. Information within the device is typically stored in the ferroelectric film. Output from the ferroelectric material can be coded based on the properties of the ferroelectric film used. Summary of the Invention

[0003] According to one embodiment of the present disclosure, a memory device is provided. The memory device includes a substrate on which vertically stacked ferroelectric capacitors are formed. A first ferroelectric capacitor has a different capacitive output than a second ferroelectric capacitor when a voltage is applied. First and second electrodes are in electrical contact with the vertically stacked ferroelectric capacitors.

[0004] In one embodiment, the first capacitor plate in the first ferroelectric capacitor and the second capacitor plate in the second ferroelectric capacitor have different thicknesses. As can be appreciated, the different thicknesses enable the capacitive output of each capacitor to generate different electric field outputs. Correspondingly, different output signal combinations can be generated based on the different threshold voltage levels of each capacitor contributing to the output.

[0005] According to one embodiment of the present disclosure, a programmable memory device is provided. The memory device includes a plurality of ferroelectric capacitor plate pairs stacked in layers. A thickness of a first capacitor plate is different from a thickness of a second capacitor plate. An isolation layer is disposed between the stacked ferroelectric capacitor plate pairs. First and second electrodes contact the ferroelectric capacitor plate pairs. As can be understood, "stacking" refers to the process of stacking a plurality of ferroelectric capacitor plate pairs.

[0006] In one embodiment, consistent with the preceding embodiment, a first electrode surrounds the dielectric mandrel and contacts a first surface of the plurality of ferroelectric capacitor plate pairs. A second electrode contacts a second surface of the plurality of ferroelectric capacitor plate pairs. As can be appreciated, by forming the electrode contacts as described, multiple memory cell units can be formed adjacent to each other, since the second electrode can be shared between two memory cells. In this manner, more programmable devices can occupy a smaller footprint on the chip.

[0007] According to one embodiment, a manufacturing method includes forming a stack of sheets on a substrate. The stack includes alternating layers of a first material and suspension layers of a second material. A plurality of fin structures are formed on the stack of sheets. Shallow trench isolation structures are formed between the fin structures and into the stack of sheets. Dummy electrode placeholders are formed. Sheets of the first material are removed. Dielectric mandrels are formed in the removed areas of the first material. The suspension layers are recessed to form capacitor cavities. Each layer is recessed inward by a different amount. The capacitor cavities are filled with a ferroelectric material. The ferroelectric material has a different thickness at each level of the dielectric mandrel. The dummy electrode placeholders and suspension layers are selectively removed, leaving an empty space. A first electrode is formed in the empty space. The first electrode contacts a first surface of the ferroelectric material at each level of the dielectric mandrel. A second electrode is formed outside the dielectric mandrel. A second electrode contacts the second surface of the ferroelectric material at each level of the dielectric mandrel.

[0008] In one embodiment, consistent with the preceding embodiment, the method further comprises forming an isolation layer disposed over the substrate and beneath the plurality of vertically stacked ferroelectric capacitors, the isolation layer preventing parasitic leakage between electrodes through the substrate that could cause short circuits.

[0009] In general, it should be further understood that the above embodiments provide devices that offer multiple memory states for programming, in some embodiments exceeding the two memory states (0 and 1 states) of a binary device. In this sense, the device is a multistate memory device. While the below embodiments illustrate examples of multistate memory that can be realized with three capacitors per cell, it is understood that additional layers of capacitors may be included that increase the potential combinations of outputs for programming beyond those described in the below examples. Accordingly, devices of the subject technology can be produced that range from one capacitor to n capacitors (n is an integer) to increase the number of states available for programming. Furthermore, the use of ferroelectric-based capacitors makes the device nonvolatile, which is useful for speeding up the startup of computing devices. Ferroelectric capacitors are also power-efficient and easy to program.

[0010] The techniques described herein may be implemented in a number of ways. Example implementations are provided below with reference to the following figures: [Brief explanation of the drawings]

[0011] The drawings are of exemplary embodiments. The drawings do not depict every embodiment. Other embodiments may be used in addition or instead. Details that may be obvious or unnecessary may be omitted to save space or for a more effective illustration. Some embodiments may be practiced with additional components or steps and / or without all of the components or steps shown. When the same numeral appears in different drawings, it refers to the same or similar components or steps.

[0012] [Figure 1] 1 is a diagram of a cross-sectional view of a ferroelectric memory device according to one embodiment of the present disclosure.

[0013] [Figure 2]2A-2D are partial views of the memory device of FIG. 1 shown in a series of states consistent with an embodiment of the present disclosure.

[0014] [Figure 3] 19A / 19B / 19C / 19D. FIG. 19A is a legend illustrating the projection axes of viewpoints for FIGS. 4A / 4B / 4C / 4D through 19A / 19B / 19C / 19D, consistent with an embodiment of the present disclosure.

[0015] [Figure 4] 4A-4D are cross-sectional views of a substrate during an early portion of a process for fabricating a ferroelectric memory device according to one embodiment.

[0016] [Figure 5] 5A-5D show diagrams of forming epitaxial growth of a placeholder and suspension layer according to one embodiment.

[0017] [Figure 6] 6A-6D illustrate the formation of fins for a multi-state device structure according to one embodiment.

[0018] [Figure 7] 7A-7D illustrate the formation of a dummy oxide layer and placeholders for electrode regions according to one embodiment.

[0019] [Figure 8] 8A-8D show diagrams of selective removal of an isolation placeholder layer according to one embodiment.

[0020] [Figure 9] 9A-9D show diagrams of forming electrode spacers and isolation layers according to one embodiment.

[0021] [Figure 10] 10A-10D illustrate the formation of trench areas between fins according to one embodiment.

[0022] [Figure 11] 11A-11D illustrate the selective removal of a dielectric placeholder layer according to one embodiment.

[0023] [Figure 12] 12A-12D illustrate the deposition of silicon nitride in the open spaces separating one ferroelectric layer from another, according to one embodiment.

[0024] [Figure 13] 13A-13D show diagrams of recessing the suspension material according to one embodiment.

[0025] [Figure 14] 14A-14D illustrate the formation of a ferroelectric contact plate in the recess of FIGS. 13A-13D, according to one embodiment.

[0026] [Figure 15] 15A-15D illustrate filling a space with an interlevel dielectric followed by planarization according to one embodiment.

[0027] [Figure 16] 16A-16D illustrate the selective removal of dummy electrodes and suspension layers according to one embodiment.

[0028] [Figure 17] 17A-17D illustrate forming a first electrode in the electrode region and in the area of ​​the removed suspension layer, according to one embodiment.

[0029] [Figure 18] 18A-18D show diagrams of forming a second electrode in contact with the outer surface of the ferroelectric plate, according to one embodiment.

[0030] [Figure 19] 19A-19D illustrate the formation of a middle-of-line metal contact according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0031] overview Generally, embodiments of the present disclosure provide a stacked multi-state ferroelectric RAM device that uses vertically stacked capacitors with plates of different thicknesses. The different plate thicknesses allow for the design of different states for the output from the device, enabling increased programming flexibility compared to traditional binary memories.

[0032] In the following detailed description, by way of example, numerous specific details are set forth in order to provide a thorough understanding of the relevant teachings. However, it should be apparent that the present teachings may be practiced without such details. In other instances, well-known methods, procedures, components, and / or circuits have been described in relatively broad terms, without detail, in order to avoid unnecessarily obscuring aspects of the present teachings.

[0033] In one aspect, spatial terms such as "front," "rear," "top," "bottom," "lower," "belower," "upper," "side," "left," "right," etc. are used with reference to the orientation of the figures being described. Because components of embodiments of the present disclosure can be positioned in multiple different orientations, the directional terms are used for illustrative purposes and are in no way limiting. As such, it is understood that spatial terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures were inverted, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, for example, the term "below" can encompass both an orientation of above and below. A device may be oriented differently (rotated 90 degrees or viewed or referred to in other directions), and therefore spatial descriptors used herein should be interpreted accordingly.

[0034] As used herein, the terms "lateral," "planar," and "horizontal" describe an orientation parallel to a first surface of a chip or substrate. In this disclosure, the "first surface" may be the top layer of a semiconductor device where individual circuit devices are patterned in the semiconductor material.

[0035] As used herein, the term "vertical" describes an orientation that is disposed perpendicular to the first surface of a chip, chip carrier, chip substrate, or semiconductor body.

[0036] As used herein, the terms "coupled" and / or "electrically coupled" are not intended to imply that elements must be directly coupled together -- intervening elements may be provided between elements that are "coupled" or "electrically coupled." In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. The term "electrically connected" refers to a low resistance electrical connection between elements that are electrically connected together.

[0037] Terms such as "first," "second," etc. may be used herein to describe various elements, and these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the exemplary embodiments. Describing an element as "first" or "second," etc., does not necessarily imply an order or priority for any of the elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0038] Exemplary embodiments are described herein with reference to cross-sectional views that are schematic illustrations of idealized or simplified embodiments (and intermediate structures). As such, variations from the shapes of the illustrations due, for example, to manufacturing techniques and / or tolerances, are to be expected. Accordingly, the regions illustrated in the figures are schematic in nature, and their shapes do not necessarily depict the actual shapes of regions of a device and are not limiting in scope. It should be understood that the figures and / or drawings accompanying this disclosure are illustrative, non-limiting, and not necessarily drawn to scale.

[0039] It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope as defined by the claims. The description of the embodiments is not intended to be limiting. In particular, elements of the embodiments described below may be combined with elements of different embodiments. Device Structure

[0040] FIG. 1 illustrates a stacked multistate ferroelectric RAM device 100 (sometimes referred to collectively as "device 100"). Device 100 is a multistate type memory device. Generally, device 100 comprises stacked levels of electrodes 180 and ferroelectric capacitor plates 130 (sometimes referred to collectively as "capacitors 130"). Device 100 comprises a plurality of FRAM units 150 (the process for fabricating which is described below in FIGS. 3 through 19A-19D). Memory cells 155 are formed from an electrode 180 to an adjacent electrode 120. As can be seen in FIG. 1, electrode 180 may be shared by two adjacent electrodes 120. Each memory cell 155 may have three ferroelectric layers (the ferroelectric layers include capacitors 130 and electrodes 180). As will be appreciated, some embodiments may have fewer or more layers than shown. Depending on how a voltage is applied between electrode 180 and electrode 120, the first, second, or third ferroelectric layer is selectively polarized.

[0041] Other features shown in FIG. 1 that will be described below in the fabrication of device 100 may include, for example, substrate 110, dielectric 105 at the top of the device, isolation layer 112 that isolates memory cell 155 from substrate 110 (and from any structure below substrate 110) (also eliminating the risk of parasitic leakage between electrodes 120 and 180 through substrate 110), metal contact 125 that connects electrode 120 to a middle-of-line connection, dielectric mandrel layer 160 that isolates ferroelectric layers from each other, spacer 170 that isolates electrode 120 from electrode 180, and cap 190 that protects electrode 180 in the first electrode region of the device.

[0042] Referring now to Figures 2A-2D, partial views of the FRAM unit 150 from Figure 1 are shown in different states. Each ferroelectric layer has capacitor plates 130 of different horizontal thicknesses (or widths). The thickness of the plates affects the ferroelectric field output from the capacitor 130. Application of an electric field to the layer inherently generates spontaneous electric polarization in the crystalline structure of the ferroelectric material. The ferroelectric layer may exhibit two stable polarization states with hysteresis behavior. A given ferroelectric material exhibits a given electric field threshold above which the electric field causes polarization reversal. Furthermore, the polarization does not disappear even when the electric field is removed. The electric field generated by applying a voltage between the two electrodes of the memory cell is used to program the device. The electric field E of the capacitor is controlled by Equation 1:

[0043]

number

[0044] For a capacitor medium of thickness d at a constant voltage:

[0045] d1 <d2<d3であれば、

number

[0046] In relation to the above, assuming a constant applied voltage, the resulting applied electric field in a ferroelectric capacitor increases as the capacitor thickness decreases from the bottom ferroelectric layer to the top ferroelectric layer. Figures 2A-2D show capacitors 130a, 130b, and 130c. Capacitor 130a (the top capacitor) has the shortest thickness d. Capacitor 130b (the intermediate capacitor) has a thickness d greater than that of capacitor 130a but less than that of capacitor 130c (the bottom capacitor). During programming of a given memory cell 155 (Figure 1), capacitors that experience an applied electric field that exceeds the threshold electric field of the ferroelectric material will reverse their polarization. Information for programming can be encoded in capacitors that retain information when in a polarization-reversed state. However, capacitors that experience an applied electric field that is below the threshold electric field of the ferroelectric material will not reverse their polarization. Information will not be retained in these capacitors. Thus, it is possible to selectively program individual capacitors within a given memory cell through gradually increasing voltages applied between the first and second electrodes leading to the multi-state memory cell.

[0047] Figure 2A shows the V BL2B shows an example State 0 where V = 0V. In State 0, the direction of polarization in the ferroelectric layer assumes the same orientation (indicated by the arrows in capacitor 130), for example, after resetting the memory cell. "State 0" may be the starting state. In FIG. 2B, a voltage is applied in State 1 (V = V1). V1 exceeds the threshold electric field of the ferroelectric material, thereby creating an applied electric field sufficient to trigger polarization reversal in the first capacitor 130a. The ferroelectric electric field in the first capacitor 130a reverses. Because the threshold electric field for the other two capacitors (130b and 130c) has not been reached, their spontaneous polarizations remain unchanged. This polarization configuration defines "State 1." FIG. 2C shows the voltage increased to V2 such that V2 > V1. Voltage V2 exceeds the threshold electric field of the ferroelectric material, thereby creating an applied electric field sufficient to trigger polarization reversal in the second capacitor 130b. This polarization configuration defines "State 2." Because the threshold electric field for the third capacitor 130c has not been reached, its spontaneous polarization remains unchanged. Figure 2D shows the voltage increased to V3 such that V3 > V2 > V1, which exceeds the threshold electric field of the ferroelectric material and thus creates an applied electric field sufficient to trigger polarization reversal in the third capacitor 130c. As can be seen, the polarization directions of all three capacitors 130a, 130b, and 130c have reversed for all three capacitors. This polarization configuration defines "State 3." During device programming, a read function may read the net electric fields resulting from the different states of the capacitors 130. The memory cell may be programmed using an applied voltage step function calibrated to provide gradual control of each individual capacitor within the memory cell. Accordingly, the above structure provides more than two memory states, making it a multistate memory cell.

[0048] As will be appreciated, while the construction cost of FRAM can be similar to that of DRAM, FRAM has several advantages over DRAM. For example, the ferroelectric material is non-volatile so that information is not lost when power is removed from the device. Furthermore, the programming time for FRAM is shorter than other devices, including DRAM. FRAM is more power efficient. The above advantages make FRAM an alternative to flash-based devices. Exemplary Methods of Manufacture

[0049] By way of example, reference is now made beginning with FIG. 3 to describe a method for fabricating a stacked multistate ferroelectric RAM device. FIGS. 4A-4D through 19A-19D illustrate a fabrication process that includes additive and subtractive processes to form several circuit elements in the final device. The additive and subtractive processes involved (e.g., masking, deposition, etching, lithography, etc.) may be known to those skilled in the art and are not necessarily specified in each operation shown. Fabrication of the devices described herein may include multi-step sequences of photolithography and / or chemical processing steps that facilitate the incremental creation of electronic-based systems, devices, components, and / or circuits in, for example, semiconductor and / or superconducting devices (e.g., integrated circuits).For example, the device may be fabricated using techniques including, but not limited to, photolithography, microlithography, nanolithography, nanoimprint lithography, photomasking techniques, patterning techniques, photoresist techniques (e.g., positive-tone photoresist, negative-tone photoresist, hybrid-tone photoresist, and / or other photoresist techniques), etching techniques (e.g., reactive ion etching (RIE), dry etching, wet etching, ion beam etching, plasma etching, laser ablation, and / or other etching techniques), evaporation techniques, sputtering techniques, plasma ashing techniques, thermal treatments (e.g., rapid thermal annealing, furnace annealing, thermal oxidation, and / or other thermal treatments), chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), electrochemical deposition (ECD), chemical-mechanical planarization (CMP), and the like. The steps may be fabricated on one or more substrates (e.g., silicon (Si) substrates and / or other substrates) by utilizing techniques including planarization, back-grinding techniques, and / or other techniques for fabricating integrated circuits. In some figures, some reference numerals for elements not affected by a step may not be repeated.

[0050] The following figures are shown along four perspectives: one from the electrode cross-perspective across the fin (X-axis), one from the fin cross-perspective across the fin (Y1-axis), one from the spacer cross-perspective across the fin (Y2-axis), and one from the second electrode cross-perspective across the fin (Y3-axis). Figure 3 shows a legend providing the axes of the perspective views. Figures 4A / 4B / 4C / 4D through 19A / 19B / 19C / 19D should be viewed while constantly referring back to Figure 3 to recall the perspective views shown. Alternatively, it can be recalled that each "A" view is shown along the X-axis perspective, each "B" view is shown along the Y1-axis perspective, each "C" view is shown along the Y2-axis perspective, and each "D" view is shown along the Y3-axis perspective.

[0051] 4A-4D, an initial portion of the process illustrates a substrate 110 used to form the base of a device during fabrication. The substrate 110 may be a semiconductor, typically comprising silicon. FIGS. 5A-5D illustrate the formation of a nanosheet stack using an epitaxial growth process, forming alternating layers of two different material types over the substrate 110. The two different material types may include suspension material layers 114, 115, and 116 formed between a sacrificial silicon layer 110. The suspension material layers 114, 115, and 116 are placeholders for stacked electrodes 180 (see FIG. 1) that will form part of the ferroelectric capacitor in the final device. The sacrificial silicon layer 110 replaces a dielectric mandrel.

[0052] Suspension layers 114, 115, and 116 may be composed of silicon germanium with different Ge concentrations. The concentration of germanium in the suspension layers determines the final thickness of the ferroelectric capacitor and the width of the first electrode in that particular layer. In one embodiment, the suspension layers may be arranged with decreasing concentrations of germanium such that the resulting electrode 180 is widest at the top electrode and shortest at the bottom electrode. (See again FIG. 1 for the resulting electrode structure in the capacitor area, showing electrodes with decreasing widths from top to bottom.)

[0053] The bottom layer 118 may be a sacrificial layer having the highest germanium concentration (e.g., 75%) and may be grown directly on the substrate 110. Layer 118 may be a placeholder for the formation of a bottom isolation layer, described further below. A suspension layer 116 may be grown directly on top of layer 118. The suspension layer 116 may have the next highest germanium concentration (45%). A sacrificial layer 110 of silicon may be grown on top of layer 116, and a suspension layer 114 may be grown on the sacrificial layer of silicon. The suspension layer 114 may have a germanium concentration of 30%. A sacrificial layer 110 of silicon may be grown on the suspension layer 114. A suspension layer 115 may be grown on the sacrificial layer 110. The suspension layer 115 may have a germanium concentration of 15%. Another sacrificial layer 110 of silicon may be grown over the suspension layer 115. While three suspension layers (114, 115, and 116) and three silicon sacrificial layers are shown, it is understood that more layers (or fewer in some embodiments) may be included. Additionally, while decreasing concentrations of germanium for the suspension layers are shown, configurations may use increasing concentrations to form electrodes with smaller widths at the top and larger widths at the bottom. Additionally, the amount of germanium concentration may vary depending on the desired edge width for the electrode.

[0054] 6A-6D illustrate the formation of fins and the deposition of shallow trench isolation (STI) layer 112. A hard mask (not shown) may be used to pattern the fin and trench structures. STI layer 112 material may be used to fill back the etched-away portions of substrate 110 between the fins. In some embodiments, the upper edge of STI layer 112 is aligned with or below the bottom surface of sacrificial layer 118.

[0055] 7A-7D illustrate the formation of a dummy oxide layer 126 and a dummy electrode placeholder material 188. The dummy oxide layer 126 may be conformally deposited on the fin structure. The dummy electrode placeholder material 188 may be deposited and planarized on the dummy oxide layer 126. The dummy electrode placeholder material 188 may be, for example, amorphous or polycrystalline silicon. A hard mask 198 may be disposed over the dummy electrode placeholder material 188 and the dummy oxide layer 126. The resulting pattern may be transferred downward into the dummy electrode placeholder material 188 and the dummy oxide layer 126 to provide the resulting structure shown.

[0056] 8A-8D illustrate the selective removal of sacrificial layer 118. Removal may be performed by conformal dry or wet etching techniques, including, for example, dry gas phase etching. Figure 8B illustrates the surrounding support structure after layer 118 has been removed (compared to other figures, where the overlying stack may appear as if it is floating).

[0057] 9A-9D illustrate the conformal deposition of a low-k dielectric 170. The dielectric material 170 may cover the fins, the sides of the dummy electrodes, and may fill the space left by the removal of the sacrificial layer 118. The layer of dielectric material 170 between the substrate 110 and the suspension layer 116 may serve as a bottom isolation layer insulating the ferroelectric memory cells from the substrate 110. The layer of dielectric material 170 on the sides of the dummy electrodes serves as an electrically insulating spacer between adjacent first and second electrodes. The electrode spacers are formed, for example, by performing an anisotropic etch-back to remove the dielectric material from horizontal surfaces after the conformal deposition of the dielectric material 170, including the top of the dummy electrodes (which expose the hard mask layer 198) and the trench areas on and between the sides of the fins.

[0058] 10A-10D illustrate the execution of an anisotropic directional fin recess process. Referring specifically to FIG. 10A, the material in the stack of alternating layers is recessed down to the isolation layer of material 170, thereby extending the trenches between the fin structures. FIG. 10D shows the fin stack protrusions 172 in the dummy electrode regions that have not been removed by the recess process. FIG. 10C shows the fins in the electrode spacer regions.

[0059] 11A-11D illustrate the selective removal of silicon sacrificial layer 110. The targeted silicon removal may be performed by any number of known commercial conformal etching processes. In suspension regions 114, 115, and 116, a dummy oxide layer 126 protects the dummy electrodes (amorphous silicon) during the etching process.

[0060] 12A-12D show the formation of dielectric mandrels in the ferroelectric capacitor region. In one embodiment, a conformal deposition of a dielectric 160 (e.g., silicon nitride) is used to cover all exposed surfaces, including the dielectric material 160 filling the void spaces left from the silicon removal shown in FIGS. 11A-11D. An isotropic etch-back process may be used to etch back excess dielectric material 160 from areas outside the mandrel locations. FIGS. 12A-12D show the results after the etch-back process.

[0061] 13A-13D illustrate selective recessing of suspension layers 114, 115, and 116. An isotropic dry or wet etching process may be used to remove portions of the suspension layer material from the outside inward. Because suspension layers 114, 115, and 116 have different concentrations of germanium, the chemical etch rate differs for each layer. For example, depending on the etchant used, higher concentrations of germanium may be etched back faster than lower concentrations. Because all layers may be exposed simultaneously, the process removes more material from some suspension layers than others during the exposure time. The amount removed (or the final width of the layer) may be controlled by the exposure time applied to the layer. The spaces defining the recesses for each suspension layer are referred to as capacitor cavities 114e, 115e, and 116e (using the same reference numerals associated with each layer). The depth of the capacitor cavities in each respective suspension layer may be selected based on the desired capacitance contribution and electrical parameters (e.g., programming voltage) for multistate memory cell operation.

[0062] 14A-14D illustrate the formation of capacitors (collectively referred to as "130" in FIG. 1) within the mandrels. The formation involves conformal deposition of ferroelectric material within recesses 114e, 115e, and 116e, followed by an isotropic etch-back. Capacitor 130a contacts the end of suspension layer 115. Capacitor 130b contacts the end of suspension layer 114. Capacitor 130c contacts the end of suspension layer 116. In one embodiment, the ferroelectric material may be deposited using a conformal deposition technique, followed by an isotropic etch process to remove excess material from the remainder of the device structure. As can be seen in FIG. 14A, the ferroelectric material forms two plates, one on each side of each of suspension layers 114, 115, and 116. The plates in each layer are separated by a different distance from the plates in other levels, creating different capacitances at each level of the mandrels.

[0063] 15A-15D show the deposition of interlayer dielectric 105 (e.g., oxide) into the trenches between the fins and around the sides of the fins. Some embodiments may include planarization to remove material from the top of the structure (e.g., including hard mask pattern 198 and part of dielectric 170) down to shallow trench isolation 122.

[0064] 16A-16D show sequential etching of materials. This sequence may include removal of dummy electrode material 188. Dummy oxide layer 126 may be removed. Once dummy oxide layer 126 is removed, suspension layers 114, 115, and 116 may be removed (leaving the cavity free of suspension material).

[0065] 17A-17D illustrate the formation of the first electrode. Metal material may be deposited in the empty areas left from the removal of the dummy electrode material and in the cavities formed from the removal of the suspension layers 114, 115, and 116. The metal wraps around the mandrel area (best shown in FIG. 17B). The metal material area defines the first electrode 180. The metal material contacts each of the capacitors 130. Planarization may be used to flatten the electrode 180 in the electrode area. Some embodiments recess the metal in the electrode area to form a dielectric cap 190 that covers the first electrode 180. The dielectric cap 190 isolates the electrode 180 and protects it from potential electrical shorts when forming an adjacent second electrode.

[0066] 18A-18D illustrate the formation of the second electrode. A metal material, which may be the same material used in the first electrode, is deposited to form the second electrode 120. The second electrode 120 may be formed in the trench and on the sides of the mandrels such that the metal contacts the outer surface of the capacitor 130. The second electrode 120 disposed in the trench may be shared by adjacent capacitors 130 in different mandrels. The shape of the second electrode 120 may be determined by patterned etching (the results of which can be seen, for example, in FIG. 18D). As can be seen, the results shown in FIGS. 18A-18D provide multistate memory cells each comprising stacked ferroelectric capacitors 130 of varying thicknesses.

[0067] 19A-19D illustrate the formation of a middle-of-line contact. A blanket interlayer dielectric 105 may be deposited over the memory cell structure. Patterning may be used to place a metal contact 125 on the second electrode 120. An electrical contact 128 is formed through the interlayer dielectric 105 and a dielectric cap 190 to contact the first electrode 180 and is in a different plane than the metal contact 125. conclusion

[0068] The description of various embodiments of the present teachings has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein have been selected to best explain the principles, practical applications, or technical improvements of the embodiments over art found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0069] While the above describes what is believed to be the best mode and / or alternative examples, it is understood that various modifications may be made therein, that the subject matter disclosed herein may be embodied in various forms and examples, and that the teachings may be applied to many applications, only some of which are described herein. It is intended that the following claims claim any and all applications, modifications, and variations that fall within the true scope of the present teachings.

[0070] The components, steps, features, objects, benefits, and advantages described herein are merely exemplary. Neither they nor the descriptions associated therewith are intended to limit the scope of protection. While various advantages have been described herein, it will be understood that not all embodiments necessarily include all advantages. Unless otherwise stated, all measurements, values, ratings, positions, dimensions, sizes, and other specifications described herein, including the following claims, are approximate and not precise. They are intended to have a reasonable range consistent with the functions to which they pertain and that which is customary in the technical field to which they pertain.

[0071] Many other embodiments are also contemplated, including embodiments having fewer, additional, and / or different components, steps, features, objects, benefits, and advantages, including other embodiments in which the components and / or steps are configured and / or ordered differently.

[0072] While the foregoing has been described in conjunction with exemplary embodiments, it is understood that the term "exemplary" is intended to mean by way of example only, and not best or optimal. Except as noted immediately above, nothing described or illustrated is intended to, or should be construed to, provide to the public any component, step, feature, object, benefit, advantage, or equivalent, whether claimed or not.

[0073] It will be understood that the terms and expressions used herein have the ordinary meanings ascribed to such terms and expressions with respect to their respective fields of inquiry and study, unless a specific meaning is otherwise stated herein. Relationship terms, such as first and second, may be used solely to distinguish one entity or action from another, without necessarily requiring or implying any actual relationship or order between such entities or actions. The terms "comprises," "comprising," or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements does not include only those elements, but may also include other elements not expressly listed or inherent in such process, method, article, or apparatus. An element preceded by "a" or "an" does not, in the absence of further constraints, exclude the presence of additional identical elements in a process, method, article, or apparatus that includes that element.

[0074] An Abstract of the Disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Additionally, in the foregoing Detailed Description, it can be seen that various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments have more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Accordingly, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as separately claimed subject matter.

Claims

1. substrate; a plurality of vertically stacked ferroelectric capacitors formed on the substrate, wherein a first ferroelectric capacitor has a capacitance output in response to an applied constant voltage that is different from that of a second ferroelectric capacitor; a first electrode in electrical contact with the vertically stacked ferroelectric capacitor; and a second electrode in electrical contact with the vertically stacked ferroelectric capacitor; A memory device comprising:

2. 10. The memory device of claim 1, further comprising a first capacitor plate in the first ferroelectric capacitor and a second capacitor plate in the second ferroelectric capacitor, the first capacitor plate having a thickness different from a thickness of the second capacitor plate.

3. a first capacitor plate and a second capacitor plate of the first ferroelectric capacitor; and a third capacitor plate and a fourth capacitor plate of the second ferroelectric capacitor; a distance between the first capacitor plate and the second capacitor plate is different from a distance between the third capacitor plate and the fourth capacitor plate; The memory device of claim 1 .

4. 4. The memory device of claim 3, wherein the distance between the first capacitor plate and the second capacitor plate is greater than the distance between the third capacitor plate and the fourth capacitor plate.

5. The memory device of claim 4 , wherein the first ferroelectric capacitor is disposed above the second ferroelectric capacitor.

6. The memory device of claim 1 further comprising a dielectric mandrel disposed between layers of the vertically stacked ferroelectric capacitors.

7. 7. The memory device of claim 6, wherein the first electrode is wrapped around the dielectric mandrel and contacts a first surface of the ferroelectric capacitor.

8. The memory device of claim 7 , wherein the second electrode contacts a second surface of the ferroelectric capacitor.

9. The memory device of claim 1 , further comprising an isolation layer disposed above said substrate and below said plurality of vertically stacked ferroelectric capacitors.

10. The memory device of claim 9 , wherein the isolation layer extends horizontally beneath the first electrode and beneath the second electrode.

11. 10. The memory device of claim 1, wherein the first ferroelectric capacitor has an applied threshold voltage for polarization reversal that is higher or lower than an applied threshold voltage of the second ferroelectric capacitor.

12. a plurality of ferroelectric capacitor plate pairs stacked in layers, wherein a thickness of a first capacitor plate pair of the plurality of ferroelectric capacitor plate pairs is different from a thickness of a second capacitor plate pair of the plurality of ferroelectric capacitor plate pairs; one or more isolation layers disposed between the plurality of stacked ferroelectric capacitor plate pairs; a first electrode in contact with the plurality of ferroelectric capacitor plate pairs; and a second electrode in contact with the plurality of ferroelectric capacitor plate pairs; A programmable memory device comprising:

13. 13. The programmable memory device of claim 12, wherein a distance between the first pair of capacitor plates is different from a distance between the second pair of capacitor plates.

14. 14. The semiconductor device of claim 13, wherein the distance between the first pair of capacitor plates is greater than the distance between the second pair of capacitor plates.

15. 13. The semiconductor device of claim 12, further comprising a dielectric mandrel disposed between the layers of the ferroelectric capacitor plate pair.

16. 16. The semiconductor device of claim 15, wherein the first electrode is wrapped around the dielectric mandrel and contacts first surfaces of the plurality of ferroelectric capacitor plate pairs.

17. 17. The semiconductor device of claim 16, wherein the second electrode contacts second surfaces of the plurality of ferroelectric capacitor plate pairs.

18. forming a stack of sheets on a substrate, said stack including alternating layers of a first material and suspension layers of a second material; forming a plurality of fin structures on the stack of sheets; forming shallow trench isolation (STI) structures between the fin structures and into the stack of sheets; forming a dummy electrode placeholder; removing said sheet of said first material; forming a dielectric mandrel in the area of ​​the removed first material; recessing the suspension layers to form a capacitor cavity, wherein each layer is recessed inwardly by a different amount; filling the capacitor cavity with a ferroelectric material, wherein the ferroelectric material has a different thickness at each level of the dielectric mandrel; selectively removing the dummy electrode placeholder and the suspension layer to leave an empty space; forming a first electrode in the void space, wherein the first electrode contacts a first surface of the ferroelectric material at each level of the dielectric mandrel; and forming a second electrode on the exterior of the dielectric mandrel, wherein the second electrode contacts a second surface of the ferroelectric material at each level of the dielectric mandrel. A method for manufacturing a memory device comprising:

19. 20. The method of claim 18, further comprising forming an isolation layer disposed above the substrate and below the plurality of vertically stacked ferroelectric capacitors.

20. 20. The method of claim 18, further comprising forming the suspension layer of a second material by including a different concentration of polycrystalline material.

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