Processing method, device, storage medium, and electronic device relating to circuit reliability

Abstract

The present application provides a processing method, device, storage medium, and electronic device related to circuit reliability, the processing method related to circuit reliability including: acquiring a failure rate of each element and a failure coefficient corresponding to each element; determining an expected failure value for each element based on the failure rate and the failure coefficient corresponding to each element; comparing a plurality of expected failure values ​​to determine elements awaiting repair; and reducing the expected failure value of the elements awaiting repair based on the failure coefficient of the elements awaiting repair.

Description

[Technical Field]

[0001] The present application relates to the field of battery technology, and more particularly to a processing method, an apparatus, a storage medium, and an electronic device relating to circuit reliability.

[0002] This application claims priority to Chinese patent applications bearing application numbers 202311231712.X, 202322584916.3, 202322583013.3, and 202311230696.2, filed with the China Patent Office on September 21, 2023, the entire contents of which are incorporated herein by reference. [Background technology]

[0003] In the prior art, insulation testing is an important means to ensure the safe operation of electrical equipment. Summary of the Invention [Problem to be solved by the invention]

[0004] The associated insulation resistance testing circuit does not allow for determining how the circuit should be improved to increase its reliability and reduce the likelihood of failure during operation. [Means for solving the problem]

[0005] In a first aspect, an embodiment of the present application provides a processing method for circuit reliability, the processing method for circuit reliability comprising: Obtaining a failure rate for each element in a given circuit and a failure coefficient corresponding to each said element; determining an expected failure value for each of the elements based on the failure rate of each of the elements and a failure coefficient corresponding to each of the elements; The method includes comparing the plurality of expected failure values ​​to determine elements awaiting repair in the predetermined circuit, and reducing the expected failure value of the elements awaiting repair based on the failure coefficients of the elements awaiting repair.

[0006] In a second aspect, an embodiment of the present application provides a processing device for circuit reliability, the processing device for circuit reliability comprising: A parameter acquisition module is used to acquire the failure rate of each element in a predetermined circuit and the failure coefficient corresponding to each element; a processing module used to determine a failure expectancy for each of the elements based on the failure rate of each of the elements and a failure coefficient corresponding to each of the elements; and an implementation module used to compare a plurality of the failure expectancies to determine elements awaiting repair in a given circuit, and to reduce the failure expectancies of the elements awaiting repair based on the failure coefficients of the elements awaiting repair.

[0007] In a third aspect, an embodiment of the present application provides a storage medium having a computer program stored therein, the computer program, when executed by a computer, causing the computer to perform the processing method relating to circuit reliability described above.

[0008] In a fourth aspect, an embodiment of the present application provides an electronic device, the electronic device including a processor and a memory, a computer program stored in the memory, and the processor performing the processing method related to circuit reliability described above by calling the computer program. [Effects of the Invention]

[0009] The present invention obtains the failure rate of each element in a given circuit and the corresponding failure coefficient, and determines the expected failure value of each element based on the failure rate and the corresponding failure coefficient, thereby quantifying the reliability of the insulation test circuit using a unified calculation method, and determining the elements that need optimization based on the multiple expected failure values, thereby reducing the expected failure value of the elements waiting to be repaired. In this way, by quantifying the reliability of each element in a given circuit, the reliability of each element can be directly reflected by the magnitude of the expected failure value, and by comparing the multiple expected failure values, it is possible to determine which elements in the given circuit mainly affect the reliability of the given circuit, apply the repairs to the specific elements, and ultimately determine the direction of the repairs to the given circuit more directly and simply, thereby achieving the effect of higher reliability when the repaired circuit is operational. This solves the technical problem of not being able to quantify the reliability of the insulation test circuit and not being able to determine how to repair the circuit to improve its reliability. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a flowchart 1 showing a processing method for circuit reliability provided in an embodiment of the present application. [Figure 2] 1 is a flowchart 1 showing step S100 provided in an embodiment of the present application. [Figure 3] 1 is a flowchart 1 showing an embodiment of step S300 provided in the embodiment of the present application. [Figure 4] 10 is a flowchart illustrating step S320 provided in an embodiment of the present application. [Figure 5] 2 is a flowchart 2 showing step S300 provided in an embodiment of the present application. [Figure 6] 2 is a flowchart 2 illustrating a processing method for circuit reliability provided in an embodiment of the present application. [Figure 7] 1 is a circuit connection diagram 1 according to a specific circuit provided in an embodiment of the present application. [Figure 8]1 is a modified circuit diagram provided in an embodiment of the present application. [Figure 9] 3 is a flowchart 3 illustrating a processing method for circuit reliability provided in an embodiment of the present application. [Figure 10] 2 is a flowchart 2 showing step S1000 provided in an embodiment of the present application. [Figure 11] 3 is a flowchart 3 showing step S3000 provided in an embodiment of the present application. [Figure 12] 4 is a flowchart 4 showing a processing method for circuit reliability provided in an embodiment of the present application. [Figure 13] 6 is a flowchart illustrating step S6000 provided in an embodiment of the present application. [Figure 14] 6 is a flowchart illustrating step S6200 provided in an embodiment of the present application. [Figure 15] 5 is a flowchart 5 illustrating a processing method for circuit reliability provided in an embodiment of the present application. [Figure 16] FIG. 2 is a circuit connection diagram 2 according to a specific circuit provided in an embodiment of the present application. [Figure 17] 2 is a modified circuit diagram provided in an embodiment of the present application. [Figure 18] FIG. 2 is a block diagram of a processing device for circuit reliability provided in an embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0011] In the present description, unless otherwise expressly specified or limited, the terms "connected to each other," "connected," and "fixed" are to be understood in a broad sense. For example, they may refer to a fixed connection, a detachable connection, an integral connection, a mechanical connection, an electrical connection, a direct connection, an indirect connection via an intermediate medium, an internal communication between two elements, or an interaction between two elements. Those skilled in the art may understand the specific meaning of the above terms in the present application depending on the particular situation.

[0012] In this application, unless expressly specified or limited, a first feature being "above" or "below" a second feature may include the first feature being in direct contact with the second feature, or the first feature being in contact with the second feature but not directly but via another feature therebetween. Furthermore, a first feature being "above," "above," or "on the upper surface" of a second feature means that the first feature is directly above or diagonally above the second feature, or that the first feature is higher than the second feature in the horizontal direction, etc. A first feature being "below," "below," or "on the lower surface" of a second feature means that the first feature is directly below or diagonally below the second feature, or that the first feature is lower than the second feature in the horizontal direction, etc.

[0013] In the description of the present embodiment, terms relating to orientations or positional relationships, such as "upper," "lower," "left," "right," "front," and "rear," are based on the orientations or positional relationships shown in the drawings and are intended to simplify the description and operation, and should not be construed as limiting the present application, as they do not indicate or suggest devices or elements having a specific orientation, configuration, or operation in a specific orientation. Furthermore, the terms "first" and "second" are used to distinguish between the above and other terms in the description, and do not have any special meaning.

[0014] The present embodiment provides a method for processing circuit reliability.

[0015] A failure rate for each element in a given circuit and a failure coefficient corresponding to each said element are obtained.

[0016] An expected failure value for each of the elements is determined based on the failure rate of each of the elements and the failure coefficient corresponding to each of the elements.

[0017] A plurality of the failure expectancies are compared to determine elements in the predetermined circuit that are to be repaired, and the failure expectancy of the elements that are to be repaired is reduced based on the failure coefficients of the elements that are to be repaired.

[0018] Referring to FIG. 1, in some embodiments, a processing method for circuit reliability includes the following steps.

[0019] In S100, the failure rate of each first element in a predetermined circuit and the failure coefficient corresponding to each of the first elements are obtained.

[0020] In some embodiments, the predetermined circuit is a circuit waiting to be processed, input by a user via a device such as a PC, and the first element is an initial element in the predetermined circuit, i.e., an element that has not been replaced.

[0021] The failure rate is obtained by the processing equipment based on an existing component failure rate standard. In some embodiments, the standard adopted is standard SN29500. In other cases, other component failure rate standards, such as IEC62380, may be adopted according to actual needs. The failure coefficient is the proportion of possible failure conditions of each first component to all failure conditions. For example, for a switching transistor, all of its failure conditions include parameter shift, short circuit, and open circuit. However, when the switching transistor is turned off, the possible failure conditions include parameter shift and short circuit. At this time, the failure coefficient of the switching transistor is the sum of the probability of both parameter shift and short circuit occurring.

[0022] When a user wants to optimize the reliability of a first insulation test circuit, he or she must first determine the required element failure rate standard, and then determine the failure rate of each first element in the existing first insulation test circuit according to the standard. For example, when calculating the failure rates of the switching transistor and resistor according to the standard SN29500, the failure rate of the switching transistor is 40 FIT, and the failure rate of the resistor is 1.26 FIT. The total probability of the target failure scenario that can occur for each first element is determined, and the failure scenario parameters of the first elements are calculated.

[0023] In S200, a failure expectancy of each of the first elements is determined based on the failure rate of each of the first elements and the failure coefficient corresponding to each of the first elements.

[0024] In some embodiments, the failure expectancy is the proportion of the failure status of each element to the failure status of the entire circuit. Take FIG. 7 as an example. A given circuit is shown in FIG. 7. The failure expectancy of the first switching transistor K1 in FIG. 7 is expressed as follows: P K1_1 =a*F K1 / (F R1 +F R2 +a*F K1 +b*F K2 ) where a is the failure factor of the first switching transistor K1, b is the failure factor of the second switching transistor K2, and F R1 is the failure rate of the first resistor R1, and F R2 is the failure rate of the second resistor R2, and F K1 is the failure rate of the first switching transistor K1, and F K2 is the failure rate of the second switching transistor K2, (F R1 +F R2 +a*F K1 +b*F K2 ) is the target fault condition of the total circuit.

[0025] In S300, a plurality of expected failure values ​​are compared to determine a first element awaiting correction in a specified circuit as a target first element, and the target first element is the element awaiting correction, and the first element is replaced with a second element based on the failure coefficient of the target first element.

[0026] The circuit in which the first element is replaced with the second element includes a first insulation inspection circuit, and the first insulation inspection circuit includes: a first resistor R1 and a second resistor R2, wherein a first terminal of the first resistor R1 is connected to a first terminal of a ground resistor Rx of a positive bus, a second terminal of the first resistor R1 is connected to a first terminal of the second resistor R2, and a second terminal of the second resistor R2 is connected to a first terminal of a ground resistor Ry of a negative bus; a third resistor R3, a first terminal of which is electrically connected to a first terminal of a ground resistor Rx of a positive bus and a first terminal of the first resistor R1, and a second terminal of which is electrically connected to a second terminal of the first resistor R1 and a first terminal of the second resistor R2, respectively; a first switching transistor K1 and a second switching transistor K2, wherein a first terminal of the second switching transistor K2 is connected to the second terminal of the third resistor R3, a second terminal of the second switching transistor K2 is connected to the first terminal of the first switching transistor K1, the second terminal of the first resistor R1, and the first terminal of the second resistor R2, respectively, and the second terminal of the first switching transistor K1 is grounded.

[0027] When the first insulation inspection circuit is in a first operating state, the first switching transistor K1 is turned on and the second switching transistor K2 is turned off, and when the first insulation inspection circuit is in a second operating state, both the first switching transistor K1 and the second switching transistor K2 are turned on.

[0028] The first switching transistor K1 and the second switching transistor K2 are relays.

[0029] Here, the failure coefficients of the second element and the first element are different.

[0030] The circuit failure rate is primarily determined by the number of elements, their inherent failure rate, failure mode, and circuit architecture. Elements with the same function may experience different failure scenarios depending on the element type. For example, consider a reference ambient temperature of 40°C, single point failures, and Birolini failure modes. In this case, short circuits, open circuits, and shifts account for 10%, 50%, and 40% of all failure scenarios for an optical Mos transistor, while short circuits and functional failures account for 20% and 80%, respectively. Therefore, although relays and optical Mos transistors both have switching functions, they experience different failure scenarios, with different failure rates for each scenario. Consequently, the calculated failure coefficients are different. Therefore, the expected failure values ​​calculated for relays and optical Mos transistors after they are applied to a circuit are also different.

[0031] In some embodiments, the failure rate and failure coefficient of each element are obtained, and the failure expectancy of each first element is calculated based on these parameters. Then, the multiple failure expectancies are compared. If the failure expectancy of one first element is higher than that of other first elements, the first element is more likely to fail and be damaged. Therefore, the first element is processed. Specifically, if the failure coefficient of the first element is mainly affected by open circuits, the connection relationship between the first element and the surrounding first elements may be corrected, thereby avoiding the situation where multiple first elements of the same type are turned on at the same time.

[0032] The technical solution of the present invention obtains the failure rate of each element in a given circuit and the corresponding failure coefficient for each element, determines the expected failure value of each element based on the failure rate and the corresponding failure coefficient for each element, and quantifies the reliability of the first insulation testing circuit using a unified calculation method. It also determines which first elements need to be optimized based on the expected failure values, and replaces the first elements based on the failure coefficients of the elements. This quantifies the reliability of each first element in a given circuit, so that the reliability of each first element can be directly reflected by the magnitude of the expected failure value. By comparing the expected failure values, it is determined which elements in the given circuit mainly affect the reliability of the given circuit, and modifications to the given circuit can be applied to specific elements, thereby more directly and simply determining the direction of modification of the given circuit, which achieves the effect of achieving higher reliability when the modified circuit is operational. This solves the technical problem of being unable to quantify the reliability of the first insulation testing circuit and being unable to determine how to modify the given circuit to improve its reliability.

[0033] 1-2, in some embodiments, obtaining the fault coefficients corresponding to each element in a given circuit includes the following steps.

[0034] In S110, all failure states present in each first element according to a predetermined standard failure mode and the failure rate corresponding to each failure state are acquired.

[0035] In S120, a circuit connection method in a predetermined circuit of each first element is obtained, and at least one target fault situation that exists when the first element operates is determined based on the circuit connection method.

[0036] In S130, a failure coefficient of the first element is determined based on the sum of the failure rates of at least one target failure state corresponding to each first element.

[0037] In some embodiments, the standard failure modes capture various failure modes that exist in each first element, but not all failure modes can occur due to different circuit connections. For example, a switching transistor in an off state has three standard failure modes: short circuit, open circuit, and parameter shift. However, for a switching transistor that is off, an open circuit does not affect its operational effectiveness, so an open circuit failure is not considered. Therefore, when calculating the failure coefficient of each element, the circuit connection state is first determined to determine whether there are any failure conditions that do not affect the operational effectiveness. Failure conditions that affect the operational effectiveness are considered as target failure conditions, and the probabilities corresponding to at least one target failure condition are accumulated to determine the failure coefficient of the first element.

[0038] Furthermore, when the first insulation inspection circuit is operating, the operating state of each of its elements is not always constant. To calculate the resistance values ​​of the positive and negative ground resistors in the first insulation inspection circuit, there are usually at least two operating states, and each operating state corresponds to one type of connection circuit. Therefore, when calculating the expected failure value of the elements in the first insulation inspection circuit, it is necessary to simultaneously calculate the expected failure values ​​of the elements in the first insulation inspection circuit in multiple operating states.

[0039] According to the standard SN29500, as shown in Figure 7, The failure rate of a resistor in a given circuit is F R1 =F R2 =F R3 =F R41 =1.26FIT, The failure rate of switching transistors in a given circuit is F K1 =F K2 =40FIT.

[0040] The predetermined circuit includes a first operating state and a second operating state.

[0041] When the first insulation testing circuit is in a first working state, the fault states of the first resistor R1, the second resistor R2 and the third resistor R3 all include an open circuit of the resistors and a parameter shift of the resistors, the fault state of the first switching transistor K1 includes a functional failure of the relay, and the fault state of the second switching transistor K2 includes a short circuit of the relay.

[0042] When the first insulation testing circuit is in the second operating state, the fault states of the first resistor R1, the second resistor R2, and the third resistor R3 all include resistor open circuit and resistor parameter shift, and the fault states of the first switching transistor K1 and the second switching transistor K2 all include relay malfunction.

[0043] When a given circuit is in a first operating state, the first switching is turned on and the second switching is turned off.

[0044] When the predetermined circuit is in the second operating state, the first switch and the second switch are both turned on.

[0045] (1) When the first switching transistor K1 is turned on and the second switching transistor K2 is turned off, the failure of the first insulation test circuit is calculated based on the following:

[0046] (Number 2)P R1_1 =P R2_1 =F R1 / (F R1 +F R2 +0.9*F K1 +0.5*F K2 )=0.0215

[0047] (number 3)P K1_1 =0.9*F K1 / (F R1 +F R2 +0.9*F K1 +0.5*F K2 )=0.6152

[0048] (Number 4)P K2_1 =0.5*F R2 / (F R1 +F R2 +0.9*F K1 +0.5*F K2 )=0.3418

[0049] The total expected failure value for a given circuit in a first operating state is then calculated based on:

[0050] (Number 5) F1 = F R1 *P R1_1 +F R1 *P R2_1 +0.9*F K1 *P K1_1 +0.5*F K2 *P K2_1=29.03738FIT

[0051] (2) When both the first switching transistor K1 and the second switching transistor K2 are turned on, the failure of the first insulation inspection circuit is calculated based on the following:

[0052] (Number 6)P R1_2 =P R2_2 =P R3_2 =P R41_2 =F R1 / (F R1 +F R2 +F R3 +F R41 +0.9*F K1 +0.9*F K2 )=0.0164

[0053] (number 7)P K1_2 =P K2_2 =0.9*F K1 / (F R1 +F R2 +F R3 +F R41 +0.9*F K1 +0.9*F K2 )=0.4672

[0054] The total failure expectancy for a given circuit in the second operating state is then calculated based on:

[0055] (Number 8) F2 = F R1 *P R1_2 +F R2 *P R2_2 +F R3 *P R3_2 +F R41 *P R41_2 +0.9*F K1 *P K1_2 +0.9*F K2 *P K2_2 =33.721056FIT

[0056] 1 and 3, in some embodiments, replacing a first element with a second element based on a failure coefficient of the first element includes the following steps.

[0057] In S310, a plurality of types of target fault conditions corresponding to the fault coefficient of the target first element are acquired.

[0058] In S320, a second element to be awaited replacement is determined based on at least one target failure state remaining after removing one or more target failure states from the plurality of target failure states.

[0059] In some embodiments, the circuit failure rate is mainly composed of the number of elements, their own failure rate, failure mode, and circuit architecture. When calculating the expected failure value of a first element in a given circuit, the target failure conditions that have a major impact on the value of the failure coefficient in the at least one remaining target failure condition are determined based on the failure coefficient corresponding to the target first element, and these target failure conditions are eliminated. Then, based on the remaining target failure conditions, a second element is determined in the existing standard failure conditions.

[0060] 1 and 4, in some embodiments, the first element of interest is an optical Mos transistor and the second element is a relay; The relay is sealed with a plastic seal that complies with vehicle standards.

[0061] In one embodiment, in a fault state of the first switching transistor K1 and the second switching transistor K2, the short circuit rate of the relay is smaller than the malfunction rate of the relay, specifically, the short circuit rate of the relay is 20%, and the malfunction rate of the relay is 80%.

[0062] Based on this, taking the case where the reference environmental temperature is 40°C, only a single fault point is considered, and the failure mode is a Birolini Failure Mode as an example, in one embodiment, in the fault state of the first resistor R1, the second resistor R2, and the third resistor R3, the open circuit rate of the resistors is greater than the parameter shift rate of the resistors, specifically, the open circuit rate of the resistors is 60%, and the parameter shift rate of the resistors is 40%.

[0063] The first resistor R1, the second resistor R2, and the third resistor R3 are carbon film resistors.

[0064] Determining a second element to be awaited replacement based on the plurality of target failure situations remaining after removing one or more target failure situations from the plurality of target failure situations includes the following steps.

[0065] In S321, if the first element is a MOS transistor, it is determined that the target fault condition of the photoMOS transistor includes at least one of a shift of the switching transistor and an open circuit of the switching transistor.

[0066] In S322, an element in which the target fault condition does not include either a shift of the switching transistor or an open circuit of the switching transistor is determined as a relay, and the relay is set as the second element.

[0067] In some embodiments, the circuit architecture of Figure 7 is optimized as shown in Figure 8. When calculating the expected failure value of the optical MOS element, the coefficient is mainly affected by the optical MOS open circuit and the optical MOS parameter shift, so these two major influencing failure conditions are eliminated, and the second element is determined under the existing standard failure conditions according to the remaining short circuit, i.e., there are only relays with two types of failure conditions: short circuit and functional failure.

[0068] As can be seen from the explanation of failure modes, relay short circuit and functional failure account for 20% and 80% respectively, when the relay is in the OFF state, the target failure situation of the relay only includes relay short circuit situations, while the failure rate of relay short circuit is 20%, so the failure coefficient of the relay's expected failure value at this time is 0.2. When the relay is in the ON state, the target failure situation of the relay only includes relay functional failure situations, while the failure rate of relay functional failure is 80%, so the failure coefficient of the relay's expected failure value at this time is 0.8.

[0069] Specifically, (1) when the first relay K3 is turned on and the second relay K4 is turned off, the failure of the first insulation test circuit is calculated based on the following:

[0070] (Number 9)P R51_1 =P R61_1 =F R51 / (F R51 +F R61 +0.8*F K3 +0.2*F K4 )

[0071] (Number 10)P K3_1 =0.8*F K3 / (F R51 +F R61 +0.8*F K3 +0.2*FK4 )

[0072] (Number 11)P K4_1 =0.2*F K4 / (F R51 +F R61 +0.8*F K3 +0.2*F K4 )

[0073] (2) When both the first relay K3 and the second relay K4 are turned on, the failure of the first insulation test circuit is calculated based on the following:

[0074] (Number 12)P R51_2 =P R61_2 =P R71_2 =F R51 / (F R51 +F R61 +F R71 +0.8*F K3 +0.8*F K4 )=0.2342

[0075] (Number 13)P K3_2 =P K4_2 =0.8*F K9 / (F R51 +F R61 +F R71 +0.8*F K3 +0.8*F K4 )

[0076] As can be seen from the above-mentioned formula for the expected value, when the optical MOS transistor is replaced with a relay, the failure coefficients of the expected failure values ​​of the switching elements are all reduced to a certain extent. After the first switching transistor K1 is replaced with the first relay K3, with the same connection method, the failure coefficients of the expected failure values ​​are reduced from 0.9 to 0.8, and the expected failure value of the switching element at this position can be significantly reduced.

[0077] Furthermore, the failure rate of the replacement second element based on the element failure rate standard must be lower than the failure rate of the first element it replaces based on the element failure rate standard. The failure coefficient of the second element in a different connection state must also be lower than the failure coefficient of the first element it replaces in a different connection state.

[0078] Therefore, referring to FIGS. 1 and 8, in some embodiments, after comparing a plurality of expected failure values ​​to determine a first target element to be repaired in a predetermined circuit, the method further includes:

[0079] Based on the failure rate of the target first element, the first element is replaced with a third element, where the failure rate of the third element is lower than the failure rate of the first element.

[0080] The circuit is redesigned according to the above design direction, and the expected failure value of each element is recalculated.

[0081] According to the standard SN29500 The failure rate of the resistor in the modified circuit is F R51 =F R61 =F R71 =1.26FIT, The failure rate of the switching transistor in the modified circuit is F K3 =F K4 =1FIT.

[0082] According to the above, the failure rate of the relay is much lower than that of the optical MOS according to the element failure rate standard, so the failure rate of the relay is used in the formula for the expected failure value.

[0083] (1) When the first relay K3 is turned on and the second relay K4 is turned off, the failure of the first insulation test circuit is calculated based on the following:

[0084] (Number 14)P R51_1 =P R61_1 =F R51 / (F R51 +F R61 +0.8*F K3 +0.2*FK4 )=0.3580

[0085] (Number 15)P K3_1 =0.8*F K3 / (F R51 +F R61 +0.8*F K3 +0.2*F K4 )=0.2272

[0086] (Number 16)P K4_1 =0.2*F K4 / (F R51 +F R61 +0.8*F K3 +0.2*F K4 )=0.0568

[0087] The total expected failure value for a given circuit in a first operating state is then calculated based on:

[0088] (Number 17) F3 = F R51 *P R51_1 +F R61 *P R61_1 +0.8*F K3 *P K3_1 +0.2*F K4 *P K4_1 =1.09528FIT

[0089] (2) When both the first relay K3 and the second relay K4 are turned on, the failure of the first insulation test circuit is calculated based on the following:

[0090] (Number 18)P R51_2 =P R61_2 =P R71_2 =F R51 / (F R51 +F R61 +F R71 +0.8*F K3 +0.8*F K4 )=0.2342

[0091] (Number 19)P K3_2 =P K4_2 =0.9*F K9 / (F R51 +F R61+F R71 +0.8*F K3 +0.8*F K4 )=0.1487

[0092] At that time, the first 2 The total expected failure value under operating conditions is calculated based on the following:

[0093] (Number 20) F4=F R51 *P R51_2 +F R61 *P R61_2 +F R71 *P R71_2 +0.8*F K3 *P K3_2 +0.8*F K4 *P K4_2 =1.12320FIT

[0094] As can be seen from the above calculation results, for a single element, P K1_1 >P K3_1 and P K2_1 >P K4_1 and P K1_2 >P K3_2 and P K2_2 >P K4_2 Therefore, the expected failure value of the switching elements at each position is greatly reduced, and for the entire circuit, F1>F3 and F2>F4, so the total expected failure value of the circuit is also greatly reduced, thereby improving the reliability of the entire circuit and reducing the possibility of circuit failure.

[0095] 1 and 5, in some embodiments, replacing the first element with the second element based on the failure condition at the failure factor of the first element includes the following steps.

[0096] In S330, the failure rates corresponding to the multiple types of target failure situations of the target first element are sorted in descending order, and the sorted queue is acquired.

[0097] In S340, a target failure situation corresponding to a failure rate higher than a predetermined ranking is set as a target failure situation waiting for correction according to the order of the queue.

[0098] In S350, one or more types of target failures awaiting repair in the target failure situations awaiting repair Expected value After lowering the threshold, the second element to be replaced is determined based on the failure rates of the multiple target failure situations.

[0099] In some embodiments, since different processes for the same type of device result in different failure rates, the expected failure values ​​for each device are obtained, and then the expected failure values ​​are sorted in descending order to determine which devices in a given circuit have a greater impact on the circuit. Then, those devices are processed, and devices manufactured by a process type different from that of the devices are selected. If there is an element among the devices having the same function that has one or more target failure conditions awaiting repair that are lower than the target first element, that element is designated as a second element and is replaced with the corresponding target first element. Specifically, for example, in the first insulation test circuit of FIG. 7, when the given circuit is in the first operating state, P R1_1 =P R2_1 =0.0215, and P K1_1 =0.6152, and P K2_1 =0.3418, then the order of expected failures is P K1_1 >P K2_1 >P R1_1 =P R2_1 On the other hand, when the predetermined circuit is in the second operating state, P R1_2 =P R2_2 =P R3_2 =P R41_2 =0.0164, and P K1_2 =P K2_2 =0.4672, then the order of expected failures is P K1_2 =P K2_2 >P R1_2 =P R2_2 =P R3_2 =P R41_2 is.

[0100] Therefore, in accordance with the order of the expected failure value of the first element described above, the first switching transistor K1 is usually selected for replacement, and similarly, in order to further reduce the total expected failure value of the circuit, the first switching transistor K1 and the second switching transistor K2, which are ranked first in the second state, may be replaced simultaneously.

[0101] It should be noted that the predetermined ranking may relate to the number of first elements in the predetermined circuit and / or the number of elements with relatively large expected values. The more first elements in the predetermined circuit, the higher the predetermined ranking and thus the more first elements that are replaced; similarly, the more first elements with relatively large expected values, the higher the predetermined ranking.

[0102] 1 and 6, in some embodiments, after determining the failure expectancy of each first element based on the failure rate of each first element and the failure coefficient corresponding to each first element, the method further includes:

[0103] In S500, the total expected failure value of the predetermined circuit is obtained based on the expected failure value of each first element, the failure rate, and the failure coefficient corresponding to each first element.

[0104] In S600, it is determined whether or not to modify the predetermined circuit based on the relationship between the total expected failure value of the predetermined circuit and the expected threshold value.

[0105] In some embodiments, the circuit of the input device does not necessarily need to be modified. Because the circuit of the input device may have relatively high reliability in some cases, it is necessary to first determine the total expected failure value of the circuit of the input device and pre-store an expected failure threshold in the device. The expected failure threshold is a critical value for classifying the total expected failure value. For example, if the total expected failure value is lower than the expected failure threshold, the circuit does not need to be modified.

[0106] Here, a first total expected failure value of the circuit to be optimized is determined based on the failure rates, expected failure values, and failure coefficients corresponding to the first plurality of elements.

[0107] A second total failure expectancy of the circuit to be optimized is determined based on the failure rates, failure expectancies, and failure coefficients corresponding to the plurality of first elements and the failure rates, failure expectancies, and failure coefficients corresponding to the at least one replaced second element.

[0108] Please refer to FIG. 9, which is a flowchart 3 illustrating a processing method for circuit reliability provided in an embodiment of the present application.

[0109] In S1000, the failure rate of each element in a predetermined circuit and the failure coefficient corresponding to each element are obtained.

[0110] In some embodiments, the predetermined circuit is a circuit waiting to be processed and is input by a user via a device such as a PC.

[0111] The failure rate is Processing Equipment is obtained based on an existing element failure rate standard. In some embodiments, the standard adopted is standard SN29500. In other cases, other element failure rate standards, such as IEC62380, may be adopted according to actual needs. The failure coefficient is the proportion of possible failure conditions of each first element to all failure conditions. For example, in the case of a switching transistor, all of its failure conditions include parameter shift, short circuit, and open circuit. However, when the switching transistor is turned off, the possible target failure conditions include parameter shift and short circuit. In this case, the standard failure coefficient of the switching transistor is the sum of the probability of both parameter shift and short circuit occurring.

[0112] When a user wants to optimize the reliability of the first insulation test circuit, they first determine the required element failure rate standard, and then determine the failure rate of each element in the existing first insulation test circuit according to the standard. For example, when calculating the failure rates of the switching transistor and resistor according to the standard SN29500, the failure rate of the switching transistor is 40 FIT, and the failure rate of the resistor is 1.26 FIT. They then determine the total probability of the target failure scenarios that can occur for each element and calculate the parameters of the element failure scenarios.

[0113] In S2000, the expected failure value of each element is determined based on the failure rate of each element and the failure coefficient corresponding to each element.

[0114] In some embodiments, the expected failure value is the proportion of the target failure conditions of each element to the target failure conditions of the total circuit. Take FIG. 17 as an example, which shows the second insulation test circuit before improvement. The expected failure value of the fifth switching transistor K5 of FIG. 8 is calculated based on the following:

[0115] (Number 21)P K5_1 =a*F K5 / (F R4 +F R5 +F R6 +F R7 +a*F K5 +b*F K6 +c*F K7 ), where a is the failure factor of the fifth switching transistor K5, b is the failure factor of the sixth switching transistor K6, c is the failure factor of the sixth switching transistor K7, and F R4 is the failure rate of the fourth resistor R4, and F R5 is the failure rate of the fifth resistor R5, and F R6 is the failure rate of the sixth resistor R6, and F R7 is the failure rate of the seventh resistor R7, and F K5 is the failure rate of the fifth switching transistor K5, and F K6 is the failure rate of the sixth switching transistor K6, and F K7 is the failure rate of the seventh switching transistor K7, (F R4 +F R5 +F R6 +F R7 +a*F K5 +b*F K6 +c*F K7 ) is the target fault condition of the total circuit.

[0116] In S3000, a plurality of expected failure values ​​are compared to determine a target element in a predetermined circuit that is waiting to be corrected, and the connection method of the target element is changed based on the failure coefficient of the target element to reduce the expected failure value of the target element.

[0117] The fourth resistor R4, the fifth resistor R5, the sixth resistor R6, and the seventh resistor R7 are carbon film resistors, and the fifth switching transistor K5, the sixth switching transistor K6, and the seventh switching transistor K7 are photoMOS transistors.

[0118] The circuit failure rate is mainly determined by the number of elements, their own failure rate, failure mode, and circuit architecture. However, the target failure conditions for several identical elements will also be different due to their different connection relationships. For example, if the reference ambient temperature is 40°C and only single-point failure modes are considered, then short circuit, open circuit, and shift account for 10%, 50%, and 40% of all failure conditions for an optical Mos transistor. Therefore, even if both are optical Mos transistors, the failure rates for short circuit and open circuit conditions will be different, and the calculated failure coefficients will also be different. Therefore, when several identical elements are applied to a circuit, the calculated expected failure values ​​will also be different.

[0119] In some embodiments, the failure rate and failure coefficient of each element are obtained, and the expected failure value of each element is calculated based on these parameters. Then, the multiple expected failure values ​​are compared. If the expected failure value of one element is higher than that of other elements, the element is more likely to fail and be damaged. Therefore, the element is processed. Specifically, if the failure coefficient of an element is mainly affected by open circuits, the connection relationship between the element and surrounding elements can be modified, thereby avoiding the situation where multiple elements of the same type are turned on at the same time.

[0120] The technical solution of the present application obtains the failure rate of each element in a given circuit and the corresponding failure coefficient for each element, determines the expected failure value of each element based on the failure rate of each element and the corresponding failure coefficient for each element, quantifies the reliability of the second insulation testing circuit using a unified calculation method, determines the elements that need to be optimized based on the multiple expected failure values, and replaces the elements based on the element's failure coefficient, thereby quantifying the reliability of each element in the given circuit so that the reliability of each element can be directly reflected by the magnitude of the expected failure value, and by comparing the multiple expected failure values, it is determined which element in the given circuit mainly affects the reliability of the given circuit, and modifications to the given circuit can be applied to specific elements, thereby more directly and simply determining the direction of modification of the given circuit, thereby achieving the effect of achieving higher reliability when the modified circuit is operational, which solves the technical problem of not being able to quantify the reliability of the second insulation testing circuit and not being able to determine how to modify the given circuit to improve its reliability.

[0121] 9-10, in some embodiments, obtaining the fault coefficients corresponding to each element in a given circuit includes the following steps.

[0122] In S1100, all failure states present in each element according to a predetermined standard failure mode and the failure rate corresponding to each failure state are acquired.

[0123] In S1200, the circuit connection method for a predetermined circuit of each element is acquired, and multiple types of target fault conditions that exist when the element operates are determined based on the circuit connection method.

[0124] In S1300, the failure coefficient of each element is determined based on the sum of the failure rates of a plurality of target failure situations corresponding to each element.

[0125] In some embodiments, the standard failure modes capture various failure modes that exist for each element, but not all failure modes will result in failure conditions due to different circuit connections. For example, a switching transistor in an off state has three standard failure modes: short circuit, open circuit, and parameter shift. However, for a switching transistor that is off, an open circuit does not affect its operational effectiveness, so the open circuit failure condition is not considered. Therefore, when calculating the failure coefficient for each element, the circuit connection state is first determined to determine whether there are any failure conditions that do not affect the operational effectiveness, and then the probabilities corresponding to the target failure conditions that affect the operational effectiveness are accumulated. element The failure coefficient is

[0126] When the second insulation test circuit is operating, the operating state of each element is not always constant. To calculate the resistance values ​​of the positive and negative ground resistors in the second insulation test circuit, there are usually at least two operating states, and each operating state corresponds to one type of connection circuit. Therefore, when calculating the expected failure value of the elements in the second insulation test circuit, it is necessary to simultaneously calculate the expected failure values ​​of the elements in the second insulation test circuit in multiple operating states.

[0127] According to the standard SN29500, as shown in Figure 16, The failure rate of a resistor in a given circuit is F R4 =F R5 =F R6 =F R7 =1.26FIT, The failure rate of switching transistors in a given circuit is F K5 =F K6 =F K7 =40FIT.

[0128] The predetermined circuit includes a first operating state and a second operating state.

[0129] When a given circuit is in a first operating state, the first switching is turned on and the second switching is turned off.

[0130] When the predetermined circuit is in the second operating state, the first switch and the second switch are both turned on.

[0131] (1) When the fifth switching transistor K5 and the sixth switching transistor K6 are turned on and the seventh switching transistor K7 is turned off, the failure of the second insulation test circuit is calculated based on the following:

[0132] (Number 22)P R4_1 =P R5_1 =P R6_1 =P R7_1 =F R4 / (F R4 +F R5 +F R6 +F R7 +0.9*F K5 +0.9*F K6 +0.5*F K7 )=0.013

[0133] (Number 23)P K5_1 =P K6_1 =0.9*F K5 / (F R4 +F R5 +F R6 +F R7 +0.9*F K5 +0.9*F K6 +0.5*F K7 )=0.371

[0134] (Number 24)P K7_1 =0.5*F K7 / (F R4 +F R5 +F R6 +F R7 +0.9*F K5 +0.9*F K6 +0.5*F K7 )=0.206

[0135] (2) When the fifth switching transistor K5 and the seventh switching transistor K7 are turned on and the sixth switching transistor K6 is turned off, the failure of the second insulation test circuit is calculated based on the following:

[0136] (Number 25)P R5_2 =P R6_2 =P R7_2 =F R4 / (F R5 +F R6 +F R7 +0.9*F K5 +0.5*F K6 +0.9*F K7 )=0.0132

[0137] (Number 26)P K5_2 =P K6_2 =0.9*F K5 / (F R5 +F R6 +F R7 +0.9*F K5 +0.5*F K6 +0.9*F K7 )=0.3758

[0138] (Number 27)P K7_2 =0.5*F K7 / (F R5 +F R6 +F R7 +0.9*F K5 +0.5*F K6 +0.9*F K7 )=0.2088

[0139] 9, 10 and 16, in some embodiments, comparing a plurality of failure expectations includes the following steps.

[0140] In S3100, the multiple failure expectation values ​​are sorted in descending order, and the sorted queue is obtained.

[0141] In S3200, according to the order of the queue, it is determined whether the element can be repaired based on the connection method of the element corresponding to the expected fault value in order, and a predetermined number of target elements that can be repaired are determined.

[0142] And / or, in S3300, the element corresponding to the expected failure value higher than a predetermined ranking is determined as the target element according to the order of the queue.

[0143] In some embodiments, if the expected failure value of one element is higher than that of other elements, the element is more likely to fail and be damaged. Therefore, after obtaining the expected failure value of each element, the expected failure values ​​need to be sorted in descending order to determine which elements in a given circuit have a greater impact on the circuit, and then processing should be performed on those elements. Specifically, for example, in the second insulation test circuit shown in FIG. 8, when the given circuit is in the first operating state, P R4_1 =P R5_1 =P R6_1 =P R7_1 =0.013, P K5_1 =P K6_1 =0.371, P K7_1 =0.206, then the order of expected failures is P K5_1 =P K6_1 >P K7_1 >P R4_1 =P R5_1 =P R6_1 =P R7_1 and when the given circuit is in the second operating state, P R4_2 =P R5_2 =P R6_2 =P R7_2 =0.0132, and P K5_2 =P K6_2 =0.3758, and P K7_2 =0.2088, then the order of expected failures is P K5_2 =P K6_2 >P K7_2 >P R4_2 =P R5_2 =P R6_2 =P R7_2 is.

[0144] Since not all elements in a given circuit can be moved, the order of expected failures determined in the above example, P K5_1 =P K6_1 >P K7_1 >P R4_1 =P R5_1 =P R6_1 =P R7_1For example, since the fifth switching transistor K5 is limited to its circuit function and no adjustment is made to its configuration, the sixth switching transistor K6 and the seventh switching transistor K7, which have a relatively high failure rate, are selected and moved according to the ranking.

[0145] Note that the predetermined number and the predetermined ranking may both relate to the number of elements in the predetermined circuit and / or the number of elements with relatively large expected values. The greater the number of elements in the predetermined circuit, the greater the predetermined number and the higher the predetermined ranking; similarly, the greater the number of elements with relatively large expected values, the greater the predetermined number and the higher the predetermined ranking.

[0146] Referring to FIGS. 9 to 17, changing the connection manner of the target device based on the failure coefficient of the target device specifically includes:

[0147] The connection method between the target element and surrounding elements is changed based on the failure rate of the target failure state of the element.

[0148] In some embodiments, the circuit configuration of the sixth switching transistor K6 and the seventh switching transistor K7 is optimized because the fifth switching transistor K5 is limited to its circuit function and no adjustments are made to its configuration. 17 1. The parallel configuration of the ninth switching transistor K9 and the tenth switching transistor K10 shown in FIG. 1 is optimized to avoid a breakdown condition of the elements of the sixth switching transistor K6 and the seventh switching transistor K7.

[0149] The circuit failure rate is mainly determined by the number of elements, the failure rate itself, the failure mode, and the circuit architecture, and is optimized as shown in Figure 9 by optimizing the circuit architecture of Figure 8. The optimized circuit architecture combines the balanced bridge method and the unbalanced bridge method, so that if the ninth switching transistor K9 has an open circuit fault, the tenth switching transistor K10 is substituted and an insulation test is performed using the balanced bridge method; similarly, if the tenth switching transistor K10 has an open circuit fault, the ninth switching transistor K9 is substituted and an insulation test is performed using the unbalanced bridge method, thereby improving the reliability of the second insulation test circuit.

[0150] The circuit is redesigned according to the above design direction, and the expected failure value of each element is recalculated.

[0151] According to the standard SN29500 The failure rate of the resistor in the modified circuit is F R8 =F R9 =F R10 =F R11 =1.26FIT, The failure rate of the switching transistor in the modified circuit is F K8 =F K9 =F K10 =40FIT.

[0152] In some embodiments, when the modified circuit is installed in an unbalanced test bridge, the following occurs:

[0153] (1) When the unbalanced test bridge is in the first working state, the eighth switching transistor K8 and the ninth switching transistor K9 are turned on, and the tenth switching transistor K10 is turned off. The fault states of the eighth resistor, the ninth resistor, the tenth resistor and the eleventh resistor all include an open circuit of the resistor and a parameter shift of the resistor. The fault state of the eighth switching transistor K8 includes an open circuit of the switching transistor and a parameter shift of the switching transistor. The fault state of the ninth switching transistor K9 includes a parameter shift of the switching transistor. The fault state of the tenth switching transistor K10 includes a short circuit of the switching transistor.

[0154] The failure of the second insulation test circuit is then calculated based on:

[0155] (Number 28)P R8_1 =P R9_1 =P R10_1 =F R8 / (F R8 +F R9 +F R10 +0.9*F K8 +0.4*F K9 +0.1*F K10 )=0.0211

[0156] (Number 29)P K8_1 =0.9*F K8 / (F R8 +F R9 +F R10 +0.9*F K8 +0.4*F K9 +0.1*F K10 )=0.6022

[0157] (number 30)P K9_1 =0.4*F K8 / (F R8 +F R9 +F R10 +0.9*F K8 +0.4*F K9 +0.1*F K10 )=0.2676

[0158] (Number 31)PK10_1 =0.1*FK8 / (F R8 +F R9 +F R10 +0.9*F K8 +0.4*F K9 +0.1*F K10 )=0.0669

[0159] (2) When the unbalanced test bridge is in the second working state, the eighth switching transistor K8 is turned on, and the ninth switching transistor K9 and the tenth switching transistor K10 are turned off. The fault states of the eighth resistor, the ninth resistor, the tenth resistor and the eleventh resistor all include an open circuit of the resistor and a parameter shift of the resistor. The fault state of the eighth switching transistor K8 includes an open circuit of the switching transistor and a parameter shift of the switching transistor. The fault states of the ninth switching transistor K9 and the tenth switching transistor K10 all include a short circuit of the switching transistor and a parameter shift of the switching transistor.

[0160] The failure of the second insulation test circuit is then calculated based on:

[0161] (Number 32)P R9_2 =P R10_2 =F R9 / (F R9 +F R10 +0.9*F K8 +0.5*F K9 +0.5*F K10 )=0.016

[0162] (Number 33)P K8_2 =0.9*F K8 / (F R9 +F R10 +0.9*F K8 +0.5*F K9 +0.5*F K10 )=0.4586

[0163] (number 34)P K9_2 =P K10_2 =0.5*F K9 / (F R9 +FR10 +0.9*F K8 +0.5*F K9 +0.5*F K10 )=0.2547

[0164] In another embodiment, when the modified circuit is installed in a balanced test bridge, it is as follows.

[0165] (1) When the balanced check bridge is in the first working state, the eighth switching transistor K8 and the tenth switching transistor K10 are turned on, and the ninth switching transistor K9 is turned off. The fault states of the eighth resistor, the ninth resistor, the tenth resistor and the eleventh resistor all include an open circuit and a parameter shift of the resistor. The fault state of the eighth switching transistor K8 includes an open circuit and a parameter shift. The fault state of the ninth switching transistor K9 includes a short circuit of the switching transistor. The fault state of the tenth switching transistor K10 includes a parameter shift of the switching transistor.

[0166] The failure of the second insulation test circuit is then calculated based on:

[0167] (number 35)P R8_3 =P R9_2 =P R10_2 =P R11_2 =F R8 / (F R8 +F R9 +F R10 +F R11 +0.9*F K8 +0.1*F K9 +0.4*F K10 )=0.0206

[0168] (number 36)P K8_3 =0.9*F K8 / (F R8 +F R9 +F R10 +F R11 +0.9*F K8 +0.1*F K9 +0.4*F K10 )=0.5898

[0169] (number 37)P K9_3 =0.1*F K8 / (F R8 +F R9 +F R10 +F R11 +0.9*F K8 +0.1*F K9 +0.4*F K10 )=0.0655

[0170] (number 38)P K10_3 =0.4*F K8 / (F R8 +F R9 +F R10 +F R11 +0.9*F K8 +0.1*F K9 +0.4*F K10 )=0.0419

[0171] (2) When the balanced check bridge is in the second working state, the eighth switching transistor K8 is turned on, and the ninth switching transistor K9 and the tenth switching transistor K10 are turned off. The fault states of the eighth resistor, the ninth resistor, the tenth resistor and the eleventh resistor all include an open circuit of the resistor and a parameter shift of the resistor. The fault state of the eighth switching transistor K8 includes an open circuit of the switching transistor and a parameter shift of the switching transistor. The fault states of the ninth switching transistor K9 and the tenth switching transistor K10 all include a short circuit of the switching transistor and a parameter shift of the switching transistor.

[0172] The failure of the second insulation test circuit is then calculated based on:

[0173] (Number 39)P R9_4 =P R10_2 =F R9 / (F R9 +F R10 +0.9*F K8 +0.5*F K9 +0.5*F K10 )=0.016

[0174] (number 40)P K8_4 =0.9*F K8 / (F R9 +F R10 +0.9*F K8 +0.5*F K9 +0.5*F K10 )=0.4586

[0175] (Number 41)P K9_4 =P K10_2 =0.5*F K9 / (F R9 +F R10 +0.9*F K8 +0.5*F K9 +0.5*F K10 )=0.2547

[0176] 9 and 12, in some embodiments, after determining the failure expectancy of each element based on the failure rate of each element and the failure coefficient corresponding to each element, the method further includes the following steps:

[0177] In S5000, the total expected failure value of a predetermined circuit is obtained based on the expected failure value of each element, the failure rate, and the failure coefficient corresponding to each element.

[0178] In S6000, it is determined whether or not to modify the predetermined circuit based on the relationship between the total expected failure value of the predetermined circuit and the expected threshold value.

[0179] In some embodiments, the circuit of the input device does not necessarily need to be modified. Because the circuit of the input device may have relatively high reliability in some cases, it is necessary to first determine the total expected failure value of the circuit of the input device and pre-store an expected failure threshold in the device. The expected failure threshold is a critical value for classifying the total expected failure value. For example, if the total expected failure value is lower than the expected failure threshold, the circuit does not need to be modified.

[0180] A first total expected failure value for the given circuit is determined based on the failure rates, expected failure values, and failure coefficients corresponding to the plurality of elements.

[0181] A second total failure expectancy for the given circuit is determined based on the failure rates, failure expectancies, and failure coefficients corresponding to the plurality of elements and the failure rates, failure expectancies, and failure coefficients corresponding to the at least one replaced second element.

[0182] For example, for the given circuit shown in FIG. 8, the total failure expectancy in the first operating state is F1=F R1 *P R1_1 +F R2 *P R2_1 +F R3 *P R3_1 +F R4 *P R4_1 +0.9*F K5 *P K5_1 +0.9*F K6 *P K6_1 +0.5*F K7 *P K7_1 =30.89752FIT.

[0183] The total expected failure value in the second operating state is F2=F R2 *P R2_2 +F R3 *P R3_2 +F R4 *P R4_2 +0.9*F K5 *P K5_2 +0.5*F K6 *P K6_2 +0.9*F K7 *P K7_2 =31.283496FIT.

[0184] From the above, we can obtain the total expected failure value of the modified circuit.

[0185] In some embodiments, if the modified circuit is an unbalanced test bridge, the total expected failure value in its first operating state is: F3=F R8 *P R8_1 +F R9 *P R9_1 +F R10 *P R10_1 +0.9*F K8 *P K8_1+0.4*F K9 *P K9_1 +0.1*F K10 *P K10_1 =28.426558FIT.

[0186] The total expected failure value in the second operating state is F4=F R9 *P R9_2 +F R10 *P R10_2 +0.9*F K8 *P K8_2 +0.5*F K9 *P K9_2 +0.5*F K10 *P K10_2 =21.64392FIT.

[0187] In another embodiment, if the modified circuit is a balanced check bridge, the total expected failure value in its first operating state is: F5=F R8 *P R8_3 +F R9 *P R9_3 +F R10 *P R10_3 +0.9*F K8 *P K8_3 +0.1*F K9 *P K9_3 +0.4*F K10 *P K10_3 =22.243068FIT.

[0188] The total expected failure value in the second operating state is F6=F R9 *P R9_4 +F R10 *P R10_4 +0.9*F K8 *P K8_4 +0.5*F K9 *P K9_4 +0.5*F K10 *P K10_4 =21.64392FIT.

[0189] Therefore, F5 < F3 < F1 and F6 = F4 < F2 are obtained. That is, regardless of whether the modified circuit is in the balanced inspection bridge or the unbalanced inspection bridge, its total failure expectation value is always lower than that of the predetermined circuit. Therefore, the modified circuit has higher reliability than the predetermined circuit. In addition, since the 10th switching transistor K10 in the modified circuit is further connected in series to one 11th resistor R11, there are fewer elements with faults in the balanced inspection bridge, and the balanced inspection bridge has higher reliability than the unbalanced inspection bridge.

[0190] Referring to FIGS. 9 to 15, in some embodiments, there are multiple expected thresholds, and the multiple expected thresholds include a first expected threshold and a second expected threshold, and the first expected threshold is greater than the second expected threshold. Determining whether to modify a predetermined circuit based on the relationship between the total failure expectation value of the predetermined circuit and the expected threshold includes the following steps.

[0191] In S6110, when the total failure expectation value is greater than the first expected threshold, a plurality of target elements in the predetermined circuit are modified based on the difference between the total failure expectation value and the first expected threshold.

[0192] In S6120, when the total failure expectation value is less than the first expected threshold and greater than the second expected threshold, it is determined whether to modify one target element in the predetermined circuit based on the relationship between the failure expectation value of each element and the predetermined element threshold corresponding to the element.

[0193] In S6130, when the total failure expectation value is less than the second expected threshold, the predetermined circuit is not modified.

[0194] In some embodiments, the first desirability threshold is the maximum critical value for a given circuit. That is, if the total expected failure value of a given circuit is greater than the first desirability threshold, it indicates that its reliability is very low and needs to be modified. Meanwhile, the basis for the modification is the difference between the total expected failure value and the first desirability threshold. The greater the difference between the total expected failure value and the first desirability threshold, the lower the reliability of the given circuit. In this case, more elements need to be modified. When selecting elements according to the ranking of expected failure values, the value of the given ranking will be larger. Therefore, the setting for the given ranking has a positive relationship with the difference between the total expected failure value and the first desirability threshold.

[0195] The second desired threshold is the minimum critical value of a given circuit. If the total expected failure value of a given circuit is lower than the second desired threshold, it indicates that the reliability of the given circuit is very good, and no modification to the circuit is required and it can be applied as is.

[0196] Therefore, only if the total expected failure value of a given circuit is between the first and second desired thresholds, is it necessary to further determine whether the circuit needs to be modified.

[0197] 9-15, in some embodiments, determining whether a circuit needs to be modified based on the relationship between the total expected failure value of a given circuit and an expected threshold value includes the following steps:

[0198] In S6210, if the total expected failure value is greater than the expected threshold, the predetermined circuit is modified.

[0199] In S6220, if the total expected failure value is equal to or less than the desired threshold, it is determined whether there is a case where the expected failure value of an element is greater than a predetermined element threshold corresponding to that element.

[0200] In the S6230, There are cases where the expected failure value of an element is greater than the predetermined element threshold value corresponding to the element. If so, modify the given circuit.

[0201] On the S6240, There are cases where the expected failure value of an element is greater than the predetermined element threshold value corresponding to the element.If not, the given circuit is not modified. In some embodiments, if it is determined that the total expected failure value of the given circuit is between the first and second expected failure thresholds, the device analyzes the expected failure value of each element in the circuit, and the device is configured with an element failure threshold corresponding to each element, which is used to evaluate the reliability of each element. If the expected failure value of each element is lower than the element failure threshold corresponding to that element, it indicates that each element in the given circuit has good reliability and is not likely to fail during long-term operation of the circuit. In this case, the given circuit does not need to be modified and can be used as is.

[0202] On the other hand, when there exists a case where the expected failure value of at least one element is higher than its corresponding element failure threshold, it indicates that there is an element with low reliability in the given circuit, and the failure rate of this element is too high and the circuit is prone to failure during the execution of the circuit. In this case, in the given circuit, the element with the expected failure value higher than the element failure threshold needs to be corrected by changing the connection method with surrounding elements until the expected failure value of the element is lower than the corresponding element failure threshold.

[0203] 9 and 14, in some embodiments, after determining the failure expectancy of each element based on the failure rate of each element and the failure coefficient corresponding to each element, the method further includes the following steps:

[0204] In S710, a plurality of modified circuits are automatically generated based on the target element, and a total expected fault value of each modified circuit is obtained.

[0205] In S720, the plurality of total failure expectancies are sorted, and one or more target circuits are determined according to the sorted rankings.

[0206] In some embodiments, automatic generation of multiple modified circuits can be achieved by the layout based on input device parameters. When automatically generating the second insulation test circuit, the result is not unique, and it is not possible to determine whether the generated second insulation test circuit is the circuit required by the user. Therefore, when multiple modified circuits are obtained, the total expected value of the circuits is calculated to determine the effect of improving reliability, and the circuit with the highest reliability, i.e., the lowest total expected value of failure, is selected as the target circuit required by the user.

[0207] Referring to FIG. 18 , the present application further provides a processing device related to circuit reliability, the processing device related to circuit reliability comprising: A parameter acquisition module 810 is used to acquire the failure rate of each element in a given circuit and the failure coefficient corresponding to each element; a processing module 820 used to determine the expected failure value of each of the elements based on the failure rate of each of the elements and the failure coefficient corresponding to each of the elements; and an implementation module 830 used to compare a plurality of the failure expectancies to determine elements awaiting repair in a given circuit, and reduce the failure expectancies of the elements awaiting repair based on the failure coefficients of the elements awaiting repair.

[0208] In some embodiments, the parameter acquisition module 810 may include a memory. The processing module 820 may include a main control chip, a processor, etc. The implementation module 830 may include a comparison circuit integrated in the main control chip.

[0209] The circuit reliability processing device may be connected to an industrial control computer, a home PC, or the like. When processing circuit reliability, an external device such as an industrial control computer or a home PC inputs a circuit to be repaired as a predetermined circuit into the processing device, causing the processing device to identify each element in the predetermined circuit. The parameter acquisition module 810 obtains the failure rate and corresponding failure coefficient of each element in the predetermined circuit based on the identified element type, and outputs the failure rate and corresponding failure coefficient of each element in the predetermined circuit to the processing module 820, allowing the processing module 820 to determine the expected failure value of each element based on the failure rate and corresponding failure coefficient of each element. After the processing module 820 determines the expected failure value of each element, the implementation module 830 compares the expected failure values ​​to determine the target elements in the predetermined circuit that need to be repaired.

[0210] The present application further provides a storage medium, the storage medium storing a computer program, which, when executed by a computer, causes the computer to perform the above-mentioned processing method for circuit reliability, and the specific configuration of the processing method for circuit reliability can be referred to the above-mentioned embodiments. Since the storage medium employs all the technical solutions of all the above-mentioned embodiments, it has at least all the inventive effects of the technical solutions of the above-mentioned embodiments, and therefore further description will be omitted here.

[0211] The present application further provides an electronic device, the electronic device including a processor and a memory, a computer program stored in the memory, the processor is used to execute the above-mentioned processing method for circuit reliability by calling the computer program, the specific configuration of the processing method for circuit reliability can be referred to the above-mentioned embodiments. Since the electronic device adopts all the technical solutions of all the above-mentioned embodiments, it has at least all the inventive effects of the technical solutions of the above-mentioned embodiments, and therefore the description will be omitted here.

[0212] The above describes in detail the embodiments of the present application. The principles and embodiments of the present application are explained by applying specific examples, and the explanation of the above embodiments is intended only to facilitate understanding of the method and core idea of ​​the present application. Furthermore, those skilled in the art may modify the specific embodiments and application scope according to the idea of ​​the present application. Therefore, the description in this specification should not be construed as limiting the present application.

Claims

1. Obtaining a failure rate for each element in a given circuit and a failure coefficient corresponding to each said element; determining an expected failure value for each of the elements based on the failure rate of each of the elements and a failure coefficient corresponding to each of the elements; comparing the plurality of failure expectancies to determine elements awaiting repair in the predetermined circuit, and reducing the failure expectancy of the elements awaiting repair based on the failure coefficients of the elements awaiting repair; Processing methods for circuit reliability.

2. the elements include a first element and a second element; Obtaining a failure rate for each element in a given circuit and a failure coefficient corresponding to each said element includes: obtaining a failure rate of each first element in a predetermined circuit and a failure coefficient corresponding to each of the first elements; determining an expected failure value for each of the elements based on a failure rate for each of the elements and a failure coefficient corresponding to each of the elements, determining an expected failure value for each of the first elements based on a failure rate of each of the first elements and a failure coefficient corresponding to each of the first elements; Comparing the plurality of expected failure values ​​to determine elements awaiting repair in a predetermined circuit, and reducing the expected failure value of the elements awaiting repair based on the failure coefficients of the elements awaiting repair, comparing a plurality of the failure expectation values ​​to determine a first element awaiting correction in a predetermined circuit as a target first element, the target first element being the element awaiting correction, and replacing the first element with a second element based on a failure coefficient of the target first element, the failure coefficient of the second element being smaller than the failure coefficient of the first element; The method for processing circuit reliability according to claim 1 .

3. Obtaining a fault coefficient corresponding to each first element in a given circuit includes: Obtaining all failure states present in each of the first elements and a failure rate corresponding to each failure state based on a predetermined standard failure mode; acquiring a circuit connection scheme in the predetermined circuit of each of the first elements, and determining a plurality of target fault conditions that exist when the first elements are operating based on the circuit connection scheme; determining a failure coefficient of the first element based on a sum of failure rates of the plurality of target failure conditions corresponding to each of the first elements; The processing method for circuit reliability according to claim 2.

4. Replacing the first element with a second element based on a failure coefficient of the first element includes: acquiring a plurality of types of target fault conditions corresponding to the fault coefficients of the target first element; determining the second element to be replaced based on a plurality of target failure situations remaining after removing one or more target failure situations from the plurality of target failure situations; The processing method for circuit reliability according to claim 3.

5. The target first element is an optical Mos transistor, and the second element is a relay, and determining the second element to be replaced based on a plurality of target failure situations remaining after removing one or more target failure situations from the plurality of target failure situations includes: determining, if the first element is a MOS transistor, that a target fault condition of the optical MOS transistor includes at least one of a shift of the switching transistor and an open circuit of the switching transistor; determining an element in which the target fault condition does not include one of the shift of the switching transistor and the open circuit of the switching transistor as a relay, and designating the relay as a second element; The processing method for circuit reliability according to claim 4.

6. Replacing the first element with a second element based on a failure condition of the first element at a failure coefficient, sorting the failure rates of the target first element corresponding to the plurality of target failure situations in descending order, and obtaining a sorted queue; According to the order of the queue, the target failure situation corresponding to the failure rate higher than a predetermined ranking is set as the target failure situation waiting for correction; determining the second element to be replaced based on the failure rates of the plurality of target failure conditions after lowering one or more target failure conditions to be fixed in the target failure conditions to be fixed, The processing method for circuit reliability according to claim 3.

7. After comparing the plurality of the failure expectation values ​​to determine a first element to be repaired in the predetermined circuit, and replacing the first element with a third element based on the failure rate of the target first element, wherein the failure rate of the third element is lower than the failure rate of the first element. The processing method for circuit reliability according to claim 2.

8. After determining an expected failure value of each of the first elements based on the failure rate of each of the first elements and the failure coefficient corresponding to each of the first elements, Obtaining a total expected failure value of the predetermined circuit based on the expected failure value, the failure rate, and the failure coefficient corresponding to each of the first elements; determining whether to modify the predetermined circuit based on a relationship between a total expected failure value of the predetermined circuit and an expected threshold value; The processing method for circuit reliability according to claim 2.

9. The circuit in which the first element is replaced with the second element includes a first insulation inspection circuit, and the first insulation inspection circuit includes: a first resistor and a second resistor, a first terminal of the first resistor being connected to a first terminal of a grounding resistor of a positive bus, a second terminal of the first resistor being connected to a first terminal of the second resistor, and a second terminal of the second resistor being connected to a first terminal of a grounding resistor of a negative bus; a third resistor, a first terminal of which is electrically connected to a first terminal of a grounding resistor of a positive bus and a first terminal of the first resistor, and a second terminal of which is connected to a second terminal of the first resistor and a first terminal of the second resistor, respectively; a first switching transistor and a second switching transistor, wherein a first terminal of the second switching transistor is connected to the second terminal of the third resistor, a second terminal of the second switching transistor is connected to the first terminal of the first switching transistor, the second terminal of the first resistor, and the first terminal of the second resistor, respectively, and the second terminal of the first switching transistor is grounded; The processing method for circuit reliability according to claim 2.

10. When the first insulation inspection circuit is in a first operating state, the first switching transistor is turned on and the second switching transistor is turned off; When the first insulation inspection circuit is in a second operating state, the first switching transistor and the second switching transistor are both turned on. The method for processing circuit reliability according to claim 9.

11. the first switching transistor and the second switching transistor are relays; The method for processing circuit reliability according to claim 10.

12. The relay is sealed in a plastic manner in accordance with vehicle standards.

12. The method for processing circuit reliability according to claim 11.

13. When the first insulation inspection circuit is in a first operating state, the fault states of the first resistor, the second resistor and the third resistor all include an open circuit of the resistor and a parameter shift of the resistor, the fault state of the first switching transistor includes a functional failure of the relay, and the fault state of the second switching transistor includes a short circuit of the relay; When the first insulation inspection circuit is in a second operating state, the fault states of the first resistor, the second resistor, and the third resistor all include an open circuit of the resistor and a parameter shift of the resistor, and the fault states of the first switching transistor and the second switching transistor all include a functional failure of the relay. The method for processing circuit reliability according to claim 11.

14. In a fault condition of the first switching transistor and the second switching transistor, a short circuit rate of the relay is less than a functional failure rate of the relay. The method for processing circuit reliability according to claim 13.

15. In a fault state of the first resistor, the second resistor, and the third resistor, a rate of open circuit of the resistors is greater than a rate of parameter shift of the resistors. The method for processing circuit reliability according to claim 13.

16. the first resistor, the second resistor, and the third resistor are carbon film resistors; The method for processing circuit reliability according to claim 9.

17. Comparing the plurality of expected failure values ​​to determine elements awaiting repair in a predetermined circuit, and reducing the expected failure value of the elements awaiting repair based on the failure coefficients of the elements awaiting repair, comparing the plurality of expected failure values ​​to determine a target element in the predetermined circuit that is waiting to be corrected, and changing a connection method of the target element based on the failure coefficient of the target element to reduce the expected failure value of the target element; The method for processing circuit reliability according to claim 1 .

18. Obtaining the fault coefficients corresponding to each element in a given circuit includes: Obtaining all failure states present in each of the elements and a failure rate corresponding to each failure state based on a predetermined standard failure mode; acquiring a circuit connection scheme for each of the elements in the predetermined circuit, and determining a plurality of target fault conditions that exist when the elements are operating based on the circuit connection scheme; determining a failure coefficient of the element based on a sum of failure rates of the plurality of target failure conditions corresponding to each of the elements; 18. The method for processing circuit reliability according to claim 17.

19. Comparing the plurality of expected failure values ​​includes: sorting the plurality of failure expectations in descending order to obtain a sorted queue; Determine whether to modify the elements based on the connection method of the elements corresponding to the expected failure value in order according to the queue order, thereby determining a predetermined number of the target elements to be modified; and / or and determining, according to the order of the queue, the element corresponding to the failure expectancy value higher than a predetermined ranking as the target element.

18. The method for processing circuit reliability according to claim 17.

20. Specifically, changing the connection method of the target element based on the failure coefficient of the target element includes: changing a connection method between the target element and surrounding elements based on a failure rate of the target failure state of the element; 20. The method for processing circuit reliability according to claim 19.

21. After determining the expected failure value of each of the elements based on the failure rate of each of the elements and the failure coefficient corresponding to each of the elements, Obtaining a total expected failure value of the predetermined circuit based on the expected failure value, the failure rate, and the failure coefficient corresponding to each of the elements; determining whether to modify the predetermined circuit based on a relationship between a total expected failure value of the predetermined circuit and an expected threshold value; 18. The method for processing circuit reliability according to claim 17.

22. The number of the desired thresholds is plural, and the plural desired thresholds include a first desired threshold and a second desired threshold, and the first desired threshold is greater than the second desired threshold, and determining whether to repair the predetermined circuit based on a relationship between the total failure expectancy of the predetermined circuit and the desired threshold is If the total failure expectancy is greater than the first desired threshold, modifying the plurality of target elements in the predetermined circuit based on a difference between the total failure expectancy and the first desired threshold; If the total expected failure value is less than the first expected failure value threshold and greater than the second expected failure value threshold, determining to repair one of the target elements in the predetermined circuit based on a relationship between the expected failure value of each of the elements and a predetermined element threshold corresponding to the element; not modifying the predetermined circuit if the total failure expectancy is less than the second expected threshold.

22. The method for processing circuit reliability according to claim 21.

23. determining whether to modify the predetermined circuit based on a relationship between a total expected failure value of the predetermined circuit and an expected threshold value; modifying the given circuit if the total expected failure value is greater than the expected threshold; If the total failure expectancy is less than or equal to the desired threshold, determining whether there are any instances where the failure expectancy of the device is greater than a predetermined device threshold corresponding to the device; modifying said predetermined circuit if present; and if not present, not modifying the predetermined circuit.

22. The method for processing circuit reliability according to claim 21.

24. After determining the expected failure value of each of the elements based on the failure rate of each of the elements and the failure coefficient corresponding to each of the elements, automatically generating a plurality of modified circuits based on the target device, and obtaining a total expected fault value for each of the modified circuits; sorting the plurality of total fault expectancies and determining one or more target circuits according to the sorted order; 18. The method for processing circuit reliability according to claim 17.

25. The predetermined circuit in which the connection method of the target element is changed includes a second insulation inspection circuit, and the second insulation inspection circuit is a fourth resistor, a fifth resistor, and a sixth resistor, wherein a first terminal of the fourth resistor is connected to a first terminal of a grounding resistor of a positive bus, a second terminal of the fifth resistor is connected to a first terminal of the sixth resistor, and a second terminal of the sixth resistor is connected to a second terminal of a grounding resistor of a negative bus; a seventh resistor, the second terminal of which is connected to the first terminal of the fifth resistor; a fifth switching transistor and a sixth switching transistor, a first terminal of the fifth switching transistor being connected to the second terminal of the sixth switching transistor, the second terminal of the fifth resistor, and the second terminal of the seventh resistor, respectively, a second terminal of the fifth switching transistor being grounded, and a first terminal of the sixth switching transistor being connected to the second terminal of the fourth resistor; a seventh switching transistor, a first terminal of the seventh switching transistor being connected to the second terminal of the fourth resistor and the first terminal of the sixth switching transistor, and a second terminal of the seventh switching transistor being connected to the first terminal of the seventh resistor; 18. The method for processing circuit reliability according to claim 17.

26. When an open circuit fault occurs in the seventh switching transistor, the fifth switching transistor and the seventh switching transistor form an unbalanced check bridge; When the unbalanced check bridge is in a first operating state, the fifth switching transistor is turned on and the sixth switching transistor is turned off; When the unbalanced check bridge is in a second working state, the fifth switching transistor and the sixth switching transistor are both turned on.

26. The method for processing circuit reliability according to claim 25.

27. When the unbalanced check bridge is in a first working state, the fault states of the fourth resistor, the fifth resistor, the sixth resistor and the seventh resistor all include an open circuit of the resistor and a parameter shift of the resistor; the fault state of the fifth switching transistor includes an open circuit of the switching transistor and a parameter shift of the switching transistor; the fault state of the sixth switching transistor includes a parameter shift of the switching transistor; and the fault state of the seventh switching transistor includes a short circuit of the switching transistor; When the unbalanced check bridge is in a second working state, the fault states of the fourth resistor, the fifth resistor, the sixth resistor and the seventh resistor all include an open circuit of the resistor and a parameter shift of the resistor; the fault state of the fifth switching transistor all include an open circuit of the switching transistor and a parameter shift of the switching transistor; and the fault states of the sixth switching transistor and the seventh switching transistor all include a short circuit of the switching transistor and a parameter shift of the switching transistor.

27. The method for processing circuit reliability according to claim 26.

28. When an open circuit fault occurs in the sixth switching transistor, the fifth switching transistor and the seventh switching transistor form a balanced check bridge; When the balanced check bridge is in a first operating state, the fifth switching transistor is turned on and the seventh switching transistor is turned off; When the balanced check bridge is in a second working state, the fifth switching transistor and the seventh switching transistor are both turned on.

26. The method for processing circuit reliability according to claim 25.

29. When the balanced check bridge is in a first working state, the fault states of the fourth resistor, the fifth resistor, the sixth resistor and the seventh resistor all include an open circuit of the resistor and a parameter shift of the resistor; the fault state of the fifth switching transistor includes an open circuit and a parameter shift; the fault state of the sixth switching transistor includes a short circuit of the switching transistor; and the fault state of the seventh switching transistor includes a parameter shift of the switching transistor; When the balanced check bridge is in a second working state, the fault states of the fourth resistor, the fifth resistor, the sixth resistor and the seventh resistor all include an open circuit of the resistor and a parameter shift of the resistor; the fault state of the fifth switching transistor all include an open circuit of the switching transistor and a parameter shift of the switching transistor; and the fault states of the sixth switching transistor and the seventh switching transistor all include a short circuit of the switching transistor and a parameter shift of the switching transistor.

30. The method for processing circuit reliability according to claim 28.

30. In a fault state of the fourth resistor, the fifth resistor, the sixth resistor, and the seventh resistor, the percentage of open circuits of the resistors is 60%, and the percentage of parameter shifts of the resistors is 40%.

30. The method for processing circuit reliability according to claim 29.

31. In a fault state of the fifth switching transistor, the sixth switching transistor, and the seventh switching transistor, a short circuit rate of the switching transistor is 10%, an open circuit rate of the switching transistor is 50%, and a shift rate of the switching transistor is 40%.

30. The method for processing circuit reliability according to claim 29.

32. the fourth resistor, the fifth resistor, the sixth resistor, and the seventh resistor are carbon film resistors, the fifth switching transistor, the sixth switching transistor, and the seventh switching transistor are optical MOSs; 26. The method for processing circuit reliability according to claim 25.

33. A parameter acquisition module is used to acquire the failure rate of each element in a predetermined circuit and the failure coefficient corresponding to each said element; a processing module used for determining a failure expectancy of each of the elements based on the failure rate of each of the elements and a failure coefficient corresponding to each of the elements; an implementation module used to compare a plurality of the failure expectancies to determine elements awaiting repair in a predetermined circuit, and reduce the failure expectancies of the elements awaiting repair based on the failure coefficients of the elements awaiting repair; Processing equipment for circuit reliability.

34. a computer program stored therein, the computer program causing the computer to perform the processing method relating to circuit reliability according to any one of claims 1 to 32 when the computer program is executed by the computer; storage medium.

35. a processor and a memory, wherein a computer program is stored in the memory, and the processor executes the processing method relating to circuit reliability according to any one of claims 1 to 32 by calling the computer program; electronic equipment.

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