Reusing branch information queue entries for multiple instances of a predicted control instruction within a captured loop in a processor - Patents.com

Abstract

Reusing branch information queue entries for multiple instances of a predicted control instruction within a captured loop in a processor, and related methods and computer-readable media. The processor sets and updates branch entries in a branch information queue (BIQ) circuit with branch information in response to speculative predictions made for the predicted control instruction. The branch information is used to make and track flow path predictions for the predicted control instruction and to verify such predictions against their resolutions for possible misprediction recovery. The processor is configured to reuse the same branch entry in the BIQ circuit for each instance of the predicted control instruction. This saves space in the BIQ circuit, thereby allowing for the use of a smaller BIQ circuit, thus saving area and power consumption. The branch information for each instance of the predicted control instruction within the loop remains consistent.

Description

[Technical Field]

[0001] The techniques of this disclosure relate generally to speculative prediction of control flow computer instructions (“instructions”) in a processor's instruction pipeline, and more specifically to misprediction recovery after speculative prediction of a control flow instruction is resolved as a misprediction at runtime. [Background technology]

[0002] Instruction pipelining is a processing technique that can increase the throughput of computer instructions executed by a processor by dividing the processing of each instruction into a series of steps. These steps are performed in an execution pipeline consisting of multiple stages. Optimal processor performance can be achieved if all stages in the execution pipeline can process instructions in parallel and sequentially as the instructions are ordered in the instruction pipeline. However, structural hazards can occur in an instruction pipeline, in which the next instruction cannot be executed without producing an erroneous computational result. For example, a control hazard can occur as a result of the execution of a prediction control instruction. One example of a prediction control instruction that can cause a control hazard is a conditional branch instruction. A prediction control instruction, such as a conditional branch instruction, can redirect the flow path of instruction execution based on a condition evaluated when the condition of the control branch instruction is executed. Another example of a prediction control instruction that can cause a structural hazard is an indirect branch instruction with an indirect branch target (address) stored in a memory location that needs to be loaded. The processor may have to stall fetching additional instructions until the prediction control instruction has executed, resulting in reduced processor performance and increased power consumption.

[0003] One technique for maximizing processor performance to reduce stalls resulting from processing predictive control instructions involves using a prediction circuit. A prediction circuit can be used in a processor to speculatively predict the outcome (e.g., branch condition or branch target address) of a predictive control instruction that will control an instruction execution flow path. For example, a prediction of whether a conditional branch instruction will be taken may be based on the branch prediction history of previous conditional branch instructions. When a control flow instruction eventually reaches the execute stage of the instruction pipeline and is executed, the destination address of the resulting control flow instruction is verified by comparing it with the previously predicted destination address when the control flow instruction was fetched. If the predicted and actual destination addresses match, this means that a correct prediction was made, and no delay occurs in instruction execution because the subsequent instruction at the destination address was correctly fetched and will already be in the instruction pipeline when the conditional branch instruction reaches the execute stage of the instruction pipeline. However, if the predicted and actual destination addresses do not match, misprediction recovery occurs, which may require flushing of younger instructions and refetching of instructions in the correctly resolved instruction flow path. In either case, the branch condition history can be "trained" to track and maintain resolved outcomes of the prediction control instructions determined at runtime to contribute to further predictions of such prediction control instructions. A misprediction of a prediction control instruction can result in a flush of the instruction pipeline and redirection of instruction pipeline fetch units to fetch new instructions starting from the destination address. However, a misprediction results in a delay called a "misprediction penalty," which reduces instruction pipeline throughput performance. Additionally, stages in the execution pipeline may remain idle until the newly fetched instruction advances through the instruction pipeline to the execution stage, thereby reducing performance. Mispredicting the processing of instructions in a processor can be costly in terms of delays and reduced performance.

[0004] In conventional processors, when a prediction is made for a prediction control instruction, the processor is also configured to update a branch information queue associated with the prediction control instruction. The branch information queue is also referred to as a branch reorder buffer. The predicted branch instruction is assigned a branch entry in the branch information queue, and the branch prediction is updated in the branch entry in the branch information queue associated with the prediction control instruction. When the prediction control instruction is resolved at runtime, the resolved branch outcome is also updated in the branch entry in the branch information queue associated with the prediction control instruction. The information stored in the branch information queue of the prediction control instruction is used to perform branch prediction training. The information stored in the branch information queue of the prediction control instruction can be used to nullify the impact of a mispredicted prediction control instruction on the branch prediction history so that the mispredicted prediction control instruction does not adversely affect future predictions of the prediction control instruction. In this regard, the branch prediction history is updated in response to a flush event generated in response to a mispredicted prediction control instruction so that future predictions are based on the actual resolved condition of the prediction control instruction to improve prediction accuracy. Additionally, if the predictive control instruction is part of a loop in which multiple instances of the predictive control instruction appear for multiple iterations of the loop, a branch entry is created in the branch information queue for each iteration of the branch instruction so that the branch instruction prediction and its resolution are tracked for each iteration of the branch instruction in each iteration of the loop. Summary of the Invention

[0005] Example aspects disclosed herein include reusing branch information queue entries for multiple instances of a predictive control instruction within a captured loop in a processor. Related methods and computer-readable media are also disclosed. The processor includes instruction processing circuitry configured to fetch computer program instructions (“instructions”) into an instruction stream within an instruction pipeline for processing and execution. The processor is configured to speculatively predict the condition or destination of the fetched predictive control instruction (e.g., a branch instruction) to fetch a younger instruction within the predicted instruction flow path for processing (referred to as speculatively predicting the predictive control instruction). In response to the speculative prediction, the processor is configured to set and update a branch entry in a branch information queue (BIQ) with branch information associated with the predictive control instruction. For example, the branch information can be used in combination with a branch prediction history to make and track flow path predictions for the predictive control instruction and to verify such predictions against resolved conditions or destinations at runtime. Misprediction recovery measures can be taken in response to a detected misprediction, such as flushing and refetching instructions in the correct instruction flow path. The branch information stored in the BIQ circuit can also be used to nullify the impact of a mispredicted branch prediction control instruction on the branch prediction history as part of misprediction recovery, so that the misprediction does not adversely affect future predictions of the prediction control instruction. In an exemplary embodiment, to avoid the need to set up a separate branch entry in the BIQ circuit for each instance of a prediction control instruction in a loop for each iteration of the loop, the processor is configured to reuse the same branch entry in the BIQ circuit for each instance of a prediction control instruction. This is useful because the branch information for each instance of a prediction control instruction in a loop remains consistent for each iteration of the loop. This saves space in the BIQ circuit, thereby allowing a smaller BIQ circuit to be used, thereby saving area and power consumption.

[0006] In an exemplary embodiment, the entry in the BIQ circuit also includes an instance indicator so that the processor knows how many instances of the predicted control instruction in the loop for which branch information needs to be maintained. The instance indicator is updated for each instance of the predicted control instruction in the branch entry in the BIQ circuit associated with the predicted control instruction to track the number of instances of the predicted control instruction in the loop. The instance indicator may be, for example, a counter that is incremented for each new instance predicted and decremented for each instance resolved at runtime. In response to execution of an instance of the predicted control instruction in the loop, the instance indicator and its associated branch entry in the BIQ circuit are accessed so that resolution of an earlier prediction can be verified. When the instance indicator indicates that resolution of each instance of the predicted control instruction in the loop has been verified (by the instance indicator indicating that zero (0) instances remain unresolved), the branch entry in the BIQ circuit can be deallocated and reallocated for a new predicted control instruction encountered in the instruction stream.

[0007] In this regard, in one exemplary aspect, a processor is provided. The processor includes an instruction processing circuit and a branch information queue (BIQ) circuit including a plurality of branch entries and an instance indicator, each configured to store branch information associated with a predictive control instruction. The instruction processing circuit is configured to fetch a plurality of instructions into an instruction pipeline as an instruction stream. The instruction processing circuit is further configured to store first branch information associated with a first instance of a first predictive control instruction among the plurality of instructions in a first branch entry associated with the first predictive control instruction among the plurality of branch entries in the BIQ circuit. The instruction processing circuit is further configured to speculatively predict the first instance of the first predictive control instruction based on the first branch information stored in the first branch entry. The instruction processing circuit is further configured to detect a first iteration of a first loop including a second instance of the first predictive control instruction in the instruction stream. In response to detecting the first iteration of the first loop in the instruction stream, the instruction processing circuitry is further configured to update a first instance indicator in the first branch entry to indicate a second instance of the first predictive control instruction.

[0008] In another example aspect, a method for reusing branch information for multiple instances of a predictive control instruction in a captured loop in a processor is provided. The method includes fetching multiple instructions into an instruction pipeline as an instruction stream. The method also includes storing first branch information associated with a first instance of a first predictive control instruction of the multiple instructions in a first branch entity of multiple branch entities in a branch information queue (BIQ) circuit, the first branch entry being associated with the first predictive control instruction. The method also includes speculatively predicting a first condition of the first instance of the first predictive control instruction based on the first branch information stored in the first branch entry. The method also includes detecting a first iteration of a first loop including a second instance of the first predictive control instruction in the instruction stream. The method also includes updating a first instance indicator in the first branch entry to indicate the second instance of the first predictive control instruction in response to detecting the first iteration of the first loop in the instruction stream.

[0009] In another example aspect, a non-transitory computer-readable medium having computer-readable instructions stored thereon is provided that, when executed by a processor, cause the processor to fetch a plurality of instructions into an instruction pipeline as an instruction stream, store first branch information associated with a first instance of a first prediction control instruction among the plurality of instructions in a first branch entry associated with the first branch control instruction among a plurality of branch entries in a branch information queue (BIQ) circuit, speculatively predict the first instance of the first prediction control instruction based on the first branch information stored in the first branch entry, detect a first iteration of a first loop including a second instance of the first prediction control instruction in the instruction stream, and update a first instance indicator in the first branch entry to indicate the second instance of the first prediction control instruction in response to detecting the first iteration of the first loop in the instruction stream.

[0010] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects of the present disclosure after reading the following detailed description of the preferred embodiments in connection with the accompanying drawing figures. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several aspects of the present disclosure and, together with the description, serve to explain the principles of the disclosure. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 illustrates an example processor including an example instruction processing circuit including a speculative prediction circuit configured to make speculative predictions for fetched predictive control instructions based on speculative prediction history and update branch information in a branch information queue (BIQ) circuit used to make, track, and resolve such predictions, wherein the processor is also configured to reuse entities in the BIQ circuit for multiple instances of the predictive control instructions within a captured loop in the processor. [Figure 2] 2 illustrates an example instruction stream including a loop of instructions that are fetched and processed in multiple iterations within the instruction processing circuitry of FIG. 1. [Figure 3] 1 illustrates an exemplary BIQ circuit that may be included in the processor of FIG. 1 and configured to store branch information for fetched and speculatively predicted predicted control instructions within the loop in FIG. 2, wherein each branch entry within the BIQ circuit includes an instance indicator field configured to store an instance indicator indicating the number of instances for which the predicted control instruction within the loop was fetched and speculatively predicted, such that such an entry may be reused for multiple instances of the predicted control instruction within the loop. [Figure 4A] 2 is a diagram of an example predicted branch recovery trace record that may be included in the processor of FIG. 1, showing predicted control instructions in fetch order and example speculative predictions for each predicted control instruction. [Figure 4B]2 is a diagram of an example actual branch recovery trace record that may be included in the processor of FIG. 1 , illustrating predicted control instructions and their actual resolution at execution time. [Figure 4C] 2A-2C illustrate example speculative and non-speculative histories that may be included in the processor of FIG. 1 and that are used by the speculative prediction circuitry of FIG. 1 to perform speculative predictions. [Figure 4D] A figure showing an example speculative history based on the speculative prediction of the prediction control instruction of Figures 4A and 4B before misprediction recovery used by the speculative prediction circuit in the prediction control instruction to make a speculative prediction, and the speculative history restored as a result of the misprediction recovery. [Figure 5] 10 is a flowchart illustrating an example process of the processor of FIG. 1 speculatively predicting a fetched predicted control instruction and reusing entries in a BIQ circuit for multiple instances of the speculatively predicted predicted control instruction within a captured loop. [Figure 6] FIG. 2 illustrates an example loop buffer circuit that may be provided in the processor of FIG. 1 , including a loop detection circuit configured to detect a loop in an instruction stream in an instruction pipeline, a loop capture circuit configured to capture instructions for the detected loop, and a loop re-execution circuit configured to re-execute such optimized loop based on the captured loop through loop optimization in the instruction pipeline. [Figure 7] 1 is a block diagram illustrating an example processor-based system including a processor and an instruction processing circuit having one or more instruction pipelines for processing computer instructions for execution, wherein the processor is configured to speculatively predict fetched predicted control instructions and to reuse entries in a BIQ circuit for multiple instances of the speculatively predicted predicted control instructions in a captured loop. DETAILED DESCRIPTION OF THE INVENTION

[0012] Embodiments disclosed herein include reusing a branch information queue for multiple instances of a predictive control instruction within a captured loop in a processor. Related methods and computer-readable media are also disclosed. The processor includes instruction processing circuitry configured to fetch computer program instructions (“instructions”) into an instruction stream within an instruction pipeline for processing and execution. The processor is configured to speculatively predict the condition or destination of a fetched predictive control instruction (e.g., a branch instruction) to fetch a younger instruction within the predicted instruction flow path for processing (referred to as speculatively predicting the predictive control instruction). In response to the speculative prediction, the processor is configured to set and update a branch entry in a branch information queue (BIQ) with branch information associated with the predictive control instruction. For example, the branch information can be used in combination with a branch prediction history to make and track flow path predictions for the predictive control instruction and to verify such predictions against the resolution (e.g., its condition or branch destination) of the predictive control instruction at runtime. Misprediction recovery measures can be taken in response to a detected misprediction, such as flushing and refetching instructions in the correct instruction flow path. The branch information stored in the BIQ circuit can also be used to nullify the impact of a mispredicted branch prediction control instruction on the branch prediction history as part of misprediction recovery, so that the misprediction does not adversely affect future predictions of the prediction control instruction. In an exemplary embodiment, to avoid the need to set up a separate branch entry in the BIQ circuit for each instance of a prediction control instruction in a loop for each iteration of the loop, the processor is configured to reuse the same branch entry in the BIQ circuit for each instance of a prediction control instruction. This is useful because the branch information for each instance of a prediction control instruction in a loop remains consistent for each iteration of the loop. This saves space in the BIQ circuit, thereby allowing a smaller BIQ circuit to be used, thus saving area and power consumption.

[0013] In this regard, FIG. 1 is a diagram of an exemplary processor 100 that is part of a processor-based system 102. The processor 100 may, by way of non-limiting example, be an in-order processor or an out-of-order processor (OoP). As described in more detail below, the processor 100 includes exemplary instruction processing circuitry 104, including speculative prediction circuitry 106 configured to make speculative predictions for predicted control instructions 108F-C fetched as part of a fetched instruction 108F in an instruction stream 110 based on speculative prediction history for the predicted control instructions 208F-C. The processor 100 is configured to update branch information in a branch information queue (BIQ) circuit 112 that is used to make, track, and resolve such predictions. As also described in more detail below, the processor 100 is also configured to reuse entries in the BIQ circuit 112 for multiple instances of the predicted control instructions 208F-C within captured loops from the instruction stream 110.

[0014] 1, the processor 100 of this embodiment includes instruction processing circuitry 104, which includes instruction fetch circuitry 114 configured to fetch instructions 108 from an instruction memory 116. The instruction memory 116 may, by way of example, be provided in or part of a cache memory or system memory in the processor-based system 102. The instruction fetch circuitry 114 of this embodiment is configured to provide instructions 108 as fetched instructions 108F to the instruction pipeline IP as an instruction stream 110 in the instruction processing circuitry 104, which are decoded in a decode circuitry 118. The decode circuitry 118 decodes the fetched instructions 108F as decoded instructions 208D, which are processed before ultimately being executed by the execution circuitry 120. Product values ​​produced by the execution circuitry 120 due to execution of the decoded instructions 108D are committed (i.e., written back) to memory locations indicated by the destinations of the decoded instructions 108D. This storage location may be, for example, memory 122 of processor-based system 102 or physical registers P0-P in physical register file (PRF) 124. XIt can be said that:

[0015] 1, after fetched instruction 108F is decoded as decoded instruction 108D, decoded instruction 108D is provided to rename / allocate circuitry 126 within instruction processing circuitry 104, in this embodiment. Rename / allocate circuitry 126 is configured to determine whether any register names in decoded instruction 108D need to be renamed to resolve register dependencies that would prevent parallel or out-of-order processing. Rename / allocate circuitry 126 allocates the logical source register operands and / or destination register operands of decoded instruction 108D to available physical registers P0-P1 within PRF 124. X The RMT 128 is also configured to consult a register map table (RMT) 128 to write to a respective logical register R0-R1. P The mapping entries are mapped to (i.e., associated with) physical registers P0 to P1 in the PRF 124. X Each physical register P0 to P124 is configured to store information in the form of an address pointer pointing to the physical register P0 to P124. X includes data entries 130(0)-130(X) configured to store data for source and / or destination register operands of decoded instruction 108D.

[0016] The processor 100 also includes a speculative prediction circuit 106 configured to speculatively predict values ​​associated with operations in the processor 100. For example, the speculative prediction circuit 106 can be configured to predict fetched prediction control instructions 108F-C, such as conditional branch instructions or indirect branch instructions whose branch targets are stored in loaded memory addresses, which will determine in which flow path the next instruction 108 will be fetched by the instruction fetch circuit 114 for processing. For example, if the prediction control instructions 108F-C are conditional branch instructions, the speculative prediction circuit 106 can predict whether the condition of the conditional branch instructions 108F-C will later be resolved as “taken” or “not taken” in the execution circuit 120. In this embodiment, the speculative prediction circuit 106 is configured to examine a prediction history indicator 132 to make the speculative prediction. In one embodiment, the prediction history indicator 132 includes a global history of previous predictions. The prediction history indicator 132 can be hashed using the program counter (PC) of the predicted current predicted control instruction 108F-C to generate a prediction index for the prediction table circuit 134 in this embodiment. The prediction table circuit 134 includes a prediction value (e.g., a counter value) that can be mapped to the predicted control instruction 108F-C based on the prediction index assigned to the predicted control instruction 108F-C. As described in more detail below, the prediction index of the predicted control instruction 108F-C can be stored in the BIQ circuit 112. The indexed prediction value in the prediction table circuit 134 is used to generate a current speculative prediction for the predicted control instruction 108F-C. In this manner, the prediction of the newly fetched predicted control instruction 108F-C is based on recent and past resolutions of the predicted control instruction in the instruction processing circuit 104. This prediction value will be used by the instruction fetch circuit 114 to determine whether to fetch the next instruction 108 that follows (i.e., is younger than) the conditional branch instruction 108F-C in the taken or not-taken instruction flow path.

[0017] If the speculatively predicted decoded predictive control instruction 108D is determined to be mispredicted at execution time, the instruction processing circuit 104 can perform misprediction recovery. In this regard, in this embodiment, the execution circuit 120 issues a flush event 136 to the commit / flush circuit 138. The commit / flush circuit 138 is configured to stall the instruction pipeline IP and flush instructions 108F, 108D in the instruction pipeline IP within the instruction processing circuit 104 that are younger than the mispredicted predictive control instruction 108. In this regard, the commit / flush circuit 138 is configured to consult a reorder buffer circuit 140 that stores and maintains the order of the instructions 108F fetched into the instruction pipeline IP. The rename / allocate circuit 126 is configured to insert the decoded instruction 108D into an entry in the reorder buffer circuit 140 as part of the in-order portion of the instruction processing circuit 104 before the decoded instruction 108D is scheduled for execution by the scheduler circuit 143. The scheduler circuit 143 can schedule the decoded instructions 108D out-of-order for execution based on their dependencies and when their source data is available. In this manner, the reorder buffer circuit 140 can be used by the commit / flush circuit 138 to identify instructions 108 for flushing that are younger than the mispredicted predicted control instruction 108. The commit / flush circuit 138 can then instruct the instruction fetch circuit 114 to fetch new instructions 108 in the instruction pipeline IP from the correct instruction flow path of the predicted control instruction 108 based on the resolution of the speculatively predicted decoded predicted control instruction 108D.

[0018] When the mispredicted predicted control instruction 108 is resolved and a flush event 136 is generated, the instruction processing circuit 104 is also configured to update the prediction history indicator 132 and the BIQ circuit 112 as part of prediction training. This is so that previous updates of the prediction history indicator 230 and the BIQ circuit 112 based on the mispredicted predicted control instruction 108 can be invalidated without substantially affecting future predictions of the predicted control instruction 108, including the correct instruction flow path from the mispredicted predicted control instruction 108 after the flush. In this regard, the prediction history indicator 132 is updated in response to the flush event 136 so that future predictions are based on the resolution of the predicted control instruction 108 to improve prediction accuracy. The BIQ circuit 112 is also updated in response to the flush event 136 so that the prediction value at the prediction index in the prediction table circuit 134, which was previously indexed and accessed to predict the mispredicted predicted control instruction 108, is updated (i.e., trained) to record the misprediction. For example, the prediction value at the prediction index in the prediction table circuit 134 can be decremented to indicate the misprediction. The predicted value at a prediction index in prediction table circuit 134 can be incremented to indicate a correct prediction. In this way, for future predictions that access the predicted value at the same prediction index in prediction table circuit 134, the predicted value at a prediction index in prediction table circuit 134 can be used to indicate a prediction (e.g., taken or not taken) and the reliability or strength of such prediction.

[0019] The instructions 108 in the instruction stream 110 in the instruction pipeline IP of FIG. 1 may include loops. A loop is a series of instructions 108 in the instruction stream 110 that iterate (i.e., process) sequentially in a consecutive arrangement. Note that a loop may include additional inner loops. A loop may exist in the instruction stream 110 as a result of a programmed software structure that is compiled into a loop of instructions 108. A loop may also exist in the instruction stream 110 as a result of instructions 108 that are repeated sequentially in the instruction stream 110, even if they are not part of a high-level programmed software structure, such as based on binary instructions resulting from compilation of a high-level programmed software structure. If instructions that are part of a loop are detected when such instructions 108 are processed in the instruction pipeline IP, those instructions 108 may be captured in the instruction stream 110 and re-executed in a processing stage in the instruction pipeline IP without having to refetch and / or re-decode such instructions 108, e.g., for a subsequent iteration of the loop. Thus, a sequence of instructions 108 that is detected and captured as a captured loop may capture one path of the loop and thus appear to be a branchless loop body with no further inner branches. For example, if a loop has alternating conditions that are taken and not taken, two (2) loops may be captured to represent the entire loop.

[0020] In this regard, the instruction processing circuit 104 of FIG. 1 in this embodiment includes a loop buffer circuit 142 for performing loop buffering. The loop buffer circuit 142 is configured to detect a loop 144 in instructions 108 fetched into the instruction pipeline IP as the instruction stream 110 is processed and executed. To avoid or reduce the need to refetch the instructions 108 in the detected loop as processing of the instructions 108 is repeated in the instruction pipeline IP, the loop buffer circuit 142 is configured to capture (i.e., loop buffer) the instructions 108 to be re-executed in the detected loop in response to the detected loop 144. In this regard, the loop buffer circuit 142 is configured to insert (i.e., re-execute) the captured loop instructions 108 into the detected loop 144 in the instruction pipeline IP for an iteration of the loop 144. In this manner, the captured instructions 108 in the loop do not need to be refetched and / or re-decoded, for example, for a subsequent iteration of the loop 144. Thus, loop buffering can save power by not requiring instruction fetch circuitry 114 to re-fetch instructions 108 in a detected loop 144 for subsequent iterations of the loop 144. Loop buffering can also save power by not requiring decode circuitry 118 to re-decode instructions 108 in a detected loop 144 for subsequent iterations of the loop.

[0021] 2 is an example instruction stream 110 of fetched instructions 108F in processor 100 of FIG. 1, illustrating an example loop present within instruction stream 110. As shown in FIG. 1, instruction stream 110 includes three (3) iterations 146(0) through 146(2) of loop 144. Loop 144 in this example consists of instructions I0 through I3 as part of instruction 108, each of which includes a load instruction I0, an add instruction I1, a compare instruction I2, and a branch instruction I3. These instructions I0 through I3 within loop 144 are fetched into instruction stream 110 three (3) times in three (3) iterations 146(0) through 146(2) of loop 144, i.e., instructions I0 through I3 within loop 144 are repeated three (3) times in instruction stream 110. 3, in response to a branch instruction I3 (as a prediction control instruction) being fetched into instruction stream 110 in instruction pipeline IP of FIG. 1 for a first instance of branch instruction I3 in a first iteration 146(0) of loop 144, a branch entry 300(0) among a plurality of branch entries 300(0)-300(B) is allocated for each branch instruction I3 in BIQ circuit 112 in each loop iteration 146(0)-146(2) of loop 144. As described in more detail below, processor 100 is configured to store branch information 302(0)-302(B) in each allocated branch entry 300(0)-300(B) in BIQ circuit 112 to be used to make speculative predictions for prediction control instructions 108 associated with branch entries 300(0)-300(B). In this example, branch entry 300(0) will contain branch information 302(2) associated with branch instruction I3 in loop 144 that is used by speculative prediction circuitry 106 of FIG. 1 to speculatively predict branch instruction I3 to determine which flow path will fetch instructions following branch instruction I3.

[0022] 2 and 3, when branch instruction I3 repeats within instruction stream 110 in second iteration 146(1) of loop 144, loop buffer circuit 142 is configured to detect repeated load instruction I0 as a second instance of load instruction I0. Loop buffer circuit 142 is configured to detect add, compare, and branch instructions I1-I3 repeated in second iteration 146(1) of loop 144 as second instances of such instructions I1-I3. In response to loop buffer circuit 142 detecting loop 144 by detecting second repeated instances of instructions I0-I3 in second iteration 146(1), loop buffer circuit 142 detects instructions I0-I3 as loop instructions I0-I3 as part of detected loop 144. Loop buffer circuit 142 is configured to capture loop instructions I0-I3 as part of captured loop 144. In this manner, as described above in FIG. 1, loop buffer circuit 142 is configured to insert (i.e., re-execute) captured loop instructions I0-I3 from detected loop 144 into instruction pipeline IP for iterations of loop 144, including third iteration 146(2) of loop 144 shown in FIG. 2. In this manner, loop instructions I0-I3, 108 in the captured loop do not need to be refetched and / or re-decoded, for example, for subsequent iterations of loop 144. Thus, loop buffering may save power by not requiring instruction fetch circuit 114 of FIG. 1 to refetch instructions 108, I0-I3 in detected loop 144 for subsequent iteration 146 of loop 144. Loop buffering may also save power by not requiring decode circuit 118 of FIG. 1 to re-decode instructions 108, I0-I3 in detected loop 144 for subsequent iterations of the loop.

[0023] 2, because loop 144 is a repetition of the same instructions I0-I3 that are successively repeated within instruction stream 110, the branch information for each instance of branch instruction I3 in each respective iteration 146(0)-146(2) of loop 144 within the loop remains consistent. Thus, in this example, to avoid having to establish a separate branch entry 300 in BIQ circuit 112 for each instance of branch instruction I3 for each iteration 146(2)-146(2) of loop 144, processor 100 of FIG. 1 is configured to reuse the same branch entry 300(0) in BIQ circuit 112 for each instance of branch instructions I0-I3 for each iteration 146(2)-146(2) of loop 144. This saves space in BIQ circuit 112, thereby allowing a smaller BIQ circuit 112 to be used, thus saving area and power consumption in processor 100.

[0024] 3 also illustrates an example of the state of BIQ circuit 112 with branch information 302(0) set in branch entry 300(0) for branch instruction I3 in instruction stream 110 of FIG. 2. As shown in FIG. 3, BIQ circuit 112 includes multiple branch entries 300(0)-300(B), each configured to store branch information 302(0)-302(B) for a predicted control instruction 108 fetched and processed in instruction pipeline IP. The branch information 302(0)-302(B) in BIQ circuit 112 is maintained by speculative prediction circuit 106 of FIG. 1 in this example. Branch information 302(0)-300(B) in this example include respective predicted control instruction identifiers 304(0)-304(B) to identify the inserted control instruction 108, which may be the branch PC of the predicted control instruction 108. For example, prediction control instruction identifier 304(0) in branch information 302(0) in branch entry 300(2) in BIQ circuit 112 for instruction I3 in loop 144 of Figure 2 stores, as an example, the PC value of branch instruction I3, which is 0x1014. In this way, when another instance of branch instruction I3 is encountered in the instruction stream, it is possible to determine branch information 302(0) in BIQ circuit 112 that contains branch information 302(0) of the next instance of branch instruction I3 to be reused for speculative prediction. Branch information 302(0)-302(B) also include respective hit table indicators 306(0)-306(B), set number indicators 308(0)-308(B), and entry tags 310(0)-310(B), which collectively provide a prediction address pointer that provides a prediction index into prediction table circuit 134 of FIG. 1 to obtain a prediction of the respective prediction control instruction 101 for branch entries 300(0)-300(B). For example, in branch information 302(0) for branch entry 300(2) in BIQ circuit 112 for instruction I3, the values ​​"2," "15," and "0x1a" are stored in respective hit table indicator 306(0), set number indicator 308(0), and entry tag 310(0), which are used to access stored prediction values ​​in prediction table circuit 134 of FIG. 1 to determine the branch prediction for instruction I3.Hit table identifiers 306(0)-306(B), set number identifiers 308(0)-308(B), and entry tags 310(0)-310(B) may be determined by speculative prediction circuitry 106 for a given prediction control instruction 108 based on prediction history indicator 132 and a hash of the PC of the prediction control instruction 108. In this embodiment, separate hit table indicators 306(0)-306(B), set number indicators 308(0)-308(B), and entry tags 310(0)-310(B) are provided because prediction table circuitry 134 may include multiple prediction table circuits, each with a different set and entries within each set. Thus, in this embodiment, hit table indicators 306(0)-306(B), set number indicators 308(0)-308(B), and entry tags 310(0)-(B) can be used to identify a particular prediction table circuit 134, a set within that particular prediction table circuit 134, and an entry within that set.

[0025] Continuing with FIG. 3, each branch entry 300(0)-300(X) also includes a respective prediction entry 312(0)-312(B) and an actual entry 314(0)-314(B) for storing the speculative prediction of the respective prediction control instruction 108 and the actual resolution of the condition of the respective prediction control instruction 108. This information is used by the speculative prediction circuit 106 to process misprediction recovery in response to a mispredicted prediction control instruction 108. For example, prediction entry 312(0) in branch entry 300(2) in BIQ circuit 112 for instruction I3 stores a storage state of "NT," meaning not taken, as the speculative prediction made for branch instruction I3. Also, in this example, actual entry 314(0) in branch entry 300(2) in BIQ circuit 112 for instruction I3 indicates a storage state of "NT," meaning not taken. Thus, processor 100 can use this information to determine whether the speculative prediction of branch instruction I3 was correctly predicted. If not, misprediction recovery actions can be taken to correct the misprediction of branch instruction I3, such as flushing younger instructions 108 fetched from the mispredicted flow path from branch instruction I3 and flushing any additional younger prediction control instructions from BIQ circuit 112 fetched from the mispredicted flow path. As described in more detail below, misprediction recovery may also require undoing any settings for prediction history indicator 132 based on prediction control instructions 108 fetched from incorrect flow paths following mispredicted prediction control instruction 108.

[0026] Each branch entry 300(0)-300(B) may also include a respective valid indicator that indicates whether the respective branch entry 300(0)-300(B) is valid. For example, if the predicted control instruction 108 stored in the branch entry 300(0)-300(B) is resolved, the branch entry 300(0)-300(B) may be reused for another processed predicted control instruction 108. If the respective branch entry 300(0)-300(B) is not valid at a given time, the valid indicator may be set to an invalid state.

[0027] 3, each branch entry 300(0)-300(X) also includes a respective instance indicator 316(0)-316(M) so that branch entry 300(0)-300(X) can be reused for multiple instances of the predicted control instruction 108 within detected loop 144, such as branch instruction I3 of FIG. 2. Instance indicators 316(0)-316(M) are used to store the number of instances that each predicted control instruction 108 was included in instruction stream 110 of FIG. 1, whether by fetching the predicted control instruction 108 or by re-executing the predicted control instruction 108 as part of a re-execution of detected loop 142. For example, as shown in branch entry 300(0) for branch instruction I3, instance indicator 316(0) is a counter that stores the value "2," indicating that there are three pending (3) instances of branch instruction I3 within instruction stream 110. In this example, processor 100 increments instance indicator 316(0) for each instance of branch instruction I3 in each loop iteration 146(0)-146(X). In this example, when branch entries 300(0)-300(B) are set in the first instance of prediction control instruction 108, the respective instance indicators 316(0)-306(B) are set or initialized to zero (0). In this manner, when additional instances of branch instruction I3 are encountered in instruction stream 110, the same branch information 302(0) in branch entry 300(0) set for branch instruction I3 can be used to perform speculative prediction and other prediction-related functions and processing. Each time an instance of branch instruction I3 is resolved during execution by execution circuitry 120 of FIG. 1, the value stored in instance indicator 316(I) is decremented in this example. When instance indicator 316(I) decrements back to zero (0), it means that all instances of branch instruction I3 have been resolved due to exiting loop 144 in which branch instruction I3 is contained. In this case, branch entry 300(0) may be deallocated (e.g., set to invalid) so that it can be reused to store branch information for another prediction control instruction 108 encountered in instruction stream 110.

[0028] 4A-4D are shown to further illustrate misprediction recovery of a predicted control instruction 108 that was speculatively mispredicted by the speculative prediction circuitry 106 of FIG. 1. FIG. 4A is a diagram of an example predicted branch recovery trace record 400 for a fetched predicted control instruction 108F that was predicted in the instruction processing circuitry 104 of FIG. 1. As shown, a first predicted control instruction 108(1) fetched by the instruction processing circuitry 104 of FIG. 1 is shown as being from branch PC (BRPC) 0x1014, which is branch instruction I3 of FIG. 2. The speculative prediction circuitry 106 predicts the predicted control instruction 108(1) as not taken (NT) in this example. In this regard, the speculative prediction circuitry 106 uses the prediction history indicator 132 to generate a prediction index for the prediction table circuitry 134 of FIG. 1, as described above, to make an NT prediction for the predicted control instruction 108(1) at BRPC 0x1014. 4C , in this embodiment, the prediction history indicators 132 consist of a non-speculative prediction history indicator 132NS and a speculative prediction history indicator 132S. The non-speculative prediction history indicators 132NS each have a resolved entry 404 (e.g., a bit) that can store a record of the resolution of a predicted control instruction 108 that was previously executed in the instruction processing circuit 104. For example, a “0” bit stored in the resolved entry 404 can indicate an NT resolution, and a “1” bit stored in the resolved entry 404 can indicate a branched (T) resolution.

[0029] The speculative prediction history indicator 132S shown in FIG. 4C is also an indicator (e.g., a bit) of unresolved prediction entries 406, each of which may store a record of an unresolved prediction made for a prediction control instruction 108 in the instruction processing circuit 104 that has not yet been executed. Again, by way of example, a “0” bit stored in a prediction entry 406 indicates an NT prediction, and a “1” bit stored in a prediction entry 408 indicates a T prediction. Thus, as shown in FIG. 4C , in the speculative prediction history indicator 132S, the recorded bits “010110” in the unresolved prediction entry 408 indicate a sequential prediction history of NT, T, NT, T, T, NT (the leftmost bit being the oldest and the rightmost bit being the youngest). The recorded bit “0” in the leftmost prediction entry 408(1) of the speculative prediction history indicator 132S indicates an NT prediction for the prediction control instruction 108(1). The speculative prediction history indicators 132S are appended to the non-speculative prediction history indicators 132NS to form the prediction history indicators 132 used by the speculative prediction circuitry 106 to make predictions for the prediction control instructions 108. In this way, the prediction history indicators 132 reflect the history of predictions, including both resolved and unresolved predictions.

[0030] Continuing with reference to FIG. 4A, as a result of the NT prediction of prediction-controlled instruction 108(1), instruction fetch circuitry 114 (FIG. 1) fetches the next younger instruction 108 in the NT instruction flow path of prediction-controlled instruction 108(1). In this regard, by way of example, as shown in predicted branch recovery trace record 400, prediction-controlled instruction 108(2) at BRPC 0x1022 is the next-encountered prediction-controlled instruction in the NT instruction flow path of prediction-controlled instruction 108(1). As shown in FIG. 4A, prediction-controlled instruction 108(2) is predicted as T by speculative prediction circuitry 106 (FIG. 1) based on speculative prediction history indicator 132S. Speculative prediction history indicator 132S has a "0" recorded in prediction entry 406(1) for the NT prediction of prediction-controlled instruction 108(1), as shown in FIG. 4C. Speculative prediction circuit 106 then records the T prediction as a "1" bit for predicted control instruction 108(2) in speculative prediction history indicator 132S of prediction history indicator 132, as shown in FIG. 4C. This is so that future predictions will be based on updated speculative prediction history indicator 132S, which includes the recorded predictions for predicted control instruction 108(1) and predicted control instruction 108(2). Predicted branch recovery trace record 400 in FIG. 4A shows subsequent younger predicted control instructions 108(3)-108(6) processed by instruction processing circuit 104 of FIG. 1 and their predictions made by speculative prediction circuit 106.

[0031] FIG. 4B shows an actual branch recovery trace record 402 illustrating the resolution of prediction control instructions 108(1) through 108(6) based on execution. As shown in FIG. 4B, the NT prediction for prediction control instruction 108(1) is resolved as correct, but the T prediction for prediction control instruction 108(2) is resolved as incorrect. The correct resolution for prediction control instruction 108(2) is NT, and the NT prediction for prediction control instruction 108(2) by the speculative prediction circuit 106 was incorrect. This means that the earlier prediction control instructions 108(3) and 108(4) shown in the predicted branch recovery trace record 400 of FIG. 4A were incorrectly fetched. This is because prediction control instructions 108(3) and 108(4) are control dependent (CD) on the mispredicted prediction control instruction 108(2). Prediction control instructions 108(5) and 108(6) are instructions at the merge point of prediction control instruction 108(2). Thus, predictive control instructions 108(5) and 108(6) are CI instructions that exist on both the branched T instruction flow path and the non-branched NT instruction flow path from predictive control instruction 108(2), as shown in predicted branch recovery records and actual branch recovery trace records 400 and 402 in Figures 4A and 4B, respectively.

[0032] In response to detecting a misprediction of predicted control instruction 108(2), execution circuitry 120 of FIG. 1 issues flush event 136 to flush predicted control instructions 108(3) and 108(4) and to fetch instructions 108 in the correct NT instruction flow path from predicted control instruction 108(2) during misprediction recovery. Fetched instructions 108F in the correct NT instruction flow path from predicted control instruction 108(2) are shown in actual branch recovery trace record 402 as predicted control instructions 108(7)-108(9), 108(5), and 108(6). As described above, a prediction of newly fetched predicted control instruction 108F is made based on prediction history indicators 132, including speculative prediction history indicator 132S. Thus, because in this example, speculative prediction history indicator 132S was updated based on the misprediction of prediction control instruction 108(2), if speculative prediction history indicator 130S were not also updated in response to flush event 136 in misprediction recovery, speculative prediction history indicator 132S would not actually reflect prediction history. This is because prediction control instruction 108(2) and the younger, flushed prediction control instructions 108(3) and 108(4) would otherwise still be present in speculative prediction history indicator 132S. If speculative prediction history indicator 132S were not updated in response to flush event 136 in misprediction recovery, prediction entry 406(2) for prediction control instruction 108(2) in speculative prediction history indicator 132S would be T (e.g., a “1” bit) instead of NT (e.g., a “0” bit). Furthermore, since the prediction control instructions 108(3) and 108(4) were only fetched due to the misprediction of the prediction control instruction 108(2) and are flushed in the instruction pipeline IP during misprediction recovery, the predictions of the prediction control instructions 108(3) and 103(4) in the speculative prediction history indicator 132S may be inaccurate.

[0033] Thus, as shown in FIG. 4D , instruction processing circuit 104 can be configured to update speculative prediction history indicator 132S of prediction history indicator 132 as updated speculative prediction history indicator 132S-U in response to flush event 136 in misprediction recovery. FIG. 4D shows updated speculative prediction history indicator 132S-U with record bits “0000010” (i.e., NT, NT, NT, NT, NT, T, NT) in prediction entries 406(1)-406(7) to reflect updated predictions for prediction controlled instructions 108(1)-108(2), 108(7)-108(9), and 108(5)-108(6), respectively, according to actual branch recovery trace record 402 of FIG. 4B . Note that updated prediction entry 406(2) in updated speculative prediction history indicator 132S-U for prediction controlled instruction 108(2) is now “0,” i.e., NT. The newly fetched prediction control instructions 108(7) to 108(9) are predicted based on the more accurate updated speculative prediction history indicator 132S-U, rather than the previous speculative prediction history indicator 132S, which includes the incorrect prediction of prediction control instruction 108(2) and the predictions of prediction control instructions 108(3) and 108(4) fetched on the incorrect instruction flow path of prediction control instruction 108(2).

[0034] Further example details will now be described for the processor 100 of Figure 1 and its speculative prediction circuitry 106, which, for example, speculatively predicts the conditions of predicted control instructions 108F, 108D and reuses branch entries 300(0)-300(B) in the BIQ circuitry 112 for multiple instances of the speculatively predicted predicted control instructions 108F, 108D within a captured loop. For example, Figure 5 is a flowchart illustrating an example process 500 for the processor 100 of Figure 1 and its speculative prediction circuitry 106, which speculatively predicts the conditions of predicted control instructions 108F, 108D and reuses branch entries 300(0)-300(B) in the BIQ circuitry 112 for multiple instances of the speculatively predicted predicted control instructions 108F, 108D within a captured loop, such as loop 144 of Figure 2. The example process 500 of FIG. 5 will be described with reference to the processor 100 of FIG. 1, the loop 144 in the instruction stream 110 of FIG. 2, and the BIQ circuit 112 of FIG.

[0035] In this regard, as shown in Figure 5, a first step of the process 500 may include fetching a plurality of instructions 108 as an instruction stream 110 into the instruction pipeline IP (block 502 of Figure 5). A next step of the process 500 may then include storing first branch information 302(0)-302(B) associated with a first instance of a first predicted control instruction 108F, 108D among the plurality of instructions 108 in a first branch entry 300(0)-300(B) among the plurality of branch entries 300(0)-300(B) in the BIQ circuit 112 (block 504 of Figure 5). The first branch entry 300(0)-300(B) set in the BIQ circuit 112 is associated with the first predicted control instruction 108F, 108D (block 504 of Figure 5). A next step in the process 500 may then include speculatively predicting a first instance of the first prediction control instruction 108F, 108D based on the first branch information 302(0)-302(B) stored in the first branch entry 300(0)-300(B) (block 506 of FIG. 5 ). A next step in the process 500 may then include detecting a first iteration of the first loop 144 in the instruction stream 110 that includes a second instance of the first prediction control instruction 108F, 108D (block 508 of FIG. 5 ). Then, in response to detecting the first iteration of the first loop 144 in the instruction stream 110, updating the first instance indicators 316(0)-316(B) in the first branch entries 300(0)-300(B) to indicate the second instance of the first prediction control instruction 108F, 108D (block 510 of FIG. 5 ).

[0036] Further example information and operation of processor 100 of FIG. 1 reusing branch entries 300(0)-300(B) in BIQ circuitry 112 to store branch information 302(0)-302(B) for multiple instances of such a predictive control instruction 108 within loop 144 and making speculative predictions of the predictive control instruction 108 based on such branch information will now be described.

[0037] 1 , the instruction processing circuit 104 and / or its speculative prediction circuit 106 are configured to detect multiple instances of the predicted control instructions 108F, 108D within the detected loop 144. The instruction processing circuit 104 and / or its speculative prediction circuit 106 are configured to update (e.g., increment) respective instance indicators 316(0)-316(B) within respective branch entries 300(0)-300(B) established for the predicted control instructions 108F, 108D within the BIQ circuit 112 to track the number of instances of the predicted control instructions 108F, 108D within the instruction pipeline IP that have not yet been resolved. When a speculative prediction of a prediction control instruction 108F, 108D is made, prediction entries 312(0)-312(B) in branch entries 300(0)-300(B) corresponding to the prediction control instruction 108F, 108D are updated with the prediction of the prediction control instruction 108F, 108D in the BIQ circuit 112. When an instance of the prediction control instruction 108F, 108D is resolved, actual entries 314(0)-314(B) in branch entries 300(0)-300(B) corresponding to the prediction control instruction 108F, 108D are updated in the BIQ circuit 112 with the resolution (e.g., take or not take) of the conditional control instruction 108F, 108D. As described above, the instance indicators 316(0)-316(B) in the respective branch entries 300(0)-300(B) established for the prediction control instructions 108F, 108D in the BIQ circuit 112 are updated based on the instance and, subsequently, the resolution of the prediction control instructions 108F, 108D, such that the branch entries 300(0)-300(B) established for the prediction control instructions 108F, 108D can be substantially reused to make predictions and to track mispredictions for misprediction recovery tasks. If the prediction control instructions 108F, 108D are determined to be mispredicted based on the speculative predictions of the prediction control instructions 108F, 108D in their respective prediction entries 312(0)-312(B) and the corresponding actual entries 314(0)-314(B) in the branch entries 300(0)-300(B) in the BIQ circuit 112, misprediction recovery tasks can be performed.In one embodiment, this requires deallocating or making available the branch entries 300(0)-300(B) corresponding to the predicted control instructions 108F, 108D that are control-dependent on the mispredicted predicted control instructions 108F, 108D in the BIQ circuit 112. This is because these branch entries 300(0)-300(B) corresponding to the predicted control instructions 108F, 108D that are control-dependent on the mispredicted predicted control instructions 108F, 108D are no longer valid because the dependent predicted control instructions 108F, 108D were fetched based on the predicted control flow path of the mispredicted predicted control instructions 108F, 108D. Also, during misprediction recovery, the processor 100 can restore the prediction history indicator 132 to its previous state before it was updated based on the speculative prediction of the dependent predicted control instructions 108F, 108D that depended on the mispredicted predicted control instructions 108F, 108D. In this way, previous updates of the prediction history indicator 132 based on speculative predictions of the prediction control instructions 108F, 108D that were in the correct flow path from the mispredicted prediction control instructions 108F, 108D do not affect future speculative predictions in an undesirable manner. The processor 100 causes the instruction fetch circuitry 114 of FIG. 1 to stall fetching of additional instructions 108 into the instruction pipeline IP until the prediction history indicator 132 is restored.

[0038] As noted above, the detected loop 144 may include multiple nested prediction control instructions 108F, 108D, with each prediction control instruction 108F, 108D being assigned its own branch entry 300(0)-300(B) in the BIQ circuit 112. The operation of updating the branch information 302(0)-302(B) and instance indicators 316(0)-316(B) in such branch entries 300(0)-300(B) of the multiple nested prediction control instructions 108F, 108D in the detected loop 144 is updated at runtime based on the resolution of the speculative predictions, as described above. The instance indicators 316(0)-316(B) in such branch entries 300(0)-300(B) of multiple nested prediction control instructions 108F, 108D within the detected loop 144 are updated based on the number of instances of such nested prediction control instructions 108F, 108D and their resolution upon execution. Once all instances of a given prediction control instruction 108F, 108D within the loop 144 have been resolved and the loop 144 has been exited, the corresponding branch entries 300(0)-300(B) for that given prediction control instruction 108F, 108D within the BIQ circuit 112 can be reused (e.g., deallocated and reallocated).

[0039] FIG. 6 illustrates one embodiment of a loop buffer circuit 142 included in the processor of FIG. 1 that detects, captures, and re-executes the detected loop 144. In this embodiment, as shown in FIG. 6, the loop buffer circuit 142 of this embodiment includes a loop detection circuit 602. The loop detection circuit 602 is coupled to the instruction pipeline IP and, in this embodiment, is configured to receive a copy or instance of a decoded instruction 108D in the instruction stream 110 of the instruction processing circuit 104. The loop detection circuit 602 is configured to detect whether a loop exists in the decoded instructions 108D in the instruction stream 110 at the instruction pipeline IP. If a loop exists, the loop will include multiple loop instructions 108D among the decoded instructions 108D. For example, the loop detection circuit 602 may include an instruction buffer circuit 604 configured to store the decoded instructions 108D as they flow through the instruction pipeline IP after being decoded by the decode circuit 118 (FIG. 1). The loop detection circuit 602 can reference the stored instructions 108D to determine whether subsequent younger instructions 108D repeat the captured instructions 108D. Stored instructions 108D that are detected by the loop detection circuit 602 to repeat sequentially in the instruction pipeline IP are considered to be captured loops.

[0040] In response to loop detection circuit 602 detecting a loop of stored instructions 108D in instruction stream 110 as loop 144, loop detection circuit 602 is configured to communicate the stored instructions 108D of the loop to loop capture circuit 606 as captured loop 144. Loop capture circuit 606 captures the detected loop instructions 108D of captured loop 144 in “X” instruction entries 610(1) through 610(X) in loop buffer memory 612. In this manner, loop capture circuit 606 has a record and instance of instructions 108D of captured loop 144. It should be noted that loop buffer memory 612 can be provided as part of loop capture circuit 606 and / or loop buffer circuit 142, or as a separate memory circuit within processor 100 of FIG. 1, for example.

[0041] 6 , the loop buffer circuit 142 of this embodiment also includes a loop optimization circuit 618. As described in more detail below in several embodiments, the loop optimization circuit 618 is configured to determine, based on the captured loop 144 captured by the loop capture circuit 606, whether loop optimization is feasible for the captured loop 144. The loop optimization circuit 618 is configurable to incrementally analyze the instruction 108D once the instruction 108D is captured by the loop capture circuit 606 or after the loop capture circuit 606 has captured the fully captured loop 144. In response to the loop optimization circuit 618 determining that loop optimization is feasible for the captured loop 144, the loop optimization circuit 618 is configured to modify the captured loop 144 in the loop buffer memory 612 of the loop capture circuit 606 to generate an optimized loop 144O. The optimized loop 144O is a modified version of the instructions 108D in the captured loop 144 that are re-executed to re-execute the captured loop 144, and / or a modified version of how the captured loop 144 is processed in the instruction processing circuit 104 when re-executed, to potentially more efficiently process the captured loop 144 when re-executed. This can improve the throughput of the re-execution of the captured loop 144 in the instruction processing circuit 104. The loop re-execution circuit 614 is configured to re-execute the optimized loop 144O of the captured loop 144 based on the modified version of the captured loop 144 by the loop optimization circuit 618.

[0042] For example, a particular loop optimization performed by the loop optimization circuit 618 based on the captured loop 144 may be possible that, when processed in a re-execution of the captured loop 144 in the instruction processing circuit 104, reduces the number of instructions 108D that need to be re-executed in the captured loop 144 to achieve the same functionality of the captured loop 144. Other optimizations may also be possible by the loop optimization circuit 618 based on the captured loop 144 that reduce the number of clock cycles required to process and execute the re-execution of the captured loop 144 in the instruction processing circuit 104 compared to the number of clock cycles required to execute a re-execution of the original captured instructions 108D of the captured loop 144 having the same functionality. Other loop optimizations may also be available that are performed by the loop optimization circuit 618 based on the captured loop 144 that provide critical instructions, such as timing-critical instructions (e.g., load instructions, or instructions that are unlocking instructions for unlocking dependent flow paths that are indicated by scheduling hints to be scheduled for execution at a higher priority when re-executed in the instruction processing circuit 104). In this way, such critical instructions may be executed earlier, so that their produced results can be readily consumed earlier by other consumer instructions in the re-executed captured loop 144. This can improve the throughput of the re-execution of the captured loop 144 in the instruction processing circuit 104.

[0043] Further optimizations may also be available for implementation by the loop optimization circuit 618 based on the captured loop 144, which may identify instructions that are load / store instructions separable from the captured loop 144 as instruction execution slices. An instruction execution slice in the captured loop is a set of instructions 108D in the captured loop 144 that calculates the load / store memory addresses required for the memory load / store instructions to be executed in a re-execution of the captured loop 144. The loop optimization circuit 618 may be configured to convert the extracted instruction execution slice identified from the captured loop 144 into software prefetch instructions that may be injected into a prefetch stage in the instruction pipeline IP when the captured loop 144 is re-executed to perform loop optimization of the captured loop 144. Processing the software prefetch instructions for the instruction execution slices causes the instruction processing circuit 104 to execute the extracted instructions 108D in the instruction execution slice earlier in the instruction pipeline IP as prefetch instructions 108. Therefore, by processing the execution slice instructions extracted as prefetch instructions 108 earlier, cache misses resulting from the memory operations performed can be recovered earlier for consumption by dependent instructions within the captured loop 144 when the captured loop 144 is re-executed.

[0044] 6, the loop capture circuit 606 is configured to provide the instructions 108D of the captured loop 144 to the loop re-execution circuit 614 to be re-executed (i.e., processed again in another iteration of the loop) in the instruction pipeline IP of the instruction processing circuit 104. The loop re-execution circuit 614 determines whether the captured loop 144 should be re-executed. In response to determining whether the captured loop 144 should be re-executed, the loop re-execution circuit 614 can insert the instructions 108D of the captured loop 144 or the optimized loop 144O into the re-executed instruction pipeline IP. The loop re-execution circuit 614 is coupled to the instruction pipeline IP such that the loop re-execution circuit 614 can insert the instructions 108D of the captured loop 144 into the re-executed instruction pipeline IP. In this example, because there is no need to re-decode fetched instructions 108F in the detected loop, loop re-execution circuit 614 is configured to inject or insert instructions 108D for captured loop 144 or optimized loop 144O into the instruction pipeline IP after decode circuit 118 of Figure 1. In this example, loop re-execution circuit 614 is configured to inject or insert instructions 108D for captured loop 144 or optimized loop 144O into the instruction pipeline IP before rename / allocate circuit 126 of Figure 1 because processor 100 in this example is an out-of-order processor. Thus, decoded instructions 108D from captured loop 144 or optimized loop 144O that are re-executed can be processed and / or executed out-of-order according to the issuance of decoded instructions 108D by scheduler circuit 143.

[0045] The loop rerun circuit 614 is also coupled to the instruction fetch circuit 114 in this embodiment so that the loop rerun circuit 614 can send a loop rerun indicator 616 to the instruction fetch circuit 114 when the loop rerun circuit 614 reruns the loop. The instruction fetch circuit 114 can suspend fetching of instructions 108D for the captured loop 144 while they are rerun (inserted) into the instruction pipeline IP of the instruction processing circuit 104. FIG. 7 is a block diagram of an example processor-based system 700 including a processor 702 configured to speculatively predict fetched predicted control instructions and reuse entries in a BIQ circuit used to store branch information for multiple instances of the speculatively predicted predicted control instructions in the captured loop. The processor 702 may include, but is not limited to, the processor 100 of FIG. 1. The processor-based system 700 may include, but is not limited to, the processor-based system 102 of FIG. 1.

[0046] The processor-based system 700 may represent one or more circuits included in an electronic board card such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing pad, a mobile device, or any other device, and may correspond to, for example, a server or a user's computer. In this example, the processor-based system 700 includes a processor 702. The processor 702 represents one or more general-purpose processing circuits, such as a microprocessor, a central processing unit, or the like. The processor 702 is configured to execute processing logic in computer instructions to perform the operations and steps described herein. In this example, the processor 702 includes a speculative prediction circuit 704 for speculatively predicting fetched predicted control instructions. The speculative prediction circuit 704 may be the speculative prediction circuit 106 of FIG. 1. The speculative prediction circuit 704 may also be configured to reuse entries in a BIQ circuit used to store branch information for multiple instances of speculatively predicted predicted control instructions within a captured loop, including, but not limited to, the BIQ circuit 112 of FIG. 1.

[0047] Processor 702 also includes an instruction cache 706 for temporary fast-access memory storage of instructions and instruction processing circuits 708. Instructions fetched or prefetched from a memory, such as system memory 710, via a system bus 712 are stored in instruction cache 706. Instruction processing circuits 708 are configured to process instructions fetched into instruction cache 706 and process the instructions for execution. Instruction processing circuits 708 are configured to insert fetched instructions into one or more instruction pipelines to be processed for execution.

[0048] The processor 702 and the system memory 710 are coupled to a system bus 712, which may interconnect peripheral devices included in the processor-based system 700. As is well known, the processor 702 communicates with these other devices by exchanging address, control, and data information over the system bus 712. For example, the processor 702 may communicate bus transaction requests to a memory controller 714 in the system memory 710, serving as an example of a slave device. Although not shown in FIG. 7, multiple system buses 712 may be provided, with each system bus constituting a different fabric. In this embodiment, the memory controller 714 is configured to provide memory access requests to a memory array 716 in the system memory 710. The memory array 716 comprises an array of storage bit cells for storing data. The system memory 710 may be, by way of non-limiting example, a read-only memory (ROM), a flash memory, a dynamic random access memory (DRAM) such as a synchronous DRAM (SDRAM), and a static memory (e.g., a flash memory, a static random access memory (SRAM), etc.).

[0049] Other devices may also be connected to the system bus 712. As shown in FIG. 7, these devices may include, by way of example, a system memory 710, one or more input devices 718, one or more output devices 720, a modem 722, and one or more display controllers 724. The input devices 718 may include any type of input device, including, but not limited to, input keys, switches, sound processors, etc. The output devices 720 may include any type of output device, including, but not limited to, audio, video, or other visual indicators. The modem 722 may be any device configured to enable the exchange of data with a network 726. The network 726 may be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, and the Internet. The modem 722 may be configured to support any type of desired communication protocol. The processor 702 may also be configured to access a display controller 724 via the system bus 712 to control information sent to one or more displays 728. The display 728 may be any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc.

[0050] The processor-based system 700 of FIG. 7 may include a set of instructions 730, which may include predictive control instructions configured to be fetched and executed by the processor 702. The instructions 730 may be stored in the system memory 710, the processor 702, and / or the instruction cache 706, as examples of a non-transitory computer-readable medium 732. The instructions 730 may also reside, completely or at least partially, within the system memory 710 and / or the processor 702 during execution. The instructions 730 may further be transmitted or received over the network 726 via the modem 722, such that the network 726 includes the non-transitory computer-readable medium 732. The instructions 730 may also include instructions that, when executed by the processor 702, cause the processor 702 to speculatively predict the fetched predictive control instructions and to reuse entries in the BIQ circuitry used to store branch information for multiple instances of the speculatively predicted predictive control instructions within the captured loop.

[0051] While the illustrated embodiment depicts the non-transitory computer-readable medium 732 as a single medium, the term "computer-readable medium" should be interpreted to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more sets of instructions. The term "computer-readable medium" should also be interpreted to include any medium that can store, encode, or carry a set of instructions for execution by a processing device, causing the processing device to perform any one or more of the methodologies of the embodiments disclosed herein. Thus, the term "computer-readable medium" should be interpreted to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0052] The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be formed by hardware components or embodied in machine-readable instructions usable to cause a general-purpose or special-purpose processor programmed with the instructions to perform the steps. Alternatively, the steps may be performed by a combination of hardware and software.

[0053] The embodiments disclosed herein can be provided as a computer program product or software, which can include a machine-readable medium (or computer-readable medium) having stored thereon instructions usable to program a computer system (or other electronic device) to perform processes according to the embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, machine-readable media include machine-readable storage media (e.g., ROM, random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.).

[0054] Unless otherwise specified, and unless clear from the preceding description, throughout this specification, descriptions using terms such as "processing," "computing," "determining," "displaying," and the like refer to the operations and processing of a computer system or similar electronic computing device that manipulates and converts data and memory represented as physical (electronic) quantities in the computer system's registers into other data similarly represented as physical quantities in the computer system's memory, registers, or other such information storage, transmission, or display device.

[0055] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various systems can be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of such systems will be apparent from the above description. Additionally, the embodiments described herein are not described with reference to any particular programming language. It will be appreciated that a variety of programming languages ​​can be used to implement the teachings of the embodiments as described herein. Those skilled in the art will appreciate that the various illustrative logic blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein can be implemented as electronic hardware, as instructions stored in memory or other computer-readable media and executed by a processor or other processing device, or a combination of both. The processor and system components described herein can be employed in, by way of example, any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be any type and size of memory and can be configured to store any type of information desired. To clearly illustrate this interchangeability, the various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present embodiments.

[0056] The various illustrative logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or embodied by a processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Also, a controller may be a processor. The processor may be a microprocessor, although in alternative aspects, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more processors in conjunction with a DSP core, or any other such configuration).

[0057] The embodiments disclosed herein may be embodied in hardware and instructions stored in the hardware and may reside in, for example, RAM, flash memory, ROM, Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, hard disk, removable disk, CD-ROM, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.

[0058] It should also be noted that the operational steps described in any of the exemplary embodiments herein are provided for purposes of example and explanation. The described operations may occur in many different orders other than the order shown. Also, an operation described as a single operational step may actually occur in several different steps. Furthermore, one or more operational steps described in an exemplary embodiment may be combined. Those skilled in the art will also recognize that information and signals may be represented using any of a variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields, particles, optical fields, or optical particles, or any combination thereof.

[0059] Unless otherwise expressly stated, it is not intended that any method described herein be construed as requiring that the steps of the method be performed in any particular order. Thus, unless a method claim actually recites the order to be followed by the steps of the method, or unless the claim or description otherwise specifically states that the steps are to be limited to a particular order, no particular order is intended to be implied.

[0060] It will be apparent to those skilled in the art that various modifications and variations are possible without departing from the spirit or scope of the present invention. Since those skilled in the art may conceive of modifications, combinations, subcombinations, and variations of the disclosed embodiments that incorporate the spirit and scope of the present invention, the present invention should be construed as including all those that come within the scope of the appended claims and their equivalents.

Claims

1. an instruction processing circuit; a branch information queue (BIQ) circuit including a plurality of branch entries each configured to store branch information associated with a prediction control instruction and an instance indicator; 1. A processor comprising: The instruction processing circuit fetching a plurality of instructions into an instruction pipeline as an instruction stream; storing first branch information associated with a first instance of a first prediction control instruction of the plurality of instructions in a first branch entry associated with the first prediction control instruction of the plurality of branch entries in the BIQ circuit; speculatively predicting the first instance of the first prediction control instruction based on the first branch information stored in the first branch entry; Detecting a first iteration of a first loop that includes a second instance of the first predictive control instruction in the instruction stream; In response to detecting the first iteration of the first loop in the instruction stream, updating a first instance indicator in the first branch entry to indicate the second instance of the first predicted control instruction. It was configured as follows: Processor.

2. 2. The processor of claim 1, wherein the instruction processing circuitry comprises: Detecting a second iteration of the first loop that includes a third instance of the predictive control instruction in the instruction stream; In response to detecting the second iteration of the first loop in the instruction stream, updating the first instance indicator in the first branch entry to indicate the third instance of the first predicted control instruction. The processor further configured as follows:

3. 2. The processor of claim 1, wherein the instruction processing circuitry comprises: Detecting the first instance of the predictive control instruction; allocating the first branch entry in the BIQ circuit in response to detecting the first instance of the predictive control instruction; The processor further configured as follows:

4. 2. The processor of claim 1, wherein the instruction processing circuitry is configured to increment the first instance indicator in the first branch entry, thereby updating the first instance indicator in the first branch entry that indicates the second instance of the first predicted control instruction.

5. 2. The processor of claim 1, wherein the instruction processing circuitry comprises: executing the first instance of the first predictive control instructions to generate a solution for the first instance of the first predictive control instructions; in response to execution of the first instance of the first predictive control instruction; storing the resolution of the first instance of the first prediction control instruction in the first branch information of the first branch entry in the BIQ circuit; updating the first instance indicator in the first branch entry to indicate that the first instance of the first predicted control instruction has been resolved; The processor further configured as follows:

6. 6. The processor of claim 5, wherein the instruction processing circuitry comprises: speculatively predicting the second instance of the first prediction control instruction based on the first branch information stored in the first branch entry in the BIQ circuit; storing the speculative prediction of the second instance of the first prediction control instruction in the first branch information stored in the first branch entry; The processor further configured as follows:

7. 7. The processor of claim 6, wherein the instruction processing circuitry comprises: executing the second instance of the first predictive control instructions to generate a solution for the second instance of the first predictive control instructions; in response to execution of the second instance of the first predictive control instruction; storing the resolution of the second instance of the first predicted control instruction in the first branch information in the first branch entry in the BIQ circuit; updating the first instance indicator in the first branch entry to indicate that the second instance of the first predicted control instruction has been resolved; The processor further configured as follows:

8. 8. The processor of claim 7, wherein the instruction processing circuitry is configured to decrement the first instance indicator in the first branch entry, thereby updating the first instance indicator in the first branch entry to indicate that the second instance of the first predicted control instruction has been resolved.

9. 8. The processor of claim 7, wherein the instruction processing circuitry is configured to, in response to execution of the second instance of the first predictive control instruction: determining whether the resolution of the second instance of the first prediction control instruction in the first branch information in the first branch entry is consistent with the speculative prediction of the second instance of the prediction control instruction in the first branch information in the first branch entry; in response to the resolution of the second instance of the first prediction control instruction not being consistent with the speculative prediction of the second instance of the first prediction control instruction; deallocating one or more second branch entries in the BIQ circuit associated with one or more second prediction control instructions of the plurality of instructions that depend on the second instance of the first prediction control instruction; The processor further configured as follows:

10. 10. The processor of claim 9, the instruction processing circuitry is further configured to update a speculative history indicator based on the first branch information stored in the first branch entry; the instruction processing circuitry is configured to speculatively predict the second instance of the first prediction control instruction based on the speculative history indicator, thereby speculatively predicting the second instance of the first prediction control instruction; the instruction processing circuitry, in response to the resolution of the second instance of the first prediction control instruction not being consistent with the speculative prediction of the second instance of the first prediction control instruction, Stalling fetching of one or more additional instructions of the plurality of instructions into the instruction pipeline until the speculative prediction history indicator is restored. The processor further configured as follows:

11. 8. The processor of claim 7, wherein the instruction processing circuitry comprises: determining whether all instances of the first predicted control instruction have been resolved based on the first instance indicator in the first branch entry; deallocating the first branch entry in the BIQ circuit in response to determining that all instances of the first predicted control instruction have been resolved. The processor further configured as follows:

12. 10. The processor of claim 1, The instruction processing circuit storing second branch information associated with a first instance of a second prediction control instruction of the plurality of instructions in a second branch entry of the plurality of branch entries in the BIQ circuit; speculatively predicting the first instance of the second prediction control instruction based on the second branch information stored in the second branch entry associated with the second prediction control instruction in the BIQ circuit; further configured as follows: The instruction processing circuit Detecting the first iteration of the first loop further including a second instance of the second predictive control instruction in the instruction stream. It is configured as follows: The instruction processing circuitry, in response to detecting the first iteration of the first loop in the instruction stream, updating a second instance indicator in the second branch entry to indicate the second instance of the second predicted control instruction; The processor further configured as follows:

13. 10. The processor of claim 1, each branch entry of the one or more branch entries in the BIQ circuit configured to store the branch information including a speculative prediction indicator associated with the prediction control instruction; the instruction processing circuit is configured to speculatively predict a first condition of the first instance of the first prediction control instruction based on a first speculative prediction indicator in the first branch entry associated with the first prediction control instruction in the BIQ circuit; Processor.

14. 2. The processor of claim 1, wherein the instruction processing circuitry comprises: in response to detecting the first loop in the instruction stream; capturing a plurality of first loop instructions among the plurality of instructions in the detected first loop, the plurality of first loop instructions including the first predictive control instruction; determining whether the captured first loop should be re-executed within the instruction pipeline; In response to determining that the captured first loop should be re-executed within the instruction pipeline, inserting the captured first loop into the instruction pipeline to be re-executed. The processor further configured as follows:

15. 1. A method of reusing branch information for multiple instances of a captured predictive control instruction in a processor, comprising: fetching a plurality of instructions into an instruction pipeline as an instruction stream; storing first branch information associated with a first instance of a first prediction control instruction of the plurality of instructions in a first branch entry of a plurality of branch entries in a Branch Information Queue (BIQ) circuit, the first branch entry being associated with the first prediction control instruction; speculatively predicting the first instance of the first prediction control instruction based on the first branch information stored in the first branch entry; detecting a first iteration of a first loop that includes a second instance of the first predictive control instruction in the instruction stream; updating a first instance indicator in the first branch entry to indicate the second instance of the first predicted control instruction in response to detecting the first iteration of the first loop in the instruction stream; A method comprising:

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