On-demand adjustment of memory bandwidth utilization to display service requirements

Abstract

A system, apparatus, and method for prefetching data by a display controller are proposed. From time to time, a memory performance state change is performed. During this change, the memory clock frequency is changed for the memory subsystem (220) that stores the frame buffer (230) used to drive pixels to the display device (250). During the performance state change, memory access may be temporarily blocked. To maintain a desired quality of service for the display, the display controller (150) is configured to prefetch data prior to the performance state change. To ensure that the display controller has sufficient memory bandwidth for prefetching, the bandwidth adjustment circuits (112A, 112N) of the clients (205) of the system are configured to temporarily reduce the memory bandwidth of the corresponding client.

Description

[Background technology]

[0001] Description of Related Art Many types of computer systems include display devices for displaying images, video streams, and data. Accordingly, these systems typically include functionality for generating and / or manipulating image and video information. Typically, in digital images, the smallest item of information in an image is called a "picture element," or more commonly, a "pixel."

[0002] Some systems include multiple individual displays. In these systems, multi-display technology enables a single graphics processing unit (GPU) (or other device, such as an accelerated processing circuit (APU) or other type of system on chip (SOC), or any application-specific integrated circuit (ASIC) with a display controller) to simultaneously support multiple independent display outputs. In one example, a computing system can independently connect multiple high-resolution displays to a large, integrated display surface to provide an expanded visual workspace. Gaming, entertainment, medical, audio and video editing, business, and other applications can take advantage of the expanded visual workspace and increase opportunities for multitasking.

[0003] For one or more supported displays, the video subsystem maintains a respective frame buffer that stores data, such as one or more video frames, which may be stored in dynamic random access memory (DRAM). For each supported display, the video controller accesses the respective frame buffer by reading data through a predetermined one of one or more DRAM interfaces. A memory clock is typically used to control the data rate for accessing the frame buffer in the DRAM. In some cases, the computer is directly connected to the display device through an interface, such as DisplayPort (DP), embedded DisplayPort (eDP), high-definition multimedia interface (HDMI), or another type of interface, to provide a physical connection for transmitting the pixel bitstream from the frame buffer to the display device. In one implementation, the bandwidth of the video stream transmitted from the computer to the display device may be limited by the maximum bitrate of the DisplayPort, embedded DisplayPort, or HDMI cable.

[0004] In scenarios where multiple workloads (e.g., game rendering, video processing) are accessing the memory subsystem, the memory subsystem may be set to a relatively high frequency (e.g., its maximum possible frequency) to ensure that the operating frequency of the memory subsystem can handle a large number of reads and writes. In some cases, if the memory subsystem is not overly stressed, the system may attempt to lower the memory clock frequency to reduce power consumption. Changing the memory clock frequency may require a training session performed on the memory interface, a configuration / mode change, or another action requiring access to memory where access is temporarily halted. The halt of all memory access is sometimes referred to as a “blackout period.” If the memory interface needs to be retrained or another type of mode change needs to be performed due to this blackout period, it may be difficult or impossible to find a convenient time to halt all memory access without introducing visual artifacts to any displays. One solution to this problem is for the display controller to prefetch enough data to account for the temporary halt in memory access. This may require, for example, the display controller to temporarily double its memory bandwidth. One way to ensure that this increased memory bandwidth is available to the display controller is to statically allocate this amount of memory bandwidth to the display controller. However, this approach reduces the bandwidth available to other clients, even if the display controller does not necessarily require the increased amount of bandwidth. Therefore, improved systems and methods for managing memory bandwidth are desired.

[0005] Advantages of the methods and mechanisms described herein may be better understood by referring to the following description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram of one embodiment of a computing system. [Figure 2] FIG. 1 is a block diagram of one embodiment of a computing system. [Figure 3] FIG. 2 is a timing diagram of one embodiment of the timing of memory clock frequency updates and display data prefetching in a computing system. [Figure 4] A method for performing prefetching of display data prior to changing the performance state of a memory that stores the display data. DETAILED DESCRIPTION OF THE INVENTION

[0007] In the following description, numerous specific details are set forth to provide a thorough understanding of the methods and mechanisms presented herein. However, those skilled in the art should recognize that various embodiments can be practiced without these specific details. In some instances, well-known structures, components, signals, computer program instructions, and techniques have not been shown in detail to avoid obscuring the approaches described herein. It will be understood that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements.

[0008] Disclosed are systems, apparatus, and methods for prefetching data by a display controller in a computing system. From time to time, a memory performance state change is performed. During such a change, a memory clock frequency is changed for a memory subsystem that stores a frame buffer used to drive pixels to a display device. Memory accesses may be temporarily blocked during the performance state change. To maintain a desired quality of service for the display, the display controller is configured to prefetch data prior to the performance state change. To ensure that the display controller has sufficient memory bandwidth to accomplish the prefetching, bandwidth adjustment circuitry within a client of the system is configured to temporarily reduce the memory bandwidth available or otherwise consumed by the corresponding client. By reducing memory accesses generated by other clients, the other clients are prevented from competing with the display controller for memory bandwidth, which could prevent the display controller from meeting desired quality of service requirements.

[0009] 1, a block diagram of one embodiment of computing system 100 is shown. In one embodiment, computing system 100 includes at least processors 105A-105N, input / output (I / O) interface 120, bus 125, memory controller 130, network interface 135, memory device 140, display controller 150, display 155, and control circuitry 160. In other embodiments, computing system 100 includes other components and / or is arranged differently.

[0010] Display controller 150 represents any number of display controllers included in system 100, the number varying depending on the embodiment. Display controller 150 is configured to drive a corresponding display 155, which represents any number of displays. In some embodiments, a single display controller drives multiple displays. As shown in this example, display controller 150 includes buffer 152 for storing frame data to be displayed.

[0011] In one embodiment, control circuitry 160 determines whether conditions for performing a power state change (also referred to as a "Pstate" change) have been detected. In various embodiments, a Pstate change causes a change in the operating frequency and / or power consumption of a given device. For example, an increase in Pstate may involve an increase in the operating frequency and voltage provided to the device. Conversely, a decrease in Pstate may involve a decrease in the operating frequency and / or voltage supplied to the device.

[0012] When a condition for executing a power state change of memory device 140 is detected, control circuitry 160 determines when to execute the power state change. Before executing the power state change, control circuitry 160 is configured to communicate signal 116 to display controller 150. In response to signal 116, display controller 150 is configured to prefetch additional data into buffer 152 in anticipation of the next memory blackout period (i.e., a period during which memory access is not permitted). This will prevent interruptions in the display data, which may result in visual artifacts, etc. Thus, the memory bandwidth requirements of the display controller temporarily increase. While having display controller 150 prefetch additional data from memory 140, sufficient bandwidth may not be available due to many other clients (e.g., processor 105, I / O 120, etc.) generating memory accesses. In other words, display controller 150 may require X bandwidth to complete the prefetch. However, other clients in the system may be allocated different amounts of memory bandwidth such that X bandwidth is not available to display controller 150. Therefore, to ensure that sufficient bandwidth is available to display controller 150, bandwidth adjustment circuits 112 are implemented for one or more clients configured to generate memory accesses (shown as BR 112 in FIG. 1). Control circuit 160 is configured to communicate a signal / indication 114 to each of these bandwidth adjustment circuits. In response to the indication, the bandwidth adjustment circuit causes the corresponding client to temporarily reduce its memory bandwidth while display controller 150 increases its bandwidth.

[0013] The bandwidth adjustment circuit 112 comprises circuitry configured to cause a corresponding client to reduce memory accesses communicated to memory 140. In some embodiments, the bandwidth adjustment circuit is configured to cause one corresponding client to reduce memory bandwidth. In other embodiments, the bandwidth adjustment circuit 112 is configured to cause more than one client to reduce memory bandwidth. In some embodiments, the bandwidth adjustment circuit is part of the client's circuitry, while in other embodiments, the bandwidth adjustment circuit is implemented separately from a given client. These and other embodiments are possible and contemplated. In this manner, the display controller is provided with sufficient bandwidth to prefetch additional data.

[0014] In one embodiment, the power state change involves adjusting the memory clock frequency of one or more memory devices 140. Control circuitry 160 may be implemented using any suitable combination of circuits, memory elements, and program instructions. Note that control circuitry 160 may also be referred to by other names, such as a system management controller, system management circuitry, system controller, controller, etc. Although a single control circuitry 160 is shown in FIG. 1, it should be understood that this represents only one embodiment. In other embodiments, system 100 may include multiple control circuits 160 located in any suitable location. In another embodiment, control circuitry 160 is implemented by one of processors 105A-105N.

[0015] Processors 105A-105N represent any number of processors included in system 100. In one embodiment, processor 105A is a general-purpose processor such as a central processing unit (CPU). In this embodiment, processor 105A executes drivers 110 (e.g., graphics drivers) for communicating with and / or controlling the operation of one or more of the other processors in system 100. It should be noted that, depending on the embodiment, driver 110 may be implemented using any suitable combination of hardware, software, and / or firmware.

[0016] In one embodiment, processor 105N is a data-parallel processor having a highly parallel architecture. Data-parallel processors include graphics processing units (GPUs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), etc. In some embodiments, processors 105A-105N include multiple data-parallel processors. In one embodiment, processor 105N is a GPU that renders pixel data representing an image into frame buffer 142. This pixel data is then provided to display controller 150 to drive to display 155.

[0017] Memory controller 130 represents any number and type of memory controller accessible by processors 105A-105N. While memory controller 130 is shown as separate from processors 105A-105N, it should be understood that this represents only one contemplated embodiment. In other embodiments, memory controller 130 may be incorporated into one or more of processors 105A-105N and / or memory controller 130 may be located on the same semiconductor die as one or more of processors 105A-105N. Memory controller(s) 130 couple to any number and type of memory device(s) 140. Memory device(s) 140 represent any number and type of memory devices. For example, types of memory in memory device 140 may include dynamic random access memory (DRAM), static random access memory (SRAM), graphics double data rate (GDDR) synchronous DRAM (SDRAM), NAND flash memory, NOR flash memory, ferroelectric random access memory (FeRAM), etc.

[0018] I / O interface 120 represents any number and type of I / O interface (e.g., a peripheral component interconnect (PCI) bus, a PCI-Extended (PCI-X), a PCI Express (PCI Express) bus, a gigabit Ethernet (GBE) bus, a universal serial bus (USB)). Various types of peripheral devices (not shown) are coupled to I / O interface 120. Such peripheral devices include (but are not limited to) displays, keyboards, mice, printers, scanners, joysticks, other types of game controllers, media recording devices, external storage devices, network interface cards, etc. Network interface 135 can receive and transmit network messages across a network.

[0019] In various embodiments, computing system 100 is a computer, a laptop, a mobile device, a game console, a server, a streaming device, a wearable device, or any of a variety of other types of computing systems or devices. Note that the number of components of computing system 100 varies from embodiment to embodiment. For example, in other embodiments, more or fewer components are present than shown in FIG. 1 . Note also that in other embodiments, computing system 100 includes other components (e.g., phase-locked loops, voltage regulators) that are not shown in FIG. 1 to avoid cluttering the diagram. Additionally, in other embodiments, computing system 100 is structured in other ways than that shown in FIG. 1 .

[0020] 2, a block diagram of one embodiment of a system 200 is shown. In one embodiment, the system 200 includes a processing element 205, a control circuit 210, a fabric 215, a memory subsystem 220, a display controller 150, a prefetch controller 240, and a display device 250. While the prefetch controller 240 is shown as being included in the display controller 150, this does not preclude the prefetch controller 240 from being integrated within the display device 250. In other words, the prefetch controller 240 can be located inside or outside the display device 250, depending on the embodiment. Similarly, while the buffer 245 is shown as being located within the prefetch controller 240, this does not preclude the buffer 245 from being located outside the prefetch controller 240 in other embodiments. Generally speaking, the display controller 150 receives video image and frame data from various sources, processes the data, and then sends the data in a format compatible with the target display.

[0021] Processing elements 205 represent any number, type, and arrangement of processing resources (e.g., CPUs, GPUs, FPGAs, ASICs). As shown in FIG. 1, bandwidth adjustment circuits 112A-112N are associated with processing elements 205 that generate memory accesses. In this example, each bandwidth adjustment circuit 112A-112N is associated with a corresponding processing element (PE) 262A-262N. In addition, a queue 262A-262N is associated with each processing element 262 configured to store pending memory accesses generated by the processing element 262. In various embodiments, bandwidth adjustment circuit 112 is configured to control either or both the generation of memory accesses by processing elements 262 and the servicing of already generated memory accesses stored in pending queues 264A-264N. It should be noted that various possible arrangements of processing elements 262 and queues 264 are possible and contemplated. Control circuit 210 includes any suitable combination of execution circuitry, circuitry, memory, and program instructions. Although control circuitry 210 is shown as a separate component from processing elements 205, this represents one particular embodiment. In another embodiment, the functionality of control circuitry 210 is performed, at least in part, by processing elements 205. Fabric 215 represents any number and types of buses, communication devices / interfaces, interconnects, and other interface modules for connecting the various components of system 200 together.

[0022] In one embodiment, processing element 205 generates pixel data for display on display device 250. In one embodiment, this pixel data is written by processing element 205 to frame buffer 230 in memory 220 and then driven from frame buffer 230 to display device 250. In one embodiment, the pixel data stored in frame buffer 230 represents frames of a video sequence. In another embodiment, the pixel data stored in frame buffer 230 represents the screen content of a laptop or desktop personal computer (PC). In a further embodiment, the pixel data stored in frame buffer 230 represents the screen content of a mobile device (e.g., smartphone, tablet).

[0023] The memory subsystem 220 includes any number and type of memory controller and memory devices. In one embodiment, the memory subsystem 220 is capable of operating at a variety of different clock frequencies that can be adjusted according to various operating conditions. However, when a memory clock frequency change is implemented, memory training is typically performed to modify various parameters, adjust the characteristics of signals generated for data transfer, etc. For example, the phase, delay, and / or voltage levels of various memory interface signals are tested and adjusted during memory training. To train these memory interface signals, various signal transmissions may occur between the memory controller and memory. Memory access is generally halted during this training. Finding an appropriate time to perform this memory training when modifying the memory clock frequency can be difficult.

[0024] In one embodiment, control circuitry 210 is configured to cause memory subsystem 220 to change its performance state. When the performance state change is executed, control circuitry 210 causes display controller 150 to begin prefetching display data from memory 220 prior to the performance state change. When the performance state of memory 220 is changed, memory training is performed, which temporarily blocks access to memory 220. By having display controller 150 prefetch display data (via prefetch controller 240), the display controller is not deprived of video data during the training period. The prefetched data (e.g., pixel data) is stored in buffer 245 of prefetch controller 240 and driven to display device 250.

[0025] In one embodiment, control circuitry 210 includes memory bandwidth monitor 212, tracking circuitry 213, and frequency adjustment circuitry 214. Memory bandwidth monitor 212, tracking circuitry 213, and frequency adjustment circuitry 214 may be implemented using any combination of circuits, executing circuitry, and program instructions. Also, in another embodiment, memory bandwidth monitor 212, tracking circuitry 213, and frequency adjustment circuitry 214 are not part of control circuitry 210, but are individual circuits separate from control circuitry 210. In other embodiments, control circuitry 210 may include other arrangements of components that perform functions similar to memory bandwidth monitor 212, tracking circuitry 213, and frequency adjustment circuitry 214.

[0026] In one embodiment, memory bandwidth monitor 212 compares the real-time memory bandwidth demand of memory subsystem 220 to the memory bandwidth available at the current memory clock frequency. If the memory bandwidth available at the current memory clock frequency differs from the real-time memory bandwidth demand by more than a threshold, control circuit 210 alters the frequency of one or more clocks of memory subsystem 220.

[0027] In one embodiment, control circuitry 210 sends signals to prefetch controller 240 via sideband interface 247. Note that sideband interface 247 is separate from primary interface 242, which is used to pass pixels to prefetch controller 240. In one embodiment, primary interface 242 is an embedded display port (eDP) interface. In other embodiments, primary interface 242 is compatible with any of a variety of other protocols. Sending signals via sideband interface 247 allows prefetch timing and scheduling to occur in a relatively short period of time. This method contrasts with the traditional method of sending requests via primary interface 242, which can result in delays of several frames. FIG. 2 also shows signal 249 communicated by control circuitry 210 to memory subsystem 220, configured to cause the memory subsystem to change its current Pstate.

[0028] Once prefetch controller 240 completes prefetching data from memory 220, frequency adjustment circuit 214 generates a command to program clock signal generator 225 to generate the memory clock at a different frequency. In other embodiments, control circuit 210 includes other arrangements of logic and / or circuitry for making adjustments to the memory clock frequency. As used herein, the terms “logic” and “unit” refer to circuits or circuitry configured to perform the described functions. For example, in another embodiment, tracking circuit 213 and frequency adjustment circuit 214 are combined together into a single circuit. Other arrangements of circuits, processing elements, execution circuits, interface circuits, program instructions, and other components for implementing the functions of control circuit 210 are possible and contemplated.

[0029] System 200 can be any of a variety of types of computing systems. For example, in one embodiment, system 200 includes a laptop connected to an external display. In this embodiment, display device 250 is the laptop's internal display, and display device 270 is the external display. In another embodiment, system 200 includes a mobile device connected to an external display. In this embodiment, display device 250 is the mobile device's internal display, and display device 270 is the external display. Other scenarios employing components of system 200 to implement the techniques described herein are possible and contemplated.

[0030] Referring now to Figure 3, a timing diagram 300 is shown illustrating waveforms of one embodiment of the timing of memory clock frequency updates for a multi-display system. In the illustrated example, a signal is generated that allows the display controller to have temporarily increased memory bandwidth prior to a Pstate change to the memory device. As shown, Figure 3 illustrates a pre-Pstate change signal that is generated when it is determined that a memory Pstate change will occur. Such a determination may be made by a control circuit (e.g., 160 or 210) that includes a power management circuit.

[0031] At time 312, a pre-Pstate change 302 signal is shown. While the description describes various signals and indicators as being “asserted” and / or “communicated,” it should be noted that such assertion / communication may take various forms depending on the embodiment. For example, in some embodiments, assertion of a signal is performed by causing the signal to achieve a particular value or voltage level. In other embodiments, assertion of a signal or indicator is performed by writing a particular value to a register or memory location. All such embodiments are possible and contemplated. In various embodiments, this may be a signal asserted by a controller. In response to detection of signal 302, one or more bandwidth throttle signals 304 are generated at time 314. In another embodiment, the bandwidth throttle may be asserted by control circuitry immediately prior to initiating the pre-Pstate change. The amount of time elapsed between the assertion of signal 302 and the assertion of signal 304 varies depending on the embodiment. The bandwidth throttle signal (e.g., signal 114 of FIG. 1 ) is communicated to one or more circuits configured to generate memory accesses. In various embodiments, a bandwidth adjustment circuit corresponding to the circuit, such as bandwidth adjustment circuit 112 of FIG. 1, detects the bandwidth throttle signal and causes the corresponding memory access generating device to temporarily reduce the rate at which memory accesses are generated. In some embodiments, all memory accesses generated by the corresponding circuit are temporarily stopped (i.e., the rate goes to zero). In other embodiments, the rate is reduced or limited, but not to zero. In such embodiments, the device is permitted to generate memory accesses, but the rate is limited or reduced. The duration of the reduction (or "throttle") varies depending on the embodiment. In some embodiments, the duration is for a fixed amount of time (which may be programmable), after which memory access generation is no longer limited. In other embodiments, the duration lasts for a period determined based on a further signal indicating that prefetching is complete. A variety of such embodiments are possible and contemplated.

[0032] Following the assertion of the bandwidth throttle signal 304, at time 316, a prefetch signal 306 is communicated by the control circuitry (e.g., control circuitry 160, control circuitry 210) to the display controller. In some embodiments, the prefetch signal 306 may be communicated simultaneously with the assertion of the bandwidth throttle signal 304. In other embodiments, there is a delay between the assertion of signal 304 and the assertion of signal 306. In response to the assertion of the prefetch signal 306, the display controller (e.g., 150, 240) begins prefetching data from memory. As described above, while prefetching data from memory, other memory access generating clients temporarily reduce their memory bandwidth to ensure that the display controller has the desired increase in bandwidth. In this manner, the desired quality of service (QoS) of the displayed data can be maintained. After the display controller completes its access to memory, the bandwidth throttle 304 is deasserted, and the control circuitry changes the Pstate of the memory. In the illustrated example, the controller asserts the Pstate change signal 308 at time 318. In various embodiments, the control circuitry (160, 210) communicates or stores an indication of the new Pstate and clock frequency to which the memory should transition. In response to the Pstate change signal 308 at time 318, the memory subsystem enters the training period described above. As noted above, many memory devices (e.g., graphics double data rate (GDDR) synchronous dynamic random-access memory (SDRAM) devices) require memory training when the memory clock frequency is changed. For these memory devices, memory training is performed as part of the memory clock frequency change. After a period of time, memory training is complete at time 320, and the memory (subsystem) achieves a stable state at the new Pstate. At this point, accesses to the memory are no longer blocked (i.e., the memory blackout period ends).

[0033] 4, one embodiment of a method 500 for performing a display controller prefetch prior to a memory clock frequency change is shown. For purposes of illustration, the steps in this embodiment are shown sequentially. However, it should be noted that in various embodiments of the described method, one or more of the described elements may be performed simultaneously, in a different order than shown, or omitted entirely. Other additional elements may also be performed as desired. Any of the various systems or devices described herein may be configured to perform method 500.

[0034] In the embodiment of FIG. 4, control circuitry (such as control circuitry 160 of FIG. 1 or control circuitry 210 of FIG. 2) determines that one or more conditions are met to cause a change in the memory clock frequency of the memory subsystem (block 405). As an example, an increase or decrease in required memory bandwidth may be detected based on tasks being executed (or tasks queued for execution), thermal conditions, etc. For example, if an increase in memory accesses is detected, the memory clock frequency may be increased to increase the rate at which memory accesses can be completed. Conversely, if a decrease in the number of memory accesses is detected, the memory clock frequency may be decreased to reduce power consumption. Numerous such examples are possible and contemplated. In response to the detection of a condition, a signal (e.g., signal 302 of FIG. 3) may be asserted to one or more bandwidth adjustment circuits 112 that temporarily reduces the memory bandwidth of the corresponding client. In various embodiments, such a reduction may be implemented by preventing the selection of one or more pending memory accesses for servicing. For example, in some embodiments, the client is configured to store generated memory accesses in a queue or other location (e.g., an outgoing or pending queue), which are then selected for servicing and transmitted to the memory subsystem. In some embodiments, the bandwidth adjustment is achieved by causing the corresponding client to temporarily stop or slow down its generation of memory accesses. In one embodiment, the change to the memory clock frequency of the memory subsystem is performed as part of the power state change. The one or more conditions that trigger the change to the memory clock frequency may vary from embodiment to embodiment. For example, the condition may be triggered in response to detection of increased memory bandwidth requirements. For example, tasks corresponding to a particular type of application may have an increased need for bandwidth. In response, an increase in the memory Pstate is indicated. As another example, one or more processing circuits within the computing system may be detected to be idle or have reduced memory bandwidth needs.In response, a reduction in the memory Pstate is initiated to reduce system power consumption. In other embodiments, other conditions may cause a memory clock frequency change. For example, in one embodiment, connecting or disconnecting alternating current (AC) power or direct current (DC) power may cause the memory clock frequency to change. Different power sources may have different allowable clock ranges. In another embodiment, a change in the temperature of the host system or device may trigger a desire to change the memory clock frequency. For example, if the temperature of the host system / device exceeds a first threshold, the control circuitry will attempt to reduce power consumption to reduce the temperature. One way to reduce power consumption is by reducing the memory clock frequency. In a further embodiment, if the temperature falls below a second threshold, the control circuitry may increase the memory clock frequency, but in doing so, will not overheat the system / device. In yet another embodiment, if there is a requested performance increase or if a performance increase is deemed desirable (e.g., to increase computation speed, video display frame rate, etc.), the control circuitry will attempt to increase performance by increasing the memory clock frequency. Other conditions for changing the memory clock frequency are also possible and contemplated.

[0035] In some embodiments, the conditions for triggering a change to the memory clock frequency can be event-driven. For example, in various embodiments, the memory controller signals a throughput-related event when the throughput exceeds or falls below some threshold. Such events can be monitored during a programmable time window or can be temporally filtered in some manner. There can also be a software-, firmware-, or hardware-based mechanism that recognizes or predicts that a workload will require resources when requested before the workload is scheduled or executed. Similarly, when a workload ends, the mechanism knows which resources are no longer needed (i.e., the workload in question is completed and no longer requires the resources). Similar mechanisms can also account for periodic workloads. In another embodiment, a real-time operating system (RTOS) may be aware of deadlines, and the RTOS can choose a more optimal clock depending on the approaching deadline.

[0036] In response to detecting (405) a condition for causing a change in memory clock frequency, the control circuit generates a bandwidth throttle signal, which is then detected by one or more bandwidth adjustment circuits within the computing system. As described above, detecting the bandwidth adjustment signal causes one or more devices within the computing system to reduce their rate of memory accesses communicated to the memory system. The control circuit then generates (415) or communicates a prefetch signal (e.g., signal 247 of FIG. 2 ). In response to detecting the prefetch signal, the display controller initiates prefetching of display data from the memory subsystem. Following completion (420) of the display controller prefetching of the data, the control circuit (160, 210) initiates or causes a Pstate change to the memory. In various embodiments, completion of the prefetch (420) is determined based on the passage of a predetermined period of time (which may be programmable). In other embodiments, the display controller may communicate an indication that the prefetch is complete. In such an embodiment, the display controller may communicate an indication in response to receiving the prefetched data, or possibly in response to determining that the prefetching of data from memory is complete and in the process of being transferred to the display controller. In other words, even if not all of the prefetched data has yet reached the display controller, it is believed that no further accesses to memory are required. These and other embodiments are possible and contemplated.

[0037] Upon completion of the display controller's prefetching of data, the bandwidth throttle is released (422) (i.e., bandwidth throttling is stopped), and the control circuitry initiates a memory Pstate change. In various embodiments, the Pstate change includes changing the memory clock frequency (block 425). In one embodiment, memory training is performed as part of the memory clock frequency update. After the memory clock frequency update and training are completed (430), memory accesses can again be performed. In some embodiments, the control circuitry (e.g., 160, 210) communicates a signal to the bandwidth adjustment circuitry (112) to suspend memory bandwidth throttling of the corresponding device. In other embodiments, the bandwidth throttling continues for a predetermined period of time, as described above. Note that method 400 can be repeated each time a condition for changing the memory clock frequency is detected.

[0038] In various embodiments, program instructions of a software application are used to implement the methods and / or mechanisms described herein. For example, program instructions executable by a general-purpose or special-purpose processor are contemplated. In various embodiments, such program instructions are expressed in a high-level programming language. In other embodiments, the program instructions are compiled from the high-level programming language into binary, intermediate, or other form. Alternatively, program instructions that describe the behavior or design of hardware are written. Such program instructions are expressed in a high-level programming language such as C. Alternatively, a hardware design language (HDL) such as Verilog is used. In various embodiments, the program instructions are stored on any of a variety of non-transitory computer-readable storage media. The storage medium is accessible by the computing system during use to provide the program instructions to the computing system for program execution. Generally speaking, such a computing system includes at least one or more memories and one or more processors configured to execute the program instructions.

[0039] It should be emphasized that the above-described embodiments are merely non-limiting examples of embodiments. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.

Claims

1. 1. An apparatus comprising: A control circuit is provided, The control circuit In response to determining that a condition is met for changing the performance state of the memory subsystem, reducing memory bandwidth of clients configured to generate memory accesses to the memory subsystem; causing a display controller to prefetch display data from the memory subsystem; configured to: Device.

2. the control circuitry is configured to communicate an indication to a bandwidth adjustment circuit corresponding to the client to reduce the memory bandwidth; 10. The apparatus of claim 1.

3. the control circuitry is configured to cause the memory subsystem to enter a training period following the prefetch.

10. The apparatus of claim 1.

4. Access to memory is blocked during the training period.

4. The apparatus of claim 3.

5. After the training period is completed, the memory bandwidth reduction stops.

5. The apparatus of claim 4.

6. determining that a condition for changing the performance state of the memory subsystem is met includes one or more of detecting a client idle state, detecting an increase in a client's memory bandwidth requirement, detecting a change in temperature, determining that the memory bandwidth demand differs from the memory bandwidth available at the current memory clock frequency by more than a threshold, or detecting a requested performance increase; 6. The apparatus of claim 5.

7. the control circuitry is configured to cause the display controller to prefetch the display data by communicating a signal to the display controller; 10. The apparatus of claim 1.

8. the control circuitry is configured to reduce the memory bandwidth for a predetermined period of time.

8. The apparatus of claim 7.

9. 1. A method comprising: In response to a condition being met to change the performance state of the memory subsystem, reducing memory bandwidth of clients configured to generate memory accesses to the memory subsystem; causing a display controller to prefetch display data from the memory subsystem; method.

10. communicating an indication to a bandwidth adjustment circuit corresponding to the client to reduce the memory bandwidth.

10. The method of claim 9.

11. subsequent to said prefetching, causing said memory subsystem to enter a training period.

10. The method of claim 9.

12. access to the memory is blocked during the training period; The method of claim 11.

13. After the training period is completed, the memory bandwidth reduction stops.

13. The method of claim 12.

14. determining that a condition for changing the performance state of the memory subsystem is met includes one or more of detecting a client idle state, detecting an increase in a client's memory bandwidth requirement, detecting a change in temperature, determining that the memory bandwidth demand differs from the memory bandwidth available at the current memory clock frequency by more than a threshold, or detecting a requested performance increase; 14. The method of claim 13.

15. transmitting a signal to the display controller to cause the display controller to prefetch the display data; 10. The method of claim 9.

16. reducing the memory bandwidth for a predetermined period of time.

16. The method of claim 15.

17. 1. A system comprising: a memory subsystem; one or more clients configured to generate memory accesses to the memory subsystem; A display controller; a control circuit; The control circuit In response to determining that a condition is met for changing a performance state of the memory subsystem, reducing memory bandwidth of the one or more clients; and causing the display controller to prefetch display data from the memory subsystem; configured to: system.

18. the system includes a bandwidth adjustment circuit corresponding to the one or more clients; the control circuitry is configured to reduce memory bandwidth of the one or more clients by communicating an indicator to the bandwidth adjustment circuitry.

18. The system of claim 17.

19. the control circuitry is configured to cause the memory subsystem to enter a training period following prefetching of display data by the display controller.

20. The system of claim 18.

20. access to the memory is blocked during the training period; 20. The system of claim 19.

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