Local interconnect network bus repeater delay compensation

Abstract

An integrated circuit is described that may include: a receiver circuit coupled to a segment of a LIN bus to receive bits; a measurement circuit coupled to the receiver circuit to measure rise and fall times of the bits, or a bit time and a second bit time of the bits; control logic coupled to the measurement circuit to compare the rise and fall times or the bit time and the second bit time; a transmitter circuit coupled to the receiver circuit to transmit the bits on the second segment of the LIN bus; and a delay circuit coupled to the control logic to apply a delay to one or more rising or falling edges of the bits, or one or more bit times or the second bit times of the bits, based at least in part on the comparison.

Description

[Technical Field]

[0001] The present disclosure relates to techniques for repeater delay compensation in a local interconnect network (LIN) bus. [Background technology]

[0002] To improve safety and provide more convenient transportation, many automobile manufacturers include additional sensors and / or features in their vehicles. For example, autonomous vehicles typically include a variety of sensors, such as acoustic and / or electromagnetic sensors, that monitor the surrounding environment to detect other vehicles, people, animals, or obstacles. Additionally, many vehicles include sensors that monitor the operation of the vehicle (e.g., parking sensors or seat adjustment sensors), and more commonly, components that provide features or functionality (e.g., interior lighting).

[0003] Electrically connecting these sensors and components within a vehicle to one or more integrated circuits is often a challenge. In particular, the sensors and components within existing vehicles are often in different locations. Furthermore, the sensors and components within existing vehicles are often electrically connected to one or more integrated circuits using separate wiring. However, as the number of sensors and components continues to increase, the wiring becomes increasingly complex, costly, and difficult to install and maintain. Summary of the Invention [Means for solving the problem]

[0004] An embodiment of an integrated circuit is described that includes an input pad or connector that couples to a segment of a local interconnect network (LIN) bus, a receiver circuit coupled to the input pad or connector and receives bits, a measurement circuit coupled to the receiver circuit and measuring rise and fall times of the bits, or a bit time and a second bit time of the bits, control logic coupled to the measurement circuit and comparing the rise and fall times or the bit time and the second bit time, a transmitter circuit coupled to the receiver circuit and transmitting the bits on an output pad or connector, an output pad or connector coupled to the transmitter circuit and coupling to a second segment of the LIN bus, and a delay circuit coupled to the control logic and applying a delay to one or more rising or falling edges of the bits, or one or more bit times or the second bit times of the bits based at least in part on the comparison.

[0005] It should be noted that the measurement circuitry may perform the measurement based at least in part on a synchronous clock corresponding to the bit.

[0006] Additionally, the delay circuit may include a digital counter.

[0007] Furthermore, the bit time may correspond to a value of the bit, and the second bit time may correspond to a second value of the bit that is smaller than the above value.

[0008] Additionally, the delay may be adjustable (e.g., may have a continuous value). Alternatively, the delay may have a predefined value or a predefined value within a set of possible predefined values.

[0009] In some embodiments, the integrated circuit may include a data repeater.

[0010] Note that when the rise time is greater than the fall time, the delay circuit may delay one or more falling edges, and when the fall time is greater than the rise time, the delay circuit may delay one or more rising edges. Alternatively, or additionally, when the bit time is greater than the second bit time, the delay circuit may shorten the bit time, and when the second bit time is greater than the bit time, the delay circuit may shorten the second bit time.

[0011] The integrated circuit further includes a second input pad or connector coupled to a second segment of the LIN bus; a second receiving circuit coupled to the second input pad or connector and receiving a second bit; a second measuring circuit coupled to the second receiving circuit and measuring a second rise time and a second fall time of the second bit, or a third bit time and a fourth bit time of the second bit; and second control logic coupled to the second measuring circuit and comparing the second rise time and the second fall time, or the third bit time and the fourth bit time. , a second transmitting circuit coupled to the second receiving circuit and transmitting the received second bit on a second output pad or connector; a second output pad or connector coupled to the second transmitting circuit and coupling to a second segment of the LIN bus; and a second delay circuit coupled to the second control logic and applying a second delay to one or more second rising edges or second falling edges in the second bit, or one or more third bit times or fourth bit times in the second bit, based at least in part on the comparison.

[0012] Additionally, the second control logic may be different from the control logic. Alternatively, the second control logic may be the same as the control logic.

[0013] Another embodiment provides an electronic device including an integrated circuit.

[0014] Another embodiment provides a system including an integrated circuit.

[0015] Another embodiment provides a method for performing compensation, the method including at least some of the operations being performed by an integrated circuit.

[0016] This summary is provided for the purposes of illustrating some exemplary embodiments to provide a basic understanding of some aspects of the subject matter described herein. Accordingly, it should be appreciated that the above-described features are examples and should not be construed to narrow the scope or spirit of the subject matter described herein in any way. Other features, aspects, and advantages of the subject matter described herein will become apparent from the following detailed description, figures, and claims. [Brief explanation of the drawings]

[0017] [Figure 1] FIG. 1 is a block diagram illustrating an example of a local interconnect network (LIN) bus according to some embodiments of the present disclosure. [Figure 2] 2 is a timing diagram illustrating an example of communication using the LIN bus of FIG. 1 according to some embodiments of the present disclosure. [Figure 3] 2 is a block diagram illustrating an example of an integrated circuit including a data repeater in the LIN bus of FIG. 1 according to some embodiments of the present disclosure. [Figure 4] 2 is a timing diagram illustrating an example of communication using the LIN bus of FIG. 1 according to some embodiments of the present disclosure. [Figure 5] 2 is a timing diagram illustrating an example of communication using the LIN bus of FIG. 1 according to some embodiments of the present disclosure. [Figure 6] 2 illustrates an example of simulated propagation delay along the LIN bus of FIG. 1 in accordance with some embodiments of the present disclosure. [Figure 7] 2 is a timing diagram illustrating an example of communication using the LIN bus of FIG. 1 according to some embodiments of the present disclosure. [Figure 8] 1 is a flow diagram illustrating an example of a method for performing compensation according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0018] Note that reference numerals refer to corresponding parts throughout the drawings. Additionally, multiple instances of the same part are designated by a common prefix separated from the instance number by a dash symbol.

[0019] An integrated circuit is described that may include: a receiver circuit coupled to a segment of a LIN bus to receive bits; a measurement circuit coupled to the receiver circuit to measure rise and fall times of the bits, or a bit time and a second bit time of the bits; control logic coupled to the measurement circuit to compare the rise and fall times or the bit time and the second bit time; a transmitter circuit coupled to the receiver circuit to transmit the bits on the second segment of the LIN bus; and a delay circuit coupled to the control logic to apply a delay to one or more rising or falling edges of the bits, or one or more bit times or the second bit times of the bits, based at least in part on the comparison.

[0020] By delaying one or more rising or falling edges of a bit, or one or more bit times or second bit times of a bit, these circuit techniques can perform compensation to correct or maintain the duty cycle of the bit. This capability can allow the LIN bus to include different lengths or wires, or alternatively, a variable number of nodes or modules. Thus, the circuit techniques can improve the performance of the LIN bus as a function of different lengths or different numbers of nodes or modules. Thus, the circuit techniques can increase the adoption of the LIN bus in various applications, such as automotive applications. Furthermore, by improving the performance of the LIN bus, the circuit techniques can improve LIN bus user satisfaction.

[0021] An embodiment of this circuit technique will now be described. As mentioned above, electrically connecting sensors and components within a vehicle is often a challenge. One approach to addressing these issues is for the sensors and components to share common wiring. For example, the sensors and components may be electrically connected in series using a bus such as a LIN bus.

[0022] In particular, the LIN bus is a type of bus that is often used in automotive applications. LIN buses generally include a single wire for communication in a given direction and may communicate data frames (including data bits) using an open-drain 12V universal asynchronous receiver / transmitter (UART) operating at a maximum frequency of 20 kHz. Furthermore, LIN buses typically operate using a master-slave protocol with up to eight serially connected nodes or modules (including masters and slaves), with a given slave on the LIN bus having an associated address. For example, the eight modules may include sensors. Note that some components (e.g., parking sensors) may benefit from automatic location detection, for example, where the associated LIN bus address depends on the physical location of the given sensor. This capability may enable a single sensor or component (e.g., a bumper sensor) to be used at different sensor or component locations (e.g., multiple bumper locations).

[0023] For example, to detect a sensor or component position, a LIN bus may implement slave node position detection (SNPD) by using SNPD switch technology. In the SNPD switch technology, the LIN bus may have a LIN IN wire and a LIN OUT wire. The LIN IN wire may be electrically coupled to a LIN transmit (TRX) pin on a given module (e.g., master or slave) on the LIN bus. Additionally, there may be a bidirectional switch (e.g., a FET) on the circuit board or within a given module, which connects the LIN OUT to the LIN IN under software control. A master on the LIN bus may assign an address to a slave and instruct the slave to turn on its bidirectional switch to communicate with further downstream slaves on the LIN bus. Note that bidirectional switches generally have low resistance (less than 0.3 R). Therefore, when implemented on an integrated circuit for a given module, a bidirectional switch may consume a large amount of area, increasing cost. Alternatively, when implemented as an external component on a circuit board containing a given module, a bidirectional switch may also increase cost.

[0024] Figure 1 presents a block diagram illustrating an example of a LIN bus 100. In particular, Figure 1 shows serially daisy-chained modules 110 or nodes along the LIN bus 100 (such as segments of the bidirectional LIN bus 112) electrically coupled by a bidirectional LIN bus. Note that adjacent pairs of modules in Figure 1 are electrically coupled by separate LIN bus segments that logically operate as a single LIN bus 100.

[0025] During operation, a body control module (BCM) 114 in the LIN bus 100 may communicate one or more data frames to a receiver 116, such as one of the modules 110. In particular, the one or more data frames may be addressed to the receiver 116. While all modules 110 may have one or more data frames, only the designated (addressed) receiver 116 may act in response to receiving the one or more data frames. Thus, via a master-slave protocol, the BCM 114 may trigger communications from the receiver 116. Two or more modules 110 may be different types of modules or may be identical instances of the same type of module, such as a certain type of sensor.

[0026] 1 may implement SNPD. For example, a data repeater (such as data repeater 118) in each of modules 110 in LIN bus 100 may copy data frames upstream and downstream. Note that the data repeaters may be turned off before LIN bus 100 is configured. Thus, SNPD may be implemented when each data repeater is sequentially turned on.

[0027] Figure 2 presents a timing diagram illustrating an example of communication using the LIN bus 100 of Figure 1. In particular, Figure 2 shows electrical signals 212 on different segments of the directional LIN bus 112 as a function of time 210. In Figure 2, data bits may be transmitted from the BCM 114 and repeated with a small delay to the receiver 116.

[0028] 1, it should be noted that in some embodiments, one or more of the modules 110 shown in FIG. 1 (e.g., the first module to the right of the BCM 114, sometimes referred to as “LINA”) may not be part of a local LIN bus between components or sensors (e.g., located within the bumper). For example, the link between the BCM 114 and LINA may be part of a communication link between the BCM 114 and the bumper.

[0029] In some embodiments, a data repeater may be used to implement the SNPD switch technique. This is illustrated in FIG. 3, which presents a block diagram of an integrated circuit 300 in a module or node within the LIN bus 100 (FIG. 1) that includes a data repeater. In particular, the integrated circuit 300 that includes the data repeater may have two LIN transmitters (TRX) 306 (each LIN transmitter 306 occupies a smaller area than a low-resistance switch), and the LIN transmitters 306 may be implemented using FETs. The data repeater within the integrated circuit 300 may be implemented using small digital logic circuits. This approach may enable data bits communicated on the LIN bus 100 (FIG. 1) to be regenerated, thereby allowing the data bits to be communicated over longer wire lengths within the LIN bus 100 (FIG. 1). For example, if integrated circuit 300 is node position 1 in LIN bus 100 (FIG. 1) and a master communicates data bits in a data frame to node position 1, upstream receiver 308-1 (such as a Schmitt trigger) of integrated circuit 300 may receive the data bits and downstream transmitter 306-1 may repeat the data bits to node position 2.

[0030] In the foregoing example, it should be noted that the implementation shown in FIG. 3 does not include compensation. Thus, as explained, this implementation may only function under ideal conditions. For example, the length (and therefore capacitance) of the wires in LIN bus 100 (FIG. 1) may vary from node to node or module 110 (FIG. 1). Because path 310 in integrated circuit 300 may need to be faster than path 312, it may be necessary to add a delay to path 312. Additionally, as described further below, integrated circuit 300 may optionally include measurement circuit 314 (e.g., a digital counter), delay circuit 316, and / or control logic 318 to perform compensation for rising and / or falling edges in repeated data bits to maintain a duty cycle.

[0031] While the LIN bus can reduce the number of wires in a vehicle (thus reducing the associated complexity, expense, and difficulty of installation and maintenance), it can also pose additional challenges. For example, as the number of modules 110 (FIG. 1) on the LIN bus 100 (FIG. 1) increases, it can become increasingly difficult for the modules 110 (FIG. 1) to receive data frames due to propagation delays. This is illustrated in FIG. 4, which presents a timing diagram illustrating an example of communication using the LIN bus 100 (FIG. 1). In particular, FIG. 4 illustrates the timing for four nodes or modules 110 (e.g., LINB, LINC, LIND) in a daisy chain where rising edge 410 is the same as falling edge 412. In this case, the width of the received data bit (RXD) is the same at node positions 2, 3, and 4. RXD2 = t RXD3 = t RXD4 = t TXD1 Therefore, a data bit transmitted from node location 1 will arrive at node location 4 with the same pulse width (with a small delay). More generally, the lengths of '1' and '0' data bits typically need to be maintained throughout the LIN bus 100 (Figure 1).

[0032] Note that the LIN bus 100 (FIG. 1) is generally driven "low" by an active pulldown, but typically driven "high" by a passive resistive pullup. Therefore, when driving a 50% square wave signal, the high and low periods (as seen by the logic inputs) may have different duty cycles. However, the maximum and minimum duty cycles are limited by and specified in the LIN bus standard (from CAN in Automation (CiA) 391, Nuremburg, Germany). In particular, passive devices (such as switches) typically do not vary the duty cycle much, while active repeaters (with logic inputs) often have different propagation delays for rising and falling edges. This asymmetry causes the high and low bit times along the LIN bus 100 (FIG. 1) to become increasingly different lengths as more nodes or modules 110 (FIG. 1) are added. This dispersion is generally unpredictable (e.g., dependent on the capacitance of the LIN bus 100 in FIG. 1). If the dispersion is not compensated for, communication on the LIN bus 100 (FIG. 1) can become unreliable.

[0033] To address this issue, the disclosed circuit techniques may be used to maintain a duty cycle for high and low bit times during communication on LIN bus 100 (FIG. 1). In particular, a downstream receiver (such as downstream receiver 308-2 in FIG. 3) may be used to sense how LIN bus 100 (FIG. 1) is behaving, and low or high periods may be extended to maintain a duty cycle for high and low bits.

[0034] The effect of biased rise and fall times or delays is illustrated in FIG. 5, which presents a timing diagram illustrating an example of communication using the LIN bus 100 (FIG. 1). In particular, FIG. 5 illustrates the timing when rising edges 510 are faster than falling edges 512 for all nodes or modules 110 (FIG. 1) (e.g., LINB, LINC, LIND) on the daisy chain. This situation can occur when capacitance on the LIN bus 100 (FIG. 1) is low, such as when the LIN bus 100 (FIG. 1) has only two nodes and therefore a short wire length. In this case, the width of the received data bits can be short along the daisy chain. TXD1 > t RXD2 > t RXD3 > t RXD4 Therefore, a data bit transmitted from node location 1 may arrive at node location 4 with a smaller pulse width (with a delay).

[0035] Within a few nodes (3 nodes in the worst case), the pulse width deviation may exceed that allowed by the LIN bit width specification. Even when the pulse width does not need to meet the LIN specification, the universal asynchronous receiver / transmitter (UART) may fail after a few more nodes or modules (thus failing after fewer than the 8 nodes or modules that may be used in many applications).

[0036] FIG. 6 presents a diagram illustrating a simulated example of propagation delay along LIN bus 100 (FIG. 1) in the presence of biased rise and fall times or delays.

[0037] Ideally, a 50% square wave signal has the same duty cycle when transmitted by a data repeater. Nevertheless, the propagation delay of either the rising edge or the falling edge may be longer (depending on the capacitance of the LIN bus). When the data repeater has a sufficiently fast reference clock (e.g., 16 MHz vs. 20 kHz LIN bus clock frequency), this delay can be measured using a downstream LIN transmitter (such as downstream transmitter 306-2 in FIG. 3). Then, when the rising edge propagation delay is longer, the falling edge can be delayed using a delay circuit (e.g., using synchronization logic, e.g., using a digital counter). Alternatively, when the falling edge propagation delay is longer, the rising edge can be delayed using a delay circuit (e.g., using synchronization logic, e.g., using a digital counter). Thus, in this circuit technique, compensation can be applied to maintain the duty cycle. Notably, after compensation, the duty cycles of the high bit time and the low bit time are the same or approximately the same (e.g., within 1%, 5%, 10%, or 20% of each other).

[0038] For example, when data is received upstream and repeated downstream, a measurement of the fall time or delay associated with a '1' to '0' transition may be performed (e.g., using measurement circuit 314-1) using, for example, a high-speed synchronous clock (e.g., 16 MHz). Further, when a second data bit is received upstream and repeated downstream, a measurement of the rise time or delay associated with a '0' to '1' transition may be performed using, for example, a high-speed synchronous clock. The duration of the high bit time (e.g., the bit time associated with a '1') and the duration of the low bit time (e.g., the bit time associated with a '0') may then be compared. Alternatively, the fall time or delay may be compared to the rise time or delay. Based at least in part on the comparison, a correction may be applied to the current and / or subsequent falling or rising edge (e.g., using delay circuit 316-2) so that the duration of the high bit time is at least approximately the same as the duration of the low bit time. In particular, in some implementations, the compensation may include using a delay circuit to delay the falling edge when the rise time or delay is greater than the fall time or delay, and using a delay circuit to delay the rising edge when the fall time or delay is greater than the rise time or delay. By applying this correction to every rising or falling edge, this circuit technique may compensate for temperature variations. Note that the compensation may be applied at one transmitter (unidirectional) or two transmitters (bidirectional).

[0039] In some embodiments, the measurement may be performed using a digital counter.

[0040] Additionally, as previously mentioned, in some embodiments the comparison is made relative to two measurements, such as a rise time or delay and a fall time or delay, or a high bit time and a low bit time, but in other embodiments the comparison may be made relative to a reference or target value, such as a predefined rise time or delay, a predefined fall time or delay, a predefined high bit time, and / or a predefined low bit time.

[0041] 7 presents a timing diagram illustrating an example of communication using the LIN bus 100 (FIG. 1). In particular, as previously mentioned, asymmetries in rise / fall times or delays can be compensated for by adjusting the width of the transmitted data (the inverse of this signal can control the LIN pull-down driver). For example, at node location 1, t TXDC1 may be a symmetric bit width generated by a LIN controller (such as control logic 318). To compensate for slow falling edges, t TXDC1 Delay to high time t TXDDEL1 Add t TXD1 Therefore, the width of the data bit received at node location 2 can be "corrected" so that the data bit has the intended width, i.e., t RXD2 = t TXDC1 The net effect may be a correction (such as correction 710) such that the width of the transmitted data is insensitive to the slope of the falling and rising edges. Note that an adjustable delay may be added at each node position, allowing the daisy-chain length of LIN bus 100 (FIG. 1) to be extended to any number of nodes or modules.

[0042] Next, measuring rise and fall times or delays will be described. In particular, the delay applied at node location 1 may need to compensate for the delay on LINB as it is received at node location 2. At node location 1, this may be accomplished by having a receiver identical to the receiver at node location 2. Furthermore, if the signals seen on LINB at node location 1 and node location 2 are identical or nearly identical (e.g., 1%, 5%, 10%, or 20% of each other), the receiver at node location 1 can be used as a proxy for the receiver at node location 2. Note that there are errors that can cause the identity assumption to be incorrect, such as voltage drops on the voltage from the battery (VBAT) along the LIN bus 100 (FIG. 1). However, these errors are generally small. Therefore, with this circuit technique, the delay between the transmit (TXD) and receive (RXD) signals at any transmit pin (e.g., in integrated circuit 300 in FIG. 3) can be used to calculate the delay to apply to the transmit signal.

[0043] Note that the measured rise or fall time or delay may be measured at each transmitter (such as upstream transmitter 306-1 or downstream transmitter 306-2 in FIG. 3). The determined delay may be applied to data bits whenever this transmitter transmits data, such as when the data bits are from a controller in the same node or module as this transmitter, or when the transmitter is acting as a data repeater.

[0044] Although the above description illustrates the use of this circuit technique with a LIN bus (such as, for example, LIN bus 100 in FIG. 1), in other embodiments, the circuit technique may be used with other types of electrical or optical buses, such as a USB bus.

[0045] Method embodiments will now be described. FIG. 8 presents a flow chart illustrating an example of a method 800 for performing compensation using an integrated circuit, such as integrated circuit 300 (FIG. 3). During operation, the integrated circuit may perform rise time or delay and fall time or delay measurements for bits, e.g., data bits in a data frame (operation 810). The integrated circuit may then compare the rise time or delay with the fall time or delay (operation 812). When the rise time or delay is greater than the fall time or delay (operation 812), the integrated circuit may delay a current falling edge and / or one or more subsequent falling edges of the bit (operation 814). Alternatively, when the rise time or delay is shorter than the fall time or delay (operation 812), the integrated circuit may delay a current rising edge and / or one or more subsequent rising edges of the bit (operation 816). The integrated circuit may then optionally repeat at least some of the operations in method 800 (operation 818).

[0046] In some embodiments of method 800, there may be additional or fewer operations. Additionally, the order of the operations may be changed and / or two or more operations may be combined into a single operation.

[0047] The disclosed integrated circuits and circuit techniques can be (or can be included in) any electronic device or system. For example, the electronic device may include a mobile phone or smartphone, a tablet computer, a laptop computer, a notebook computer, a personal or desktop computer, a netbook computer, a media player device, an e-book device, a MiFi® device, a smart watch, a wearable computing device, a portable computing device, a consumer electronic device, an access point, a router, a switch, communications equipment, test equipment, a vehicle, a watercraft, an aircraft, an automobile, a truck, a bus, a motorcycle, manufacturing equipment, farm equipment, construction equipment, or another type of electronic device.

[0048] Although embodiments of an integrated circuit and / or integrated circuits containing the integrated circuit have been described using particular components, in alternative embodiments, different components and / or subsystems may be present within the integrated circuit and / or integrated circuits containing the integrated circuit. Thus, embodiments of an integrated circuit and / or integrated circuits containing the integrated circuit may include fewer components, additional components, different components, two or more components may be combined into a single component, a single component may be separated into two or more components, one or more positions of one or more components may be changed, and / or there may be different types of components.

[0049] Furthermore, the circuits and components in embodiments of the integrated circuit and / or the integrated circuit including the integrated circuit may be implemented using any combination of analog and / or digital circuits, including bipolar, PMOS, and / or NMOS gates or transistors. Furthermore, signals in these embodiments may include digital signals having generally discrete values ​​and / or analog signals having continuous values. Additionally, components and circuits may have single-ended or differential inputs, and power supplies may be unipolar or bipolar. It should be noted that electrical couplings or connections in the foregoing embodiments may be direct or indirect. In the foregoing embodiments, a single line corresponding to a route may refer to one or more single lines or routes.

[0050] As mentioned above, an integrated circuit may perform some or all of the functionality of the circuit techniques. The integrated circuit may include hardware and / or software mechanisms used to perform the functionality associated with the circuit techniques.

[0051] In some embodiments, the output of a process for designing an integrated circuit or portion of an integrated circuit including one or more of the circuits described herein may be a computer-readable medium, such as, for example, a magnetic tape or an optical or magnetic disk. The computer-readable medium may be encoded with data structures or other information describing circuits that may be physically instantiated in the integrated circuit or as part of the integrated circuit. While various formats may be used for such encoding, these data structures are commonly written in Caltech Intermediate Format (CIF), Karma GDS II Stream Format (GDSII), Format for Electronic Design Interchange (EDIF), Open Access (OA), or Open Artwork Systems Interchange Standard (OASIS). One skilled in the art of integrated circuit design can develop such data structures from schematic diagrams and corresponding descriptions of the type detailed above and encode the data structures on a computer-readable medium. One skilled in the art of integrated circuit fabrication can use such encoded data to fabricate integrated circuits including one or more of the circuits described herein.

[0052] Although some of the operations in the above-described embodiments have been implemented in hardware or software, in general, the operations in the above-described embodiments can be implemented in a wide variety of configurations and architectures. Thus, some or all of the operations in the above-described embodiments may be implemented in hardware, software, or both. For example, at least some of the operations in the circuit techniques may be implemented using program instructions executed by a processor or in firmware within an integrated circuit.

[0053] Additionally, while example values ​​are provided in the above discussion, other embodiments use different values, and therefore the values ​​provided are not intended to be limiting.

[0054] In the above description, reference is made to "some embodiments." It should be noted that "some embodiments" describes a subset of all possible embodiments, but does not necessarily designate the same subset of embodiments.

[0055] The above description is intended to enable any person skilled in the art to make and use the present disclosure, and is provided in the context of a particular application and its requirements. Moreover, the foregoing description of embodiments of the present disclosure has been presented for purposes of illustration and description only. The description is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. Accordingly, many modifications and variations will be apparent to those skilled in the art. The general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. Additionally, the discussion of the foregoing embodiments is not intended to limit the present disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein. [Explanation of symbols]

[0056] 100 LIN bus 110 modules 112 Bidirectional LIN Bus 114 Body Control Module 116 Receiver 118 Data Repeater 210 hours 212 Electrical Signals 300 Integrated Circuits 306 LIN transmitter 306-1 Upstream Transmitter 306-2 Downstream Transmitter 308-1 Upstream Receiver 308-2 Downstream Receiver 312 Routes 314 Measurement circuit 316 Delay Circuit 318 Control Logic 391 LIN bus standard 410, 510 rising edge 412, 512 Falling Edge 710 Correction

Claims

1. 1. An integrated circuit comprising: an input pad or connector configured to couple to a segment of a local interconnect network (LIN) bus; a receiving circuit coupled to the input pad or connector and configured to receive bits; a measurement circuit coupled to the receiving circuit and configured to measure a rise time and a fall time of the bit, or a bit time and a second bit time of the bit; control logic coupled to the measurement circuit and configured to compare the rise time and the fall time, or the bit time and the second bit time; a transmitter circuit coupled to the receiver circuit and configured to transmit the bits on an output pad or connector; the output pad or connector coupled to the transmitter circuit and configured to couple to a second segment of the LIN bus; a delay circuit coupled to the control logic and configured to apply a delay to one or more rising or falling edges of the bits, or to one or more bit times or second bit times of the bits, based at least in part on the comparison; 1. An integrated circuit comprising:

2. The integrated circuit of claim 1 , wherein the measurement circuit is configured to perform the measurement based at least in part on a synchronized clock corresponding to the bit.

3. The integrated circuit of claim 1 , wherein the delay circuit comprises a digital counter.

4. The integrated circuit of claim 1 , wherein the bit time corresponds to a value of the bit and the second bit time corresponds to a second value of the bit that is less than the value.

5. The integrated circuit of claim 1 , wherein the delay is adjustable.

6. The integrated circuit of claim 1 , wherein the integrated circuit comprises a data repeater.

7. the delay circuit is configured to delay the one or more falling edges when the rise time is greater than the fall time; The integrated circuit of claim 1 , wherein the delay circuit is configured to delay the one or more rising edges when the fall time is greater than the rise time.

8. the delay circuit is configured to shorten the bit time when the bit time is greater than the second bit time; The integrated circuit of claim 1 , wherein the delay circuit is configured to shorten the second bit time when the second bit time is greater than the bit time.

9. The integrated circuit comprises: a second input pad or connector configured to couple to the second segment of the LIN bus; a second receiving circuit coupled to the second input pad or connector and configured to receive a second bit; a second measurement circuit coupled to the second receiving circuit and configured to measure a second rise time and a second fall time of the second bit or a third bit time and a fourth bit time of the second bit; second control logic coupled to the second measurement circuit and configured to compare the second rise time with the second fall time, or the third bit time with the fourth bit time; a second transmitter circuit coupled to the second receiver circuit and configured to transmit the second bit on a second output pad or connector; a second output pad or connector coupled to the second transmitter circuit and configured to couple to the second segment of the LIN bus; a second delay circuit coupled to the second control logic and configured to apply a second delay to one or more second rising edges or second falling edges of the second bit, or to one or more third bit times or fourth bit times of the second bit, based at least in part on the comparison; The integrated circuit of claim 1 , comprising:

10. The integrated circuit of claim 9 , wherein the second control logic is different from the control logic.

11. 1. An electronic device comprising an integrated circuit, the integrated circuit comprising: an input pad or connector configured to couple to a segment of a local interconnect network (LIN) bus; a receiving circuit coupled to the input pad or connector and configured to receive bits; a measurement circuit coupled to the receiving circuit and configured to measure a rise time and a fall time of the bit, or a bit time and a second bit time of the bit; control logic coupled to the measurement circuit and configured to compare the rise time and the fall time, or the bit time and the second bit time; a transmitter circuit coupled to the receiver circuit and configured to transmit the bits on an output pad or connector; the output pad or connector coupled to the transmitter circuit and configured to couple to a second segment of the LIN bus; a delay circuit coupled to the control logic and configured to apply a delay to one or more rising or falling edges of the bits, or to one or more bit times or second bit times of the bits, based at least in part on the comparison; An electronic device comprising:

12. 12. The electronic device of claim 11, wherein the measurement circuitry is configured to perform the measurement based at least in part on a synchronized clock corresponding to the bit.

13. The electronic device of claim 11 , wherein the delay circuit comprises a digital counter.

14. The electronic device of claim 11 , wherein the bit time corresponds to a value of the bit, and the second bit time corresponds to a second value of the bit that is smaller than the value.

15. The electronic device of claim 11 , wherein the delay is adjustable.

16. the delay circuit is configured to delay the one or more falling edges when the rise time is greater than the fall time; The electronic device of claim 11 , wherein the delay circuit is configured to delay the one or more rising edges when the fall time is greater than the rise time.

17. The electronic device of claim 11 , wherein the electronic device comprises a vehicle.

18. 1. A method for implementing compensation, comprising: The integrated circuit receiving, on an input pad or connector, bits associated with a segment of a local interconnect network (LIN) bus; measuring a rise time and a fall time for said bit, or a bit time and a second bit time for said bit; comparing the rise time and the fall time, or the bit time and the second bit time; selectively applying a delay to one or more rising or falling edges of the bit, or to one or more bit times or second bit times of the bit, based at least in part on the comparison; transmitting the bit onto a second segment of the LIN bus on an output pad or connector; A method comprising:

19. 20. The method of claim 18, wherein the bit time corresponds to a value of the bit and the second bit time corresponds to a second value of the bit that is less than the value.

20. The method of claim 18 , wherein the delay is adjustable.

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