Comparator circuit and drive circuit

Abstract

A comparator circuit and a drive circuit with low power consumption are provided. The comparator circuit (30) of the present embodiment includes a comparator element (31) that outputs a match signal indicating whether a value of a first input signal matches a value of a second input signal, a FF circuit (33) having a data input terminal (D) to which a fixed potential is supplied and a clock input terminal (CK) that holds a value of the data input terminal (D) in response to a self-clock signal to the clock input terminal (CK), and a clock generation circuit (32) that generates the self-clock signal based on an output signal from the FF circuit (33) and the match signal (Z).

Description

Technical Field

[0001] This disclosure relates to comparator circuits and driver circuits. Background Technology

[0002] Patent Document 1 discloses a horizontal driving circuit for a liquid crystal display device. In Patent Document 1... Figure 2 In this circuit, the comparator compares the counter output with the pixel values ​​of the digital image data. The comparator outputs a coincidence pulse indicating that the two values ​​are equal to a D-type flip-flop circuit. Furthermore, the positive and negative polarity switches switch in conjunction with the output of the D-type flip-flop.

[0003] Furthermore, the horizontal drive circuit in Patent Document 1 includes a comparator clock / counter clock generation circuit section. The comparator clock / counter clock generation circuit section generates a comparator clock and a counter clock based on an external clock.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent document 1: Japanese Patent Application Publication No. 2013-105166. Summary of the Invention

[0007] In Patent Document 1, the comparator clock is generated based on an external clock signal. Therefore, a large buffer is required for the transmission of the external clock signal, making it difficult to reduce power consumption.

[0008] The present invention was made in view of the above-mentioned problems, and its object is to provide a low-power comparator circuit and a driver circuit.

[0009] The comparator circuit of this embodiment includes: a comparator element that outputs a consistency signal indicating whether the value of a first input signal is consistent with the value of a second input signal; a trigger circuit having a data input terminal and a clock input terminal provided with a fixed potential, and maintaining the value of the data input terminal in response to a self-clock signal to the clock input terminal; and a clock generation circuit that generates the self-clock signal based on the output signal from the trigger circuit and the consistency signal.

[0010] According to the present invention, a comparator circuit and a drive circuit with low power consumption can be provided. Attached Figure Description

[0011] Figure 1 This is a circuit diagram showing the configuration of a driver circuit that uses a comparator circuit.

[0012] Figure 2 It is a timing diagram that represents the operation of a comparator circuit.

[0013] Figure 3 This is a circuit diagram showing a comparison example, including a comparator circuit and a drive circuit.

[0014] Figure 4 This is a diagram showing the configuration of a liquid crystal display device that uses a driving circuit. Detailed Implementation

[0015] Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, this disclosure is not limited to the following embodiments. In addition, the following description and drawings have been appropriately simplified to make the description clearer.

[0016] The comparator circuit of this embodiment and the drive circuit using the comparator circuit will be described below. Figure 1 This is a circuit diagram showing the drive circuit 100, including the comparator circuit 30. Specifically, Figure 1 The driving circuit shown is a horizontal driving circuit for one column of pixels in a liquid crystal display device. Figure 2 This is a timing diagram showing the operation of comparator circuit 30.

[0017] The driving circuit 100 includes a latch circuit 10, a counter 20, and a comparator circuit 30. Here, 10 bits of image data DATA are input to the driving circuit 100. That is, one pixel is represented using 1024 gray levels (=10 bits). Of course, the number of bits in the image data is not particularly limited.

[0018] The latch signal LATCH and image data DATA are input to latch circuit 10. Latch circuit 10 latches 10 bits of image data DATA in response to the latch signal LATCH. Latch circuit 10 outputs the latched image data DATA in parallel to comparator circuit 30. The image data DATA output from latch circuit 10 is set as latch output A. Latch output A is 10 bits of parallel data. Figure 2 In this case, the value of the latched output A is α.

[0019] The counter clock signal CNT_CLOCK and the counter reset signal CNT_RST are input to counter 20. Counter 20 performs counting operations synchronously with the counter clock signal CNT_CLOCK. For example, counter 20 increments the count value at the clock frequency of the counter clock signal CNT_CLOCK. Counter 20 outputs the count value to comparator circuit 30.

[0020] Additionally, counter 20 resets its count value to its initial value in response to the counter reset signal CNT_RST. Furthermore, the counter reset signal CNT_RST corresponds to the horizontal scan frequency. The output of counter 20 is 10 bits. Therefore, counter 20 increments the count value from 0 to 1023. Counter 20 outputs the 10-bit count value to comparator circuit 30. The count value output from counter 20 is set as counter output B. Counter output B is 10 bits of parallel data. Figure 2 As shown, the counter output B increments in the order of α-1, α, α+1.

[0021] The comparator circuit 30 includes a comparator element 31, a clock generation circuit 32, and an FF (flip-flop) circuit 33. The comparator circuit 30 is a self-clocking comparator circuit that generates its own clock signal based on its own output. Therefore, the comparator circuit 30 does not receive an external clock signal as input.

[0022] Comparator element 31 compares the latch output A and the counter output B. Comparator element 31 generates a consistency signal Z indicating that the latch output A and the counter output B are identical. Comparator element 31 outputs the consistency signal Z to the clock generation circuit 32. The latch output A and the counter output B are each 10 bits of parallel data. Comparator element 31 compares each bit of the latch output A and the counter output B. Comparator element 31 determines that the latch output A and the counter output B are identical when all bits of the latch output A and the counter output B are identical.

[0023] When the latch output A matches the counter output B, comparator element 31 asserts the consensus signal Z. When the latch output A differs from the counter output B, comparator element 31 deassers the consensus signal Z. Therefore, the consensus signal Z becomes... Figure 2 The signal shown is a positive pulse signal. When the value of the counter output B is α, the synchronization signal Z becomes high. When the value of the counter output B is not α, the synchronization signal Z becomes low.

[0024] The clock generation circuit 32 generates a self-clock signal based on the consistency signal Z from the comparator circuit 30 and the output signal of the clock generation circuit 32. The clock generation circuit 32 outputs the self-clock signal to the FF circuit 33.

[0025] For example, clock generation circuit 32 includes a NAND (Non-AND) circuit. Specifically, clock generation circuit 32 is connected to the output terminal of comparator element 31 and the inverted output terminal QB of FF circuit 33. Therefore, the coincident signal Z from comparator element 31 and the inverted output signal from FF circuit 33 are input to clock generation circuit 32. Clock generation circuit 32 outputs the NAND (Non-AND) of the coincident signal Z and the inverted output signal. The output signal from clock generation circuit 32 is set as internal signal Z1. Clock generation circuit 32 outputs internal signal Z1 to FF circuit 33.

[0026] The FF circuit 33 is a D-type flip-flop circuit. The FF circuit 33 includes a data input terminal D, a clock input terminal CK, a non-inverting output terminal Q, and an inverting output terminal QB. The output of the clock generation circuit 32 is connected to the clock input terminal CK. An internal signal Z1 is input to the clock input terminal CK. The FF circuit 33 samples and holds the data value at the data input terminal D in response to the internal signal Z1. The FF circuit 33 holds a 1-bit value.

[0027] The in-phase output signal corresponding to the data value held by the FF circuit 33 is output from the non-inverting output terminal Q. The FF circuit 33 outputs an inverted output signal, which is the result of inverting the in-phase output signal, from the inverting output terminal QB. The inverted output signal becomes the output signal OUT from the comparator circuit 30. When the input data held by the FF circuit 33 is 1, the in-phase output signal is high and the inverted output signal is low. When the input data held by the FF circuit 33 is 0, the in-phase output signal is low and the inverted output signal is high.

[0028] A comparator reset signal CMP_RST is input to the FF circuit 33. The FF circuit 33 resets the held data in response to the comparator reset signal CMP_RST. Therefore, the data value held by the FF circuit 33 becomes 0. When the FF circuit 33 is reset by the comparator reset signal CMP_RST, the inverting output signal becomes high, and the non-inverting output signal becomes low.

[0029] A fixed power supply voltage VDD is input as data to the data input terminal D. Therefore, a fixed potential is always supplied to the data input terminal D. The clock input terminal CK is connected to the output of the clock generation circuit 32. Therefore, the internal signal Z1 from the clock generation circuit 32 is input to the clock input terminal CK of the FF circuit 33.

[0030] After being reset by the comparator reset signal CMP_RST, the FF circuit 33 responds to the internal signal Z1 and samples the fixed power supply voltage VDD. The FF circuit 33 detects the edge of the internal signal Z1 and maintains the input data to the data input terminal D. Therefore, at the edge of the internal signal Z1, the non-inverting output signal becomes high and the inverting output signal becomes low.

[0031] Therefore, as Figure 2 As shown, the inverted output signal becomes a negative step signal. The output signal OUT of comparator circuit 30 becomes high before the falling edge of the consensus signal Z, and changes to low at the falling edge of the consensus signal Z. Thus, a negative step signal is output from the inverted output terminal QB of FF circuit 33. The level of output signal OUT changes in response to the falling edge of the consensus signal Z.

[0032] The comparator circuit 30 includes a clock generation circuit 32 that generates a self-clock signal. The clock generation circuit 32 generates an internal signal Z1 as the self-clock signal based on a consistency signal Z and an output signal OUT. That is, the comparator circuit 30 becomes a self-clock comparator that operates according to the self-clock signal generated by itself. The FF circuit 33 responds to the self-clock signal, i.e., the internal signal Z1, to hold the data. Therefore, since a buffer for an external clock is not required, power consumption can be reduced.

[0033] Figure 3 This describes a drive circuit with comparator circuit 30, representing a comparison example. Furthermore, regarding the basic operation of latch circuit 10, counter 20, and comparator element 31, since... Figure 1 The details are the same, so a detailed explanation is omitted. For example, the output of comparator element 31 represents a coincidence signal Z that indicates the agreement between latch output A and counter output B. The coincidence signal Z is a positive pulse.

[0034] exist Figure 3 In the comparator circuit 30 shown, an external comparator clock signal CMP_CLOCK is input to the clock input terminal CK of the FF circuit 33. The comparator circuit 30 is a clock comparator that operates in response to the comparator clock signal CMP_CLOCK.

[0035] The inverted output signal of FF circuit 33 is input to OR circuit 3 via inverter 34. Additionally, the consensus signal Z from comparator element 31 is input to OR circuit 35. The internal signal Z1 output from OR circuit 35 is input to the data input terminal D of FF circuit 33. That is, internal signal Z1 becomes the input data to FF circuit 33. FF circuit 33 is reset by comparator reset signal CMP_RST. After reset, FF circuit 33 responds to comparator clock signal CMP_CLOCK, maintaining the value of the input data.

[0036] Ideally, the FF circuit 33 should respond to the comparator clock signal CMP_CLOCK and sample the input data at the center moment. For example, if the comparator clock signal CMP_CLOCK is jittery, in Figure 3 In the comparator circuit 30 shown, a timing error may occur between the comparator clock signal CMP_CLOCK and the input data.

[0037] In contrast, in the comparator circuit 30 of this embodiment, a fixed potential is always supplied to the data input terminal D. That is, the power supply voltage VDD is supplied to the data input terminal D. Therefore, in Figure 1 In the FF circuit 33, timing errors can be prevented between the internal signal Z1, which serves as the self-clock signal, and the input data. This improves reliability.

[0038] Furthermore, the drive circuit includes multiple Figure 1 The comparator circuit 30 eliminates the need for multiple buffers, thus reducing power consumption. For example, suppose the drive circuit 100 is applied to a WUXGA LCOS (Liquid Crystal On-Silicon) device at a frame rate of 120Hz. In this case, the device's power consumption can be reduced from 1188mW to 1087mW. That is, a power consumption reduction of 8.5% (=101mW) is possible.

[0039] use Figure 4 The configuration of the liquid crystal display device 200, in which the comparator circuit 30 is applied to the drive circuit, will be described. The liquid crystal display device 200 is an LCOS display. Figure 4 This is a block diagram representing the back panel of an LCOS display.

[0040] The liquid crystal display device 200 includes a pixel display unit 50, a vertical driving circuit 2, and a horizontal driving circuit 3. The horizontal driving circuit 3 has... Figure 1 The driving circuit 100 is shown. Specifically, the horizontal driving circuit 3 has m (m is an integer greater than or equal to 2) driving circuits 100 corresponding to the number of pixels in one row.

[0041] The pixel display unit 50 is provided with multiple data lines 6, multiple gate lines 8, and multiple pixels 42. The multiple data lines 6 are arranged in parallel with each other. The multiple gate lines 8 are arranged in parallel with each other. The multiple data lines 6 and the multiple gate lines 8 are arranged in an intersecting manner. The gate lines 8 are row scan lines.

[0042] The liquid crystal display device 200 includes multiple sets of data lines 6, arranged in groups of two. The liquid crystal display device 200 uses one set of data lines 6 to drive the pixels 42 inverting mode. Hereinafter, the data line 6 on the positive side of the set of data lines 6 is designated as data line 6a, and the data line 6 on the negative side is designated as data line 6b. Similarly, the switch 1 and video signal lines 5 are designated as switch 1a, switch 1b, and video signal lines 5a and 5b to identify polarity. For polarity inversion, a dual-system set of data lines 6, switch 1, and video signal lines 5 is provided.

[0043] Pixels 42 are arranged at the intersection of data lines 6 and gate lines 8. Pixels 42 are arranged in a matrix (row-column configuration). Each pixel 42 is driven by one set of data lines 6 and one gate line 8. For example, if there are n gate lines 8 and 2m data lines 6, then the pixels 42 are arranged in an n-row × m-column matrix. Furthermore, m and n are integers greater than or equal to 2. Pixels 42 include pixel driving circuitry for driving the liquid crystal, pixel electrodes, etc.

[0044] The vertical drive circuit 2 selects multiple gate lines 8 for vertical driving during each horizontal scan. The vertical drive circuit 2 provides scan signals to the multiple gate lines 8. That is, the vertical drive circuit 2 provides scan signals to sequentially select gate lines 8 from the first row to the nth row. Thus, pixels 42 are selected sequentially row by row. All gate lines 8 are selected within one vertical scan period. Video signals can then be written to the pixels 42 in the selected row.

[0045] The horizontal drive circuit 3 drives multiple switches 1 in the horizontal direction during horizontal scanning. This provides video signals to multiple data lines 6. As described above, two data lines 6a and 6b are connected to pixels 42 as a group. Therefore, two data lines 6a and 6b are jointly connected to pixels 42 in one row.

[0046] Data line 6a is connected to video signal line 5a via switch 1a. Data line 6b is connected to video signal line 5b via switch 1b. Video signal line 5a is supplied with the positive side video signal RAMP+. Video signal line 5b is supplied with the negative side video signal RAMP-. Horizontal drive circuit 3 controls switches 1a and 1b.

[0047] Therefore, a positive video signal RAMP+ is provided to one data line 6a of a set of data lines 6a and 6b, and a negative video signal RAMP- is provided to the other data line 6b. The positive video signal RAMP+ becomes a positive voltage relative to the common potential of the common electrode line, and the negative video signal RAMP- becomes a negative voltage relative to the common potential of the common electrode line. The horizontal drive circuit 3 can provide the positive video signal RAMP+ and the negative video signal RAMP- to the pixels 42 of the selected row, respectively. The horizontal drive circuit 3 causes each switch 1 to be turned on and off multiple times during the horizontal scan. Therefore, the positive video signal RAMP+ and the negative video signal RAMP- are alternately provided to the pixels 42.

[0048] Specifically, the horizontal drive circuit 3 includes a latch circuit 310, a counter 320, a comparator circuit 330, a shift register 360, and a buffer 370. The latch circuit 310 corresponds to... Figure 1 The latch circuit 10. That is, the latch circuit 310 includes m columns of latch circuits 10. The latch circuit 310 holds the image data DATA of the pixels 42 from the first to the mth columns.

[0049] Comparator circuit 330 corresponds to Figure 1 The comparator circuit 330. That is, the comparator circuit 330 has m columns of comparator circuits 30. (Source: [Original Source Name]) Figure 1 The output signal OUT of the comparator circuit 30 shown controls switch 1. Counter 320 corresponds to... Figure 1 Counter 20. Therefore, counter 320 performs a counting action in response to the counter clock signal CNT_CLOCK.

[0050] Shift register 360 sequentially transfers m columns of image data DATA in response to the horizontal clock HCLOCK. After holding the m columns of image data DATA, shift register 360 outputs it to latch circuit 310. Latch circuit 310 holds the image data DATA of each column in response to the latch signal LATCH.

[0051] like Figure 1 As shown, comparator circuit 330 compares latch output A and counter output B. Comparator circuit 330 controls switches 1a and 1b in pairs. In response to the output signal of comparator circuit 330, switches 1a and 1b open and close in pairs. First, since all pixels of switch 1 are closed, video signals are not provided to pixel 42. When the output signal of comparator circuit 330 is active, the corresponding switch 1 opens. Thus, the positive video signal RAMP+ and the negative video signal RAMP- are alternately applied to pixel 42. Liquid crystal display device 200 is able to perform grayscale display corresponding to image data DATA.

[0052] Buffer 370 buffers various signals output from the external controller. Since the pixel display unit 50 has a large number of columns, buffer 370 is used to drive heavier loads. For example, the horizontal clock signal HCLOCK is input to the shift register 360 via buffer 370. Similarly, the latch signal LATCH is input to the latch circuit 310 via buffer 370. The counter output from counter 320 is input to comparator circuit 330 via buffer 370.

[0053] In this embodiment, the comparator circuit 330 includes Figure 1 The comparator circuit 30 is shown. Therefore, the buffer for the comparator clock signal input to the comparator circuit 330 can be omitted. That is, the number of buffers can be reduced according to the number of columns, thus reducing power consumption. Furthermore, since timing errors can be suppressed, reliability can be improved.

[0054] The invention described above is based on specific embodiments, but the invention is not limited to the above embodiments, and various modifications can be made without departing from its spirit.

[0055] This application claims priority to Japanese Patent Application No. 2021-87341, filed on May 25, 2021, and incorporates all of its disclosures therein.

[0056] Symbol explanation:

[0057] 1 switch

[0058] 2 Vertical drive circuit

[0059] 3 Horizontal drive circuit

[0060] 6 data cables

[0061] 8 gate lines

[0062] 42 pixels

[0063] 50-pixel display

[0064] 100 drive circuit

[0065] 10 latch circuits

[0066] 20 counter

[0067] 30 comparator circuit

[0068] 31 comparator elements

[0069] 32-bit clock generation circuit

[0070] 33FF circuit

[0071] 200 LCD display device

[0072] 310 latch circuit

[0073] 320 counter

[0074] 330 comparator circuit

[0075] 360 shift register

[0076] 370 buffer

Claims

1. A comparator circuit of a drive circuit of a liquid crystal display device, comprising: a comparator element that outputs a coincidence signal indicating whether or not a value of a first input signal coincides with a value of a second input signal, the value of the first input signal being image data held by a latch circuit, the value of the second input signal being a count value of a counter configured to perform a counting operation in accordance with a counter clock signal, and the counter resetting the count value to an initial value in response to a counter reset signal corresponding to a horizontal scanning frequency; a flip-flop circuit including a clock input terminal, a data input terminal to which a fixed potential is supplied, and an inverting output terminal that outputs an inverted output signal, and holding a value of the data input terminal in response to a self-clock signal input to the clock input terminal; a clock generation circuit including an NAND gate circuit that generates the self-clock signal based on the inverted output signal from the flip-flop circuit and the coincidence signal that are input.

2. The comparator circuit according to claim 1, wherein the output of the flip-flop circuit changes at a falling edge of the coincidence signal after a reset signal for resetting the output of the flip-flop circuit is input to the flip-flop circuit.

3. The comparator circuit according to claim 1 or 2, wherein the output signal from the flip-flop circuit is the inverted output signal.

4. A drive circuit of a liquid crystal display device, comprising: the comparator circuit according to any one of claims 1 to 3; a latch circuit that holds image data, and outputs the image data as the first input signal to the comparator element; a counter that performs a counting operation in response to a counter clock signal, and outputs a count value as the second input signal to the comparator element. ​ ​

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