Peripheral circuit, memory device and method for resistor offset calibration - Patents.com

Abstract

According to one aspect of the present disclosure, A synchronous dynamic random access memory (SDRAM) is provided that includes peripheral circuitry, the peripheral circuitry including a DQ circuit that includes a plurality of decision feedback equalization (DFE) components. can The peripheral circuitry is , resistance Resistor Offset Calibration (RXOC) Circuit Including nothing can The RXOC circuit is , an oscillator. The oscillator can generate an internal clock source. The RXOC circuit can include a DQ selection component. The DQ selection component can include: Selecting a DFE component among a plurality of DFE components for calibration can The DQ selection component can output a slicer result signal that indicates the value of the offset received from the DFE component. , and control logic. The control logic may include Transmitting a calibration signal associated with the DFE component to the DQ circuit based on the slicer result signal. can .

Description

[Background technology]

[0001] The present disclosure relates to memory devices and methods of operation thereof.

[0002] An offset calibration training to adjust the DQ resistor offset calibration (RXOC) training may be performed during the power-on and initialization training sequence to account for state changes in the static dynamic random access memory (SDRAM). Summary of the Invention

[0003] According to one aspect of the present disclosure, a peripheral circuit is provided. The peripheral circuit may include a DQ circuit comprising a plurality of decision feedback equalization (DFE) components. The peripheral circuit may include a resistor offset calibration (RXOC) circuit. The RXOC circuit may include an oscillator. The oscillator may be configured to generate an internal clock source. The RXOC circuit may include a DQ selection component. The DQ selection component may be configured to select a DFE component from the plurality of DFE components for calibration. The DQ selection component may be configured to output a slicer result signal indicative of a value of an offset received from the DFE component. The RXOC circuit may include control logic. The control logic may be configured to send a calibration signal associated with the DFE component to the DQ circuit based on the slicer result signal.

[0004] In some embodiments, the DQ selection component may include a first multiplexer (MUX) and a second MUX. In some embodiments, the first MUX is configured to select a DQ circuit. In some embodiments, the second MUX is configured to select a DFE component of the DQ circuit.

[0005] In some implementations, the control logic may be further configured to receive the slicer result signal at a first edge of a clock cycle associated with the internal clock source.

[0006] In some implementations, the control logic may be further configured to perform a binary search based on the slicer result signal to identify a pull-up code or a pull-down code for the DFE component.

[0007] In some embodiments, the control logic may be further configured to send a calibration signal to the DQ circuit on a second edge of a clock cycle associated with the internal clock source. In some embodiments, the first edge may be one of a rising edge or a falling edge. In some embodiments, the second edge may be the other of a rising edge or a falling edge. In some embodiments, the calibration signal may include a pull-up code or a pull-down code.

[0008] In some implementations, the DQ circuitry may be further configured to calibrate the DFE component based on a pull-up code or a pull-down code included in a calibration signal received from the control logic on the second edge of the clock cycle.

[0009] In some implementations, the oscillator may be further configured to receive an RXOC engage signal. In some implementations, the internal clock source may be generated in response to receiving an RXOC engage command.

[0010] In some implementations, the oscillator can be made to generate an internal clock source without a column address strobe (CAS) command.

[0011] According to another aspect of the present disclosure, a memory device is provided. The memory device may include a memory array and peripheral circuitry coupled to the memory array. The peripheral circuitry may include a DQ circuit having a plurality of DFE components. The peripheral circuitry may include an RXOC circuit. The RXOC circuit may include an oscillator. The oscillator may be configured to generate an internal clock source. The RXOC circuit may include a DQ selection component. The DQ selection component may be configured to select a DFE component from the plurality of DFE components for calibration. The DQ selection component may be configured to output a slicer result signal indicative of a value of an offset received from the DFE component. The RXOC circuit may include control logic. The control logic may be configured to send a calibration signal associated with the DFE component to the DQ circuit based on the slicer result signal.

[0012] In some implementations, the DQ selection component may include a first MUX and a second MUX. In some implementations, the first MUX is configured to select a DQ circuit. In some implementations, the second MUX is configured to select a DFE component of the DQ circuit.

[0013] In some implementations, the control logic may be further configured to receive the slicer result signal at a first edge of a clock cycle associated with the internal clock source.

[0014] In some implementations, the control logic may be further configured to perform a binary search based on the slicer result signal to identify a pull-up code or a pull-down code for the DFE component.

[0015] In some embodiments, the control logic may be further configured to send a calibration signal to the DQ circuit on a second edge of a clock cycle associated with the internal clock source. In some embodiments, the first edge may be one of a rising edge or a falling edge. In some embodiments, the second edge may be the other of a rising edge or a falling edge. In some embodiments, the calibration signal may include a pull-up code or a pull-down code.

[0016] In some implementations, the DQ circuitry may be further configured to calibrate the DFE component based on a pull-up code or a pull-down code included in a calibration signal received from the control logic on the second edge of the clock cycle.

[0017] In some implementations, the oscillator may be further configured to receive an RXOC engage signal. In some implementations, the internal clock source may be generated in response to receiving an RXOC engage command.

[0018] In some embodiments, the oscillator can be made to generate an internal clock source without a CAS command.

[0019] According to a further aspect of the present disclosure, a method for RXOC by a peripheral circuit is provided. The method may include generating an internal clock source by an oscillator of the RXOC circuit. The method may include selecting, by a DQ selection component of the RXOC circuit, a DFE component from multiple DFE components of the DQ circuit for calibration. The method may include outputting, by the DQ selection component of the RXOC circuit, a slicer result signal indicative of a value of an offset received from the DFE component. The method may include transmitting, by control logic of the RXOC circuit, a calibration signal associated with the DFE component to the DQ circuit based on the slicer result signal.

[0020] In some implementations, the DQ selection component may include a first MUX and a second MUX. In some implementations, the first MUX may be configured to select a DQ circuit. In some implementations, the second MUX may be configured to select a DFE component of the DQ circuit.

[0021] In some implementations, the method may include receiving, by control logic of the RXOC circuitry, the slicer result signal at a first edge of a clock cycle associated with the internal clock source.

[0022] In some implementations, the method may include performing, by control logic of the RXOC circuit, a binary search based on the slicer result signal to identify a pull-up code or a pull-down code for the DFE component.

[0023] In some embodiments, the method may include transmitting, by control logic of the RXOC circuit, a calibration signal to the DQ circuit on a second edge of a clock cycle associated with the internal clock source. In some embodiments, the first edge may be one of a rising edge or a falling edge. In some embodiments, the second edge may be the other of a rising edge or a falling edge. In some embodiments, the calibration signal may include a pull-up code or a pull-down code.

[0024] In some embodiments, the method may include calibrating the DFE component based on a pull-up code or a pull-down code included in a calibration signal received by a DQ circuit of the RXOC circuit from the control logic at a second edge of the clock cycle.

[0025] In some embodiments, the method may include receiving, by an oscillator of the RXOC circuit, an RXOC engage signal. In some embodiments, an internal clock source may be generated in response to receiving the RXOC engage command.

[0026] In some embodiments, the oscillator can be made to generate an internal clock source without a CAS command.

[0027] According to yet another aspect of the present disclosure, a memory system is provided. The memory system may include a memory array and peripheral circuitry. The peripheral circuitry may include a DQ circuit having a plurality of DFE components. The peripheral circuitry may include an RXOC circuit. The RXOC circuit may include an oscillator. The oscillator may be configured to generate an internal clock source. The RXOC circuit may include a DQ selection component. The DQ selection component may be configured to select a DFE component from the plurality of DFE components for calibration. The DQ selection component may be configured to identify a value of an offset associated with the DFE component. The DQ selection component may be configured to output a slicer result signal received from the DFE component based on the value of the offset. The RXOC circuit may include control logic. The control logic may be configured to send a calibration signal associated with the DFE component to the DQ circuit based on the slicer result signal.

[0028] In some implementations, the DQ selection component may include a first MUX and a second MUX. In some implementations, the first MUX is configured to select a DQ circuit. In some implementations, the second MUX is configured to select a DFE component of the DQ circuit.

[0029] In some implementations, the control logic may be further configured to receive the slicer result signal at a first edge of a clock cycle associated with the internal clock source.

[0030] In some implementations, the control logic may be further configured to perform a binary search based on the slicer result signal to identify a pull-up code or a pull-down code for the DFE component.

[0031] In some embodiments, the control logic may be further configured to send a calibration signal to the DQ circuit on a second edge of a clock cycle associated with the internal clock source. In some embodiments, the first edge may be one of a rising edge or a falling edge. In some embodiments, the second edge may be the other of a rising edge or a falling edge. In some embodiments, the calibration signal may include a pull-up code or a pull-down code.

[0032] In some implementations, the DQ circuitry may be further configured to calibrate the DFE component based on a pull-up code or a pull-down code included in a calibration signal received from the control logic on the second edge of the clock cycle.

[0033] In some implementations, the oscillator may be further configured to receive an RXOC engage signal. In some implementations, the internal clock source may be generated in response to receiving an RXOC engage command.

[0034] In some embodiments, the oscillator can be made to generate an internal clock source without a CAS command. [Brief explanation of the drawings]

[0035] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable those skilled in the art to make and use the present disclosure. [Figure 1] 1 illustrates a schematic circuit diagram of a memory device including peripheral circuitry and an array of memory cells according to some aspects of the present disclosure. [Figure 2] 1 illustrates a block diagram of a memory system including a memory array coupled to an exemplary resistor offset calibration (RXOC) component and control logic in accordance with some aspects of the present disclosure. [Figure 3] 1 shows a signal timing diagram of a typical RXOC procedure. [Figure 4] 1 illustrates a detailed block diagram of an exemplary peripheral circuit including an RXOC circuit and multiple DQ circuits, in accordance with some aspects of the present disclosure. [Figure 5] 1 illustrates a block diagram of an exemplary DQ circuit according to some embodiments of the present disclosure. [Figure 6] 6 illustrates a diagram of a DFE component of the exemplary DQ circuit shown in FIG. 5 in accordance with some embodiments of the present disclosure. [Figure 7] 1 illustrates a first exemplary signal timing diagram for a typical RXOC procedure, in accordance with certain aspects of the present disclosure. [Figure 8] 1 illustrates a flowchart of a first method of RXOC procedure according to some aspects of the present disclosure. [Figure 9] 10 illustrates a second exemplary signal timing diagram for an exemplary RXOC procedure, in accordance with certain aspects of the present disclosure. [Figure 10] 10 shows a flowchart of a second method of RXOC procedure according to some aspects of the present disclosure. [Figure 11] 1 illustrates a block diagram of a system including a memory system in accordance with some aspects of the present disclosure.

[0036] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION OF THE INVENTION

[0037] In general, terms may be understood, at least in part, from their use in context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular sense, or may be used to describe a combination of features, structures, or characteristics in the plural sense, depending at least in part on the context. Similarly, terms such as "a," "an," or "the" may also be understood to convey singular usage or plural usage, depending at least in part on the context. Furthermore, the term "based on" is not intended to convey a necessarily exclusive set of factors, but rather may also be understood to allow for the presence of additional factors not necessarily explicitly described, depending at least in part on the context.

[0038] 1 shows a schematic diagram of a memory device 100 including peripheral circuitry 102 and a memory cell array 101 according to some aspects of the disclosure. In some implementations shown in FIG. 1, each memory cell 103 may include a transistor 105 and a capacitor 107. A gate of transistor 105 may be coupled to a word line 104, one of a source and a drain of transistor 105 may be coupled to a bit line 106, the other of the source and drain of transistor 105 may be coupled to one electrode of capacitor 107, and the other electrode of capacitor 107 may be coupled to ground. Further details of the memory device are presented below in connection with FIG. 11.

[0039] 2, a schematic circuit diagram of an exemplary memory device 200 including peripheral circuits is shown, in accordance with some embodiments of the present disclosure. As described above, the peripheral circuits may be coupled to at least two memory cell arrays and may include any suitable circuitry for facilitating operation of the at least two memory cell arrays by applying and sensing voltage and / or current signals to each target memory cell of the at least two memory cell arrays. The peripheral circuits may include various types of peripheral circuits formed using CMOS technology, such as, for example, RXOC circuits.

[0040] 2 shows a memory device 200 including a memory cell array 201 having one or more memory banks and various typical peripheral circuits including control logic 202, a command (CMD) decoder 204, an RXOC control logic 206, a register 208, an RXOC circuit 210, an address (ADD) register 212, a WL driver 214 (also called a row decoder), memory bank control logic 216, a BL driver 218 (also called a row decoder), a column decoder 220, a data I / O buffer 222, a DQ circuit 224, and an interface 226. It will be understood that in some examples, additional peripheral circuits may also be included.

[0041] The WL driver 214 is controlled by the control logic 202 and can be configured to select a bank of the memory cell array 201 and a word line of the selected bank. The WL driver 214 can be further configured to drive the memory cell array 201. For example, the WL driver 214 can drive NAND memory cells and / or DFM cells of the memory cell array 201 coupled to the selected word line using a word line voltage generated from a voltage generator (not shown).

[0042] The BL driver 218 is controlled by the control logic 202 and can be configured to select one or more 3D NAND memory strings and / or one or more 3D DFM cells of the memory cell array 201 by applying a bit line voltage generated from a voltage generator (not shown). For example, the BL driver 218 can apply a column signal to select a set of N bits of data from a page buffer (not shown) to be output in a read operation.

[0043] The control logic 202 may be coupled to each of the plurality of peripheral circuits and may be configured to control the operation of the plurality of peripheral circuits. The registers 208 may be coupled to the control logic 202 and may include status registers, command registers, and address registers for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit.

[0044] The command decoder 204 can decode the incoming command signal to identify the corresponding command operation. An indication of the command operation can be sent to a register 208, which can identify an associated OP code and / or command address. The OP code and / or command address can be identified by comparing the identified command operation to a lookup table of OP codes and / or command addresses.

[0045] Interface 226 can be coupled to control logic 202 and can be configured to interface memory cell array 201 with one or more memory controllers (not shown). In some implementations, interface 226 functions as a control buffer to buffer and relay control commands received from one or more memory controllers and / or a host (not shown) to control logic 202 and to relay status information received from control logic 202 to the memory controllers and / or the host. Interface 226 can also be coupled to a page buffer (not shown) and BL driver 218 via a data bus (not shown) and can function as an I / O interface and data buffer to buffer and relay program data received from one or more memory controllers and / or a host to the page buffer and to relay read data from the page buffer to one or more memory controllers and / or a host. In some implementations, interface 226 and the data bus (not shown) are part of the I / O circuitry of the peripheral circuitry.

[0046] A voltage generator (not shown) can be controlled by control logic 202 and configured to generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, and verify voltages) and bit line voltages supplied to memory cell array 201. In some implementations, the voltage generator is part of a voltage source that supplies voltages at various levels to different peripheral circuits, as described in more detail below. Consistent with the scope of the present disclosure, in some implementations, the voltages supplied by the voltage generator, for example, to WL driver 214 and BL driver 218, are above a particular level sufficient to perform memory operations. For example, the voltage supplied to the logic circuitry of control logic 202 can be between 1.3V and 5V, such as 3.3V, and the voltage supplied to the drive circuitry of WL driver 214, BL driver 218 can be between 5V and 30V.

[0047] The RXOC circuit 210 can be coupled to the control logic 202 and can include an oscillator (see FIG. 4), a DQ selection component (see FIG. 4), and the RXOC control logic 206. In some implementations, the RXOC control logic 206 can be part of the control logic 202. In some other implementations, the RXOC control logic 206 can be separate from the control logic 202. The oscillator can be configured to generate an internal clock source for, for example, the RXOC control logic 206, the DQ selection component (see FIG. 4), and the DQ circuit 224 (see FIG. 5), to name a few. By setting the internal clock source for the RXOC control logic 206, the DQ selection component, and the DQ circuit 224, synchronous calibration of the peripheral circuits can be achieved.

[0048] RXOC training involves calculating the resistance of the DQ circuit, e.g., determining how many transistors are open or closed. For example, a clock source is used to time the operations performed by the RXOC control logic and DQ selection components. Conventional RXOCs use the full-rate write clock (WCK) as the clock source. To perform RXOC using the full-rate write clock, an additional column address strobe (CAS) command (CMD) is required before training can begin. Alternatively, a WCK-to-clock (WCK2CK) synchronization state from a previous operation is required. However, various challenges arise when designing RXOC circuits due to the undesirably large frequency range of the WCK (e.g., 3200 MHz to 20 MHz). These shortcomings of existing RXOC procedures are illustrated in the signal timing diagram 300 of FIG. 3.

[0049] Referring to Figure 3, a CAS command is issued at time T0, and WCK2CK synchronization is performed between times T0 and Tc1 while the WCK is toggled at full rate. Then, an offset Cal_Start command is issued at time Tc1. This initiates RXOC training, which runs from time Tc2 to Td1. After time Td1, an existing offset calibration signal is sent. The RXOC procedure is completed after tOSCAL, e.g., 3 μs. The device then terminates the RXOC procedure. As mentioned above, the existing RXOC procedure requires additional circuitry for WCKs with different frequencies. For example, if the WCK frequency is high, underclocking is required. On the other hand, if the WCK frequency is low, each DQ uses a separate RXOC circuit to meet timing requirements and / or reduce calibration accuracy.

[0050] To address one or more of the aforementioned problems, the present disclosure provides an exemplary fully synchronized RXOC training strategy. For example, an exemplary internal clock source is provided in the RXOC circuit to synchronize the timing of the DFE selection component and the RXOC control logic. In other words, the exemplary RXOC circuit described herein includes an oscillator (e.g., an internal clock source), RXOC control logic, and a DFE selection component (e.g., one or more multiplexers (MUX)). The DFE selection component selects a DFE component from multiple DFE components (e.g., DQ circuits) in the RXOC circuit. Then, the DFE selection component selects a slicer offset result from multiple slicer offset results of the selected DFE component. The RXOC control logic performs a binary search for RXOC calibration. Including a local oscillator in the RXOC circuit eliminates the need to use a CAS command and / or synchronization state from previous operations. Furthermore, the use of a local oscillator to synchronize the operation of the DFE selection components and the RXOC control logic reduces the silicon footprint of the RXOC circuit and improves calibration stability while simplifying the operation of the RXOC control logic. Further details of a typical RXOC circuit are presented below in connection with Figures 4-11.

[0051] FIG. 4 illustrates a detailed block diagram 400 of an exemplary peripheral circuit including an RXOC circuit and multiple DQ circuits according to some embodiments of the present disclosure. FIG. 5 illustrates a block diagram 500 of an exemplary DQ circuit 502 according to some embodiments of the present disclosure. FIG. 6 illustrates a diagram 600 of a DFE component 504 of the exemplary DQ circuit 502 shown in FIG. 5 according to some embodiments of the present disclosure. FIG. 7 illustrates a first exemplary signal timing diagram 700 for an exemplary RXOC procedure for calibrating a DQ circuit according to some embodiments of the present disclosure. FIG. 8 illustrates a flowchart of a first method 800 of an RXOC procedure according to some embodiments of the present disclosure. FIG. 9 illustrates a second exemplary signal timing diagram 900 for an exemplary RXOC procedure according to some embodiments of the present disclosure. FIGS. 4, 5, and 8 are described together.

[0052] 4, the RXOC circuit may include, for example, an RXOC oscillator 404 (hereinafter referred to as “oscillator 404”) and RXOC control logic 408. Multiple DQ circuits may be included in the DFE block 406. By way of example and not limitation, the DFE block 406 (e.g., the DQ circuit 224 of FIG. 2 may correspond to the DFE block 406 of FIG. 4) is shown with four DQ circuits (e.g., DQ0, DQ1, DQ2, DQ3) and one RDQS circuit. However, the DFE block 406 may include more or less than four DQ circuits and more or less than one RDQS circuit without departing from the scope of this disclosure. The DFE selection component 410 may include a first MUX (e.g., the left-most MUX) configured to select a DQ circuit of the DFE block 406 for calibration. Further, the DFE selection component 410 may include a second MUX (e.g., the rightmost MUX) configured to select the DFE of the DQ circuit selected by the first MUX for calibration. In FIG. 4, the DQ signal input to the DFE block 406 may be I / O data via a DQ pin of a memory device. For example, the DQ signal may be transmitted from a memory controller to a memory device via an I / O buffer. During RXOC calibration, the DQ signal and Vref DQ ports shown on the left side of FIG. 4 may be shorted.

[0053] 4 and 8, RXOC operation may begin when an RXOC engage (RXOX_en) signal is received (802). When the RXOC_en signal is received, oscillator 404 may generate an internal clock source (osc_ck) having a predetermined frequency (804), which is sent to DFE block 406 and RXOC control logic 408 to synchronize their respective operations. In the following example, the RXOC procedure is performed in the order DQ0, DQ1, DQ2, DQ3, and RDQS, and each of these DQ circuits includes four DFE components.

[0054] 4, 5, and 8, the RXOC control logic 408 may perform an RXOC procedure (806) to calibrate a first DFE component 504a of the DQ circuit 502 (e.g., DQ0). Further details of the DQ circuit 502 are shown in FIG. 5, while further details of the first DFE component 504a (which may be of the same or similar structure as the other DFE components) are shown in FIG.

[0055] 4 and 5, to perform an RXOC procedure, a first MUX can select DQ0, and a second MUX can select the first DFE component 504a of DQ0 for calibration. In some implementations, the RXOC control logic 408 can send a DQ select (dq_sel) signal to the first MUX and a slicer select (slicer_sel) signal to the second MUX. The dq_sel signal can indicate which DQ circuit (e.g., DQ0, DQ1, DQ2, DQ3, RDQS, etc.) of the DFE block 406 is selected for calibration. The slicer_sel signal can indicate which DFE component (e.g., the first DFE component 504a, the second DFE component 504b, the third DFE component 504c, or the fourth DFE component 504d) of the selected DQ circuit is selected for calibration. Each DFE component can identify a slicer result signal to be sent to the first MUX. The first MUX can output the slicer result signal from the DFE component of the selected DQ circuit. In this example, the first MUX can output the slicer result signal from the DFE component of DQ0. The second MUX can output a slicer result signal indicating the value of an offset (e.g., a resistance offset value, a voltage offset value, a current offset value, etc.) associated with the selected DFE component of DQ0. The RXOC control logic 408 can receive the slicer result signal on the rising edge or the falling edge of the first clock cycle.

[0056] The RXOC control logic 408 can perform a binary search based on the slicer result (e.g., the offset value) to identify a pull-up code or a pull-down code for a selected DFE component. The pull-up code or the pull-down code can be used to calibrate the selected DFE component, e.g., the number of open or closed MOSFETs (see FIG. 6). For example, referring to FIG. 6, the pull-up code or the pull-down code can be used to minimize the current difference between the left dashed box and the right dashed box by calibrating the selected DFE component. To perform the binary search, the RXOC control logic 408 can identify a target code, e.g., 0101. Using a non-limiting exemplary target code of 0101, the RXOC control logic can determine a minus by comparing 0101 with 1000. The RXOC control logic 408 can then determine a plus by comparing 0101 with 0100. The RXOC control logic 408 can then determine a minus by comparing 0101 with 0110. Finally, the RXOC control logic can determine that the binary search is complete by comparing 0101 with 0101. Further details of the binary search performed by the RXOC control logic 408 are described below in connection with FIGS.

[0057] For example, referring to FIGS. 4 and 9, the RXOC control logic 408 sets all RXOC codes to 0. Then, the RXOC control logic 408 sets all pull-up codes and sets the pull-down codes to 0. Based on the slicer result signal received from the DQ selection component, the RXOC control logic 408 can determine how to change the pull-up codes. Then, at the rising edge of the clock cycle, the RXOC control logic 408 can set the pull-up codes to 1000. At the falling edge of the clock cycle, the RXOC control logic can perform the slicer operation. The RXOC control logic 408 can then perform a code decision to determine whether to leave the code at 1 or set it to 0. This can be performed for each bit of the code (e.g., 2 bits, 3 bits, 4 bits, etc.). This loop is performed until all four bits have been determined for the slicer result signal. The calibration code (e.g., pull-up code or pull-down code) can then be sent to the selected DFE component / DQ circuit. Further details of the calibration procedure are described below in connection with FIG.

[0058] Referring to FIG. 7, five clock pulses generated by the oscillator 404 are associated with the calibration of one DFE component. The first clock pulse may be used to indicate whether the transistor in the left dashed box or the right dashed box shown in FIG. 6 is being calibrated. Thereafter, each subsequent clock pulse may be associated with the calibration of one bit of the pull-up or pull-down code. For example, referring to FIGS. 4, 6, and 7, at the first clock pulse, the RXOC control logic 408 may indicate whether the transistor in the left dashed box or the right dashed box shown in FIG. 6 is being calibrated. At the second clock pulse, the RXOC control logic 408 may calibrate the first bit of the pull-up or pull-down code (e.g., corresponding to the dashed box shown in the first pulse). At the third clock pulse, the RXOC control logic 408 may calibrate the second bit of the pull-up or pull-down code. At the fourth clock pulse, the RXOC control logic 408 may calibrate the third bit of the pull-up or pull-down code. Finally, at the fifth clock pulse, the RXOC control logic 408 may calibrate the fourth bit of the pull-up or pull-down code.

[0059] 4, the RXOC control logic 408 can generate a calibration signal including a pull-up or pull-down code to DQ0. The calibration signal can be sent to DQ0 on the other of the rising edge or falling edge of the first clock cycle. For example, if the slicer result signal is received on the rising edge of the first clock cycle, the calibration signal can be sent on the falling edge of the first clock cycle. Alternatively, if the slicer result signal is received on the falling edge of the first clock cycle, the calibration signal can be sent on the rising edge of the first clock cycle. Each DFE component can calibrate multiple bits, for example, four bits, and can use each pulse of the clock cycle to calibrate one bit.

[0060] 4, 5, and 8, the RXOC control logic 408 may determine (808) whether the fourth DFE component 504d for DQ0 was calibrated in a previous operation (e.g., 806). If no at 808, the operation may return to 806, and the RXOC control logic 408 may perform the above-described procedure for calibrating, for example, the second DFE component 504b for DQ0. Otherwise, if yes at 808, the operation may proceed to 810, and the RXOC control logic 408 may perform (810) the RXOC procedure for DQ1. That is, operation 810 may include calibrating each of the four DFE components for DQ1. Once DQ1 is calibrated, the RXOC control logic 408 may determine (812) whether all five DQ circuits (e.g., DQ0, DQ1, DQ2, DQ3, and RDQS) have been calibrated. If 812 is "no," operation may return to 806, and the above-described RXOC procedure may be performed for the next DQ circuit and / or the next DFE component of the same or a different DQ circuit. Otherwise, if 812 is "yes," the RXOC procedure of DFE block 406 may end (814). Further details of the operation of FIG. 8 are presented below in connection with FIGS. 4, 5, and 9.

[0061] 4, 5, and 9, in a non-limiting example, the DQ circuit can include five DQs, and each DQ can include four slicers (e.g., DFE components). As described above, the timing diagrams shown in FIGS. 5 and 9 are associated with a 4-bit calibration of the pull-up or pull-down code. Referring to FIG. 9, at the rising edge of the stm_ck cycle (e.g., generated by the oscillator 404), the RXOC control logic 406 outputs a calibration code according to the slicer_result of the 4-bit calibration. In the DFE loop, there are five clock pulses (e.g., the dotted lines in FIG. 9 represent the positions of the rising edges), and the first clock pulse selects os, e.g., the left dashed box or the right dashed box in FIG. 6. At the first rising edge of the first clock pulse, os_sel_out outputs a high-level signal (set to 1). Continuing to refer to FIG. 9, rxoc_out[0]-rxoc_out[3] represent the calibration results output by performing the above-described binary search according to slicer_result for each bit. In the non-limiting example shown in FIG. 9, rxoc_out[3] rises to a high level (set to 1) at the rising edge of the first clock pulse and remains high (keeps 1) at the rising edge of the second clock pulse. rxoc_out[2] rises to a high level (set to 1) at the rising edge of the second clock pulse and falls to a low level (set to 0) at the rising edge of the third clock pulse. rxoc_out[1] rises to a high level (set to 1) at the rising edge of the third clock pulse and remains high (keeps 1) at the rising edge of the fourth clock pulse. rxoc_out[0] rises to a high level (set to 1) at the rising edge of the fourth clock pulse and falls to a low level (set to 0) at the rising edge of the fifth clock pulse. It is understood that the exemplary target code 0101 and calibrated target code 1010 are presented herein by way of example and not limitation, and other target codes and calibrated target codes may be used and / or achieved without departing from the scope of the present disclosure.

[0062] FIG. 10 shows a flowchart of a method 1000 for operating a memory device including peripheral circuitry in accordance with some aspects of the present disclosure. The memory device may be any suitable memory device disclosed herein, such as memory device 100. Method 1000 may be performed by peripheral circuitry including an RXOC circuit and a DQ circuit. The internal circuitry of the peripheral circuitry may include, for example, one or more of oscillator 404, DFE block 406, one or more of the DQ circuits of DFE block 406, one or more DFE components of the DQ circuitry, RXOC control logic 408, and / or DQ selection component 410. It is understood that the operations shown in method 1000 may not be comprehensive, and that other operations may be performed before, after, or between any of the illustrated operations. Furthermore, some of the operations may be performed simultaneously or in a different order than that shown in FIG. 10.

[0063] 10, an oscillator of the RXOC circuit may generate an internal clock source at 1002. For example, referring to FIG. 4, when an RXOC_en signal is received from outside the RXOC circuit, the oscillator 404 may generate an internal clock source (osc_ck) having a predetermined frequency (804), which is sent to the DFE block 406 and the RXOC control logic 408 to synchronize their respective operations.

[0064] At 1004, a DQ selection component of the RXOC circuit can select a DFE component from multiple DFE components of the DQ circuit for calibration. Referring to FIG. 4, to perform an RXOC procedure, a first MUX can select DQ0 and a second MUX can select the first DFE component 504a of DQ0 for calibration. In some implementations, the RXOC control logic 408 can send a DQ select (dq_sel) signal to the first MUX and a slicer select (slicer_sel) signal to the second MUX.

[0065] At 1006, the DQ selection component of the RXOC circuit may output a slicer result signal indicating the value of the offset received from the DFE component. For example, referring to FIG. 4, in the above example, the first MUX may output a slicer result signal from the DFE component for DQ0. The second MUX may output a slicer result signal indicating the value of the offset (e.g., a resistance offset value, a voltage offset value, a current offset value, etc.) associated with the selected DFE component for DQ0.

[0066] At 1008, the control logic of the RXOC circuit may perform a binary search based on the slicer result signal to identify a pull-up or pull-down code for the DFE component. For example, referring to FIG. 4, the RXOC control logic 408 may perform a binary search based on the slicer result signal to identify a pull-up or pull-down code for the selected DFE component. To perform the binary search, the RXOC control logic 408 may identify a target code, for example, 0101. Using a non-limiting exemplary target code of 0101, the RXOC control logic may determine a minus by comparing 0101 with 1000. The RXOC control logic 408 may then determine a plus by comparing 0101 with 0100. Next, the RXOC control logic 408 may determine a minus by comparing 0101 with 0110. Finally, the RXOC control logic may determine that the binary search is complete by comparing 0101 with 0101.

[0067] At 1010, the control logic of the RXOC circuit can send a calibration signal associated with the pull-up code or the pull-down code to the DQ circuit. For example, referring to FIG. 4, the RXOC control logic 408 can generate a calibration signal including a pull-up code or a pull-down code to DQ0. The calibration signal can be sent to DQ0 on the other of the rising edge or the falling edge of the first clock cycle. For example, if the slicer result signal is received on the rising edge of the first clock cycle, the calibration signal can be sent on the falling edge of the first clock cycle. Alternatively, if the slicer result signal is received on the falling edge of the first clock cycle, the calibration signal can be sent on the rising edge of the first clock cycle.

[0068] At 1012, the DQ circuit can calibrate the DFE component based on the pull-up or pull-down code included in the calibration signal. For example, referring to FIG. 4, DQ0 can calibrate the first DFE component 504a based on the pull-up or pull-down code included in the calibration signal. For example, the pull-up or pull-down code can be used to calibrate a selected DFE component (e.g., the first DFE component 504a), i.e., the number of MOSFETs that are open or closed (see FIG. 6), etc. For example, referring to FIG. 6, the pull-up or pull-down code can be used to minimize the current difference between the dashed box on the left and the dashed box on the right by calibrating the selected DFE component. For example, referring to FIGS. 4 and 9, the RXOC control logic 408 sets all RXOC codes to 0. Then, the RXOC control logic 408 sets all pull-up codes and sets the pull-down codes to 0. Based on the slicer result signal received from the DQ selection component, the RXOC control logic 408 can determine how to change the pull-up code. Then, on the rising edge of the clock cycle, the RXOC control logic 408 can set the pull-up code to 1000. On the falling edge of the clock cycle, the RXOC control logic can perform the slicer operation. The RXOC control logic 408 can then perform a code decision to determine whether to leave the code at 1 or set it to 0. This can be performed for each of the bits of the code (e.g., 2 bits, 3 bits, 4 bits, etc.). This loop is performed until all four bits have been determined for the slicer result signal. A calibration code (e.g., a pull-up code or a pull-down code) can then be sent to the selected DFE component / DQ circuit. Further details of the calibration procedure are described below in connection with FIG. 7. Referring to FIG. 7, five pulses generated by the oscillator 404 are associated with the calibration of one DFE component.A first pulse may be used to indicate whether the transistor in the left dashed box or the right dashed box shown in FIG. 6 is being calibrated. Thereafter, each subsequent pulse may be associated with calibrating one bit of the pull-up or pull-down code. For example, with reference to FIGS. 4, 6, and 7, in the first pulse, the RXOC control logic 408 may indicate whether the transistor in the left dashed box or the right dashed box in FIG. 6 is being calibrated. In the second pulse, the RXOC control logic 408 may calibrate the first bit of the pull-up or pull-down code (e.g., corresponding to the dashed box shown in the first pulse). In the third pulse, the RXOC control logic 408 may calibrate the second bit of the pull-up or pull-down code. In the fourth pulse, the RXOC control logic 408 may calibrate the third bit of the pull-up or pull-down code. Finally, in the fifth pulse, the RXOC control logic 408 may calibrate the fourth bit of the pull-up or pull-down code.

[0069] FIG. 11 illustrates a block diagram of a system 1100 including a memory system 1102 according to some aspects of the present disclosure. The system 1100 may be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. As shown in FIG. 11 , the system 1100 may include a host 1108 and a memory system 1102 having one or more memory devices 1104 and a memory controller 1106. The host 1108 may be a processor of the electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 1108 may be configured to send and receive data (also known as user data or host data) to and from the memory system 1102. The memory system 1102 may be a storage product that integrates a memory controller 1106 and one or more memory devices 1104, including volatile memory devices such as dynamic random access memory (DRAM) or synchronous dynamic random access memory (SDRAM), to name a few.

[0070] The memory device 1104 can communicate with the memory controller 1106 via the system bus 1101. Data, commands / addresses (CMD / ADD), and a clock signal CLK can be transmitted and received between the memory device 1104 and the memory controller 1106 via the system bus 1101. As described above, the memory controller 1106 can send an RXOC_en signal to the RXOC circuit to initiate an operation in the RXOC circuit used for RXOC calibration.

[0071] According to some embodiments, the memory controller 1106 is coupled to the memory device 1104 and the host 1108 and configured to control the memory device 1104. The memory controller 1206 can manage data stored in the memory device 1104 and communicate with the host 1108. In some embodiments, the memory controller 1106 is designed to operate in high-duty-cycle environments involving solid-state disks (SSDs) or embedded multimedia cards (eMMCs) used as data storage in mobile devices such as smartphones, tablets, and laptop computers, and in enterprise storage arrays. The memory controller 1106 can be configured to control operations of the memory device 1104, such as read, program / write, and / or erase operations. The memory controller 1106 can also be configured to manage various functions related to data stored or to be stored in the memory device 1104, including, but not limited to, bad block management, garbage collection, logical-to-physical (L2P) address translation, wear leveling, etc. In some implementations, memory controller 1106 is further configured to process error correcting codes (ECC) on data read from or written to memory device 1104. Any other suitable functions, such as formatting memory device 1104, may also be performed by memory controller 1106. Memory controller 1106 may communicate with an external device (e.g., host 1108) according to a particular communication protocol.For example, the memory controller 1106 may communicate with external devices via at least one of a variety of interface protocols, such as a Non-Volatile Memory Express (NVMe) protocol, an NVMe over Fabric (NVMe-oF) protocol, a PCI Express (PCI-E) protocol, a Universal Serial Bus (USB) protocol, a Multimedia Card (MMC) protocol, a Peripheral Component Interconnect (PCI) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial-ATA protocol, a Parallel-ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and the like.

[0072] In various aspects of the present disclosure, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored as instructions on a non-transitory computer-readable medium. Computer-readable media include computer storage media. The storage medium may be any available medium that can be accessed by a memory controller, such as memory controller 1106 of FIG. 11. By way of example and not limitation, such computer-readable media may include RAM, ROM, Electrically Erasable Programmable ROM (EEPROM), compact disc read-only memory (CD-ROM) or other optical disk storage, hard disk drives (HDDs) such as magnetic disk storage or other magnetic storage devices, flash drives, SSDs, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a processing system, such as a mobile device or computer. As used herein, disk and disc include CDs, laser discs, optical discs, digital video discs (DVDs), and floppy disks, where disks typically reproduce data magnetically, while discs reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0073] The foregoing descriptions of specific embodiments may be readily modified and / or adapted for a variety of uses. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the taught embodiments, based on the teaching and guidance presented herein.

[0074] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

[0075] While specific configurations and arrangements are described, it should be understood that this is done for illustrative purposes only. Accordingly, other configurations and arrangements can be used without departing from the scope of the present disclosure. The subject matter described in this disclosure can also be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, modified, and rearranged with one another in a manner consistent with the scope of the present disclosure.

Claims

1. A peripheral circuit, a DQ circuit comprising a plurality of decision feedback equalization (DFE) components; 1. A resistor offset calibration (RXOC) circuit, comprising: an oscillator configured to generate an internal clock source; A DQ selection component comprising: selecting a DFE component from the plurality of DFE components for calibration; a DQ selection component configured to output a slicer result signal indicative of the value of the offset received from the DFE component; control logic configured to send a calibration signal associated with the DFE component to the DQ circuit based on the slicer result signal; and peripheral circuitry, including:

2. the DQ selection component includes a first multiplexer (MUX) and a second MUX; the first MUX is configured to select the DQ circuit; The peripheral circuit of claim 1 , wherein the second MUX is configured to select the DFE component of the DQ circuit.

3. The control logic The peripheral circuit of claim 1 , further configured to receive the slicer result signal at a first edge of a clock cycle associated with the internal clock source.

4. The control logic The peripheral circuit of claim 3 , further configured to perform a binary search based on the slicer result signal to identify a pull-up code or a pull-down code of the DFE component.

5. The control logic further configured to send the calibration signal to the DQ circuitry on a second edge of the clock cycle associated with the internal clock source; the first edge is one of a rising edge or a falling edge; the second edge is the other of the rising edge and the falling edge, The peripheral circuit according to claim 4 , wherein the calibration signal includes the pull-up code or the pull-down code.

6. The DQ circuit includes:

6. The peripheral circuit of claim 5, further configured to calibrate the DFE component based on a pull-up code or a pull-down code included in the calibration signal received from the control logic at the second edge of the clock cycle.

7. The oscillator comprises: further configured to receive an RXOC engage signal; The peripheral circuit of claim 1 , wherein the internal clock source is generated in response to receiving the RXOC engage command.

8. 8. The peripheral circuit of claim 7, wherein the oscillator generates the internal clock source without a column address strobe (CAS) command.

9. 1. A memory device comprising: a memory array; a peripheral circuit coupled to the memory array, a DQ circuit comprising a plurality of decision feedback equalization (DFE) components; 1. A resistor offset calibration (RXOC) circuit, comprising: an oscillator configured to generate an internal clock source; A DQ selection component comprising: selecting a DFE component from the plurality of DFE components for calibration; a DQ selection component configured to output a slicer result signal indicative of the value of the offset received from the DFE component; control logic configured to send a calibration signal associated with the DFE component to the DQ circuit based on the slicer result signal; and and peripheral circuits including a memory device.

10. the DQ selection component includes a first multiplexer (MUX) and a second MUX; the first MUX is configured to select the DQ circuit; The memory device of claim 9 , wherein the second MUX is configured to select the DFE component of the DQ circuitry.

11. The control logic 10. The memory device of claim 9, further configured to receive the slicer result signal at a first edge of a clock cycle associated with the internal clock source.

12. The control logic The memory device of claim 11 , further configured to perform a binary search based on the slicer result signal to identify a pull-up code or a pull-down code of the DFE component.

13. The control logic further configured to send the calibration signal to the DQ circuitry on a second edge of the clock cycle associated with the internal clock source; the first edge is one of a rising edge or a falling edge; the second edge is the other of the rising edge and the falling edge, The memory device of claim 12 , wherein the calibration signal includes the pull-up cord or the pull-down cord.

14. The DQ circuit includes:

14. The memory device of claim 13, further configured to calibrate the DFE component based on a pull-up code or a pull-down code included in the calibration signal received from the control logic at the second edge of the clock cycle.

15. The oscillator comprises: further configured to receive an RXOC engage signal; The memory device of claim 9 , wherein the internal clock source is generated in response to receiving the RXOC engage command.

16. 16. The memory device of claim 15, wherein the oscillator generates the internal clock source without a column address strobe (CAS) command.

17. 1. A method for resistor offset calibration (RXOC) by peripheral circuitry, comprising: generating an internal clock source by an oscillator of the RXOC circuit; selecting, by a DQ selection component of the RXOC circuit, a decision feedback equalization (DFE) component from a plurality of DFE components of the DQ circuit for calibration; Identifying, by the DQ selection component of the RXOC circuit, a value of an offset associated with the DFE component; outputting, by the DQ selection component of the RXOC circuit, a slicer result signal received from the DFE component based on the value of the offset; transmitting, by control logic of the RXOC circuit, a calibration signal associated with the DFE component to the DQ circuit based on the slicer result signal.

18. the DQ selection component includes a first multiplexer (MUX) and a second MUX; the first MUX is configured to select the DQ circuit; 18. The method of claim 17, wherein the second MUX is configured to select the DFE component of the DQ circuit.

19. 18. The method of claim 17, further comprising receiving, by the control logic of the RXOC circuit, the slicer result signal on a first edge of a clock cycle associated with the internal clock source.

20. 20. The method of claim 19, further comprising: performing, by the control logic of the RXOC circuit, a binary search based on the slicer result signal to identify a pull-up code or a pull-down code of the DFE component.

21. transmitting, by the control logic of the RXOC circuit, the calibration signal to the DQ circuit on a second edge of the clock cycle associated with the internal clock source; the first edge is one of a rising edge or a falling edge; the second edge is the other of the rising edge and the falling edge, 21. The method of claim 20, wherein the calibration signal includes the pull-up cord or the pull-down cord.

22. 22. The method of claim 21, further comprising calibrating the DFE component based on a pull-up code or a pull-down code included in the calibration signal received by the DQ circuit of the RXOC circuit from the control logic at the second edge of the clock cycle.

23. receiving, by the oscillator of the RXOC circuit, an RXOC engage signal; 20. The method of claim 17, wherein the internal clock source is generated in response to receiving the RXOC engage command.

24. 24. The method of claim 23, further comprising causing the oscillator to generate the internal clock source without a column address strobe (CAS) command.

25. 1. A memory system comprising:

1. A memory device comprising: a memory array; A peripheral circuit, a DQ circuit comprising a plurality of decision feedback equalization (DFE) components; 1. A resistor offset calibration (RXOC) circuit, comprising: an oscillator configured to generate an internal clock source; A DQ selection component comprising: selecting a DFE component from the plurality of DFE components for calibration; a DQ selection component configured to output a slicer result signal indicative of the value of the offset received from the DFE component; a resistor offset calibration (RXOC) circuit including: control logic configured to send a calibration signal associated with the DFE component to the DQ circuit based on the slicer result signal; and peripheral circuits including a memory device including: a memory controller coupled to the memory device and configured to control operation of the memory device.

26. the DQ selection component includes a first multiplexer (MUX) and a second MUX; the first MUX is configured to select the DQ circuit; 26. The memory system of claim 25, wherein the second MUX is configured to select the DFE component of the DQ circuitry.

27. The control logic 26. The memory system of claim 25, further configured to receive the slicer result signal at a first edge of a clock cycle associated with the internal clock source.

28. The control logic 28. The memory system of claim 27, further configured to perform a binary search based on the slicer result signal to identify a pull-up code or a pull-down code for the DFE component.

29. The control logic further configured to send the calibration signal to the DQ circuitry on a second edge of the clock cycle associated with the internal clock source; the first edge is one of a rising edge or a falling edge; the second edge is the other of the rising edge and the falling edge, 30. The memory system of claim 28, wherein the calibration signal includes the pull-up cord or the pull-down cord.

30. The DQ circuit includes:

30. The memory system of claim 29, further configured to calibrate the DFE component based on a pull-up code or a pull-down code included in the calibration signal received from the control logic at the second edge of the clock cycle.

31. The oscillator comprises: further configured to receive an RXOC engage signal; 26. The memory system of claim 25, wherein the internal clock source is generated in response to receiving the RXOC engage command.

32. 32. The memory system of claim 31, wherein the oscillator generates the internal clock source without a column address strobe (CAS) command.

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