Back contact solar cell and its manufacturing method

Abstract

The present invention relates to a back-contact solar cell. The back surface field region is positioned using a prismatic hole structure, which allows the thickness of the silicon substrate to be fully utilized to form the bottom and prismatic back surface field regions, thereby increasing the back surface field collection area without occupying the back surface area and maximizing the area of ​​the back surface emitter region. In a solar cell, the larger the emitter area ratio within a certain range, the more efficient the capture and transport of minority carriers, resulting in higher cell efficiency. Furthermore, because the back surface field region is positioned deep into the silicon wafer, majority carriers can be collected within the silicon wafer, shortening the transport and collection distance and enhancing the collection effect. As a result, this structure efficiently increases the collection of both minority and majority carriers, improving overall cell efficiency.

Description

[Technical Field]

[0001] This application claims priority from a Chinese patent application bearing application number 202310501272.9 and entitled "Back-contact solar cell and manufacturing method thereof," filed with the State Intellectual Property Office of the People's Republic of China on April 28, 2023, the entire contents of which are incorporated herein by reference.

[0002] The present invention relates to the technical field of solar cells, and more particularly to a back-contact solar cell and a method for fabricating the same. [Background technology]

[0003] Currently, as fossil fuel resources are gradually depleted, solar cells are becoming increasingly widely used as a new alternative energy source. Solar cells are devices that convert the light energy of sunlight into electrical energy by generating carriers using the photovoltaic effect and extracting the carriers using electrodes to efficiently utilize the electrical energy.

[0004] Back-contact cells, also known as back contact cells, include p-type back-contact solar cells known as interdigitated back-contact (IBC) cells. The key feature of IBC cells is that the emitter and metal contacts are located on the backside of the cell, with no front-side metal electrode interruption. This allows for higher short-circuit current density (Jsc) and allows for the placement of wide metal gate lines on the backside to reduce series resistance (Rs) and improve fill factor (FF). Furthermore, such cells without front-side interruption not only have high conversion efficiency, but also have a beautiful appearance and facilitate the assembly of all backside electrode components. IBC cells are currently one of the technological directions that can achieve high efficiency in crystalline silicon cells.

[0005] Currently, conventional p-type interdigitated back-contact solar cells have either a p-type base electrode or a diffused n-type emitter in their backside region, but selecting a dielectric layer that can adequately passivate both regions presents a significant challenge. Most dielectric layers also have surface charges that can cause current shunting, potentially reducing cell efficiency. For example, well-known passivation dielectric layers include aluminum oxide (alumina, Al2O3), which has a negative surface charge, and hydrogenated amorphous silicon nitride (α-SiN), which has a positive surface charge. x :H). In addition, in back-junction back-contact cells, carriers must be collected by diffusing from the front to the back surface field on the back side, which results in poor collection efficiency and further reduces the efficiency of the cell.

[0006] Chinese patent publication number CN1111108609A discloses an interdigitated back-contact solar cell with p-type conductivity, which has a front surface and a back surface for receiving radiation, the back surface comprising a tunnel oxide layer and a doped polysilicon layer with n-type conductivity, the tunnel oxide layer and the doped polysilicon layer with n-type conductivity forming a patterned stack with gaps, where an Al-Si alloyed contact is located within each of the gaps and is arranged to be in electrical contact with a base electrode layer of the substrate, and one or more Ag or transition metal contacts are located on the patterned doped polysilicon layer and are arranged to be in electrical contact with the patterned doped polysilicon layer. This structure can reduce shunt current and improve cell efficiency, but its structure is complex and its manufacturing method is difficult. Summary of the Invention [Problem to be solved by the invention]

[0007] The present invention has been made in view of this, and the technical problem to be solved is to provide a back-contact solar cell and a manufacturing method thereof that can increase carrier collection efficiency and improve cell effectiveness. [Means for solving the problem]

[0008] According to the present invention, there is provided a back contact solar cell as follows. The back-contact solar cell comprises a silicon substrate; a cylindrical hole and a non-cylindrical hole region are provided on a rear surface of the silicon substrate; a doped back surface field layer is provided in the pillar-shaped hole; a first electrode is provided on a back surface of the silicon substrate in electrical contact with the doped back surface field layer; a doped emitter layer including a doped polycrystalline silicon layer is provided in the non-columnar hole region; a second electrode is provided on the back surface of the silicon substrate in electrical contact with the doped polycrystalline silicon layer; The first electrode and the second electrode have opposite polarities and are insulated from each other.

[0009] The doped back surface field layer is preferably provided on the sidewalls and bottom surface of the pillar-shaped hole.

[0010] It is preferable that the diameter of the columnar holes is 50 to 300 μm, there are multiple columnar holes, the spacing between adjacent columnar holes is 500 to 3000 μm, and the depth of the columnar holes is 30% to 80% of the thickness of the silicon substrate.

[0011] The cylindrical holes are plural, and a first electrode is provided in each of the cylindrical holes; the first electrodes are plural, and the plural first electrodes are connected by first conductive paste lines; the second electrodes are plural, and the plural second electrodes are connected by second conductive paste lines; In addition, it is preferable that the first conductive paste wire and the second conductive paste wire are not in contact with each other.

[0012] the first electrodes are connected by the first conductive paste lines to form a "circle" spiral shape; The second electrodes are preferably connected by the second conductive paste lines so as to form a "wound" shape.

[0013] Preferably, the doped emitter layer further comprises a tunnel oxide layer provided between the silicon substrate in the non-pillar hole region and the doped polycrystalline silicon layer.

[0014] Preferably, the tunnel oxide layer has a thickness of 0.1 to 5 nm, the doped polycrystalline silicon layer has a thickness of 30 to 300 nm, the first electrode has a diameter of 200 to 100 μm, and the second electrode has a diameter of 10 to 30 μm.

[0015] Preferably, the silicon substrate is a P-type silicon substrate, the doped back surface field layer is a back surface field layer doped with a group III element, and the doped polycrystalline silicon layer is a polycrystalline silicon layer doped with a group V element.

[0016] Preferably, the silicon substrate is an N-type silicon substrate, the doped back surface field layer is a back surface field layer doped with a Group V element, and the doped polycrystalline silicon layer is a polycrystalline silicon layer doped with a Group III element.

[0017] The present invention further provides a method for manufacturing a back-contact solar cell as follows. The method for manufacturing the back contact solar cell includes: Step S1 of depositing an intrinsic amorphous silicon layer on the back surface of a silicon substrate; a step S2 of performing a primary doping process on the silicon substrate on which the intrinsic amorphous silicon layer has been deposited to form a doped polycrystalline silicon layer; a step S3 of printing an acidic etching material on the back surface of the silicon substrate on which the doped polycrystalline silicon layer is formed, and then performing a polishing process to form a columnar hole; Step S4: performing a secondary doping process on the silicon substrate with the cylindrical holes formed therein to form a doped back surface field layer; a step S5 of acid-washing the silicon substrate on which the doped back surface field layer is formed; and step S6 of fabricating a first electrode electrically contacting the doped back surface field layer and a second electrode electrically contacting the doped polycrystalline silicon layer on the back surface of the silicon substrate after the acid washing, the first electrode and the second electrode having opposite polarities and being insulated from each other, to obtain a back-contact solar cell.

[0018] The present invention provides a back-contact solar cell comprising a silicon substrate, the back surface of which has a cylindrical hole and a non-cylindrical hole region, a doped back surface field (BSF) layer in the cylindrical hole, a first electrode in electrical contact with the doped BSF layer in the back surface of the silicon substrate, a doped emitter layer including a doped polycrystalline silicon layer in the non-cylindrical hole region, and a second electrode in electrical contact with the doped polycrystalline silicon layer in the back surface of the silicon substrate. Compared to the prior art, the present invention utilizes a cylindrical hole structure to position the BSF region, thereby fully utilizing the thickness of the silicon substrate to form the bottom region and the pillar-wall BSF region. This increases the BSF collection area without occupying the back surface area and maximizes the area of ​​the back surface emitter region. In a solar cell, within a certain range, the larger the emitter area, the more efficiently minority carriers can be captured and transported, resulting in higher cell efficiency. Furthermore, since the back surface field region is located deep inside the silicon wafer, majority carriers can be collected inside the silicon wafer, shortening the transport and collection distance and enhancing the collection effect. As a result, this structure efficiently increases the collection of both minority and majority carriers, improving the overall efficiency of the battery. [Brief explanation of the drawings]

[0019] [Figure 1] 1 is a structural schematic diagram of a back-contact solar cell according to the present invention; [Figure 2] 1 is a schematic diagram of the distribution of prismatic holes in a back-contact solar cell according to the present invention; [Figure 3] 1 is a schematic diagram of the electrode arrangement of a back-contact solar cell according to the present invention. [Figure 4] 1 is a schematic structural diagram of a P-type silicon substrate after forming a pillar-shaped hole by erosion polishing according to the present invention; FIG. [Figure 5] 1 is a schematic diagram of the structure of a P-type silicon substrate after forming a doped back surface field layer by a secondary doping process according to the present invention; FIG. [Figure 6] 1 is a schematic structural diagram of a silicon substrate after pickling according to the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0020] Hereinafter, the technical solutions in the embodiments of the present invention will be clearly and completely explained with reference to the embodiments of the present invention. It is obvious that the embodiments described below are only some of the embodiments of the present invention, and are not all of the embodiments. Based on the embodiments of the present invention, other embodiments that can be obtained by those skilled in the art without creative work are all within the technical scope of the present invention.

[0021] According to the present invention, a silicon substrate; a cylindrical hole and a non-cylindrical hole region are provided on a rear surface of the silicon substrate; a doped back surface field layer is provided in the pillar-shaped hole; a first electrode is provided on a back surface of the silicon substrate in electrical contact with the doped back surface field layer; a doped emitter layer including a doped polycrystalline silicon layer is provided in the non-columnar hole region; A back-contact solar cell is provided, wherein a second electrode is provided on a back surface of the silicon substrate in electrical contact with the doped polycrystalline silicon layer.

[0022] Please refer to FIG. 1, which is a structural schematic diagram of a back-contact solar cell according to the present invention.

[0023] The silicon substrate in the back-contact solar cell according to the present invention is not particularly limited as long as it is a substrate well known to those skilled in the art, and may be either a P-type silicon substrate or an N-type silicon substrate.

[0024] The rear surface of the silicon substrate is provided with cylindrical holes and / or tapered holes. The cylindrical holes may be cylindrical holes and / or rhombic cylindrical holes, and are not particularly limited. In a specific embodiment of the present invention, the silicon substrate is preferably provided with cylindrical holes. Referring to FIG. 2, FIG. 2 is a schematic diagram of the distribution of cylindrical holes in a back-contact solar cell according to the present invention. The diameter of the cylindrical holes is preferably 50 to 300 μm, more preferably 80 to 200 μm, and even more preferably 100 to 150 μm. There are preferably a plurality of the cylindrical holes. The spacing between adjacent cylindrical holes is preferably 500 to 3000 μm, more preferably 800 to 2000 μm, even more preferably 800 to 1500 μm, and most preferably 1000 μm. The depth of the cylindrical holes is preferably 30% to 80% of the thickness of the silicon substrate. In one specific embodiment of the present invention, the bottom and / or sidewall of the cylindrical hole and / or the conical hole is provided with a textured structure. The number of textured structures may be one or more, and is not particularly limited. By providing a textured structure on the bottom and / or sidewall of the cylindrical hole and / or the conical hole, the area of ​​the back surface field region can be further increased.

[0025] A doped BSF layer is provided in the cylindrical hole. The thickness of the doped BSF layer is preferably 0.3 to 1 μm. In the present invention, the doped BSF layer is preferably provided on the sidewalls and bottom surface of the cylindrical hole. The doping element in the doped BSF layer can be selected depending on the type of silicon substrate. When the silicon substrate is a P-type silicon substrate, the doped BSF layer is a BSF layer doped with a Group III element, preferably a boron-doped BSF layer and / or a gallium-doped BSF layer, and is used as a P+ BSF region to selectively transport hole carriers. When the silicon substrate is an N-type silicon substrate, the doped BSF layer is a BSF layer doped with a Group V element, preferably a phosphorus-doped BSF layer, and is used as an N+ BSF region to selectively transport electron carriers. In the present invention, a BSF layer is preferably further provided on the surface of the doped BSF layer. The thickness of the BSF layer is preferably 62 to 220 nm. The back surface passivation layer is not particularly limited as long as it is a back surface passivation layer well known to those skilled in the art, but preferably includes an aluminum oxide layer and a silicon nitride layer stacked in the present invention. The thickness of the aluminum oxide layer is preferably 2 to 20 nm. The thickness of the silicon nitride layer is preferably 60 to 200 nm.

[0026] A first electrode is provided on the back surface of the silicon substrate, i.e., the first electrode is provided in the cylindrical hole. The first electrode is in electrical contact with the doped BSF layer. The shape of the first electrode may be columnar or conical, and is not particularly limited, but in the present invention, a cylindrical shape is preferred. The diameter of the first electrode is preferably 200 to 100 μm. The height of the first electrode preferably extends to near the surface of the flat region of the silicon substrate, i.e., the height of the first electrode is equal to or smaller than the depth of the cylindrical hole and / or conical hole. More specifically, the height of the first electrode is equal to or smaller than the depth of the cylindrical hole. The first electrode is preferably an aluminum electrode. The first electrode functions to be in electrical contact with the doped BSF layer.

[0027] In the present invention, there are a plurality of cylindrical holes and / or tapered holes, each of which has a first electrode disposed therein. Since there are a plurality of first electrodes, the first conductive gate lines are also referred to as first conductive paste lines, and the plurality of first electrodes are connected by the first conductive gate lines or first conductive paste lines. More preferably, the first conductive gate lines or first conductive paste lines are provided so as to connect the plurality of first electrodes to the surface of the back surface passivation layer. Even more preferably, the first electrodes connected by the first conductive gate lines or first conductive paste lines have a "wound" spiral shape. The line width of the first conductive gate lines or first conductive paste lines is preferably 20 to 300 μm. The type of the first conductive gate lines or first conductive paste lines may be any gate line or paste line well known to those skilled in the art, and is not particularly limited. However, in the present invention, aluminum paste is preferably used (formed by sintering using a method well known to those skilled in the art).

[0028] The back surface of the silicon substrate is a non-columnar hole region except for the cylindrical holes and / or tapered holes. A doped emitter layer is provided on the front surface of the silicon substrate in the non-columnar hole region. The doped emitter layer includes a doped polycrystalline silicon layer. The thickness of the doped polycrystalline silicon layer is preferably 30 to 300 nm. The type of doping element in the doped polycrystalline silicon layer can be selected depending on the type of silicon substrate. When the silicon substrate is a P-type silicon substrate, the doped polycrystalline silicon layer is a polycrystalline silicon layer doped with a Group V element, preferably a phosphorus-doped polycrystalline silicon layer. When the silicon substrate is an N-type silicon substrate, the doped polycrystalline silicon layer is a polycrystalline silicon layer doped with a Group III element, preferably a boron-doped polycrystalline silicon layer and / or a gallium-doped polycrystalline silicon layer. In the present invention, the doped emitter layer preferably further includes a tunnel oxide layer, which is provided between the silicon substrate and the doped polycrystalline silicon layer in the non-columnar hole region. The thickness of the tunnel oxide layer is preferably 0.1 to 5 nm, more preferably 0.5 to 4 nm, and even more preferably 1 to 3 nm. The tunnel oxide layer may be a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer. In the present invention, a back surface passivation layer is preferably provided on the surface of the doped emitter layer, and more preferably, the back surface passivation layer in the non-columnar hole region and the back surface passivation layer in the columnar hole and / or conical hole are provided integrally. That is, in the present invention, the back surface passivation layer is provided on the back surface of the silicon substrate and covers the doped back surface field layer and the doped polycrystalline silicon layer. The back surface passivation layer has an opening, and the first electrode is in electrical contact with the doped back surface field layer through the opening, and the second electrode is in electrical contact with the doped polycrystalline silicon layer through the opening. The thickness of the back surface passivation layer in the non-columnar hole region is preferably 62 to 220 nm.The back surface passivation layer is not particularly limited as long as it is a back surface passivation layer well known to those skilled in the art, but in the present invention, it preferably includes an aluminum oxide layer, and more preferably includes an aluminum oxide layer and a silicon nitride layer stacked together. The thickness of the aluminum oxide layer is preferably 2 to 20 nm. The thickness of the silicon nitride layer is preferably 60 to 200 nm.

[0029] A second electrode is provided on the rear surface of the silicon substrate, i.e., the second electrode is provided in the non-columnar hole region of the silicon substrate. The second electrode and the first electrode have opposite polarities and are insulated from each other. The shape of the second electrode is preferably cylindrical. The diameter of the second electrode is preferably 10 to 30 μm. The type of the second electrode is preferably a silver electrode. There are preferably a plurality of second electrodes. Preferably, the plurality of second electrodes are connected by second conductive gate lines, also called second conductive paste lines, and the first conductive gate line or first conductive paste line is not in contact with the second conductive gate line or second conductive paste line. More preferably, the second conductive gate line or second conductive paste line is provided so as to connect the plurality of second electrodes to the surface of the rear surface passivation layer. Even more preferably, the second electrodes connected by the second conductive gate line or second conductive paste line have a "wound" shape. Referring to Figure 3, Figure 3 is a schematic diagram of the electrode arrangement of a back-contact solar cell according to the present invention. In the figure, black dots represent first electrodes, black lines represent first conductive gate lines or first conductive paste lines, gray dots represent second electrodes, and gray lines represent second conductive gate lines or second conductive paste lines. The line width of the second conductive gate lines or second conductive paste lines is preferably 100 to 2000 µm. The type of the second conductive gate lines or second conductive paste lines may be any type well known to those skilled in the art and is not particularly limited, but in the present invention, aluminum paste is preferred (it may be formed by sintering using a method well known to those skilled in the art).

[0030] The front surface of the silicon substrate is a pyramidal textured surface. A front passivation layer is provided on the front surface of the silicon substrate, and the front passivation layer is provided on the light-receiving surface of the silicon substrate. The thickness of the front passivation layer is preferably 57 to 120 nm. The front passivation layer may be any front passivation layer well known to those skilled in the art, and is not particularly limited. However, in the present invention, it is preferably an aluminum oxide layer, and more preferably includes an aluminum oxide layer, a silicon nitride layer, and a silicon oxide layer provided in a stacked manner. The aluminum oxide layer has a high density of negative fixed charges and is suitable for surface passivation of p-type silicon. The thickness of the aluminum oxide layer is preferably 2 to 20 nm. The thickness of the silicon nitride layer is preferably 50 to 80 nm. The thickness of the silicon oxide layer is preferably 5 to 20 nm.

[0031] In the present invention, the back surface field region is arranged using a cylindrical hole and / or a conical hole structure, which allows the thickness of the silicon substrate to be fully utilized to form the bottom region and the pillar-shaped back surface field region, thereby increasing the back surface field collection area without occupying the back surface area and maximizing the area of ​​the back surface emitter region. In solar cells, the larger the emitter area ratio within a certain range, the more efficient the capture and transport of minority carriers, resulting in higher cell efficiency. Furthermore, because the back surface field region is arranged deep into the silicon wafer, majority carriers can be collected within the silicon wafer, shortening the transport and collection distance and enhancing the collection effect. As a result, this structure efficiently increases the collection of both minority and majority carriers, improving overall cell efficiency.

[0032] The present invention further provides a method for manufacturing a back-contact solar cell, including the steps of: S1 depositing an intrinsic amorphous silicon layer on a back surface of a silicon substrate; S2 performing a first doping process on the silicon substrate on which the intrinsic amorphous silicon layer has been deposited to form a doped polycrystalline silicon layer; S3 printing an acidic etching material on the back surface of the silicon substrate on which the doped polycrystalline silicon layer has been formed, followed by polishing to form prismatic holes and / or conical holes; S4 performing a second doping process on the silicon substrate on which the prismatic holes and / or conical holes have been formed to form a doped BSF layer; S5 acid-washing the silicon substrate on which the doped BSF layer has been formed; and S6 fabricating a first electrode in electrical contact with the doped BSF layer and a second electrode in electrical contact with the doped polycrystalline silicon layer on the back surface of the silicon substrate after the acid-washing process, the first electrode and the second electrode having opposite polarities and being insulated from each other, thereby obtaining a back-contact solar cell.

[0033] In the present invention, the supply sources of all the raw materials are not particularly limited, and commercially available products may be used.

[0034] In the present invention, it is preferable to first subject the silicon substrate to double-sided polishing. The double-sided polishing method may be any method well known to those skilled in the art and is not particularly limited, but it is preferable to use alkaline polishing in the present invention. The alkali in the alkaline polishing liquid used in the alkaline polishing is preferably one or more of potassium hydroxide, sodium hydroxide, and tetramethylammonium hydroxide (TMAH). The mass concentration of the alkali in the alkaline polishing liquid is preferably 5% to 20%. A polishing additive may be added to the alkaline polishing liquid in addition to the alkali, as this contributes to surface planarization. The temperature of the polishing treatment is preferably 60°C to 90°C. The polishing treatment can remove cutting damage on the surface, smooth the surface, and reduce surface defects.

[0035] Next, an intrinsic amorphous silicon layer is deposited on the rear surface of the silicon substrate. More preferably, a tunnel oxide layer is deposited on the rear surface of the silicon substrate, followed by the deposition of the intrinsic amorphous silicon layer. The tunnel oxide layer in the present invention may be a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer. The tunnel oxide layer may be deposited by any method well known to those skilled in the art, and is not particularly limited. However, it is preferred to use one or more of LPCVD (low-pressure chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), and PEALD (plasma-enhanced atomic layer deposition). The thickness of the tunnel oxide layer is preferably 0.1 to 5 nm. The intrinsic amorphous silicon layer may be deposited by any method well known to those skilled in the art, and in the present invention, it is preferred to use one or more of LPCVD, PEALD, and PVD (physical vapor deposition). The thickness of the intrinsic amorphous silicon layer is preferably 30 to 300 nm.

[0036] A primary doping process is performed on a silicon substrate on which an intrinsic amorphous silicon layer has been deposited, to form a doped polycrystalline silicon layer. The doping process method is selected depending on the type of silicon substrate and the doping element in the doped polycrystalline silicon layer. When the silicon substrate is a P-type silicon substrate, this process preferably involves diffusion of a group V element or ion implantation of a group V element, and more preferably involves phosphorus diffusion or phosphorus ion implantation. The phosphorus diffusion is preferably phosphorus diffusion using a high-temperature tubular furnace. The phosphorus source for the phosphorus diffusion is preferably phosphoryl chloride. The temperature for the phosphorus diffusion is preferably 930°C to 980°C. The duration of the phosphorus diffusion is preferably 60 to 80 minutes. The energy required for the phosphorus ion implantation is preferably 5 to 200 keV. The dose for the phosphorus ion implantation is 1×10 19 / cm 3 ~10×10 19 / cm 3Preferably, an oxidation annealing treatment is also performed after the phosphorus ion implantation. The temperature of the oxidation annealing treatment is preferably 900°C to 980°C. The duration of the oxidation annealing treatment is preferably 30 to 50 minutes. The oxidation annealing treatment is preferably performed in an air environment. The sheet resistance of the silicon substrate after phosphorus diffusion or phosphorus ion implantation is preferably 20 to 80 Ω / □, more preferably 20 to 50 Ω / □. In this process, a phosphorus-containing silicon oxide layer, commonly known as a PSG layer, is formed on the surface, preferably with a thickness of 40 to 60 nm. When doped by phosphorus diffusion in this process, a phosphorus-doped general emitter is also formed on the front surface, which has the effect of absorbing impurities. In the subsequent texturing process, this emitter is removed along with the absorbed impurities. In this process, the intrinsic amorphous silicon is converted into the corresponding doped polycrystalline silicon. When the silicon substrate is an N-type silicon substrate, the primary doping treatment is preferably a doping treatment of a Group III element, more preferably boron diffusion. The boron diffusion is preferably a boron diffusion treatment using a high-temperature tubular furnace. The boron source for the boron diffusion is preferably boron trichloride and / or boron tribromide. The temperature for the boron diffusion is preferably 930°C to 980°C. The duration of the boron diffusion is preferably 60 to 80 minutes. The sheet resistance of the silicon substrate after the boron diffusion treatment is preferably 20 to 80 Ω / □, more preferably 40 to 50 Ω / □. During this process, a boron-containing silicon oxide layer, commonly known as a BSG layer, is formed on the surface, and its thickness is preferably 40 to 60 nm.

[0037] An acidic etching material is printed on the backside of a silicon substrate on which a doped polycrystalline silicon layer has been formed. In the present invention, the acidic etching material is printed by screen printing according to the distribution of columnar and / or tapered holes, and the acidic etching material can remove the PSG or BSG layer formed during the primary doping process, exposing the underlying silicon substrate. The acidic etching material preferably contains oxalic acid, a surfactant, a thickener, modified silica, deionized water, and sodium fluoride, and can etch the PSG or BSG layer at room temperature or under heated conditions. The mass concentration of the oxalic acid in the acidic etching material is preferably 5% to 20%. The mass concentration of the surfactant in the acidic etching material is preferably 5% to 10%. The surfactant is preferably sodium citrate. The mass concentration of the thickener in the acidic etching material is preferably 10% to 20%. The thickener is preferably a resin. The mass concentration of the modified silica in the acidic etching material is preferably 20% to 40%. The modified silica is preferably silica particles with a smoothed surface and a diameter of 10 to 20 μm. The mass concentration of deionized water in the acidic etching material is preferably 5% to 20%. The mass concentration of sodium fluoride in the acidic etching material is preferably 1% to 10%. After printing the acidic etching material, the remaining etching material is removed by washing. The PSG or BSG layer on the back side, where the acidic etching material is not printed, remains and functions as an alkali barrier layer to protect the underlying doped polycrystalline silicon layer during the polishing process. The PSG or BSG layer, as an accessory layer formed during the primary doping process, can serve to block alkaline etching. This eliminates the need to separately deposit a silicon oxide or silicon nitride layer as an alkaline etching barrier layer, thereby reducing process steps and costs.

[0038] The silicon substrate from which the acidic etching material has been removed by washing is polished to form columnar and / or conical holes. While the polishing method is not particularly limited and may be any method well known to those skilled in the art, alkaline polishing is preferably used in the present invention. The alkali in the alkaline polishing solution used for alkaline polishing is preferably one or more of potassium hydroxide, sodium hydroxide, and tetramethylammonium hydroxide (TMAH). The mass concentration of the alkali in the alkaline polishing solution is preferably 5% to 20%. In addition to the alkali, a polishing additive may be added to the alkaline polishing solution. This has the function of protecting the oxide layer by ensuring that the PSG or BSG layer is not completely corroded, and preferably leaves a PSG or BSG layer of 30 to 50 nm thick. The polishing temperature is preferably 60°C to 90°C. A polished flat structure is formed in the areas not covered or protected by the PSG or BSG layer, i.e., a polished structure with a certain depth appears in the pattern area on the backside, forming columnar and / or conical holes. The depth of the cylindrical holes and / or tapered holes is preferably 30-80% of the thickness of the silicon wafer. In this process, the front surface of the silicon substrate is not polished because it is protected by the PSG or BSG layer. Referring to Figure 4, Figure 4 is a schematic diagram of the structure of a P-type silicon substrate after the formation of cylindrical holes by corrosive polishing.

[0039] A doped BSF layer is formed by performing a secondary doping process on the silicon substrate with the cylindrical holes and / or conical holes formed therein. The method of the secondary doping process is selected depending on the type of silicon substrate and the doping element in the doped polycrystalline silicon layer. If the silicon substrate is a P-type silicon substrate, this process preferably involves doping with a Group III element, and more preferably boron diffusion. The boron diffusion method is the same as above, and will not be further described here. If the silicon substrate is an N-type silicon substrate, this process preferably involves Group V element diffusion or Group V element ion implantation, and more preferably phosphorus diffusion or phosphorus ion implantation. The phosphorus diffusion and phosphorus ion implantation methods are both the same as above, and will not be further described here. Referring to FIG. 5, this is a schematic diagram of the structure of a P-type silicon substrate after the doped BSF layer is formed by the secondary doping process.

[0040] Since a PSG or BSG layer is formed on the front surface of the silicon substrate during the first doping process, it is preferable to remove the front PSG or BSG layer of the silicon substrate on which the doped back surface field layer is formed, then perform a texturing process, and then remove the back surface PSG and BSG layers by acid washing. The front PSG or BSG layer is preferably removed using an in-line etching machine, and the solution used for removal using the in-line etching machine is preferably a hydrofluoric acid solution, more preferably a 1% to 10% hydrofluoric acid solution. The solution used for the texturing process is preferably an alkaline solution. The alkali in the solution used for the texturing process is preferably one or more of potassium hydroxide, sodium hydroxide, and tetramethylammonium hydroxide (TMAH). The mass concentration of the alkali in the solution used for the texturing process is preferably 5% to 20%. A texturing additive is preferably added during the texturing process. The additive is preferably an additive with an oxide layer protection function. After the texturing process, the front surface of the silicon substrate becomes a pyramidal textured surface, which exhibits an optical trapping effect. The back surface is protected by an oxide layer, so the texture phenomenon does not occur. After the front surface texturing process, the BGS layer and PSG layer on the back surface are removed by acid pickling. The solution used for the acid pickling is preferably a hydrofluoric acid solution, more preferably a 1% to 10% hydrofluoric acid solution. Referring to FIG. 6, FIG. 6 is a schematic diagram of the structure of the silicon substrate after acid pickling.

[0041] According to the present invention, it is preferable to further deposit a backside passivation layer on the backside of the silicon substrate after pickling, and more preferably to further deposit a frontside passivation layer on the frontside of the silicon substrate after pickling. In the present invention, the deposition order of the frontside passivation layer and the backside passivation layer is not particularly limited, and either the frontside passivation layer or the backside passivation layer may be deposited first, but is not particularly limited. In the present invention, to save manufacturing steps, it is preferable to manufacture the frontside passivation layer and the backside passivation layer simultaneously, more preferably in the same reaction chamber. The types of the frontside passivation layer and the backside passivation layer are all the same as above, and will not be further described here. More preferably, in the present invention, the frontside passivation layer and the backside passivation layer are manufactured by applying double-sided aluminum oxide film plating to the silicon substrate after pickling. The deposition method for the front passivation layer and the back passivation layer is not particularly limited and may be any method well known to those skilled in the art. In the present invention, it is preferable to use the PECVD method, the ALD method or the PEALD method.

[0042] A first electrode electrically contacting the doped back surface field layer and a second electrode electrically contacting the doped polycrystalline silicon layer are fabricated on the back surface of a silicon substrate on which a back surface passivation layer has been deposited. Specifically, the first electrode is fabricated in the cylindrical and / or conical holes on the back surface of the silicon substrate on which the back surface passivation layer has been deposited, and the second electrode is fabricated in the non-cylindrical hole area, thereby obtaining a back-contact solar cell. The first electrode is preferably fabricated by the following method: An opening is formed in the cylindrical and / or conical hole using a laser or an acid etching material, the back surface passivation layer in the opening area is removed, and the first electrode is printed. In the present invention, a first conductive paste is preferably simultaneously printed to form a first conductive paste line to connect the first electrode. The diameter of the opening is preferably 10 to 50 μm. The first electrode is preferably a low-corrosive aluminum paste or a non-corrosive aluminum paste. The first conductive paste is preferably a low-corrosive aluminum paste or a non-corrosive aluminum paste. The method for manufacturing the second electrode is preferably as follows: a corrosive paste is printed in the non-columnar hole area to form the second electrode, and then a second conductive paste is printed to form a second conductive paste line to connect the second electrode. The corrosive paste is preferably a corrosive silver paste. The glass frit in the corrosive paste opens the backside passivation layer, allowing the paste to contact the doped polycrystalline silicon layer. The second conductive paste is preferably a low-corrosive aluminum paste or a non-corrosive aluminum paste. Finally, electrical contact is preferably formed by sintering to obtain a back-contact solar cell. The sintering temperature is preferably 600°C to 800°C. The sintering time is preferably 2 to 5 minutes.

[0043] To further illustrate the present invention, the back contact solar cell and the method for fabricating the same according to the present invention will be described in detail below with reference to examples.

[0044] All reagents used in the following examples are commercially available. The polishing additive used in the examples was a polishing additive manufactured by Tuobang New Energy Co., Ltd., model number PI10V02. The resin thickener used in the examples was a polishing additive manufactured by Xiamen Hao'er New Materials Co., Ltd., model number HR575. The silica particles used for surface smoothing treatment were manufactured by Xiamen Hao'er New Materials Co., Ltd., model number HR575. The texturing additive was manufactured by Tuobang New Energy Co., Ltd., model number EP32.

[0045] [Example 1] 1.1: Double-sided polishing of P-type silicon wafers In order to remove the cutting damage on the surface, smooth the surface, and reduce surface defects, polishing was performed with ordinary alkali, followed by chemical reaction at 80°C for 300 seconds using 10% potassium hydroxide solution and 1% polishing additive.

[0046] 1.2: Deposition of a tunnel layer and an intrinsic amorphous silicon layer on the backside A tunneling silicon oxide layer was deposited on the backside by LPCVD (low pressure chemical vapor deposition) to a thickness of 1.5 nm, followed by deposition of intrinsic amorphous silicon by LPCVD to a thickness of 150 nm.

[0047] 1.3: Double-sided phosphorus diffusion The silicon wafer obtained in 1.2 was subjected to double-sided phosphorus diffusion. Specifically, phosphorus diffusion was carried out in a high-temperature tubular furnace under the following conditions: phosphorus source was phosphoryl chloride POCl3, phosphorus diffusion temperature was 950°C, phosphorus diffusion duration was 60 minutes, and phosphorus diffusion was then carried out in an air environment at 900°C for 30 minutes. The sheet resistance of the silicon wafer after phosphorus diffusion was 50 Ω / □. During this process, a 40 nm thick phosphorus-containing silicon oxide layer, commonly known as a PSG layer, was formed on the surface.

[0048] The double-sided phosphorus diffusion performed here created a common phosphorus-doped emitter on the front side, which absorbed the impurities. In a subsequent texturing process, this emitter was removed along with the absorbed impurities. This process transformed the intrinsic amorphous silicon into the corresponding N-type doped polycrystalline silicon.

[0049] 1.4: Printing acidic corrosion materials After double-sided phosphorus diffusion, a phosphorus-containing silica layer was formed on the front and back surfaces of the silicon wafer as a PSG layer. Then, an acidic etching material was screen-printed according to the pattern of cylindrical hole-shaped BSF regions. The cylindrical hole-shaped BSF regions had a diameter of 100 μm and a spacing of 1000 μm. The etching material etched and removed the PSG layer in these areas, exposing the underlying P-type silicon substrate.

[0050] This etching material, consisting of oxalic acid, surfactant, thickener, modified silica, deionized water, and sodium fluoride, is corrosive to the PSG layer at room temperature or under heat. The components are 10 wt% oxalic acid, 8 wt% sodium citrate (surfactant), 10 wt% resin thickener, 30 wt% silica particles for surface smoothing, 5 wt% sodium fluoride, and the remainder deionized water. After printing, the remaining etching material was removed by washing. To protect the underlying N-type doped polycrystalline silicon, the backside PSG layer, which was not printed with the acidic etching material, was left as an alkaline barrier layer during the S5 polishing process. Furthermore, the PSG layer acts as an accessory to the phosphorus diffusion process, blocking alkaline etching. This eliminates the need for a separate silicon oxide or silicon nitride layer as an alkaline etching barrier, reducing process steps and costs.

[0051] 1.5: Hole formation by polishing the cylindrical hole-shaped area on the backside The silicon wafers, after cleaning to remove the acidic corrosion materials, were polished using 10% potassium hydroxide and a 1% polishing additive, which protected the oxide layer. The polishing time was 300 seconds and the temperature was 80°C. A 30-nm layer of PSG was left to ensure excessive corrosion. A polished, flat structure was formed in the areas not covered and protected by the PSG layer. In other words, the patterned area on the backside produced a polished structure with a constant depth, with the depth of the columns being 50% of the thickness of the silicon wafer. The front surface of the silicon wafer was not polished because it was protected by the PSG layer.

[0052] 1.6: Backside boron diffusion The silicon wafers obtained in 1.5 were subjected to backside boron diffusion. Specifically, the boron source was boron trichloride BCl3, the boron diffusion temperature was 950°C, and the boron diffusion duration was 60 minutes in a high-temperature tubular furnace. The sheet resistance of the silicon wafers after boron diffusion was 40 Ω / □. During this process, a boron-containing silicon oxide layer, commonly known as a BSG layer, was formed on the surface to a thickness of 50 nm.

[0053] 1.7: Removal of front PSG layer and texturing of front surface The silicon wafer obtained in 1.6 had the front PSG layer removed using an in-line etching machine in a 5% HF solution. Then, texturing was performed in a 10% potassium hydroxide solution with a 1.5% texturing additive, which functions as an oxide layer protection agent, at 80°C for 400 seconds. This resulted in a pyramidal textured surface on the entire front surface, demonstrating the light tweezers effect. The back surface was protected by the oxide layer, so no texture phenomenon occurred. After front surface texturing, the BGS and PSG layers on the back surface were removed by pickling in a 50% HF solution for 300 seconds.

[0054] 1.8: Front and backside laminate passivation To achieve chemical passivation effects on the front and back surfaces, hydrogen-containing dielectric layers were deposited on both the front and back surfaces. Specifically, the back surface had a stacked passivation of 10 nm thick aluminum oxide grown by PECVD and 100 nm thick silicon nitride grown by PECVD. The front surface had stacked layers of aluminum oxide, silicon nitride, and silicon oxide, all grown by PECVD, with thicknesses of 10 nm, 50 nm, and 5 nm, respectively.

[0055] 1.9: Backside metallization (distribution structure shown in Figure 3) A 50 μm diameter opening was created in the cylindrical hole of the P-type region using a laser or acid etching material. However, only the dielectric layer in the opening area was removed. A low-corrosion aluminum paste (black dot) was printed above the opening area of ​​the P-type region, so that it was cylindrical in shape, 50 μm in diameter, and extended to near the back surface of the silicon wafer. This achieved the effect of electrical contact with the P-type region. Additionally, a 20 μm wide black low-corrosion aluminum paste was printed to connect the black contact points of the P-type region.

[0056] Corrosive silver paste (gray dots are contact points of the emitter firing paste, 20 μm in diameter) was printed at localized locations on the N-type polycrystalline silicon. Note that the glass frit in the corrosive silver paste opened the dielectric layer, allowing the silver to contact the N-type polycrystalline silicon. Next, non-corrosive connecting lines (gray lines) with a line width of 100 μm were printed to connect the gray contact points, and finally, the electrodes were formed by co-sintering at 800°C for 3 minutes.

[0057] [Example 2] 2.1: Double-sided polishing of P-type silicon wafers In order to remove the cutting damage on the surface, smooth the surface, and reduce surface defects, conventional alkaline polishing using 20% ​​potassium hydroxide solution and 1.5% polishing additive was performed, and a chemical reaction was carried out at 80°C for 300 seconds.

[0058] 2.2: Deposition of a tunnel layer and an intrinsic amorphous silicon layer on the backside A tunneling silicon oxide layer was deposited on the backside by LPCVD (low pressure chemical vapor deposition) to a thickness of 2 nm, followed by deposition of intrinsic amorphous silicon by LPCVD to a thickness of 250 nm.

[0059] 2.3: Double-sided phosphorus diffusion The silicon wafer obtained in 2.2 was subjected to double-sided phosphorus diffusion. Specifically, phosphorus diffusion was carried out in a high-temperature tubular furnace under the following conditions: phosphorus source was phosphoryl chloride POCl3, the phosphorus diffusion temperature was 935°C, and the phosphorus diffusion duration was 60 minutes. The wafer was then subjected to oxidation annealing in an air environment at 900°C for 30 minutes. The sheet resistance of the silicon wafer after phosphorus diffusion was 20 Ω / □. During this process, a 40-nm-thick layer of phosphorus-containing silicon oxide, commonly known as a PSG layer, was formed on the surface.

[0060] The double-sided phosphorus diffusion performed here created a phosphorus-doped general emitter on the front side, which acts as an impurity absorber. In a subsequent texturing process, this emitter is removed along with the absorbed impurities. This process converts the intrinsic amorphous silicon into the corresponding N-type doped polycrystalline silicon.

[0061] 2.4: Printing acid-corrosive materials Using double-sided phosphorus diffusion, a PSG layer, a phosphorus-containing silica layer, was formed on the front and back surfaces of a silicon wafer. Then, using a screen printing method, an acidic etching material was printed according to the pattern of cylindrical hole-shaped BSF regions, with a diameter of 100 μm and spacing of 1000 μm. Using this etching material, the PSG layer was etched and removed, exposing the underlying P-type silicon substrate.

[0062] This etching material consists of oxalic acid, surfactant, thickener, modified silica, deionized water, and sodium fluoride, and acts on the PSG layer at room temperature or under heat. The components are 10 wt% oxalic acid, 8 wt% sodium citrate (surfactant), 10 wt% resin thickener, 30 wt% silica particles for surface smoothing, 5 wt% sodium fluoride, and the remainder is deionized water. After printing the etching material, the remaining etching material was removed by washing. To protect the underlying N-type doped polycrystalline silicon, the PSG layer on the back side, where the acidic etching material was not printed, was left as an alkaline barrier layer during the S5 polishing process. Furthermore, the PSG layer acts as an accessory to the phosphorus diffusion process, blocking alkaline etching, eliminating the need to separately deposit a silicon oxide or silicon nitride layer as an alkaline etching barrier, reducing process steps and costs.

[0063] 2.5: Hole formation by polishing the cylindrical hole-shaped area on the backside After cleaning to remove the acidic etching material, the silicon wafer was polished for 300 seconds at 80°C in the presence of 15% potassium hydroxide and a 1.2% polishing additive, which acts as a protective layer for the oxide layer. A 30nm layer of PSG was left behind to ensure that the PSG was not excessively corroded. A polished, flat structure was formed in the areas not protected by the PSG layer. In other words, the patterned area on the backside produced a polished structure with a constant depth, with the depth of the columns being 40% of the thickness of the silicon wafer. The frontside of the silicon wafer was not polished because it was protected by the PSG layer.

[0064] 2.6: Backside boron diffusion The silicon wafers obtained in 2.5 were subjected to backside boron diffusion. Specifically, boron diffusion was carried out in a high-temperature tubular furnace under the following conditions: boron source was boron trichloride BCl3, the boron diffusion temperature was 950°C, and the boron diffusion duration was 60 minutes. The sheet resistance of the silicon wafers after boron diffusion was 40 Ω / □. During this process, a boron-containing silicon oxide layer, commonly known as a BSG layer, was formed on the surface to a thickness of 40 to 50 nm.

[0065] 2.7: Removal of front PSG layer and front texturing The front PSG layer of the silicon wafer obtained in 2.6 was removed using an in-line etching machine in a 5% HF solution. The texturing process was performed at 80°C for 400 seconds under the action of a 1.5% texturing additive in a 10% potassium hydroxide solution. This texturing additive had the function of protecting the oxide layer. The entire front surface became a pyramidal textured surface, providing a light trapping effect. Because the back surface was protected by the oxide layer, no texture phenomenon occurred. After the front texturing process, the BGS and PSG layers on the back surface were removed by pickling in a 50% HF solution for 300 seconds.

[0066] 2.8: Front and backside laminate passivation To provide chemical passivation for the front and back surfaces, hydrogen-containing dielectric layers were deposited on both the front and back surfaces. Specifically, the back surface had a 10-nm thick stack of aluminum oxide (deposited by PECVD) and a 100-nm thick stack of silicon nitride (deposited by PECVD). The front surface had stacks of aluminum oxide, silicon nitride, and silicon oxide (deposited by PECVD) with thicknesses of 10 nm, 50 nm, and 5 nm, respectively.

[0067] 2.9: Backside metallization (distribution structure shown in Figure 3) A 50 μm diameter opening was created in the cylindrical hole of the P-type region using a laser or acid etching material. However, only the dielectric layer in the opening area was removed. A low-corrosion aluminum paste (black dot) was printed above the opening area of ​​the P-type region, so that it was cylindrical in shape, 50 μm in diameter, and extended to near the backside of the silicon wafer. This achieved electrical contact with the P-type region. Additionally, a 50 μm wide black low-corrosion aluminum paste was printed to connect the black contact points of the P-type region.

[0068] Corrosive silver paste (gray dots were contact points for the emitter's sintered paste, 20 μm in diameter) was printed at localized locations on the N-type polysilicon. The glass frit in the corrosive silver paste opened the dielectric layer, allowing the silver to contact the N-type polysilicon. Next, non-corrosive connecting lines (gray lines) with a line width of 100 μm were printed to connect the gray contact points, and finally, the electrodes were formed by co-sintering at 780°C for 3 minutes.

[0069] The performance of the back-contact solar cells obtained in Examples 1 and 2 was measured under standard STC conditions (25°C, 1000 W / m 2 The battery's electrical performance was tested using a 1000kJ / s 1000kcal / s 1.5G light source. The results are shown in Table 1 below. The common IBC battery in Table 1 is a "Zebra" structure IBC battery manufactured by State Power Xining Solar Energy Co., Ltd., measuring 166 x 166 mm and the specific model number is the "Andromeda" series.

[0070] [Table 1]

[0071] The specific embodiments described herein are merely illustrative of the spirit of the present invention, and those skilled in the art may make various modifications and additions to the specific embodiments described, or substitute similar methods, without departing from the spirit of the present invention or the scope defined by the appended claims.

Claims

1. a silicon substrate; a rear surface of the silicon substrate is provided with a columnar hole and a non-columnar hole region; a doped back surface field layer is provided in the pillar-shaped hole; a first electrode is provided on a back surface of the silicon substrate in electrical contact with the doped back surface field layer; a doped emitter layer including a doped polycrystalline silicon layer is provided in the non-columnar hole region; a second electrode is provided on a back surface of the silicon substrate in electrical contact with the doped polycrystalline silicon layer; A back-contact solar cell, characterized in that the first electrode and the second electrode have opposite polarities and are insulated from each other.

2. a silicon substrate having a first doping type; a rear surface of the silicon substrate is provided with cylindrical holes and / or tapered holes and a non-cylindrical hole region; a doped back surface field layer having a first doping type is provided in the pillar-shaped hole; a first electrode is provided on a back surface of the silicon substrate in electrical contact with the doped back surface field layer; a doped emitter layer in the non-columnar hole region, the doped emitter layer including a doped polycrystalline silicon layer having a second doping type; a second electrode is provided on a back surface of the silicon substrate in electrical contact with the doped polycrystalline silicon layer; A back-contact solar cell, characterized in that the first electrode and the second electrode have opposite polarities and are insulated from each other.

3. 3. The back contact solar cell of claim 1, wherein the doped back surface field layer is provided on the sidewalls and bottom surface of the cylindrical and / or conical holes.

4. 3. The back-contact solar cell of claim 1, wherein the prismatic and / or conical holes have a diameter of 50-300 μm, there are a plurality of the prismatic and / or conical holes, the spacing between adjacent prismatic and / or conical holes is 500-3000 μm, and the depth of the prismatic and / or conical holes is 30-80% of the thickness of the silicon substrate.

5. the cylindrical hole and / or the tapered hole are plural, and a first electrode is provided in each of the cylindrical hole and / or the tapered hole; the first electrodes are plural, and the plural first electrodes are connected by a first conductive gate line; the second electrodes are plural, and the plural second electrodes are connected by a second conductive gate line; 3. The back-contact solar cell according to claim 1, wherein the first conductive gate line and the second conductive gate line are not in contact with each other.

6. the first conductive gate line connects the first electrodes to form a "whirl" shape; 6. The back contact solar cell of claim 5, wherein the second electrode is connected by the second conductive gate line to form a "wound" shape.

7. 3. The back contact solar cell of claim 1, wherein the doped emitter layer further comprises a tunnel oxide layer disposed between the silicon substrate in the non-columnar hole region and the doped polycrystalline silicon layer.

8. 8. The back contact solar cell of claim 7, wherein the tunnel oxide layer has a thickness of 0.1-5 nm, the doped polycrystalline silicon layer has a thickness of 30-300 nm, the first electrode has a diameter of 200-100 μm, and the second electrode has a diameter of 10-30 μm.

9. the silicon substrate is a P-type silicon substrate, the doped back surface field layer is a back surface field layer doped with a group III element, 3. The back contact solar cell according to claim 1, wherein the doped polycrystalline silicon layer is a polycrystalline silicon layer doped with a Group V element.

10. a front passivation layer provided on the light-receiving surface of the silicon substrate; and a back passivation layer provided on the back surface of the silicon substrate and covering the doped back surface field layer and the doped polycrystalline silicon layer; the front and back passivation layers comprise aluminum oxide; the first electrode is in electrical contact with the doped back surface field layer through an opening in the back surface passivation layer; 9. The back contact solar cell of claim 8, wherein the second electrode is in electrical contact with the doped polycrystalline silicon layer through the opening.

11. 3. The back contact solar cell according to claim 1, wherein the bottom and / or sidewall of the cylindrical hole and / or the conical hole has a textured structure.

12. Step S1 of depositing an intrinsic amorphous silicon layer on the back surface of a silicon substrate; a step S2 of performing a primary doping process on the silicon substrate on which the intrinsic amorphous silicon layer has been deposited to form a doped polycrystalline silicon layer; a step S3 of printing an acidic etching material on the back surface of the silicon substrate on which the doped polycrystalline silicon layer is formed, and then performing a polishing process to form a columnar hole and / or a tapered hole; Step S4: performing a secondary doping process on the silicon substrate in which the cylindrical holes and / or the conical holes are formed to form a doped back surface field layer; A step S5 of pickling the silicon substrate on which the doped back surface field layer is formed; and step S6 of forming a first electrode in electrical contact with the doped back surface field layer and a second electrode in electrical contact with the doped polycrystalline silicon layer on the back surface of the silicon substrate after acid washing, the first electrode and the second electrode having opposite polarities and being insulated from each other, thereby obtaining a back-contact solar cell.

13. 13. The manufacturing method according to claim 12, wherein the first doping process in step S2 is a double-sided diffusion doping, and further comprises, after step S4, a front texturing process for removing a dopant layer formed on the front surface during the first doping process.

14. The acidic etching material in step S3 includes oxalic acid, a surfactant, a thickener, modified silica, deionized water, and sodium fluoride; The mass concentration of oxalic acid in the acidic corrosion material is 5% to 20%, The mass concentration of the surfactant in the acidic corrosion material is 5% to 10%; The mass concentration of the thickener in the acidic corrosive material is 10% to 20%; The mass concentration of the modified silica in the acidic corrosion material is 20% to 40%; The mass concentration of deionized water in the acidic corrosion material is 5% to 20%; 13. The method according to claim 12, wherein the mass concentration of sodium fluoride in the acidic corrosion material is 1% to 10%.

15. After step S5, the method further includes the steps of depositing a back surface passivation layer on the back surface of the silicon substrate after the acid cleaning, and depositing a front surface passivation layer on the front surface of the silicon substrate after the acid cleaning; The method of claim 12 , wherein the backside passivation layer and the frontside passivation layer are fabricated in the same reaction chamber.

16. 16. The manufacturing method according to claim 15, wherein the back passivation layer and the front passivation layer are manufactured by plating aluminum oxide films on both sides of the silicon substrate after acid washing.

17. 13. The manufacturing method according to claim 12, wherein the first electrode in step S6 is manufactured by forming an opening in the cylindrical hole and / or the tapered hole using a laser or an acid etching material, removing the rear surface passivation layer in the opening area, and printing the first electrode.

18. 18. The manufacturing method according to claim 17, further comprising: printing a first electrode which is a low-corrosion aluminum paste or a non-corrosion aluminum; and printing a first conductive paste which is a low-corrosion aluminum paste or a non-corrosion aluminum paste to form a first conductive paste line to connect the first electrode.

19. 13. The manufacturing method according to claim 12, wherein the second electrode is specifically manufactured by printing a corrosive paste, which is a corrosive silver paste, in the non-columnar hole region to form a second electrode, and then printing a second conductive paste, which is a low-corrosion aluminum paste or a non-corrosive aluminum paste, to form a second conductive paste line to connect the second electrode.

20. 13. The method of claim 12, wherein the steps of forming a first electrode in electrical contact with the doped back surface field layer and a second electrode in electrical contact with the doped polycrystalline silicon layer on the back surface of the silicon substrate after pickling include sintering the electrodes at a sintering temperature of 600°C to 800°C for 2 to 5 minutes to form the electrical contacts.

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